regress: Regression tester updates
Regression tester updates required by the following patches: brad/moved_python_protocol_files: config: moved python protocol config files brad/ruby_options_movement: config: reorganized how ruby specifies command-line options brad/config_token_bcast: ruby: added token broadcast config params to cmd options brad/topology_name: config: Added the topology description to m5 config.ini brad/ruby_system_names: config: Improve ruby simobject names brad/consolidated_protocol_stats: slicc: Consolidated the protocol stats printing brad/ruby_request_type_ostream_fix: ruby: Added ruby_request_type ostream def to libruby.hh brad/memtest_dma_extension: memtest: Memtester support for DMA brad/token_dma_lockdown_fix: MOESI_CMP_token: Fixed dma persistent lockdown bugs brad/profile_generic_mach_type: ruby: Reincarnated the responding machine profiling brad/network_msg_consolidated_stats: ruby: Added consolidated network msg stats brad/bcast_msg_profiling: ruby: Added bcast msg profiling to hammer and token brad/l2cache_profiling_fix: ruby: Fixed L2 cache miss profiling brad/llsc_ruby_m5_fix: ruby: fix ruby llsc support to sync sc outcomes brad/ruby_latency_fixes: ruby: Reduced ruby latencies brad/hammer_l2_cache_latency: ruby: Updated MOESI_hammer L2 latency behavior brad/deterministic_resurrection: ruby: Resurrected Ruby's deterministic tests brad/token_dma_fixes: ruby: MOESI_CMP_token dma fixes brad/ruby_cmd_options: config: added cmd options to control ruby debug brad/token_owner_fixes: ruby: fixed token bugs associated with owner token counts brad/ruby_remove_try_except: ruby: Improved try except blocks in ruby creation brad/ruby_port_callback_fix: ruby: Fixed RubyPort sendTiming callbacks brad/interrupt_drain_fix: devices: Fixed periodic interrupts to work with draining brad/llsc_trace_profile: ruby: Added SC fail indication to trace profiling brad/no_migrate_atomic: ruby: Disable migratory sharing for token and hammer brad/ruby_start_time_fix: ruby: Reset ruby stats in RubySystem unserialize brad/numa_bit_select_fix: ruby: fixed DirectoryMemory's numa_high_bit configuration brad/hammer_probe_filter: ruby: added probe filter support to hammer brad/miss_latency_detail_profile: MOESI_hammer: break down miss latency stalled cycles brad/recycle_latency_fix: ruby: Recycle latency fix for hammer brad/stall_and_wait: ruby: Stall and wait input messages instead of recycling brad/rubytest_request_flag_fix: ruby: Fixed minor bug in ruby test for setting the request type brad/hammer_merge_gets: ruby: Added merge GETS optimization to hammer brad/regress_updates: regress: Regression tester updates
This commit is contained in:
Brad Beckmann
parent
8557480300
commit
3d93afe348
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@ -42,28 +42,33 @@ config_root = os.path.dirname(config_path)
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m5_root = os.path.dirname(config_root)
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addToPath(config_root+'/configs/common')
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addToPath(config_root+'/configs/ruby')
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addToPath(config_root+'/configs/ruby/protocols')
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addToPath(config_root+'/configs/ruby/topologies')
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import Ruby
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parser = optparse.OptionParser()
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#
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# Set the default cache size and associativity to be very small to encourage
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# races between requests and writebacks.
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# Add the ruby specific and protocol specific options
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#
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parser.add_option("--l1d_size", type="string", default="256B")
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parser.add_option("--l1i_size", type="string", default="256B")
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parser.add_option("--l2_size", type="string", default="512B")
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parser.add_option("--l1d_assoc", type="int", default=2)
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parser.add_option("--l1i_assoc", type="int", default=2)
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parser.add_option("--l2_assoc", type="int", default=2)
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Ruby.define_options(parser)
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execfile(os.path.join(config_root, "configs/common", "Options.py"))
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(options, args) = parser.parse_args()
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#
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# Set the default cache size and associativity to be very small to encourage
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# races between requests and writebacks.
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#
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options.l1d_size="256B"
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options.l1i_size="256B"
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options.l2_size="512B"
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options.l3_size="1kB"
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options.l1d_assoc=2
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options.l1i_assoc=2
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options.l2_assoc=2
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options.l3_assoc=2
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#MAX CORES IS 8 with the fals sharing method
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nb_cores = 8
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@ -80,7 +85,7 @@ system = System(cpu = cpus,
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funcmem = PhysicalMemory(),
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physmem = PhysicalMemory())
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system.ruby = Ruby.create_system(options, system.physmem)
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system.ruby = Ruby.create_system(options, system)
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assert(len(cpus) == len(system.ruby.cpu_ruby_ports))
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@ -43,28 +43,33 @@ config_root = os.path.dirname(config_path)
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m5_root = os.path.dirname(config_root)
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addToPath(config_root+'/configs/common')
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addToPath(config_root+'/configs/ruby')
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addToPath(config_root+'/configs/ruby/protocols')
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addToPath(config_root+'/configs/ruby/topologies')
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import Ruby
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parser = optparse.OptionParser()
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#
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# Set the default cache size and associativity to be very small to encourage
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# races between requests and writebacks.
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# Add the ruby specific and protocol specific options
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#
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parser.add_option("--l1d_size", type="string", default="256B")
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parser.add_option("--l1i_size", type="string", default="256B")
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parser.add_option("--l2_size", type="string", default="512B")
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parser.add_option("--l1d_assoc", type="int", default=2)
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parser.add_option("--l1i_assoc", type="int", default=2)
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parser.add_option("--l2_assoc", type="int", default=2)
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Ruby.define_options(parser)
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execfile(os.path.join(config_root, "configs/common", "Options.py"))
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(options, args) = parser.parse_args()
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#
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# Set the default cache size and associativity to be very small to encourage
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# races between requests and writebacks.
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#
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options.l1d_size="256B"
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options.l1i_size="256B"
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options.l2_size="512B"
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options.l3_size="1kB"
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options.l1d_assoc=2
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options.l1i_assoc=2
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options.l2_assoc=2
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options.l3_assoc=2
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#
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# create the tester and system, including ruby
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#
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@ -72,7 +77,7 @@ tester = RubyTester(checks_to_complete = 100, wakeup_frequency = 10)
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system = System(tester = tester, physmem = PhysicalMemory())
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system.ruby = Ruby.create_system(options, system.physmem)
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system.ruby = Ruby.create_system(options, system)
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assert(options.num_cpus == len(system.ruby.cpu_ruby_ports))
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@ -41,28 +41,33 @@ config_root = os.path.dirname(config_path)
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m5_root = os.path.dirname(config_root)
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addToPath(config_root+'/configs/common')
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addToPath(config_root+'/configs/ruby')
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addToPath(config_root+'/configs/ruby/protocols')
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addToPath(config_root+'/configs/ruby/topologies')
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import Ruby
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parser = optparse.OptionParser()
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#
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# Set the default cache size and associativity to be very small to encourage
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# races between requests and writebacks.
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# Add the ruby specific and protocol specific options
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#
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parser.add_option("--l1d_size", type="string", default="256B")
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parser.add_option("--l1i_size", type="string", default="256B")
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parser.add_option("--l2_size", type="string", default="512B")
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parser.add_option("--l1d_assoc", type="int", default=2)
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parser.add_option("--l1i_assoc", type="int", default=2)
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parser.add_option("--l2_assoc", type="int", default=2)
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Ruby.define_options(parser)
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execfile(os.path.join(config_root, "configs/common", "Options.py"))
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(options, args) = parser.parse_args()
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#
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# Set the default cache size and associativity to be very small to encourage
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# races between requests and writebacks.
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#
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options.l1d_size="256B"
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options.l1i_size="256B"
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options.l2_size="512B"
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options.l3_size="1kB"
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options.l1d_assoc=2
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options.l1i_assoc=2
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options.l2_assoc=2
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options.l3_assoc=2
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nb_cores = 4
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cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
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@ -70,10 +75,9 @@ cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
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options.num_cpus = nb_cores
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# system simulated
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system = System(cpu = cpus,
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physmem = PhysicalMemory())
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system = System(cpu = cpus, physmem = PhysicalMemory())
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system.ruby = Ruby.create_system(options, system.physmem)
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system.ruby = Ruby.create_system(options, system)
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assert(options.num_cpus == len(system.ruby.cpu_ruby_ports))
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@ -41,36 +41,40 @@ config_root = os.path.dirname(config_path)
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m5_root = os.path.dirname(config_root)
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addToPath(config_root+'/configs/common')
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addToPath(config_root+'/configs/ruby')
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addToPath(config_root+'/configs/ruby/protocols')
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addToPath(config_root+'/configs/ruby/topologies')
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import Ruby
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parser = optparse.OptionParser()
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#
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# Set the default cache size and associativity to be very small to encourage
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# races between requests and writebacks.
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# Add the ruby specific and protocol specific options
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#
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parser.add_option("--l1d_size", type="string", default="256B")
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parser.add_option("--l1i_size", type="string", default="256B")
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parser.add_option("--l2_size", type="string", default="512B")
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parser.add_option("--l1d_assoc", type="int", default=2)
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parser.add_option("--l1i_assoc", type="int", default=2)
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parser.add_option("--l2_assoc", type="int", default=2)
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Ruby.define_options(parser)
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execfile(os.path.join(config_root, "configs/common", "Options.py"))
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(options, args) = parser.parse_args()
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#
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# Set the default cache size and associativity to be very small to encourage
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# races between requests and writebacks.
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#
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options.l1d_size="256B"
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options.l1i_size="256B"
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options.l2_size="512B"
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options.l3_size="1kB"
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options.l1d_assoc=2
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options.l1i_assoc=2
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options.l2_assoc=2
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options.l3_assoc=2
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# this is a uniprocessor only test
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options.num_cpus = 1
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cpu = TimingSimpleCPU(cpu_id=0)
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system = System(cpu = cpu,
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physmem = PhysicalMemory())
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system = System(cpu = cpu, physmem = PhysicalMemory())
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system.ruby = Ruby.create_system(options, system.physmem)
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system.ruby = Ruby.create_system(options, system)
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assert(len(system.ruby.cpu_ruby_ports) == 1)
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@ -5,7 +5,7 @@ dummy=0
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[system]
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type=System
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children=cpu physmem ruby
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children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
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mem_mode=timing
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physmem=system.physmem
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@ -32,8 +32,8 @@ progress_interval=0
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system=system
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tracer=system.cpu.tracer
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workload=system.cpu.workload
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dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
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icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
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dcache_port=system.l1_cntrl0.sequencer.port[1]
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icache_port=system.l1_cntrl0.sequencer.port[0]
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[system.cpu.dtb]
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type=AlphaTLB
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@ -54,7 +54,7 @@ egid=100
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env=
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errout=cerr
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euid=100
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executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
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executable=tests/test-progs/hello/bin/alpha/linux/hello
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gid=100
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input=cin
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max_stack_size=67108864
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@ -65,166 +65,28 @@ simpoint=0
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system=system
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uid=100
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[system.physmem]
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type=PhysicalMemory
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file=
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latency=30
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latency_var=0
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null=false
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range=0:134217727
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zero=false
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port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
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[system.ruby]
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type=RubySystem
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children=debug network profiler tracer
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block_size_bytes=64
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clock=1
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debug=system.ruby.debug
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mem_size=134217728
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network=system.ruby.network
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profiler=system.ruby.profiler
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random_seed=1234
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randomization=false
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stats_filename=ruby.stats
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tracer=system.ruby.tracer
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[system.ruby.debug]
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type=RubyDebug
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filter_string=none
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output_filename=none
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protocol_trace=false
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start_time=1
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verbosity_string=none
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[system.ruby.network]
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type=SimpleNetwork
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children=topology
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adaptive_routing=true
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buffer_size=0
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control_msg_size=8
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endpoint_bandwidth=10000
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link_latency=1
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number_of_virtual_networks=10
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topology=system.ruby.network.topology
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[system.ruby.network.topology]
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type=Topology
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children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
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ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
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int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
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num_int_nodes=4
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print_config=false
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[system.ruby.network.topology.ext_links0]
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type=ExtLink
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children=ext_node
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bw_multiplier=64
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ext_node=system.ruby.network.topology.ext_links0.ext_node
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int_node=0
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latency=1
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weight=1
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[system.ruby.network.topology.ext_links0.ext_node]
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type=L1Cache_Controller
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children=sequencer
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L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
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L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
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buffer_size=0
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l1_request_latency=2
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l1_response_latency=2
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l2_select_num_bits=0
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number_of_TBEs=256
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recycle_latency=10
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sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
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to_l2_latency=1
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transitions_per_cycle=32
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version=0
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[system.ruby.network.topology.ext_links0.ext_node.sequencer]
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type=RubySequencer
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children=dcache icache
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dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
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deadlock_threshold=500000
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icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
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max_outstanding_requests=16
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physmem=system.physmem
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using_ruby_tester=false
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version=0
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physMemPort=system.physmem.port[0]
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port=system.cpu.icache_port system.cpu.dcache_port
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[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
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type=RubyCache
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assoc=2
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latency=3
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replacement_policy=PSEUDO_LRU
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size=256
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[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
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type=RubyCache
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assoc=2
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latency=3
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replacement_policy=PSEUDO_LRU
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size=256
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[system.ruby.network.topology.ext_links1]
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type=ExtLink
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children=ext_node
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bw_multiplier=64
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ext_node=system.ruby.network.topology.ext_links1.ext_node
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int_node=1
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latency=1
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weight=1
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[system.ruby.network.topology.ext_links1.ext_node]
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type=L2Cache_Controller
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children=L2cacheMemory
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L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
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buffer_size=0
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l2_request_latency=2
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l2_response_latency=2
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number_of_TBEs=256
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recycle_latency=10
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to_l1_latency=1
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transitions_per_cycle=32
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version=0
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[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory]
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type=RubyCache
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assoc=2
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latency=15
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replacement_policy=PSEUDO_LRU
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size=512
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[system.ruby.network.topology.ext_links2]
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type=ExtLink
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children=ext_node
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bw_multiplier=64
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ext_node=system.ruby.network.topology.ext_links2.ext_node
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int_node=2
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latency=1
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weight=1
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[system.ruby.network.topology.ext_links2.ext_node]
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[system.dir_cntrl0]
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type=Directory_Controller
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children=directory memBuffer
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buffer_size=0
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directory=system.ruby.network.topology.ext_links2.ext_node.directory
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directory=system.dir_cntrl0.directory
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directory_latency=6
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memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer
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memBuffer=system.dir_cntrl0.memBuffer
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number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
to_mem_ctrl_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.directory]
|
||||
[system.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=6
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.memBuffer]
|
||||
[system.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
|
|
@ -245,6 +107,149 @@ refresh_period=1560
|
|||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
|
||||
L1IcacheMemory=system.l1_cntrl0.sequencer.icache
|
||||
buffer_size=0
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.l1_cntrl0.sequencer
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.l1_cntrl0.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.l1_cntrl0.sequencer.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l2_cntrl0]
|
||||
type=L2Cache_Controller
|
||||
children=L2cacheMemory
|
||||
L2cacheMemory=system.l2_cntrl0.L2cacheMemory
|
||||
buffer_size=0
|
||||
l2_request_latency=2
|
||||
l2_response_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
to_l1_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l2_cntrl0.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=15
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
start_index_bit=6
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.l1_cntrl0.sequencer.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
no_mem_vec=false
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
output_filename=none
|
||||
protocol_trace=false
|
||||
start_time=1
|
||||
verbosity_string=none
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=false
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
link_latency=1
|
||||
number_of_virtual_networks=10
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
|
||||
name=Crossbar
|
||||
num_int_nodes=4
|
||||
print_config=false
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
bw_multiplier=64
|
||||
ext_node=system.l1_cntrl0
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
bw_multiplier=64
|
||||
ext_node=system.l2_cntrl0
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links2]
|
||||
type=ExtLink
|
||||
bw_multiplier=64
|
||||
ext_node=system.dir_cntrl0
|
||||
int_node=2
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links0]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@ RubySystem config:
|
|||
Network Configuration
|
||||
---------------------
|
||||
network: SIMPLE_NETWORK
|
||||
topology:
|
||||
topology: Crossbar
|
||||
|
||||
virtual_net_0: active, unordered
|
||||
virtual_net_1: active, unordered
|
||||
|
|
@ -34,7 +34,7 @@ periodic_stats_period: 1000000
|
|||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Jan/28/2010 13:57:44
|
||||
Real time: Aug/05/2010 10:23:43
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
|
|
@ -43,31 +43,20 @@ Elapsed_time_in_minutes: 0.0166667
|
|||
Elapsed_time_in_hours: 0.000277778
|
||||
Elapsed_time_in_days: 1.15741e-05
|
||||
|
||||
Virtual_time_in_seconds: 0.95
|
||||
Virtual_time_in_minutes: 0.0158333
|
||||
Virtual_time_in_hours: 0.000263889
|
||||
Virtual_time_in_days: 1.09954e-05
|
||||
Virtual_time_in_seconds: 0.32
|
||||
Virtual_time_in_minutes: 0.00533333
|
||||
Virtual_time_in_hours: 8.88889e-05
|
||||
Virtual_time_in_days: 3.7037e-06
|
||||
|
||||
Ruby_current_time: 275313
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 275313
|
||||
|
||||
mbytes_resident: 34.4609
|
||||
mbytes_total: 34.4688
|
||||
mbytes_resident: 34.8867
|
||||
mbytes_total: 34.8945
|
||||
resident_ratio: 1
|
||||
|
||||
Total_misses: 0
|
||||
total_misses: 0 [ 0 ]
|
||||
user_misses: 0 [ 0 ]
|
||||
supervisor_misses: 0 [ 0 ]
|
||||
|
||||
ruby_cycles_executed: 275314 [ 275314 ]
|
||||
|
||||
transactions_started: 0 [ 0 ]
|
||||
transactions_ended: 0 [ 0 ]
|
||||
cycles_per_transaction: 0 [ 0 ]
|
||||
misses_per_transaction: 0 [ 0 ]
|
||||
|
||||
ruby_cycles_executed: [ 275314 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
|
|
@ -82,9 +71,23 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 |
|
|||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 2 max: 281 count: 8464 average: 31.5275 | standard deviation: 62.4195 | 0 6974 0 0 0 0 0 0 0 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 156 439 246 330 220 8 7 9 11 3 2 9 4 5 1 0 0 1 1 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_1: [binsize: 2 max: 269 count: 6414 average: 20.6784 | standard deviation: 51.1007 | 0 5723 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 59 203 95 191 106 4 5 4 6 2 1 1 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_2: [binsize: 2 max: 281 count: 1185 average: 82.5848 | standard deviation: 82.5677 | 0 602 0 0 0 0 0 0 0 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 64 191 73 123 92 4 2 3 3 1 1 7 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_3: [binsize: 2 max: 215 count: 865 average: 42.0289 | standard deviation: 69.8546 | 0 649 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33 45 78 16 22 0 0 2 2 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 2 max: 269 count: 6414 average: 20.6784 | standard deviation: 51.1007 | 0 5723 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 59 203 95 191 106 4 5 4 6 2 1 1 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 2 max: 281 count: 1185 average: 82.5848 | standard deviation: 82.5677 | 0 602 0 0 0 0 0 0 0 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 64 191 73 123 92 4 2 3 3 1 1 7 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 2 max: 215 count: 865 average: 42.0289 | standard deviation: 69.8546 | 0 649 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33 45 78 16 22 0 0 2 2 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_NULL: [binsize: 2 max: 281 count: 8464 average: 31.5275 | standard deviation: 62.4195 | 0 6974 0 0 0 0 0 0 0 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 156 439 246 330 220 8 7 9 11 3 2 9 4 5 1 0 0 1 1 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_wCC_Times: 0
|
||||
miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_dir_Times: 0
|
||||
miss_latency_IFETCH_NULL: [binsize: 2 max: 269 count: 6414 average: 20.6784 | standard deviation: 51.1007 | 0 5723 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 59 203 95 191 106 4 5 4 6 2 1 1 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD_NULL: [binsize: 2 max: 281 count: 1185 average: 82.5848 | standard deviation: 82.5677 | 0 602 0 0 0 0 0 0 0 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 64 191 73 123 92 4 2 3 3 1 1 7 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_NULL: [binsize: 2 max: 215 count: 865 average: 42.0289 | standard deviation: 69.8546 | 0 649 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33 45 78 16 22 0 0 2 2 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
|
|
@ -116,8 +119,8 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 7392
|
||||
page_faults: 2212
|
||||
page_reclaims: 7576
|
||||
page_faults: 2166
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
|
|
@ -125,6 +128,14 @@ block_outputs: 0
|
|||
Network Stats
|
||||
-------------
|
||||
|
||||
total_msg_count_Control: 8850 70800
|
||||
total_msg_count_Request_Control: 3123 24984
|
||||
total_msg_count_Response_Data: 9681 697032
|
||||
total_msg_count_Response_Control: 14286 114288
|
||||
total_msg_count_Writeback_Data: 864 62208
|
||||
total_msg_count_Writeback_Control: 867 6936
|
||||
total_msgs: 37671 total_bytes: 976248
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 0.0889147
|
||||
|
|
@ -186,352 +197,346 @@ links_utilized_percent_switch_3: 0.246247
|
|||
outgoing_messages_switch_3_link_2_Response_Data: 277 19944 [ 0 277 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Response_Control: 1175 9400 [ 0 1175 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan
|
||||
Cache Stats: system.l1_cntrl0.sequencer.icache
|
||||
system.l1_cntrl0.sequencer.icache_total_misses: 0
|
||||
system.l1_cntrl0.sequencer.icache_total_demand_misses: 0
|
||||
system.l1_cntrl0.sequencer.icache_total_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: nan
|
||||
Cache Stats: system.l1_cntrl0.sequencer.dcache
|
||||
system.l1_cntrl0.sequencer.dcache_total_misses: 0
|
||||
system.l1_cntrl0.sequencer.dcache_total_demand_misses: 0
|
||||
system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
--- L1Cache 0 ---
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load 1185
|
||||
Ifetch 6414
|
||||
Store 865
|
||||
Inv 1041
|
||||
L1_Replacement 1354
|
||||
Fwd_GETX 0
|
||||
Fwd_GETS 0
|
||||
Fwd_GET_INSTR 0
|
||||
Data 0
|
||||
Data_Exclusive 583
|
||||
DataS_fromL1 0
|
||||
Data_all_Acks 907
|
||||
Ack 0
|
||||
Ack_all 0
|
||||
WB_Ack 436
|
||||
Load [1185 ] 1185
|
||||
Ifetch [6414 ] 6414
|
||||
Store [865 ] 865
|
||||
Inv [1041 ] 1041
|
||||
L1_Replacement [1354 ] 1354
|
||||
Fwd_GETX [0 ] 0
|
||||
Fwd_GETS [0 ] 0
|
||||
Fwd_GET_INSTR [0 ] 0
|
||||
Data [0 ] 0
|
||||
Data_Exclusive [583 ] 583
|
||||
DataS_fromL1 [0 ] 0
|
||||
Data_all_Acks [907 ] 907
|
||||
Ack [0 ] 0
|
||||
Ack_all [0 ] 0
|
||||
WB_Ack [436 ] 436
|
||||
|
||||
- Transitions -
|
||||
NP Load 525
|
||||
NP Ifetch 646
|
||||
NP Store 191
|
||||
NP Inv 356
|
||||
NP L1_Replacement 0 <--
|
||||
NP Load [525 ] 525
|
||||
NP Ifetch [646 ] 646
|
||||
NP Store [191 ] 191
|
||||
NP Inv [356 ] 356
|
||||
NP L1_Replacement [0 ] 0
|
||||
|
||||
I Load 58
|
||||
I Ifetch 45
|
||||
I Store 25
|
||||
I Inv 0 <--
|
||||
I L1_Replacement 556
|
||||
I Load [58 ] 58
|
||||
I Ifetch [45 ] 45
|
||||
I Store [25 ] 25
|
||||
I Inv [0 ] 0
|
||||
I L1_Replacement [556 ] 556
|
||||
|
||||
S Load 0 <--
|
||||
S Ifetch 5723
|
||||
S Store 0 <--
|
||||
S Inv 325
|
||||
S L1_Replacement 362
|
||||
S Load [0 ] 0
|
||||
S Ifetch [5723 ] 5723
|
||||
S Store [0 ] 0
|
||||
S Inv [325 ] 325
|
||||
S L1_Replacement [362 ] 362
|
||||
|
||||
E Load 454
|
||||
E Ifetch 0 <--
|
||||
E Store 71
|
||||
E Inv 219
|
||||
E L1_Replacement 291
|
||||
E Fwd_GETX 0 <--
|
||||
E Fwd_GETS 0 <--
|
||||
E Fwd_GET_INSTR 0 <--
|
||||
E Load [454 ] 454
|
||||
E Ifetch [0 ] 0
|
||||
E Store [71 ] 71
|
||||
E Inv [219 ] 219
|
||||
E L1_Replacement [291 ] 291
|
||||
E Fwd_GETX [0 ] 0
|
||||
E Fwd_GETS [0 ] 0
|
||||
E Fwd_GET_INSTR [0 ] 0
|
||||
|
||||
M Load 148
|
||||
M Ifetch 0 <--
|
||||
M Store 578
|
||||
M Inv 141
|
||||
M L1_Replacement 145
|
||||
M Fwd_GETX 0 <--
|
||||
M Fwd_GETS 0 <--
|
||||
M Fwd_GET_INSTR 0 <--
|
||||
M Load [148 ] 148
|
||||
M Ifetch [0 ] 0
|
||||
M Store [578 ] 578
|
||||
M Inv [141 ] 141
|
||||
M L1_Replacement [145 ] 145
|
||||
M Fwd_GETX [0 ] 0
|
||||
M Fwd_GETS [0 ] 0
|
||||
M Fwd_GET_INSTR [0 ] 0
|
||||
|
||||
IS Load 0 <--
|
||||
IS Ifetch 0 <--
|
||||
IS Store 0 <--
|
||||
IS Inv 0 <--
|
||||
IS L1_Replacement 0 <--
|
||||
IS Data_Exclusive 583
|
||||
IS DataS_fromL1 0 <--
|
||||
IS Data_all_Acks 691
|
||||
IS Load [0 ] 0
|
||||
IS Ifetch [0 ] 0
|
||||
IS Store [0 ] 0
|
||||
IS Inv [0 ] 0
|
||||
IS L1_Replacement [0 ] 0
|
||||
IS Data_Exclusive [583 ] 583
|
||||
IS DataS_fromL1 [0 ] 0
|
||||
IS Data_all_Acks [691 ] 691
|
||||
|
||||
IM Load 0 <--
|
||||
IM Ifetch 0 <--
|
||||
IM Store 0 <--
|
||||
IM Inv 0 <--
|
||||
IM L1_Replacement 0 <--
|
||||
IM Data 0 <--
|
||||
IM Data_all_Acks 216
|
||||
IM Ack 0 <--
|
||||
IM Load [0 ] 0
|
||||
IM Ifetch [0 ] 0
|
||||
IM Store [0 ] 0
|
||||
IM Inv [0 ] 0
|
||||
IM L1_Replacement [0 ] 0
|
||||
IM Data [0 ] 0
|
||||
IM Data_all_Acks [216 ] 216
|
||||
IM Ack [0 ] 0
|
||||
|
||||
SM Load 0 <--
|
||||
SM Ifetch 0 <--
|
||||
SM Store 0 <--
|
||||
SM Inv 0 <--
|
||||
SM L1_Replacement 0 <--
|
||||
SM Ack 0 <--
|
||||
SM Ack_all 0 <--
|
||||
SM Load [0 ] 0
|
||||
SM Ifetch [0 ] 0
|
||||
SM Store [0 ] 0
|
||||
SM Inv [0 ] 0
|
||||
SM L1_Replacement [0 ] 0
|
||||
SM Ack [0 ] 0
|
||||
SM Ack_all [0 ] 0
|
||||
|
||||
IS_I Load 0 <--
|
||||
IS_I Ifetch 0 <--
|
||||
IS_I Store 0 <--
|
||||
IS_I Inv 0 <--
|
||||
IS_I L1_Replacement 0 <--
|
||||
IS_I Data_Exclusive 0 <--
|
||||
IS_I DataS_fromL1 0 <--
|
||||
IS_I Data_all_Acks 0 <--
|
||||
IS_I Load [0 ] 0
|
||||
IS_I Ifetch [0 ] 0
|
||||
IS_I Store [0 ] 0
|
||||
IS_I Inv [0 ] 0
|
||||
IS_I L1_Replacement [0 ] 0
|
||||
IS_I Data_Exclusive [0 ] 0
|
||||
IS_I DataS_fromL1 [0 ] 0
|
||||
IS_I Data_all_Acks [0 ] 0
|
||||
|
||||
M_I Load 0 <--
|
||||
M_I Ifetch 0 <--
|
||||
M_I Store 0 <--
|
||||
M_I Inv 0 <--
|
||||
M_I L1_Replacement 0 <--
|
||||
M_I Fwd_GETX 0 <--
|
||||
M_I Fwd_GETS 0 <--
|
||||
M_I Fwd_GET_INSTR 0 <--
|
||||
M_I WB_Ack 436
|
||||
M_I Load [0 ] 0
|
||||
M_I Ifetch [0 ] 0
|
||||
M_I Store [0 ] 0
|
||||
M_I Inv [0 ] 0
|
||||
M_I L1_Replacement [0 ] 0
|
||||
M_I Fwd_GETX [0 ] 0
|
||||
M_I Fwd_GETS [0 ] 0
|
||||
M_I Fwd_GET_INSTR [0 ] 0
|
||||
M_I WB_Ack [436 ] 436
|
||||
|
||||
E_I Load 0 <--
|
||||
E_I Ifetch 0 <--
|
||||
E_I Store 0 <--
|
||||
E_I L1_Replacement 0 <--
|
||||
E_I Load [0 ] 0
|
||||
E_I Ifetch [0 ] 0
|
||||
E_I Store [0 ] 0
|
||||
E_I L1_Replacement [0 ] 0
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_misses_per_transaction: nan
|
||||
Cache Stats: system.l2_cntrl0.L2cacheMemory
|
||||
system.l2_cntrl0.L2cacheMemory_total_misses: 0
|
||||
system.l2_cntrl0.L2cacheMemory_total_demand_misses: 0
|
||||
system.l2_cntrl0.L2cacheMemory_total_prefetches: 0
|
||||
system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
|
||||
system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
--- L2Cache 0 ---
|
||||
--- L2Cache ---
|
||||
- Event Counts -
|
||||
L1_GET_INSTR 691
|
||||
L1_GETS 592
|
||||
L1_GETX 220
|
||||
L1_UPGRADE 0
|
||||
L1_PUTX 436
|
||||
L1_PUTX_old 0
|
||||
Fwd_L1_GETX 0
|
||||
Fwd_L1_GETS 0
|
||||
Fwd_L1_GET_INSTR 0
|
||||
L2_Replacement 142
|
||||
L2_Replacement_clean 1310
|
||||
Mem_Data 1460
|
||||
Mem_Ack 1452
|
||||
WB_Data 141
|
||||
WB_Data_clean 0
|
||||
Ack 0
|
||||
Ack_all 900
|
||||
Unblock 0
|
||||
Unblock_Cancel 0
|
||||
Exclusive_Unblock 799
|
||||
MEM_Inv 0
|
||||
L1_GET_INSTR [691 ] 691
|
||||
L1_GETS [592 ] 592
|
||||
L1_GETX [220 ] 220
|
||||
L1_UPGRADE [0 ] 0
|
||||
L1_PUTX [436 ] 436
|
||||
L1_PUTX_old [0 ] 0
|
||||
Fwd_L1_GETX [0 ] 0
|
||||
Fwd_L1_GETS [0 ] 0
|
||||
Fwd_L1_GET_INSTR [0 ] 0
|
||||
L2_Replacement [142 ] 142
|
||||
L2_Replacement_clean [1310 ] 1310
|
||||
Mem_Data [1460 ] 1460
|
||||
Mem_Ack [1452 ] 1452
|
||||
WB_Data [141 ] 141
|
||||
WB_Data_clean [0 ] 0
|
||||
Ack [0 ] 0
|
||||
Ack_all [900 ] 900
|
||||
Unblock [0 ] 0
|
||||
Unblock_Cancel [0 ] 0
|
||||
Exclusive_Unblock [799 ] 799
|
||||
MEM_Inv [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
NP L1_GET_INSTR 686
|
||||
NP L1_GETS 570
|
||||
NP L1_GETX 204
|
||||
NP L1_PUTX 0 <--
|
||||
NP L1_PUTX_old 0 <--
|
||||
NP L1_GET_INSTR [686 ] 686
|
||||
NP L1_GETS [570 ] 570
|
||||
NP L1_GETX [204 ] 204
|
||||
NP L1_PUTX [0 ] 0
|
||||
NP L1_PUTX_old [0 ] 0
|
||||
|
||||
SS L1_GET_INSTR 5
|
||||
SS L1_GETS 0 <--
|
||||
SS L1_GETX 0 <--
|
||||
SS L1_UPGRADE 0 <--
|
||||
SS L1_PUTX 0 <--
|
||||
SS L1_PUTX_old 0 <--
|
||||
SS L2_Replacement 0 <--
|
||||
SS L2_Replacement_clean 681
|
||||
SS MEM_Inv 0 <--
|
||||
SS L1_GET_INSTR [5 ] 5
|
||||
SS L1_GETS [0 ] 0
|
||||
SS L1_GETX [0 ] 0
|
||||
SS L1_UPGRADE [0 ] 0
|
||||
SS L1_PUTX [0 ] 0
|
||||
SS L1_PUTX_old [0 ] 0
|
||||
SS L2_Replacement [0 ] 0
|
||||
SS L2_Replacement_clean [681 ] 681
|
||||
SS MEM_Inv [0 ] 0
|
||||
|
||||
M L1_GET_INSTR 0 <--
|
||||
M L1_GETS 13
|
||||
M L1_GETX 12
|
||||
M L1_PUTX 0 <--
|
||||
M L1_PUTX_old 0 <--
|
||||
M L2_Replacement 134
|
||||
M L2_Replacement_clean 277
|
||||
M MEM_Inv 0 <--
|
||||
M L1_GET_INSTR [0 ] 0
|
||||
M L1_GETS [13 ] 13
|
||||
M L1_GETX [12 ] 12
|
||||
M L1_PUTX [0 ] 0
|
||||
M L1_PUTX_old [0 ] 0
|
||||
M L2_Replacement [134 ] 134
|
||||
M L2_Replacement_clean [277 ] 277
|
||||
M MEM_Inv [0 ] 0
|
||||
|
||||
MT L1_GET_INSTR 0 <--
|
||||
MT L1_GETS 0 <--
|
||||
MT L1_GETX 0 <--
|
||||
MT L1_PUTX 436
|
||||
MT L1_PUTX_old 0 <--
|
||||
MT L2_Replacement 8
|
||||
MT L2_Replacement_clean 352
|
||||
MT MEM_Inv 0 <--
|
||||
MT L1_GET_INSTR [0 ] 0
|
||||
MT L1_GETS [0 ] 0
|
||||
MT L1_GETX [0 ] 0
|
||||
MT L1_PUTX [436 ] 436
|
||||
MT L1_PUTX_old [0 ] 0
|
||||
MT L2_Replacement [8 ] 8
|
||||
MT L2_Replacement_clean [352 ] 352
|
||||
MT MEM_Inv [0 ] 0
|
||||
|
||||
M_I L1_GET_INSTR 0 <--
|
||||
M_I L1_GETS 9
|
||||
M_I L1_GETX 4
|
||||
M_I L1_UPGRADE 0 <--
|
||||
M_I L1_PUTX 0 <--
|
||||
M_I L1_PUTX_old 0 <--
|
||||
M_I Mem_Ack 1452
|
||||
M_I MEM_Inv 0 <--
|
||||
M_I L1_GET_INSTR [0 ] 0
|
||||
M_I L1_GETS [9 ] 9
|
||||
M_I L1_GETX [4 ] 4
|
||||
M_I L1_UPGRADE [0 ] 0
|
||||
M_I L1_PUTX [0 ] 0
|
||||
M_I L1_PUTX_old [0 ] 0
|
||||
M_I Mem_Ack [1452 ] 1452
|
||||
M_I MEM_Inv [0 ] 0
|
||||
|
||||
MT_I L1_GET_INSTR 0 <--
|
||||
MT_I L1_GETS 0 <--
|
||||
MT_I L1_GETX 0 <--
|
||||
MT_I L1_UPGRADE 0 <--
|
||||
MT_I L1_PUTX 0 <--
|
||||
MT_I L1_PUTX_old 0 <--
|
||||
MT_I WB_Data 6
|
||||
MT_I WB_Data_clean 0 <--
|
||||
MT_I Ack_all 2
|
||||
MT_I MEM_Inv 0 <--
|
||||
MT_I L1_GET_INSTR [0 ] 0
|
||||
MT_I L1_GETS [0 ] 0
|
||||
MT_I L1_GETX [0 ] 0
|
||||
MT_I L1_UPGRADE [0 ] 0
|
||||
MT_I L1_PUTX [0 ] 0
|
||||
MT_I L1_PUTX_old [0 ] 0
|
||||
MT_I WB_Data [6 ] 6
|
||||
MT_I WB_Data_clean [0 ] 0
|
||||
MT_I Ack_all [2 ] 2
|
||||
MT_I MEM_Inv [0 ] 0
|
||||
|
||||
MCT_I L1_GET_INSTR 0 <--
|
||||
MCT_I L1_GETS 0 <--
|
||||
MCT_I L1_GETX 0 <--
|
||||
MCT_I L1_UPGRADE 0 <--
|
||||
MCT_I L1_PUTX 0 <--
|
||||
MCT_I L1_PUTX_old 0 <--
|
||||
MCT_I WB_Data 135
|
||||
MCT_I WB_Data_clean 0 <--
|
||||
MCT_I Ack_all 217
|
||||
MCT_I L1_GET_INSTR [0 ] 0
|
||||
MCT_I L1_GETS [0 ] 0
|
||||
MCT_I L1_GETX [0 ] 0
|
||||
MCT_I L1_UPGRADE [0 ] 0
|
||||
MCT_I L1_PUTX [0 ] 0
|
||||
MCT_I L1_PUTX_old [0 ] 0
|
||||
MCT_I WB_Data [135 ] 135
|
||||
MCT_I WB_Data_clean [0 ] 0
|
||||
MCT_I Ack_all [217 ] 217
|
||||
|
||||
I_I L1_GET_INSTR 0 <--
|
||||
I_I L1_GETS 0 <--
|
||||
I_I L1_GETX 0 <--
|
||||
I_I L1_UPGRADE 0 <--
|
||||
I_I L1_PUTX 0 <--
|
||||
I_I L1_PUTX_old 0 <--
|
||||
I_I Ack 0 <--
|
||||
I_I Ack_all 681
|
||||
I_I L1_GET_INSTR [0 ] 0
|
||||
I_I L1_GETS [0 ] 0
|
||||
I_I L1_GETX [0 ] 0
|
||||
I_I L1_UPGRADE [0 ] 0
|
||||
I_I L1_PUTX [0 ] 0
|
||||
I_I L1_PUTX_old [0 ] 0
|
||||
I_I Ack [0 ] 0
|
||||
I_I Ack_all [681 ] 681
|
||||
|
||||
S_I L1_GET_INSTR 0 <--
|
||||
S_I L1_GETS 0 <--
|
||||
S_I L1_GETX 0 <--
|
||||
S_I L1_UPGRADE 0 <--
|
||||
S_I L1_PUTX 0 <--
|
||||
S_I L1_PUTX_old 0 <--
|
||||
S_I Ack 0 <--
|
||||
S_I Ack_all 0 <--
|
||||
S_I MEM_Inv 0 <--
|
||||
S_I L1_GET_INSTR [0 ] 0
|
||||
S_I L1_GETS [0 ] 0
|
||||
S_I L1_GETX [0 ] 0
|
||||
S_I L1_UPGRADE [0 ] 0
|
||||
S_I L1_PUTX [0 ] 0
|
||||
S_I L1_PUTX_old [0 ] 0
|
||||
S_I Ack [0 ] 0
|
||||
S_I Ack_all [0 ] 0
|
||||
S_I MEM_Inv [0 ] 0
|
||||
|
||||
ISS L1_GET_INSTR 0 <--
|
||||
ISS L1_GETS 0 <--
|
||||
ISS L1_GETX 0 <--
|
||||
ISS L1_PUTX 0 <--
|
||||
ISS L1_PUTX_old 0 <--
|
||||
ISS L2_Replacement 0 <--
|
||||
ISS L2_Replacement_clean 0 <--
|
||||
ISS Mem_Data 570
|
||||
ISS MEM_Inv 0 <--
|
||||
ISS L1_GET_INSTR [0 ] 0
|
||||
ISS L1_GETS [0 ] 0
|
||||
ISS L1_GETX [0 ] 0
|
||||
ISS L1_PUTX [0 ] 0
|
||||
ISS L1_PUTX_old [0 ] 0
|
||||
ISS L2_Replacement [0 ] 0
|
||||
ISS L2_Replacement_clean [0 ] 0
|
||||
ISS Mem_Data [570 ] 570
|
||||
ISS MEM_Inv [0 ] 0
|
||||
|
||||
IS L1_GET_INSTR 0 <--
|
||||
IS L1_GETS 0 <--
|
||||
IS L1_GETX 0 <--
|
||||
IS L1_PUTX 0 <--
|
||||
IS L1_PUTX_old 0 <--
|
||||
IS L2_Replacement 0 <--
|
||||
IS L2_Replacement_clean 0 <--
|
||||
IS Mem_Data 686
|
||||
IS MEM_Inv 0 <--
|
||||
IS L1_GET_INSTR [0 ] 0
|
||||
IS L1_GETS [0 ] 0
|
||||
IS L1_GETX [0 ] 0
|
||||
IS L1_PUTX [0 ] 0
|
||||
IS L1_PUTX_old [0 ] 0
|
||||
IS L2_Replacement [0 ] 0
|
||||
IS L2_Replacement_clean [0 ] 0
|
||||
IS Mem_Data [686 ] 686
|
||||
IS MEM_Inv [0 ] 0
|
||||
|
||||
IM L1_GET_INSTR 0 <--
|
||||
IM L1_GETS 0 <--
|
||||
IM L1_GETX 0 <--
|
||||
IM L1_PUTX 0 <--
|
||||
IM L1_PUTX_old 0 <--
|
||||
IM L2_Replacement 0 <--
|
||||
IM L2_Replacement_clean 0 <--
|
||||
IM Mem_Data 204
|
||||
IM MEM_Inv 0 <--
|
||||
IM L1_GET_INSTR [0 ] 0
|
||||
IM L1_GETS [0 ] 0
|
||||
IM L1_GETX [0 ] 0
|
||||
IM L1_PUTX [0 ] 0
|
||||
IM L1_PUTX_old [0 ] 0
|
||||
IM L2_Replacement [0 ] 0
|
||||
IM L2_Replacement_clean [0 ] 0
|
||||
IM Mem_Data [204 ] 204
|
||||
IM MEM_Inv [0 ] 0
|
||||
|
||||
SS_MB L1_GET_INSTR 0 <--
|
||||
SS_MB L1_GETS 0 <--
|
||||
SS_MB L1_GETX 0 <--
|
||||
SS_MB L1_UPGRADE 0 <--
|
||||
SS_MB L1_PUTX 0 <--
|
||||
SS_MB L1_PUTX_old 0 <--
|
||||
SS_MB L2_Replacement 0 <--
|
||||
SS_MB L2_Replacement_clean 0 <--
|
||||
SS_MB Unblock_Cancel 0 <--
|
||||
SS_MB Exclusive_Unblock 0 <--
|
||||
SS_MB MEM_Inv 0 <--
|
||||
SS_MB L1_GET_INSTR [0 ] 0
|
||||
SS_MB L1_GETS [0 ] 0
|
||||
SS_MB L1_GETX [0 ] 0
|
||||
SS_MB L1_UPGRADE [0 ] 0
|
||||
SS_MB L1_PUTX [0 ] 0
|
||||
SS_MB L1_PUTX_old [0 ] 0
|
||||
SS_MB L2_Replacement [0 ] 0
|
||||
SS_MB L2_Replacement_clean [0 ] 0
|
||||
SS_MB Unblock_Cancel [0 ] 0
|
||||
SS_MB Exclusive_Unblock [0 ] 0
|
||||
SS_MB MEM_Inv [0 ] 0
|
||||
|
||||
MT_MB L1_GET_INSTR 0 <--
|
||||
MT_MB L1_GETS 0 <--
|
||||
MT_MB L1_GETX 0 <--
|
||||
MT_MB L1_UPGRADE 0 <--
|
||||
MT_MB L1_PUTX 0 <--
|
||||
MT_MB L1_PUTX_old 0 <--
|
||||
MT_MB L2_Replacement 0 <--
|
||||
MT_MB L2_Replacement_clean 0 <--
|
||||
MT_MB Unblock_Cancel 0 <--
|
||||
MT_MB Exclusive_Unblock 799
|
||||
MT_MB MEM_Inv 0 <--
|
||||
MT_MB L1_GET_INSTR [0 ] 0
|
||||
MT_MB L1_GETS [0 ] 0
|
||||
MT_MB L1_GETX [0 ] 0
|
||||
MT_MB L1_UPGRADE [0 ] 0
|
||||
MT_MB L1_PUTX [0 ] 0
|
||||
MT_MB L1_PUTX_old [0 ] 0
|
||||
MT_MB L2_Replacement [0 ] 0
|
||||
MT_MB L2_Replacement_clean [0 ] 0
|
||||
MT_MB Unblock_Cancel [0 ] 0
|
||||
MT_MB Exclusive_Unblock [799 ] 799
|
||||
MT_MB MEM_Inv [0 ] 0
|
||||
|
||||
M_MB L1_GET_INSTR 0 <--
|
||||
M_MB L1_GETS 0 <--
|
||||
M_MB L1_GETX 0 <--
|
||||
M_MB L1_UPGRADE 0 <--
|
||||
M_MB L1_PUTX 0 <--
|
||||
M_MB L1_PUTX_old 0 <--
|
||||
M_MB L2_Replacement 0 <--
|
||||
M_MB L2_Replacement_clean 0 <--
|
||||
M_MB Exclusive_Unblock 0 <--
|
||||
M_MB MEM_Inv 0 <--
|
||||
M_MB L1_GET_INSTR [0 ] 0
|
||||
M_MB L1_GETS [0 ] 0
|
||||
M_MB L1_GETX [0 ] 0
|
||||
M_MB L1_UPGRADE [0 ] 0
|
||||
M_MB L1_PUTX [0 ] 0
|
||||
M_MB L1_PUTX_old [0 ] 0
|
||||
M_MB L2_Replacement [0 ] 0
|
||||
M_MB L2_Replacement_clean [0 ] 0
|
||||
M_MB Exclusive_Unblock [0 ] 0
|
||||
M_MB MEM_Inv [0 ] 0
|
||||
|
||||
MT_IIB L1_GET_INSTR 0 <--
|
||||
MT_IIB L1_GETS 0 <--
|
||||
MT_IIB L1_GETX 0 <--
|
||||
MT_IIB L1_UPGRADE 0 <--
|
||||
MT_IIB L1_PUTX 0 <--
|
||||
MT_IIB L1_PUTX_old 0 <--
|
||||
MT_IIB L2_Replacement 0 <--
|
||||
MT_IIB L2_Replacement_clean 0 <--
|
||||
MT_IIB WB_Data 0 <--
|
||||
MT_IIB WB_Data_clean 0 <--
|
||||
MT_IIB Unblock 0 <--
|
||||
MT_IIB MEM_Inv 0 <--
|
||||
MT_IIB L1_GET_INSTR [0 ] 0
|
||||
MT_IIB L1_GETS [0 ] 0
|
||||
MT_IIB L1_GETX [0 ] 0
|
||||
MT_IIB L1_UPGRADE [0 ] 0
|
||||
MT_IIB L1_PUTX [0 ] 0
|
||||
MT_IIB L1_PUTX_old [0 ] 0
|
||||
MT_IIB L2_Replacement [0 ] 0
|
||||
MT_IIB L2_Replacement_clean [0 ] 0
|
||||
MT_IIB WB_Data [0 ] 0
|
||||
MT_IIB WB_Data_clean [0 ] 0
|
||||
MT_IIB Unblock [0 ] 0
|
||||
MT_IIB MEM_Inv [0 ] 0
|
||||
|
||||
MT_IB L1_GET_INSTR 0 <--
|
||||
MT_IB L1_GETS 0 <--
|
||||
MT_IB L1_GETX 0 <--
|
||||
MT_IB L1_UPGRADE 0 <--
|
||||
MT_IB L1_PUTX 0 <--
|
||||
MT_IB L1_PUTX_old 0 <--
|
||||
MT_IB L2_Replacement 0 <--
|
||||
MT_IB L2_Replacement_clean 0 <--
|
||||
MT_IB WB_Data 0 <--
|
||||
MT_IB WB_Data_clean 0 <--
|
||||
MT_IB Unblock_Cancel 0 <--
|
||||
MT_IB MEM_Inv 0 <--
|
||||
MT_IB L1_GET_INSTR [0 ] 0
|
||||
MT_IB L1_GETS [0 ] 0
|
||||
MT_IB L1_GETX [0 ] 0
|
||||
MT_IB L1_UPGRADE [0 ] 0
|
||||
MT_IB L1_PUTX [0 ] 0
|
||||
MT_IB L1_PUTX_old [0 ] 0
|
||||
MT_IB L2_Replacement [0 ] 0
|
||||
MT_IB L2_Replacement_clean [0 ] 0
|
||||
MT_IB WB_Data [0 ] 0
|
||||
MT_IB WB_Data_clean [0 ] 0
|
||||
MT_IB Unblock_Cancel [0 ] 0
|
||||
MT_IB MEM_Inv [0 ] 0
|
||||
|
||||
MT_SB L1_GET_INSTR 0 <--
|
||||
MT_SB L1_GETS 0 <--
|
||||
MT_SB L1_GETX 0 <--
|
||||
MT_SB L1_UPGRADE 0 <--
|
||||
MT_SB L1_PUTX 0 <--
|
||||
MT_SB L1_PUTX_old 0 <--
|
||||
MT_SB L2_Replacement 0 <--
|
||||
MT_SB L2_Replacement_clean 0 <--
|
||||
MT_SB Unblock 0 <--
|
||||
MT_SB MEM_Inv 0 <--
|
||||
MT_SB L1_GET_INSTR [0 ] 0
|
||||
MT_SB L1_GETS [0 ] 0
|
||||
MT_SB L1_GETX [0 ] 0
|
||||
MT_SB L1_UPGRADE [0 ] 0
|
||||
MT_SB L1_PUTX [0 ] 0
|
||||
MT_SB L1_PUTX_old [0 ] 0
|
||||
MT_SB L2_Replacement [0 ] 0
|
||||
MT_SB L2_Replacement_clean [0 ] 0
|
||||
MT_SB Unblock [0 ] 0
|
||||
MT_SB MEM_Inv [0 ] 0
|
||||
|
||||
Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer:
|
||||
Memory controller: system.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 1737
|
||||
memory_reads: 1460
|
||||
memory_writes: 277
|
||||
|
|
@ -551,67 +556,66 @@ Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer:
|
|||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 92 21 45 54 57 174 48 18 19 22 35 37 56 59 44 36 41 24 22 28 32 48 122 36 32 25 35 96 114 185 19 61
|
||||
|
||||
--- Directory 0 ---
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
Fetch 1460
|
||||
Data 277
|
||||
Memory_Data 1460
|
||||
Memory_Ack 277
|
||||
DMA_READ 0
|
||||
DMA_WRITE 0
|
||||
CleanReplacement 1175
|
||||
Fetch [1460 ] 1460
|
||||
Data [277 ] 277
|
||||
Memory_Data [1460 ] 1460
|
||||
Memory_Ack [277 ] 277
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
CleanReplacement [1175 ] 1175
|
||||
|
||||
- Transitions -
|
||||
I Fetch 1460
|
||||
I DMA_READ 0 <--
|
||||
I DMA_WRITE 0 <--
|
||||
I Fetch [1460 ] 1460
|
||||
I DMA_READ [0 ] 0
|
||||
I DMA_WRITE [0 ] 0
|
||||
|
||||
ID Fetch 0 <--
|
||||
ID Data 0 <--
|
||||
ID Memory_Data 0 <--
|
||||
ID DMA_READ 0 <--
|
||||
ID DMA_WRITE 0 <--
|
||||
ID Fetch [0 ] 0
|
||||
ID Data [0 ] 0
|
||||
ID Memory_Data [0 ] 0
|
||||
ID DMA_READ [0 ] 0
|
||||
ID DMA_WRITE [0 ] 0
|
||||
|
||||
ID_W Fetch 0 <--
|
||||
ID_W Data 0 <--
|
||||
ID_W Memory_Ack 0 <--
|
||||
ID_W DMA_READ 0 <--
|
||||
ID_W DMA_WRITE 0 <--
|
||||
ID_W Fetch [0 ] 0
|
||||
ID_W Data [0 ] 0
|
||||
ID_W Memory_Ack [0 ] 0
|
||||
ID_W DMA_READ [0 ] 0
|
||||
ID_W DMA_WRITE [0 ] 0
|
||||
|
||||
M Data 277
|
||||
M DMA_READ 0 <--
|
||||
M DMA_WRITE 0 <--
|
||||
M CleanReplacement 1175
|
||||
M Data [277 ] 277
|
||||
M DMA_READ [0 ] 0
|
||||
M DMA_WRITE [0 ] 0
|
||||
M CleanReplacement [1175 ] 1175
|
||||
|
||||
IM Fetch 0 <--
|
||||
IM Data 0 <--
|
||||
IM Memory_Data 1460
|
||||
IM DMA_READ 0 <--
|
||||
IM DMA_WRITE 0 <--
|
||||
IM Fetch [0 ] 0
|
||||
IM Data [0 ] 0
|
||||
IM Memory_Data [1460 ] 1460
|
||||
IM DMA_READ [0 ] 0
|
||||
IM DMA_WRITE [0 ] 0
|
||||
|
||||
MI Fetch 0 <--
|
||||
MI Data 0 <--
|
||||
MI Memory_Ack 277
|
||||
MI DMA_READ 0 <--
|
||||
MI DMA_WRITE 0 <--
|
||||
MI Fetch [0 ] 0
|
||||
MI Data [0 ] 0
|
||||
MI Memory_Ack [277 ] 277
|
||||
MI DMA_READ [0 ] 0
|
||||
MI DMA_WRITE [0 ] 0
|
||||
|
||||
M_DRD Data 0 <--
|
||||
M_DRD DMA_READ 0 <--
|
||||
M_DRD DMA_WRITE 0 <--
|
||||
M_DRD Data [0 ] 0
|
||||
M_DRD DMA_READ [0 ] 0
|
||||
M_DRD DMA_WRITE [0 ] 0
|
||||
|
||||
M_DRDI Fetch 0 <--
|
||||
M_DRDI Data 0 <--
|
||||
M_DRDI Memory_Ack 0 <--
|
||||
M_DRDI DMA_READ 0 <--
|
||||
M_DRDI DMA_WRITE 0 <--
|
||||
M_DRDI Fetch [0 ] 0
|
||||
M_DRDI Data [0 ] 0
|
||||
M_DRDI Memory_Ack [0 ] 0
|
||||
M_DRDI DMA_READ [0 ] 0
|
||||
M_DRDI DMA_WRITE [0 ] 0
|
||||
|
||||
M_DWR Data 0 <--
|
||||
M_DWR DMA_READ 0 <--
|
||||
M_DWR DMA_WRITE 0 <--
|
||||
|
||||
M_DWRI Fetch 0 <--
|
||||
M_DWRI Data 0 <--
|
||||
M_DWRI Memory_Ack 0 <--
|
||||
M_DWRI DMA_READ 0 <--
|
||||
M_DWRI DMA_WRITE 0 <--
|
||||
M_DWR Data [0 ] 0
|
||||
M_DWR DMA_READ [0 ] 0
|
||||
M_DWR DMA_WRITE [0 ] 0
|
||||
|
||||
M_DWRI Fetch [0 ] 0
|
||||
M_DWRI Data [0 ] 0
|
||||
M_DWRI Memory_Ack [0 ] 0
|
||||
M_DWRI DMA_READ [0 ] 0
|
||||
M_DWRI DMA_WRITE
|
||||
|
|
@ -5,10 +5,10 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 28 2010 13:54:58
|
||||
M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
|
||||
M5 started Jan 28 2010 13:57:42
|
||||
M5 executing on svvint03
|
||||
M5 compiled Aug 5 2010 10:22:52
|
||||
M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip
|
||||
M5 started Aug 5 2010 10:23:42
|
||||
M5 executing on svvint09
|
||||
command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 8106 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 215916 # Number of bytes of host memory used
|
||||
host_seconds 0.79 # Real time elapsed on the host
|
||||
host_tick_rate 348501 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 24630 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 212388 # Number of bytes of host memory used
|
||||
host_seconds 0.26 # Real time elapsed on the host
|
||||
host_tick_rate 1058851 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_insts 6404 # Number of instructions simulated
|
||||
sim_seconds 0.000275 # Number of seconds simulated
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ dummy=0
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu physmem ruby
|
||||
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
|
||||
|
|
@ -32,8 +32,8 @@ progress_interval=0
|
|||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
|
||||
icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
|
||||
dcache_port=system.l1_cntrl0.sequencer.port[1]
|
||||
icache_port=system.l1_cntrl0.sequencer.port[0]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
|
|
@ -54,7 +54,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -65,162 +65,27 @@ simpoint=0
|
|||
system=system
|
||||
uid=100
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
output_filename=none
|
||||
protocol_trace=false
|
||||
start_time=1
|
||||
verbosity_string=none
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=true
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
link_latency=1
|
||||
number_of_virtual_networks=10
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
|
||||
num_int_nodes=4
|
||||
print_config=false
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links0.ext_node
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
buffer_size=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links1.ext_node
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node]
|
||||
type=L2Cache_Controller
|
||||
children=L2cacheMemory
|
||||
L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
|
||||
buffer_size=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
response_latency=2
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=15
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
||||
[system.ruby.network.topology.ext_links2]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links2.ext_node
|
||||
int_node=2
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node]
|
||||
[system.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
directory=system.ruby.network.topology.ext_links2.ext_node.directory
|
||||
directory=system.dir_cntrl0.directory
|
||||
directory_latency=6
|
||||
memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer
|
||||
memBuffer=system.dir_cntrl0.memBuffer
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.directory]
|
||||
[system.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=6
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.memBuffer]
|
||||
[system.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
|
|
@ -241,6 +106,146 @@ refresh_period=1560
|
|||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
|
||||
L1IcacheMemory=system.l1_cntrl0.sequencer.icache
|
||||
buffer_size=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
sequencer=system.l1_cntrl0.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.l1_cntrl0.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.l1_cntrl0.sequencer.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l2_cntrl0]
|
||||
type=L2Cache_Controller
|
||||
children=L2cacheMemory
|
||||
L2cacheMemory=system.l2_cntrl0.L2cacheMemory
|
||||
buffer_size=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
response_latency=2
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l2_cntrl0.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=15
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
start_index_bit=6
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.l1_cntrl0.sequencer.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
no_mem_vec=false
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
output_filename=none
|
||||
protocol_trace=false
|
||||
start_time=1
|
||||
verbosity_string=none
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=false
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
link_latency=1
|
||||
number_of_virtual_networks=10
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
|
||||
name=Crossbar
|
||||
num_int_nodes=4
|
||||
print_config=false
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
bw_multiplier=64
|
||||
ext_node=system.l1_cntrl0
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
bw_multiplier=64
|
||||
ext_node=system.l2_cntrl0
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links2]
|
||||
type=ExtLink
|
||||
bw_multiplier=64
|
||||
ext_node=system.dir_cntrl0
|
||||
int_node=2
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links0]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -5,10 +5,10 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 28 2010 14:49:51
|
||||
M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
|
||||
M5 started Jan 28 2010 15:08:13
|
||||
M5 executing on svvint05
|
||||
M5 compiled Aug 5 2010 10:34:54
|
||||
M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip
|
||||
M5 started Aug 5 2010 10:35:39
|
||||
M5 executing on svvint09
|
||||
command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 11859 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 216064 # Number of bytes of host memory used
|
||||
host_seconds 0.55 # Real time elapsed on the host
|
||||
host_tick_rate 407003 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 23717 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 212528 # Number of bytes of host memory used
|
||||
host_seconds 0.27 # Real time elapsed on the host
|
||||
host_tick_rate 829037 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_insts 6404 # Number of instructions simulated
|
||||
sim_seconds 0.000224 # Number of seconds simulated
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ dummy=0
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu physmem ruby
|
||||
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
|
||||
|
|
@ -32,8 +32,8 @@ progress_interval=0
|
|||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
|
||||
icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
|
||||
dcache_port=system.l1_cntrl0.sequencer.port[1]
|
||||
icache_port=system.l1_cntrl0.sequencer.port[0]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
|
|
@ -54,7 +54,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -65,172 +65,30 @@ simpoint=0
|
|||
system=system
|
||||
uid=100
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
output_filename=none
|
||||
protocol_trace=false
|
||||
start_time=1
|
||||
verbosity_string=none
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=true
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
link_latency=1
|
||||
number_of_virtual_networks=10
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
|
||||
num_int_nodes=4
|
||||
print_config=false
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links0.ext_node
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
N_tokens=2
|
||||
buffer_size=0
|
||||
dynamic_timeout_enabled=true
|
||||
fixed_timeout_latency=300
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links1.ext_node
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node]
|
||||
type=L2Cache_Controller
|
||||
children=L2cacheMemory
|
||||
L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
|
||||
N_tokens=2
|
||||
buffer_size=0
|
||||
filtering_enabled=true
|
||||
l2_request_latency=10
|
||||
l2_response_latency=10
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=15
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
||||
[system.ruby.network.topology.ext_links2]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links2.ext_node
|
||||
int_node=2
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node]
|
||||
[system.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
directory=system.ruby.network.topology.ext_links2.ext_node.directory
|
||||
directory_latency=6
|
||||
directory=system.dir_cntrl0.directory
|
||||
directory_latency=5
|
||||
distributed_persistent=true
|
||||
fixed_timeout_latency=300
|
||||
fixed_timeout_latency=100
|
||||
l2_select_num_bits=0
|
||||
memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer
|
||||
memBuffer=system.dir_cntrl0.memBuffer
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.directory]
|
||||
[system.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=6
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.memBuffer]
|
||||
[system.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
|
|
@ -251,6 +109,154 @@ refresh_period=1560
|
|||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
|
||||
L1IcacheMemory=system.l1_cntrl0.sequencer.icache
|
||||
N_tokens=2
|
||||
buffer_size=0
|
||||
dynamic_timeout_enabled=true
|
||||
fixed_timeout_latency=300
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
sequencer=system.l1_cntrl0.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.l1_cntrl0.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.l1_cntrl0.sequencer.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l2_cntrl0]
|
||||
type=L2Cache_Controller
|
||||
children=L2cacheMemory
|
||||
L2cacheMemory=system.l2_cntrl0.L2cacheMemory
|
||||
N_tokens=2
|
||||
buffer_size=0
|
||||
filtering_enabled=true
|
||||
l2_request_latency=5
|
||||
l2_response_latency=5
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l2_cntrl0.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=10
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
start_index_bit=0
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.l1_cntrl0.sequencer.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
no_mem_vec=false
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
output_filename=none
|
||||
protocol_trace=false
|
||||
start_time=1
|
||||
verbosity_string=none
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=false
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
link_latency=1
|
||||
number_of_virtual_networks=10
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
|
||||
name=Crossbar
|
||||
num_int_nodes=4
|
||||
print_config=false
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
bw_multiplier=64
|
||||
ext_node=system.l1_cntrl0
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
bw_multiplier=64
|
||||
ext_node=system.l2_cntrl0
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links2]
|
||||
type=ExtLink
|
||||
bw_multiplier=64
|
||||
ext_node=system.dir_cntrl0
|
||||
int_node=2
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links0]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -5,13 +5,13 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 28 2010 15:54:34
|
||||
M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
|
||||
M5 started Jan 28 2010 15:55:45
|
||||
M5 executing on svvint04
|
||||
M5 compiled Aug 5 2010 10:41:36
|
||||
M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip
|
||||
M5 started Aug 5 2010 10:42:35
|
||||
M5 executing on svvint09
|
||||
command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 236654 because target called exit()
|
||||
Exiting @ tick 243131 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 35577 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 215884 # Number of bytes of host memory used
|
||||
host_seconds 0.18 # Real time elapsed on the host
|
||||
host_tick_rate 1314701 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 45740 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 212336 # Number of bytes of host memory used
|
||||
host_seconds 0.14 # Real time elapsed on the host
|
||||
host_tick_rate 1736538 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_insts 6404 # Number of instructions simulated
|
||||
sim_seconds 0.000237 # Number of seconds simulated
|
||||
sim_ticks 236654 # Number of ticks simulated
|
||||
sim_seconds 0.000243 # Number of seconds simulated
|
||||
sim_ticks 243131 # Number of ticks simulated
|
||||
system.cpu.dtb.data_accesses 2060 # DTB accesses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_hits 2050 # DTB hits
|
||||
|
|
@ -42,7 +42,7 @@ system.cpu.itb.write_acv 0 # DT
|
|||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 236654 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 243131 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 6404 # Number of instructions executed
|
||||
system.cpu.num_refs 2060 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ dummy=0
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu physmem ruby
|
||||
children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
|
||||
|
|
@ -32,8 +32,8 @@ progress_interval=0
|
|||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
|
||||
icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
|
||||
dcache_port=system.l1_cntrl0.sequencer.port[1]
|
||||
icache_port=system.l1_cntrl0.sequencer.port[0]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
|
|
@ -65,142 +65,29 @@ simpoint=0
|
|||
system=system
|
||||
uid=100
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
output_filename=none
|
||||
protocol_trace=false
|
||||
start_time=1
|
||||
verbosity_string=none
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=true
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
link_latency=1
|
||||
number_of_virtual_networks=10
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 int_links0 int_links1
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
|
||||
num_int_nodes=3
|
||||
print_config=false
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links0.ext_node
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=L2cacheMemory sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
L2cacheMemory=system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory
|
||||
buffer_size=0
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=15
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links1.ext_node
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node]
|
||||
[system.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
children=directory memBuffer probeFilter
|
||||
buffer_size=0
|
||||
directory=system.ruby.network.topology.ext_links1.ext_node.directory
|
||||
memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer
|
||||
memory_controller_latency=12
|
||||
directory=system.dir_cntrl0.directory
|
||||
memBuffer=system.dir_cntrl0.memBuffer
|
||||
memory_controller_latency=2
|
||||
number_of_TBEs=256
|
||||
probeFilter=system.dir_cntrl0.probeFilter
|
||||
probe_filter_enabled=false
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.directory]
|
||||
[system.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=6
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.memBuffer]
|
||||
[system.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
|
|
@ -221,6 +108,136 @@ refresh_period=1560
|
|||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.dir_cntrl0.probeFilter]
|
||||
type=RubyCache
|
||||
assoc=4
|
||||
latency=1
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=1024
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0]
|
||||
type=L1Cache_Controller
|
||||
children=L2cacheMemory sequencer
|
||||
L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
|
||||
L1IcacheMemory=system.l1_cntrl0.sequencer.icache
|
||||
L2cacheMemory=system.l1_cntrl0.L2cacheMemory
|
||||
buffer_size=0
|
||||
cache_response_latency=10
|
||||
issue_latency=2
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.l1_cntrl0.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=10
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.l1_cntrl0.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.l1_cntrl0.sequencer.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.l1_cntrl0.sequencer.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
no_mem_vec=false
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
output_filename=none
|
||||
protocol_trace=false
|
||||
start_time=1
|
||||
verbosity_string=none
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=false
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
link_latency=1
|
||||
number_of_virtual_networks=10
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 int_links0 int_links1
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
|
||||
name=Crossbar
|
||||
num_int_nodes=3
|
||||
print_config=false
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
bw_multiplier=64
|
||||
ext_node=system.l1_cntrl0
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
bw_multiplier=64
|
||||
ext_node=system.dir_cntrl0
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links0]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,3 +1,5 @@
|
|||
Redirecting stdout to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
|
||||
Redirecting stderr to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -5,13 +7,13 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 28 2010 11:30:01
|
||||
M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
|
||||
M5 started Jan 28 2010 11:55:11
|
||||
M5 executing on svvint06
|
||||
M5 compiled Aug 5 2010 11:09:13
|
||||
M5 revision c5f5b5533e96 7536 default qtip tip brad/regress_updates
|
||||
M5 started Aug 5 2010 11:09:30
|
||||
M5 executing on SC2B0617
|
||||
command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 215528 because target called exit()
|
||||
Exiting @ tick 207970 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 45742 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 213100 # Number of bytes of host memory used
|
||||
host_seconds 0.14 # Real time elapsed on the host
|
||||
host_tick_rate 1539442 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 31390 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 211076 # Number of bytes of host memory used
|
||||
host_seconds 0.20 # Real time elapsed on the host
|
||||
host_tick_rate 1018487 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_insts 6404 # Number of instructions simulated
|
||||
sim_seconds 0.000216 # Number of seconds simulated
|
||||
sim_ticks 215528 # Number of ticks simulated
|
||||
sim_seconds 0.000208 # Number of seconds simulated
|
||||
sim_ticks 207970 # Number of ticks simulated
|
||||
system.cpu.dtb.data_accesses 2060 # DTB accesses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_hits 2050 # DTB hits
|
||||
|
|
@ -42,7 +42,7 @@ system.cpu.itb.write_acv 0 # DT
|
|||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 215528 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 207970 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 6404 # Number of instructions executed
|
||||
system.cpu.num_refs 2060 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ dummy=0
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu physmem ruby
|
||||
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
|
||||
|
|
@ -32,8 +32,8 @@ progress_interval=0
|
|||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
|
||||
icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
|
||||
dcache_port=system.l1_cntrl0.sequencer.port[1]
|
||||
icache_port=system.l1_cntrl0.sequencer.port[0]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
|
|
@ -54,7 +54,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
|
||||
executable=tests/test-progs/hello/bin/alpha/tru64/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -65,166 +65,28 @@ simpoint=0
|
|||
system=system
|
||||
uid=100
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
output_filename=none
|
||||
protocol_trace=false
|
||||
start_time=1
|
||||
verbosity_string=none
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=true
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
link_latency=1
|
||||
number_of_virtual_networks=10
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
|
||||
num_int_nodes=4
|
||||
print_config=false
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links0.ext_node
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
buffer_size=0
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links1.ext_node
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node]
|
||||
type=L2Cache_Controller
|
||||
children=L2cacheMemory
|
||||
L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
|
||||
buffer_size=0
|
||||
l2_request_latency=2
|
||||
l2_response_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
to_l1_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=15
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
||||
[system.ruby.network.topology.ext_links2]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links2.ext_node
|
||||
int_node=2
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node]
|
||||
[system.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
directory=system.ruby.network.topology.ext_links2.ext_node.directory
|
||||
directory=system.dir_cntrl0.directory
|
||||
directory_latency=6
|
||||
memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer
|
||||
memBuffer=system.dir_cntrl0.memBuffer
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
to_mem_ctrl_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.directory]
|
||||
[system.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=6
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.memBuffer]
|
||||
[system.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
|
|
@ -245,6 +107,149 @@ refresh_period=1560
|
|||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
|
||||
L1IcacheMemory=system.l1_cntrl0.sequencer.icache
|
||||
buffer_size=0
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.l1_cntrl0.sequencer
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.l1_cntrl0.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.l1_cntrl0.sequencer.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l2_cntrl0]
|
||||
type=L2Cache_Controller
|
||||
children=L2cacheMemory
|
||||
L2cacheMemory=system.l2_cntrl0.L2cacheMemory
|
||||
buffer_size=0
|
||||
l2_request_latency=2
|
||||
l2_response_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
to_l1_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l2_cntrl0.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=15
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
start_index_bit=6
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.l1_cntrl0.sequencer.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
no_mem_vec=false
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
output_filename=none
|
||||
protocol_trace=false
|
||||
start_time=1
|
||||
verbosity_string=none
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=false
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
link_latency=1
|
||||
number_of_virtual_networks=10
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
|
||||
name=Crossbar
|
||||
num_int_nodes=4
|
||||
print_config=false
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
bw_multiplier=64
|
||||
ext_node=system.l1_cntrl0
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
bw_multiplier=64
|
||||
ext_node=system.l2_cntrl0
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links2]
|
||||
type=ExtLink
|
||||
bw_multiplier=64
|
||||
ext_node=system.dir_cntrl0
|
||||
int_node=2
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links0]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@ RubySystem config:
|
|||
Network Configuration
|
||||
---------------------
|
||||
network: SIMPLE_NETWORK
|
||||
topology:
|
||||
topology: Crossbar
|
||||
|
||||
virtual_net_0: active, unordered
|
||||
virtual_net_1: active, unordered
|
||||
|
|
@ -34,7 +34,7 @@ periodic_stats_period: 1000000
|
|||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Jan/28/2010 13:57:45
|
||||
Real time: Aug/05/2010 10:31:34
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
|
|
@ -43,31 +43,20 @@ Elapsed_time_in_minutes: 0
|
|||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.45
|
||||
Virtual_time_in_minutes: 0.0075
|
||||
Virtual_time_in_hours: 0.000125
|
||||
Virtual_time_in_days: 5.20833e-06
|
||||
Virtual_time_in_seconds: 0.26
|
||||
Virtual_time_in_minutes: 0.00433333
|
||||
Virtual_time_in_hours: 7.22222e-05
|
||||
Virtual_time_in_days: 3.00926e-06
|
||||
|
||||
Ruby_current_time: 103637
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 103637
|
||||
|
||||
mbytes_resident: 33.0938
|
||||
mbytes_total: 33.1016
|
||||
mbytes_resident: 33.5703
|
||||
mbytes_total: 33.5781
|
||||
resident_ratio: 1
|
||||
|
||||
Total_misses: 0
|
||||
total_misses: 0 [ 0 ]
|
||||
user_misses: 0 [ 0 ]
|
||||
supervisor_misses: 0 [ 0 ]
|
||||
|
||||
ruby_cycles_executed: 103638 [ 103638 ]
|
||||
|
||||
transactions_started: 0 [ 0 ]
|
||||
transactions_ended: 0 [ 0 ]
|
||||
cycles_per_transaction: 0 [ 0 ]
|
||||
misses_per_transaction: 0 [ 0 ]
|
||||
|
||||
ruby_cycles_executed: [ 103638 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
|
|
@ -82,9 +71,23 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 |
|
|||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 2 max: 223 count: 3294 average: 30.4624 | standard deviation: 61.2716 | 0 2722 0 0 0 0 0 0 0 25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 68 156 96 122 80 3 4 5 3 3 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_1: [binsize: 1 max: 181 count: 2585 average: 21.5791 | standard deviation: 52.0174 | 0 0 0 2285 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 0 70 0 67 0 59 0 54 0 1 1 1 0 3 0 0 0 3 ]
|
||||
miss_latency_2: [binsize: 2 max: 217 count: 415 average: 79.6169 | standard deviation: 81.8661 | 0 211 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 58 25 52 15 1 2 2 2 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_3: [binsize: 2 max: 223 count: 294 average: 39.1837 | standard deviation: 68.3072 | 0 226 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 28 4 11 11 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 1 max: 181 count: 2585 average: 21.5791 | standard deviation: 52.0174 | 0 0 0 2285 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 0 70 0 67 0 59 0 54 0 1 1 1 0 3 0 0 0 3 ]
|
||||
miss_latency_LD: [binsize: 2 max: 217 count: 415 average: 79.6169 | standard deviation: 81.8661 | 0 211 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 58 25 52 15 1 2 2 2 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 2 max: 223 count: 294 average: 39.1837 | standard deviation: 68.3072 | 0 226 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 28 4 11 11 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_NULL: [binsize: 2 max: 223 count: 3294 average: 30.4624 | standard deviation: 61.2716 | 0 2722 0 0 0 0 0 0 0 25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 68 156 96 122 80 3 4 5 3 3 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_wCC_Times: 0
|
||||
miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_dir_Times: 0
|
||||
miss_latency_IFETCH_NULL: [binsize: 1 max: 181 count: 2585 average: 21.5791 | standard deviation: 52.0174 | 0 0 0 2285 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 0 70 0 67 0 59 0 54 0 1 1 1 0 3 0 0 0 3 ]
|
||||
miss_latency_LD_NULL: [binsize: 2 max: 217 count: 415 average: 79.6169 | standard deviation: 81.8661 | 0 211 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 58 25 52 15 1 2 2 2 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_NULL: [binsize: 2 max: 223 count: 294 average: 39.1837 | standard deviation: 68.3072 | 0 226 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 28 4 11 11 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
|
|
@ -116,8 +119,8 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 7156
|
||||
page_faults: 2112
|
||||
page_reclaims: 7325
|
||||
page_faults: 2071
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
|
|
@ -125,6 +128,14 @@ block_outputs: 0
|
|||
Network Stats
|
||||
-------------
|
||||
|
||||
total_msg_count_Control: 3357 26856
|
||||
total_msg_count_Request_Control: 1293 10344
|
||||
total_msg_count_Response_Data: 3666 263952
|
||||
total_msg_count_Response_Control: 5220 41760
|
||||
total_msg_count_Writeback_Data: 327 23544
|
||||
total_msg_count_Writeback_Control: 231 1848
|
||||
total_msgs: 14094 total_bytes: 368304
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 0.0891754
|
||||
|
|
@ -186,352 +197,346 @@ links_utilized_percent_switch_3: 0.246791
|
|||
outgoing_messages_switch_3_link_2_Response_Data: 103 7416 [ 0 103 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Response_Control: 436 3488 [ 0 436 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan
|
||||
Cache Stats: system.l1_cntrl0.sequencer.icache
|
||||
system.l1_cntrl0.sequencer.icache_total_misses: 0
|
||||
system.l1_cntrl0.sequencer.icache_total_demand_misses: 0
|
||||
system.l1_cntrl0.sequencer.icache_total_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: nan
|
||||
Cache Stats: system.l1_cntrl0.sequencer.dcache
|
||||
system.l1_cntrl0.sequencer.dcache_total_misses: 0
|
||||
system.l1_cntrl0.sequencer.dcache_total_demand_misses: 0
|
||||
system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
--- L1Cache 0 ---
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load 415
|
||||
Ifetch 2585
|
||||
Store 294
|
||||
Inv 431
|
||||
L1_Replacement 502
|
||||
Fwd_GETX 0
|
||||
Fwd_GETS 0
|
||||
Fwd_GET_INSTR 0
|
||||
Data 0
|
||||
Data_Exclusive 204
|
||||
DataS_fromL1 0
|
||||
Data_all_Acks 368
|
||||
Ack 0
|
||||
Ack_all 0
|
||||
WB_Ack 124
|
||||
Load [415 ] 415
|
||||
Ifetch [2585 ] 2585
|
||||
Store [294 ] 294
|
||||
Inv [431 ] 431
|
||||
L1_Replacement [502 ] 502
|
||||
Fwd_GETX [0 ] 0
|
||||
Fwd_GETS [0 ] 0
|
||||
Fwd_GET_INSTR [0 ] 0
|
||||
Data [0 ] 0
|
||||
Data_Exclusive [204 ] 204
|
||||
DataS_fromL1 [0 ] 0
|
||||
Data_all_Acks [368 ] 368
|
||||
Ack [0 ] 0
|
||||
Ack_all [0 ] 0
|
||||
WB_Ack [124 ] 124
|
||||
|
||||
- Transitions -
|
||||
NP Load 182
|
||||
NP Ifetch 270
|
||||
NP Store 58
|
||||
NP Inv 162
|
||||
NP L1_Replacement 0 <--
|
||||
NP Load [182 ] 182
|
||||
NP Ifetch [270 ] 270
|
||||
NP Store [58 ] 58
|
||||
NP Inv [162 ] 162
|
||||
NP L1_Replacement [0 ] 0
|
||||
|
||||
I Load 22
|
||||
I Ifetch 30
|
||||
I Store 10
|
||||
I Inv 0 <--
|
||||
I L1_Replacement 206
|
||||
I Load [22 ] 22
|
||||
I Ifetch [30 ] 30
|
||||
I Store [10 ] 10
|
||||
I Inv [0 ] 0
|
||||
I L1_Replacement [206 ] 206
|
||||
|
||||
S Load 0 <--
|
||||
S Ifetch 2285
|
||||
S Store 0 <--
|
||||
S Inv 124
|
||||
S L1_Replacement 172
|
||||
S Load [0 ] 0
|
||||
S Ifetch [2285 ] 2285
|
||||
S Store [0 ] 0
|
||||
S Inv [124 ] 124
|
||||
S L1_Replacement [172 ] 172
|
||||
|
||||
E Load 140
|
||||
E Ifetch 0 <--
|
||||
E Store 41
|
||||
E Inv 83
|
||||
E L1_Replacement 79
|
||||
E Fwd_GETX 0 <--
|
||||
E Fwd_GETS 0 <--
|
||||
E Fwd_GET_INSTR 0 <--
|
||||
E Load [140 ] 140
|
||||
E Ifetch [0 ] 0
|
||||
E Store [41 ] 41
|
||||
E Inv [83 ] 83
|
||||
E L1_Replacement [79 ] 79
|
||||
E Fwd_GETX [0 ] 0
|
||||
E Fwd_GETS [0 ] 0
|
||||
E Fwd_GET_INSTR [0 ] 0
|
||||
|
||||
M Load 71
|
||||
M Ifetch 0 <--
|
||||
M Store 185
|
||||
M Inv 62
|
||||
M L1_Replacement 45
|
||||
M Fwd_GETX 0 <--
|
||||
M Fwd_GETS 0 <--
|
||||
M Fwd_GET_INSTR 0 <--
|
||||
M Load [71 ] 71
|
||||
M Ifetch [0 ] 0
|
||||
M Store [185 ] 185
|
||||
M Inv [62 ] 62
|
||||
M L1_Replacement [45 ] 45
|
||||
M Fwd_GETX [0 ] 0
|
||||
M Fwd_GETS [0 ] 0
|
||||
M Fwd_GET_INSTR [0 ] 0
|
||||
|
||||
IS Load 0 <--
|
||||
IS Ifetch 0 <--
|
||||
IS Store 0 <--
|
||||
IS Inv 0 <--
|
||||
IS L1_Replacement 0 <--
|
||||
IS Data_Exclusive 204
|
||||
IS DataS_fromL1 0 <--
|
||||
IS Data_all_Acks 300
|
||||
IS Load [0 ] 0
|
||||
IS Ifetch [0 ] 0
|
||||
IS Store [0 ] 0
|
||||
IS Inv [0 ] 0
|
||||
IS L1_Replacement [0 ] 0
|
||||
IS Data_Exclusive [204 ] 204
|
||||
IS DataS_fromL1 [0 ] 0
|
||||
IS Data_all_Acks [300 ] 300
|
||||
|
||||
IM Load 0 <--
|
||||
IM Ifetch 0 <--
|
||||
IM Store 0 <--
|
||||
IM Inv 0 <--
|
||||
IM L1_Replacement 0 <--
|
||||
IM Data 0 <--
|
||||
IM Data_all_Acks 68
|
||||
IM Ack 0 <--
|
||||
IM Load [0 ] 0
|
||||
IM Ifetch [0 ] 0
|
||||
IM Store [0 ] 0
|
||||
IM Inv [0 ] 0
|
||||
IM L1_Replacement [0 ] 0
|
||||
IM Data [0 ] 0
|
||||
IM Data_all_Acks [68 ] 68
|
||||
IM Ack [0 ] 0
|
||||
|
||||
SM Load 0 <--
|
||||
SM Ifetch 0 <--
|
||||
SM Store 0 <--
|
||||
SM Inv 0 <--
|
||||
SM L1_Replacement 0 <--
|
||||
SM Ack 0 <--
|
||||
SM Ack_all 0 <--
|
||||
SM Load [0 ] 0
|
||||
SM Ifetch [0 ] 0
|
||||
SM Store [0 ] 0
|
||||
SM Inv [0 ] 0
|
||||
SM L1_Replacement [0 ] 0
|
||||
SM Ack [0 ] 0
|
||||
SM Ack_all [0 ] 0
|
||||
|
||||
IS_I Load 0 <--
|
||||
IS_I Ifetch 0 <--
|
||||
IS_I Store 0 <--
|
||||
IS_I Inv 0 <--
|
||||
IS_I L1_Replacement 0 <--
|
||||
IS_I Data_Exclusive 0 <--
|
||||
IS_I DataS_fromL1 0 <--
|
||||
IS_I Data_all_Acks 0 <--
|
||||
IS_I Load [0 ] 0
|
||||
IS_I Ifetch [0 ] 0
|
||||
IS_I Store [0 ] 0
|
||||
IS_I Inv [0 ] 0
|
||||
IS_I L1_Replacement [0 ] 0
|
||||
IS_I Data_Exclusive [0 ] 0
|
||||
IS_I DataS_fromL1 [0 ] 0
|
||||
IS_I Data_all_Acks [0 ] 0
|
||||
|
||||
M_I Load 0 <--
|
||||
M_I Ifetch 0 <--
|
||||
M_I Store 0 <--
|
||||
M_I Inv 0 <--
|
||||
M_I L1_Replacement 0 <--
|
||||
M_I Fwd_GETX 0 <--
|
||||
M_I Fwd_GETS 0 <--
|
||||
M_I Fwd_GET_INSTR 0 <--
|
||||
M_I WB_Ack 124
|
||||
M_I Load [0 ] 0
|
||||
M_I Ifetch [0 ] 0
|
||||
M_I Store [0 ] 0
|
||||
M_I Inv [0 ] 0
|
||||
M_I L1_Replacement [0 ] 0
|
||||
M_I Fwd_GETX [0 ] 0
|
||||
M_I Fwd_GETS [0 ] 0
|
||||
M_I Fwd_GET_INSTR [0 ] 0
|
||||
M_I WB_Ack [124 ] 124
|
||||
|
||||
E_I Load 0 <--
|
||||
E_I Ifetch 0 <--
|
||||
E_I Store 0 <--
|
||||
E_I L1_Replacement 0 <--
|
||||
E_I Load [0 ] 0
|
||||
E_I Ifetch [0 ] 0
|
||||
E_I Store [0 ] 0
|
||||
E_I L1_Replacement [0 ] 0
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_misses_per_transaction: nan
|
||||
Cache Stats: system.l2_cntrl0.L2cacheMemory
|
||||
system.l2_cntrl0.L2cacheMemory_total_misses: 0
|
||||
system.l2_cntrl0.L2cacheMemory_total_demand_misses: 0
|
||||
system.l2_cntrl0.L2cacheMemory_total_prefetches: 0
|
||||
system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
|
||||
system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
--- L2Cache 0 ---
|
||||
--- L2Cache ---
|
||||
- Event Counts -
|
||||
L1_GET_INSTR 300
|
||||
L1_GETS 209
|
||||
L1_GETX 71
|
||||
L1_UPGRADE 0
|
||||
L1_PUTX 124
|
||||
L1_PUTX_old 0
|
||||
Fwd_L1_GETX 0
|
||||
Fwd_L1_GETS 0
|
||||
Fwd_L1_GET_INSTR 0
|
||||
L2_Replacement 43
|
||||
L2_Replacement_clean 496
|
||||
Mem_Data 547
|
||||
Mem_Ack 539
|
||||
WB_Data 62
|
||||
WB_Data_clean 0
|
||||
Ack 0
|
||||
Ack_all 369
|
||||
Unblock 0
|
||||
Unblock_Cancel 0
|
||||
Exclusive_Unblock 272
|
||||
MEM_Inv 0
|
||||
L1_GET_INSTR [300 ] 300
|
||||
L1_GETS [209 ] 209
|
||||
L1_GETX [71 ] 71
|
||||
L1_UPGRADE [0 ] 0
|
||||
L1_PUTX [124 ] 124
|
||||
L1_PUTX_old [0 ] 0
|
||||
Fwd_L1_GETX [0 ] 0
|
||||
Fwd_L1_GETS [0 ] 0
|
||||
Fwd_L1_GET_INSTR [0 ] 0
|
||||
L2_Replacement [43 ] 43
|
||||
L2_Replacement_clean [496 ] 496
|
||||
Mem_Data [547 ] 547
|
||||
Mem_Ack [539 ] 539
|
||||
WB_Data [62 ] 62
|
||||
WB_Data_clean [0 ] 0
|
||||
Ack [0 ] 0
|
||||
Ack_all [369 ] 369
|
||||
Unblock [0 ] 0
|
||||
Unblock_Cancel [0 ] 0
|
||||
Exclusive_Unblock [272 ] 272
|
||||
MEM_Inv [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
NP L1_GET_INSTR 291
|
||||
NP L1_GETS 192
|
||||
NP L1_GETX 64
|
||||
NP L1_PUTX 0 <--
|
||||
NP L1_PUTX_old 0 <--
|
||||
NP L1_GET_INSTR [291 ] 291
|
||||
NP L1_GETS [192 ] 192
|
||||
NP L1_GETX [64 ] 64
|
||||
NP L1_PUTX [0 ] 0
|
||||
NP L1_PUTX_old [0 ] 0
|
||||
|
||||
SS L1_GET_INSTR 9
|
||||
SS L1_GETS 0 <--
|
||||
SS L1_GETX 0 <--
|
||||
SS L1_UPGRADE 0 <--
|
||||
SS L1_PUTX 0 <--
|
||||
SS L1_PUTX_old 0 <--
|
||||
SS L2_Replacement 0 <--
|
||||
SS L2_Replacement_clean 286
|
||||
SS MEM_Inv 0 <--
|
||||
SS L1_GET_INSTR [9 ] 9
|
||||
SS L1_GETS [0 ] 0
|
||||
SS L1_GETX [0 ] 0
|
||||
SS L1_UPGRADE [0 ] 0
|
||||
SS L1_PUTX [0 ] 0
|
||||
SS L1_PUTX_old [0 ] 0
|
||||
SS L2_Replacement [0 ] 0
|
||||
SS L2_Replacement_clean [286 ] 286
|
||||
SS MEM_Inv [0 ] 0
|
||||
|
||||
M L1_GET_INSTR 0 <--
|
||||
M L1_GETS 12
|
||||
M L1_GETX 4
|
||||
M L1_PUTX 0 <--
|
||||
M L1_PUTX_old 0 <--
|
||||
M L2_Replacement 39
|
||||
M L2_Replacement_clean 69
|
||||
M MEM_Inv 0 <--
|
||||
M L1_GET_INSTR [0 ] 0
|
||||
M L1_GETS [12 ] 12
|
||||
M L1_GETX [4 ] 4
|
||||
M L1_PUTX [0 ] 0
|
||||
M L1_PUTX_old [0 ] 0
|
||||
M L2_Replacement [39 ] 39
|
||||
M L2_Replacement_clean [69 ] 69
|
||||
M MEM_Inv [0 ] 0
|
||||
|
||||
MT L1_GET_INSTR 0 <--
|
||||
MT L1_GETS 0 <--
|
||||
MT L1_GETX 0 <--
|
||||
MT L1_PUTX 124
|
||||
MT L1_PUTX_old 0 <--
|
||||
MT L2_Replacement 4
|
||||
MT L2_Replacement_clean 141
|
||||
MT MEM_Inv 0 <--
|
||||
MT L1_GET_INSTR [0 ] 0
|
||||
MT L1_GETS [0 ] 0
|
||||
MT L1_GETX [0 ] 0
|
||||
MT L1_PUTX [124 ] 124
|
||||
MT L1_PUTX_old [0 ] 0
|
||||
MT L2_Replacement [4 ] 4
|
||||
MT L2_Replacement_clean [141 ] 141
|
||||
MT MEM_Inv [0 ] 0
|
||||
|
||||
M_I L1_GET_INSTR 0 <--
|
||||
M_I L1_GETS 5
|
||||
M_I L1_GETX 3
|
||||
M_I L1_UPGRADE 0 <--
|
||||
M_I L1_PUTX 0 <--
|
||||
M_I L1_PUTX_old 0 <--
|
||||
M_I Mem_Ack 539
|
||||
M_I MEM_Inv 0 <--
|
||||
M_I L1_GET_INSTR [0 ] 0
|
||||
M_I L1_GETS [5 ] 5
|
||||
M_I L1_GETX [3 ] 3
|
||||
M_I L1_UPGRADE [0 ] 0
|
||||
M_I L1_PUTX [0 ] 0
|
||||
M_I L1_PUTX_old [0 ] 0
|
||||
M_I Mem_Ack [539 ] 539
|
||||
M_I MEM_Inv [0 ] 0
|
||||
|
||||
MT_I L1_GET_INSTR 0 <--
|
||||
MT_I L1_GETS 0 <--
|
||||
MT_I L1_GETX 0 <--
|
||||
MT_I L1_UPGRADE 0 <--
|
||||
MT_I L1_PUTX 0 <--
|
||||
MT_I L1_PUTX_old 0 <--
|
||||
MT_I WB_Data 2
|
||||
MT_I WB_Data_clean 0 <--
|
||||
MT_I Ack_all 2
|
||||
MT_I MEM_Inv 0 <--
|
||||
MT_I L1_GET_INSTR [0 ] 0
|
||||
MT_I L1_GETS [0 ] 0
|
||||
MT_I L1_GETX [0 ] 0
|
||||
MT_I L1_UPGRADE [0 ] 0
|
||||
MT_I L1_PUTX [0 ] 0
|
||||
MT_I L1_PUTX_old [0 ] 0
|
||||
MT_I WB_Data [2 ] 2
|
||||
MT_I WB_Data_clean [0 ] 0
|
||||
MT_I Ack_all [2 ] 2
|
||||
MT_I MEM_Inv [0 ] 0
|
||||
|
||||
MCT_I L1_GET_INSTR 0 <--
|
||||
MCT_I L1_GETS 0 <--
|
||||
MCT_I L1_GETX 0 <--
|
||||
MCT_I L1_UPGRADE 0 <--
|
||||
MCT_I L1_PUTX 0 <--
|
||||
MCT_I L1_PUTX_old 0 <--
|
||||
MCT_I WB_Data 60
|
||||
MCT_I WB_Data_clean 0 <--
|
||||
MCT_I Ack_all 81
|
||||
MCT_I L1_GET_INSTR [0 ] 0
|
||||
MCT_I L1_GETS [0 ] 0
|
||||
MCT_I L1_GETX [0 ] 0
|
||||
MCT_I L1_UPGRADE [0 ] 0
|
||||
MCT_I L1_PUTX [0 ] 0
|
||||
MCT_I L1_PUTX_old [0 ] 0
|
||||
MCT_I WB_Data [60 ] 60
|
||||
MCT_I WB_Data_clean [0 ] 0
|
||||
MCT_I Ack_all [81 ] 81
|
||||
|
||||
I_I L1_GET_INSTR 0 <--
|
||||
I_I L1_GETS 0 <--
|
||||
I_I L1_GETX 0 <--
|
||||
I_I L1_UPGRADE 0 <--
|
||||
I_I L1_PUTX 0 <--
|
||||
I_I L1_PUTX_old 0 <--
|
||||
I_I Ack 0 <--
|
||||
I_I Ack_all 286
|
||||
I_I L1_GET_INSTR [0 ] 0
|
||||
I_I L1_GETS [0 ] 0
|
||||
I_I L1_GETX [0 ] 0
|
||||
I_I L1_UPGRADE [0 ] 0
|
||||
I_I L1_PUTX [0 ] 0
|
||||
I_I L1_PUTX_old [0 ] 0
|
||||
I_I Ack [0 ] 0
|
||||
I_I Ack_all [286 ] 286
|
||||
|
||||
S_I L1_GET_INSTR 0 <--
|
||||
S_I L1_GETS 0 <--
|
||||
S_I L1_GETX 0 <--
|
||||
S_I L1_UPGRADE 0 <--
|
||||
S_I L1_PUTX 0 <--
|
||||
S_I L1_PUTX_old 0 <--
|
||||
S_I Ack 0 <--
|
||||
S_I Ack_all 0 <--
|
||||
S_I MEM_Inv 0 <--
|
||||
S_I L1_GET_INSTR [0 ] 0
|
||||
S_I L1_GETS [0 ] 0
|
||||
S_I L1_GETX [0 ] 0
|
||||
S_I L1_UPGRADE [0 ] 0
|
||||
S_I L1_PUTX [0 ] 0
|
||||
S_I L1_PUTX_old [0 ] 0
|
||||
S_I Ack [0 ] 0
|
||||
S_I Ack_all [0 ] 0
|
||||
S_I MEM_Inv [0 ] 0
|
||||
|
||||
ISS L1_GET_INSTR 0 <--
|
||||
ISS L1_GETS 0 <--
|
||||
ISS L1_GETX 0 <--
|
||||
ISS L1_PUTX 0 <--
|
||||
ISS L1_PUTX_old 0 <--
|
||||
ISS L2_Replacement 0 <--
|
||||
ISS L2_Replacement_clean 0 <--
|
||||
ISS Mem_Data 192
|
||||
ISS MEM_Inv 0 <--
|
||||
ISS L1_GET_INSTR [0 ] 0
|
||||
ISS L1_GETS [0 ] 0
|
||||
ISS L1_GETX [0 ] 0
|
||||
ISS L1_PUTX [0 ] 0
|
||||
ISS L1_PUTX_old [0 ] 0
|
||||
ISS L2_Replacement [0 ] 0
|
||||
ISS L2_Replacement_clean [0 ] 0
|
||||
ISS Mem_Data [192 ] 192
|
||||
ISS MEM_Inv [0 ] 0
|
||||
|
||||
IS L1_GET_INSTR 0 <--
|
||||
IS L1_GETS 0 <--
|
||||
IS L1_GETX 0 <--
|
||||
IS L1_PUTX 0 <--
|
||||
IS L1_PUTX_old 0 <--
|
||||
IS L2_Replacement 0 <--
|
||||
IS L2_Replacement_clean 0 <--
|
||||
IS Mem_Data 291
|
||||
IS MEM_Inv 0 <--
|
||||
IS L1_GET_INSTR [0 ] 0
|
||||
IS L1_GETS [0 ] 0
|
||||
IS L1_GETX [0 ] 0
|
||||
IS L1_PUTX [0 ] 0
|
||||
IS L1_PUTX_old [0 ] 0
|
||||
IS L2_Replacement [0 ] 0
|
||||
IS L2_Replacement_clean [0 ] 0
|
||||
IS Mem_Data [291 ] 291
|
||||
IS MEM_Inv [0 ] 0
|
||||
|
||||
IM L1_GET_INSTR 0 <--
|
||||
IM L1_GETS 0 <--
|
||||
IM L1_GETX 0 <--
|
||||
IM L1_PUTX 0 <--
|
||||
IM L1_PUTX_old 0 <--
|
||||
IM L2_Replacement 0 <--
|
||||
IM L2_Replacement_clean 0 <--
|
||||
IM Mem_Data 64
|
||||
IM MEM_Inv 0 <--
|
||||
IM L1_GET_INSTR [0 ] 0
|
||||
IM L1_GETS [0 ] 0
|
||||
IM L1_GETX [0 ] 0
|
||||
IM L1_PUTX [0 ] 0
|
||||
IM L1_PUTX_old [0 ] 0
|
||||
IM L2_Replacement [0 ] 0
|
||||
IM L2_Replacement_clean [0 ] 0
|
||||
IM Mem_Data [64 ] 64
|
||||
IM MEM_Inv [0 ] 0
|
||||
|
||||
SS_MB L1_GET_INSTR 0 <--
|
||||
SS_MB L1_GETS 0 <--
|
||||
SS_MB L1_GETX 0 <--
|
||||
SS_MB L1_UPGRADE 0 <--
|
||||
SS_MB L1_PUTX 0 <--
|
||||
SS_MB L1_PUTX_old 0 <--
|
||||
SS_MB L2_Replacement 0 <--
|
||||
SS_MB L2_Replacement_clean 0 <--
|
||||
SS_MB Unblock_Cancel 0 <--
|
||||
SS_MB Exclusive_Unblock 0 <--
|
||||
SS_MB MEM_Inv 0 <--
|
||||
SS_MB L1_GET_INSTR [0 ] 0
|
||||
SS_MB L1_GETS [0 ] 0
|
||||
SS_MB L1_GETX [0 ] 0
|
||||
SS_MB L1_UPGRADE [0 ] 0
|
||||
SS_MB L1_PUTX [0 ] 0
|
||||
SS_MB L1_PUTX_old [0 ] 0
|
||||
SS_MB L2_Replacement [0 ] 0
|
||||
SS_MB L2_Replacement_clean [0 ] 0
|
||||
SS_MB Unblock_Cancel [0 ] 0
|
||||
SS_MB Exclusive_Unblock [0 ] 0
|
||||
SS_MB MEM_Inv [0 ] 0
|
||||
|
||||
MT_MB L1_GET_INSTR 0 <--
|
||||
MT_MB L1_GETS 0 <--
|
||||
MT_MB L1_GETX 0 <--
|
||||
MT_MB L1_UPGRADE 0 <--
|
||||
MT_MB L1_PUTX 0 <--
|
||||
MT_MB L1_PUTX_old 0 <--
|
||||
MT_MB L2_Replacement 0 <--
|
||||
MT_MB L2_Replacement_clean 0 <--
|
||||
MT_MB Unblock_Cancel 0 <--
|
||||
MT_MB Exclusive_Unblock 272
|
||||
MT_MB MEM_Inv 0 <--
|
||||
MT_MB L1_GET_INSTR [0 ] 0
|
||||
MT_MB L1_GETS [0 ] 0
|
||||
MT_MB L1_GETX [0 ] 0
|
||||
MT_MB L1_UPGRADE [0 ] 0
|
||||
MT_MB L1_PUTX [0 ] 0
|
||||
MT_MB L1_PUTX_old [0 ] 0
|
||||
MT_MB L2_Replacement [0 ] 0
|
||||
MT_MB L2_Replacement_clean [0 ] 0
|
||||
MT_MB Unblock_Cancel [0 ] 0
|
||||
MT_MB Exclusive_Unblock [272 ] 272
|
||||
MT_MB MEM_Inv [0 ] 0
|
||||
|
||||
M_MB L1_GET_INSTR 0 <--
|
||||
M_MB L1_GETS 0 <--
|
||||
M_MB L1_GETX 0 <--
|
||||
M_MB L1_UPGRADE 0 <--
|
||||
M_MB L1_PUTX 0 <--
|
||||
M_MB L1_PUTX_old 0 <--
|
||||
M_MB L2_Replacement 0 <--
|
||||
M_MB L2_Replacement_clean 0 <--
|
||||
M_MB Exclusive_Unblock 0 <--
|
||||
M_MB MEM_Inv 0 <--
|
||||
M_MB L1_GET_INSTR [0 ] 0
|
||||
M_MB L1_GETS [0 ] 0
|
||||
M_MB L1_GETX [0 ] 0
|
||||
M_MB L1_UPGRADE [0 ] 0
|
||||
M_MB L1_PUTX [0 ] 0
|
||||
M_MB L1_PUTX_old [0 ] 0
|
||||
M_MB L2_Replacement [0 ] 0
|
||||
M_MB L2_Replacement_clean [0 ] 0
|
||||
M_MB Exclusive_Unblock [0 ] 0
|
||||
M_MB MEM_Inv [0 ] 0
|
||||
|
||||
MT_IIB L1_GET_INSTR 0 <--
|
||||
MT_IIB L1_GETS 0 <--
|
||||
MT_IIB L1_GETX 0 <--
|
||||
MT_IIB L1_UPGRADE 0 <--
|
||||
MT_IIB L1_PUTX 0 <--
|
||||
MT_IIB L1_PUTX_old 0 <--
|
||||
MT_IIB L2_Replacement 0 <--
|
||||
MT_IIB L2_Replacement_clean 0 <--
|
||||
MT_IIB WB_Data 0 <--
|
||||
MT_IIB WB_Data_clean 0 <--
|
||||
MT_IIB Unblock 0 <--
|
||||
MT_IIB MEM_Inv 0 <--
|
||||
MT_IIB L1_GET_INSTR [0 ] 0
|
||||
MT_IIB L1_GETS [0 ] 0
|
||||
MT_IIB L1_GETX [0 ] 0
|
||||
MT_IIB L1_UPGRADE [0 ] 0
|
||||
MT_IIB L1_PUTX [0 ] 0
|
||||
MT_IIB L1_PUTX_old [0 ] 0
|
||||
MT_IIB L2_Replacement [0 ] 0
|
||||
MT_IIB L2_Replacement_clean [0 ] 0
|
||||
MT_IIB WB_Data [0 ] 0
|
||||
MT_IIB WB_Data_clean [0 ] 0
|
||||
MT_IIB Unblock [0 ] 0
|
||||
MT_IIB MEM_Inv [0 ] 0
|
||||
|
||||
MT_IB L1_GET_INSTR 0 <--
|
||||
MT_IB L1_GETS 0 <--
|
||||
MT_IB L1_GETX 0 <--
|
||||
MT_IB L1_UPGRADE 0 <--
|
||||
MT_IB L1_PUTX 0 <--
|
||||
MT_IB L1_PUTX_old 0 <--
|
||||
MT_IB L2_Replacement 0 <--
|
||||
MT_IB L2_Replacement_clean 0 <--
|
||||
MT_IB WB_Data 0 <--
|
||||
MT_IB WB_Data_clean 0 <--
|
||||
MT_IB Unblock_Cancel 0 <--
|
||||
MT_IB MEM_Inv 0 <--
|
||||
MT_IB L1_GET_INSTR [0 ] 0
|
||||
MT_IB L1_GETS [0 ] 0
|
||||
MT_IB L1_GETX [0 ] 0
|
||||
MT_IB L1_UPGRADE [0 ] 0
|
||||
MT_IB L1_PUTX [0 ] 0
|
||||
MT_IB L1_PUTX_old [0 ] 0
|
||||
MT_IB L2_Replacement [0 ] 0
|
||||
MT_IB L2_Replacement_clean [0 ] 0
|
||||
MT_IB WB_Data [0 ] 0
|
||||
MT_IB WB_Data_clean [0 ] 0
|
||||
MT_IB Unblock_Cancel [0 ] 0
|
||||
MT_IB MEM_Inv [0 ] 0
|
||||
|
||||
MT_SB L1_GET_INSTR 0 <--
|
||||
MT_SB L1_GETS 0 <--
|
||||
MT_SB L1_GETX 0 <--
|
||||
MT_SB L1_UPGRADE 0 <--
|
||||
MT_SB L1_PUTX 0 <--
|
||||
MT_SB L1_PUTX_old 0 <--
|
||||
MT_SB L2_Replacement 0 <--
|
||||
MT_SB L2_Replacement_clean 0 <--
|
||||
MT_SB Unblock 0 <--
|
||||
MT_SB MEM_Inv 0 <--
|
||||
MT_SB L1_GET_INSTR [0 ] 0
|
||||
MT_SB L1_GETS [0 ] 0
|
||||
MT_SB L1_GETX [0 ] 0
|
||||
MT_SB L1_UPGRADE [0 ] 0
|
||||
MT_SB L1_PUTX [0 ] 0
|
||||
MT_SB L1_PUTX_old [0 ] 0
|
||||
MT_SB L2_Replacement [0 ] 0
|
||||
MT_SB L2_Replacement_clean [0 ] 0
|
||||
MT_SB Unblock [0 ] 0
|
||||
MT_SB MEM_Inv [0 ] 0
|
||||
|
||||
Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer:
|
||||
Memory controller: system.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 650
|
||||
memory_reads: 547
|
||||
memory_writes: 103
|
||||
|
|
@ -551,67 +556,66 @@ Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer:
|
|||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 26 14 0 49 21 21 42 25 6 4 7 4 24 42 26 3 5 7 7 18 10 29 15 50 19 5 6 16 14 24 19 92
|
||||
|
||||
--- Directory 0 ---
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
Fetch 547
|
||||
Data 103
|
||||
Memory_Data 547
|
||||
Memory_Ack 103
|
||||
DMA_READ 0
|
||||
DMA_WRITE 0
|
||||
CleanReplacement 436
|
||||
Fetch [547 ] 547
|
||||
Data [103 ] 103
|
||||
Memory_Data [547 ] 547
|
||||
Memory_Ack [103 ] 103
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
CleanReplacement [436 ] 436
|
||||
|
||||
- Transitions -
|
||||
I Fetch 547
|
||||
I DMA_READ 0 <--
|
||||
I DMA_WRITE 0 <--
|
||||
I Fetch [547 ] 547
|
||||
I DMA_READ [0 ] 0
|
||||
I DMA_WRITE [0 ] 0
|
||||
|
||||
ID Fetch 0 <--
|
||||
ID Data 0 <--
|
||||
ID Memory_Data 0 <--
|
||||
ID DMA_READ 0 <--
|
||||
ID DMA_WRITE 0 <--
|
||||
ID Fetch [0 ] 0
|
||||
ID Data [0 ] 0
|
||||
ID Memory_Data [0 ] 0
|
||||
ID DMA_READ [0 ] 0
|
||||
ID DMA_WRITE [0 ] 0
|
||||
|
||||
ID_W Fetch 0 <--
|
||||
ID_W Data 0 <--
|
||||
ID_W Memory_Ack 0 <--
|
||||
ID_W DMA_READ 0 <--
|
||||
ID_W DMA_WRITE 0 <--
|
||||
ID_W Fetch [0 ] 0
|
||||
ID_W Data [0 ] 0
|
||||
ID_W Memory_Ack [0 ] 0
|
||||
ID_W DMA_READ [0 ] 0
|
||||
ID_W DMA_WRITE [0 ] 0
|
||||
|
||||
M Data 103
|
||||
M DMA_READ 0 <--
|
||||
M DMA_WRITE 0 <--
|
||||
M CleanReplacement 436
|
||||
M Data [103 ] 103
|
||||
M DMA_READ [0 ] 0
|
||||
M DMA_WRITE [0 ] 0
|
||||
M CleanReplacement [436 ] 436
|
||||
|
||||
IM Fetch 0 <--
|
||||
IM Data 0 <--
|
||||
IM Memory_Data 547
|
||||
IM DMA_READ 0 <--
|
||||
IM DMA_WRITE 0 <--
|
||||
IM Fetch [0 ] 0
|
||||
IM Data [0 ] 0
|
||||
IM Memory_Data [547 ] 547
|
||||
IM DMA_READ [0 ] 0
|
||||
IM DMA_WRITE [0 ] 0
|
||||
|
||||
MI Fetch 0 <--
|
||||
MI Data 0 <--
|
||||
MI Memory_Ack 103
|
||||
MI DMA_READ 0 <--
|
||||
MI DMA_WRITE 0 <--
|
||||
MI Fetch [0 ] 0
|
||||
MI Data [0 ] 0
|
||||
MI Memory_Ack [103 ] 103
|
||||
MI DMA_READ [0 ] 0
|
||||
MI DMA_WRITE [0 ] 0
|
||||
|
||||
M_DRD Data 0 <--
|
||||
M_DRD DMA_READ 0 <--
|
||||
M_DRD DMA_WRITE 0 <--
|
||||
M_DRD Data [0 ] 0
|
||||
M_DRD DMA_READ [0 ] 0
|
||||
M_DRD DMA_WRITE [0 ] 0
|
||||
|
||||
M_DRDI Fetch 0 <--
|
||||
M_DRDI Data 0 <--
|
||||
M_DRDI Memory_Ack 0 <--
|
||||
M_DRDI DMA_READ 0 <--
|
||||
M_DRDI DMA_WRITE 0 <--
|
||||
M_DRDI Fetch [0 ] 0
|
||||
M_DRDI Data [0 ] 0
|
||||
M_DRDI Memory_Ack [0 ] 0
|
||||
M_DRDI DMA_READ [0 ] 0
|
||||
M_DRDI DMA_WRITE [0 ] 0
|
||||
|
||||
M_DWR Data 0 <--
|
||||
M_DWR DMA_READ 0 <--
|
||||
M_DWR DMA_WRITE 0 <--
|
||||
|
||||
M_DWRI Fetch 0 <--
|
||||
M_DWRI Data 0 <--
|
||||
M_DWRI Memory_Ack 0 <--
|
||||
M_DWRI DMA_READ 0 <--
|
||||
M_DWRI DMA_WRITE 0 <--
|
||||
M_DWR Data [0 ] 0
|
||||
M_DWR DMA_READ [0 ] 0
|
||||
M_DWR DMA_WRITE [0 ] 0
|
||||
|
||||
M_DWRI Fetch [0 ] 0
|
||||
M_DWRI Data [0 ] 0
|
||||
M_DWRI Memory_Ack [0 ] 0
|
||||
M_DWRI DMA_READ [0 ] 0
|
||||
M_DWRI DMA_WRITE
|
||||
|
|
@ -5,10 +5,10 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 28 2010 13:54:58
|
||||
M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
|
||||
M5 started Jan 28 2010 13:57:44
|
||||
M5 executing on svvint03
|
||||
M5 compiled Aug 5 2010 10:22:52
|
||||
M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip
|
||||
M5 started Aug 5 2010 10:31:34
|
||||
M5 executing on svvint09
|
||||
command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 21475 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 214848 # Number of bytes of host memory used
|
||||
host_seconds 0.12 # Real time elapsed on the host
|
||||
host_tick_rate 863649 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 25769 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 211408 # Number of bytes of host memory used
|
||||
host_seconds 0.10 # Real time elapsed on the host
|
||||
host_tick_rate 1036329 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_seconds 0.000104 # Number of seconds simulated
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ dummy=0
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu physmem ruby
|
||||
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
|
||||
|
|
@ -32,8 +32,8 @@ progress_interval=0
|
|||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
|
||||
icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
|
||||
dcache_port=system.l1_cntrl0.sequencer.port[1]
|
||||
icache_port=system.l1_cntrl0.sequencer.port[0]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
|
|
@ -54,7 +54,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
|
||||
executable=tests/test-progs/hello/bin/alpha/tru64/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -65,162 +65,27 @@ simpoint=0
|
|||
system=system
|
||||
uid=100
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
output_filename=none
|
||||
protocol_trace=false
|
||||
start_time=1
|
||||
verbosity_string=none
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=true
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
link_latency=1
|
||||
number_of_virtual_networks=10
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
|
||||
num_int_nodes=4
|
||||
print_config=false
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links0.ext_node
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
buffer_size=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links1.ext_node
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node]
|
||||
type=L2Cache_Controller
|
||||
children=L2cacheMemory
|
||||
L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
|
||||
buffer_size=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
response_latency=2
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=15
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
||||
[system.ruby.network.topology.ext_links2]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links2.ext_node
|
||||
int_node=2
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node]
|
||||
[system.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
directory=system.ruby.network.topology.ext_links2.ext_node.directory
|
||||
directory=system.dir_cntrl0.directory
|
||||
directory_latency=6
|
||||
memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer
|
||||
memBuffer=system.dir_cntrl0.memBuffer
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.directory]
|
||||
[system.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=6
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.memBuffer]
|
||||
[system.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
|
|
@ -241,6 +106,146 @@ refresh_period=1560
|
|||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
|
||||
L1IcacheMemory=system.l1_cntrl0.sequencer.icache
|
||||
buffer_size=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
sequencer=system.l1_cntrl0.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.l1_cntrl0.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.l1_cntrl0.sequencer.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l2_cntrl0]
|
||||
type=L2Cache_Controller
|
||||
children=L2cacheMemory
|
||||
L2cacheMemory=system.l2_cntrl0.L2cacheMemory
|
||||
buffer_size=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
response_latency=2
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l2_cntrl0.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=15
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
start_index_bit=6
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.l1_cntrl0.sequencer.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
no_mem_vec=false
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
output_filename=none
|
||||
protocol_trace=false
|
||||
start_time=1
|
||||
verbosity_string=none
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=false
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
link_latency=1
|
||||
number_of_virtual_networks=10
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
|
||||
name=Crossbar
|
||||
num_int_nodes=4
|
||||
print_config=false
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
bw_multiplier=64
|
||||
ext_node=system.l1_cntrl0
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
bw_multiplier=64
|
||||
ext_node=system.l2_cntrl0
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links2]
|
||||
type=ExtLink
|
||||
bw_multiplier=64
|
||||
ext_node=system.dir_cntrl0
|
||||
int_node=2
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links0]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -5,10 +5,10 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 28 2010 14:49:51
|
||||
M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
|
||||
M5 started Jan 28 2010 15:08:15
|
||||
M5 executing on svvint05
|
||||
M5 compiled Aug 5 2010 10:34:54
|
||||
M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip
|
||||
M5 started Aug 5 2010 10:37:10
|
||||
M5 executing on svvint09
|
||||
command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 14317 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 214996 # Number of bytes of host memory used
|
||||
host_seconds 0.18 # Real time elapsed on the host
|
||||
host_tick_rate 477706 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 19822 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 211548 # Number of bytes of host memory used
|
||||
host_seconds 0.13 # Real time elapsed on the host
|
||||
host_tick_rate 661411 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_seconds 0.000086 # Number of seconds simulated
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ dummy=0
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu physmem ruby
|
||||
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
|
||||
|
|
@ -32,8 +32,8 @@ progress_interval=0
|
|||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
|
||||
icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
|
||||
dcache_port=system.l1_cntrl0.sequencer.port[1]
|
||||
icache_port=system.l1_cntrl0.sequencer.port[0]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
|
|
@ -54,7 +54,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
|
||||
executable=tests/test-progs/hello/bin/alpha/tru64/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -65,172 +65,30 @@ simpoint=0
|
|||
system=system
|
||||
uid=100
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
output_filename=none
|
||||
protocol_trace=false
|
||||
start_time=1
|
||||
verbosity_string=none
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=true
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
link_latency=1
|
||||
number_of_virtual_networks=10
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
|
||||
num_int_nodes=4
|
||||
print_config=false
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links0.ext_node
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
N_tokens=2
|
||||
buffer_size=0
|
||||
dynamic_timeout_enabled=true
|
||||
fixed_timeout_latency=300
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links1.ext_node
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node]
|
||||
type=L2Cache_Controller
|
||||
children=L2cacheMemory
|
||||
L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
|
||||
N_tokens=2
|
||||
buffer_size=0
|
||||
filtering_enabled=true
|
||||
l2_request_latency=10
|
||||
l2_response_latency=10
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=15
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
||||
[system.ruby.network.topology.ext_links2]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links2.ext_node
|
||||
int_node=2
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node]
|
||||
[system.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
directory=system.ruby.network.topology.ext_links2.ext_node.directory
|
||||
directory_latency=6
|
||||
directory=system.dir_cntrl0.directory
|
||||
directory_latency=5
|
||||
distributed_persistent=true
|
||||
fixed_timeout_latency=300
|
||||
fixed_timeout_latency=100
|
||||
l2_select_num_bits=0
|
||||
memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer
|
||||
memBuffer=system.dir_cntrl0.memBuffer
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.directory]
|
||||
[system.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=6
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.memBuffer]
|
||||
[system.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
|
|
@ -251,6 +109,154 @@ refresh_period=1560
|
|||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
|
||||
L1IcacheMemory=system.l1_cntrl0.sequencer.icache
|
||||
N_tokens=2
|
||||
buffer_size=0
|
||||
dynamic_timeout_enabled=true
|
||||
fixed_timeout_latency=300
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
sequencer=system.l1_cntrl0.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.l1_cntrl0.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.l1_cntrl0.sequencer.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l2_cntrl0]
|
||||
type=L2Cache_Controller
|
||||
children=L2cacheMemory
|
||||
L2cacheMemory=system.l2_cntrl0.L2cacheMemory
|
||||
N_tokens=2
|
||||
buffer_size=0
|
||||
filtering_enabled=true
|
||||
l2_request_latency=5
|
||||
l2_response_latency=5
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l2_cntrl0.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=10
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
start_index_bit=0
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.l1_cntrl0.sequencer.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
no_mem_vec=false
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
output_filename=none
|
||||
protocol_trace=false
|
||||
start_time=1
|
||||
verbosity_string=none
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=false
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
link_latency=1
|
||||
number_of_virtual_networks=10
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
|
||||
name=Crossbar
|
||||
num_int_nodes=4
|
||||
print_config=false
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
bw_multiplier=64
|
||||
ext_node=system.l1_cntrl0
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
bw_multiplier=64
|
||||
ext_node=system.l2_cntrl0
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links2]
|
||||
type=ExtLink
|
||||
bw_multiplier=64
|
||||
ext_node=system.dir_cntrl0
|
||||
int_node=2
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links0]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -5,13 +5,13 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 28 2010 15:54:34
|
||||
M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
|
||||
M5 started Jan 28 2010 15:55:46
|
||||
M5 executing on svvint04
|
||||
M5 compiled Aug 5 2010 10:41:36
|
||||
M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip
|
||||
M5 started Aug 5 2010 10:43:25
|
||||
M5 executing on svvint09
|
||||
command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 90308 because target called exit()
|
||||
Exiting @ tick 92099 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 18406 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 214900 # Number of bytes of host memory used
|
||||
host_seconds 0.15 # Real time elapsed on the host
|
||||
host_tick_rate 602029 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 42948 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 211392 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
host_tick_rate 1534907 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_seconds 0.000090 # Number of seconds simulated
|
||||
sim_ticks 90308 # Number of ticks simulated
|
||||
sim_seconds 0.000092 # Number of seconds simulated
|
||||
sim_ticks 92099 # Number of ticks simulated
|
||||
system.cpu.dtb.data_accesses 717 # DTB accesses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_hits 709 # DTB hits
|
||||
|
|
@ -42,7 +42,7 @@ system.cpu.itb.write_acv 0 # DT
|
|||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 90308 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 92099 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 2577 # Number of instructions executed
|
||||
system.cpu.num_refs 717 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ dummy=0
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu physmem ruby
|
||||
children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
|
||||
|
|
@ -32,8 +32,8 @@ progress_interval=0
|
|||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
|
||||
icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
|
||||
dcache_port=system.l1_cntrl0.sequencer.port[1]
|
||||
icache_port=system.l1_cntrl0.sequencer.port[0]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
|
|
@ -54,7 +54,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
|
||||
executable=tests/test-progs/hello/bin/alpha/tru64/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -65,142 +65,29 @@ simpoint=0
|
|||
system=system
|
||||
uid=100
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
output_filename=none
|
||||
protocol_trace=false
|
||||
start_time=1
|
||||
verbosity_string=none
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=true
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
link_latency=1
|
||||
number_of_virtual_networks=10
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 int_links0 int_links1
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
|
||||
num_int_nodes=3
|
||||
print_config=false
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links0.ext_node
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=L2cacheMemory sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
L2cacheMemory=system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory
|
||||
buffer_size=0
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=15
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links1.ext_node
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node]
|
||||
[system.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
children=directory memBuffer probeFilter
|
||||
buffer_size=0
|
||||
directory=system.ruby.network.topology.ext_links1.ext_node.directory
|
||||
memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer
|
||||
memory_controller_latency=12
|
||||
directory=system.dir_cntrl0.directory
|
||||
memBuffer=system.dir_cntrl0.memBuffer
|
||||
memory_controller_latency=2
|
||||
number_of_TBEs=256
|
||||
probeFilter=system.dir_cntrl0.probeFilter
|
||||
probe_filter_enabled=false
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.directory]
|
||||
[system.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=6
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.memBuffer]
|
||||
[system.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
|
|
@ -221,6 +108,136 @@ refresh_period=1560
|
|||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.dir_cntrl0.probeFilter]
|
||||
type=RubyCache
|
||||
assoc=4
|
||||
latency=1
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=1024
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0]
|
||||
type=L1Cache_Controller
|
||||
children=L2cacheMemory sequencer
|
||||
L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
|
||||
L1IcacheMemory=system.l1_cntrl0.sequencer.icache
|
||||
L2cacheMemory=system.l1_cntrl0.L2cacheMemory
|
||||
buffer_size=0
|
||||
cache_response_latency=10
|
||||
issue_latency=2
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.l1_cntrl0.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=10
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.l1_cntrl0.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.l1_cntrl0.sequencer.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.l1_cntrl0.sequencer.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
no_mem_vec=false
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
output_filename=none
|
||||
protocol_trace=false
|
||||
start_time=1
|
||||
verbosity_string=none
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=false
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
link_latency=1
|
||||
number_of_virtual_networks=10
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 int_links0 int_links1
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
|
||||
name=Crossbar
|
||||
num_int_nodes=3
|
||||
print_config=false
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
bw_multiplier=64
|
||||
ext_node=system.l1_cntrl0
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
bw_multiplier=64
|
||||
ext_node=system.dir_cntrl0
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links0]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -5,13 +5,13 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 28 2010 11:30:01
|
||||
M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
|
||||
M5 started Jan 28 2010 11:48:25
|
||||
M5 executing on svvint06
|
||||
M5 compiled Aug 5 2010 14:43:33
|
||||
M5 revision c5f5b5533e96+ 7536+ default qtip tip brad/regress_updates
|
||||
M5 started Aug 5 2010 14:44:19
|
||||
M5 executing on svvint09
|
||||
command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 81672 because target called exit()
|
||||
Exiting @ tick 78408 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 32212 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 212236 # Number of bytes of host memory used
|
||||
host_seconds 0.08 # Real time elapsed on the host
|
||||
host_tick_rate 1020887 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 42947 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 211060 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
host_tick_rate 1306713 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_seconds 0.000082 # Number of seconds simulated
|
||||
sim_ticks 81672 # Number of ticks simulated
|
||||
sim_seconds 0.000078 # Number of seconds simulated
|
||||
sim_ticks 78408 # Number of ticks simulated
|
||||
system.cpu.dtb.data_accesses 717 # DTB accesses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_hits 709 # DTB hits
|
||||
|
|
@ -42,7 +42,7 @@ system.cpu.itb.write_acv 0 # DT
|
|||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 81672 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 78408 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 2577 # Number of instructions executed
|
||||
system.cpu.num_refs 717 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -5,13 +5,14 @@ dummy=0
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcmem physmem ruby
|
||||
children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 physmem ruby
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
|
||||
[system.cpu0]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -27,6 +28,7 @@ test=system.ruby.cpu_ruby_ports0.port[0]
|
|||
[system.cpu1]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -42,6 +44,7 @@ test=system.ruby.cpu_ruby_ports1.port[0]
|
|||
[system.cpu2]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -57,6 +60,7 @@ test=system.ruby.cpu_ruby_ports2.port[0]
|
|||
[system.cpu3]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -72,6 +76,7 @@ test=system.ruby.cpu_ruby_ports3.port[0]
|
|||
[system.cpu4]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -87,6 +92,7 @@ test=system.ruby.cpu_ruby_ports4.port[0]
|
|||
[system.cpu5]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -102,6 +108,7 @@ test=system.ruby.cpu_ruby_ports5.port[0]
|
|||
[system.cpu6]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -117,6 +124,7 @@ test=system.ruby.cpu_ruby_ports6.port[0]
|
|||
[system.cpu7]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -129,6 +137,48 @@ trace_addr=0
|
|||
functional=system.funcmem.port[7]
|
||||
test=system.ruby.cpu_ruby_ports7.port[0]
|
||||
|
||||
[system.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
directory=system.dir_cntrl0.directory
|
||||
directory_latency=6
|
||||
memBuffer=system.dir_cntrl0.memBuffer
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
to_mem_ctrl_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=6
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.funcmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
|
|
@ -139,6 +189,283 @@ range=0:134217727
|
|||
zero=false
|
||||
port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
|
||||
|
||||
[system.l1_cntrl0]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports0
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl1]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.l1_cntrl1.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl1.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports1
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=1
|
||||
|
||||
[system.l1_cntrl1.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl1.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl2]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.l1_cntrl2.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl2.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports2
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=2
|
||||
|
||||
[system.l1_cntrl2.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl2.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl3]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.l1_cntrl3.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl3.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports3
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=3
|
||||
|
||||
[system.l1_cntrl3.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl3.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl4]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.l1_cntrl4.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl4.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports4
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=4
|
||||
|
||||
[system.l1_cntrl4.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl4.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl5]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.l1_cntrl5.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl5.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports5
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=5
|
||||
|
||||
[system.l1_cntrl5.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl5.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl6]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.l1_cntrl6.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl6.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports6
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=6
|
||||
|
||||
[system.l1_cntrl6.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl6.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl7]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.l1_cntrl7.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl7.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports7
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=7
|
||||
|
||||
[system.l1_cntrl7.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl7.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l2_cntrl0]
|
||||
type=L2Cache_Controller
|
||||
children=L2cacheMemory
|
||||
L2cacheMemory=system.l2_cntrl0.L2cacheMemory
|
||||
buffer_size=0
|
||||
l2_request_latency=2
|
||||
l2_response_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
to_l1_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l2_cntrl0.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=15
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
start_index_bit=6
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
|
|
@ -166,9 +493,9 @@ tracer=system.ruby.tracer
|
|||
|
||||
[system.ruby.cpu_ruby_ports0]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory
|
||||
dcache=system.l1_cntrl0.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory
|
||||
icache=system.l1_cntrl0.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
|
|
@ -178,9 +505,9 @@ port=system.cpu0.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports1]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory
|
||||
dcache=system.l1_cntrl1.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory
|
||||
icache=system.l1_cntrl1.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
|
|
@ -190,9 +517,9 @@ port=system.cpu1.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports2]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory
|
||||
dcache=system.l1_cntrl2.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory
|
||||
icache=system.l1_cntrl2.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
|
|
@ -202,9 +529,9 @@ port=system.cpu2.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports3]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory
|
||||
dcache=system.l1_cntrl3.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory
|
||||
icache=system.l1_cntrl3.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
|
|
@ -214,9 +541,9 @@ port=system.cpu3.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports4]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory
|
||||
dcache=system.l1_cntrl4.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory
|
||||
icache=system.l1_cntrl4.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
|
|
@ -226,9 +553,9 @@ port=system.cpu4.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports5]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory
|
||||
dcache=system.l1_cntrl5.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory
|
||||
icache=system.l1_cntrl5.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
|
|
@ -238,9 +565,9 @@ port=system.cpu5.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports6]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory
|
||||
dcache=system.l1_cntrl6.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory
|
||||
icache=system.l1_cntrl6.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
|
|
@ -250,9 +577,9 @@ port=system.cpu6.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports7]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory
|
||||
dcache=system.l1_cntrl7.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory
|
||||
icache=system.l1_cntrl7.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
|
|
@ -282,6 +609,7 @@ topology=system.ruby.network.topology
|
|||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 ext_links9 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 int_links9
|
||||
description=Crossbar
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8 system.ruby.network.topology.ext_links9
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8 system.ruby.network.topology.int_links9
|
||||
num_int_nodes=11
|
||||
|
|
@ -289,396 +617,84 @@ print_config=false
|
|||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links0.ext_node
|
||||
ext_node=system.l1_cntrl0
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports0
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links1.ext_node
|
||||
ext_node=system.l1_cntrl1
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports1
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links2]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links2.ext_node
|
||||
ext_node=system.l1_cntrl2
|
||||
int_node=2
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports2
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=2
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links3]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links3.ext_node
|
||||
ext_node=system.l1_cntrl3
|
||||
int_node=3
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links3.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports3
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=3
|
||||
|
||||
[system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links4]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links4.ext_node
|
||||
ext_node=system.l1_cntrl4
|
||||
int_node=4
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links4.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports4
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=4
|
||||
|
||||
[system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links5]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links5.ext_node
|
||||
ext_node=system.l1_cntrl5
|
||||
int_node=5
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links5.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports5
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=5
|
||||
|
||||
[system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links6]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links6.ext_node
|
||||
ext_node=system.l1_cntrl6
|
||||
int_node=6
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links6.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports6
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=6
|
||||
|
||||
[system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links7]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links7.ext_node
|
||||
ext_node=system.l1_cntrl7
|
||||
int_node=7
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links7.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports7
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=7
|
||||
|
||||
[system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links8]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links8.ext_node
|
||||
ext_node=system.l2_cntrl0
|
||||
int_node=8
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links8.ext_node]
|
||||
type=L2Cache_Controller
|
||||
children=L2cacheMemory
|
||||
L2cacheMemory=system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory
|
||||
buffer_size=0
|
||||
l2_request_latency=2
|
||||
l2_response_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
to_l1_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=15
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
||||
[system.ruby.network.topology.ext_links9]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links9.ext_node
|
||||
ext_node=system.dir_cntrl0
|
||||
int_node=9
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links9.ext_node]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
directory=system.ruby.network.topology.ext_links9.ext_node.directory
|
||||
directory_latency=6
|
||||
memBuffer=system.ruby.network.topology.ext_links9.ext_node.memBuffer
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
to_mem_ctrl_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links9.ext_node.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=0
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links9.ext_node.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.int_links0]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,74 +1,74 @@
|
|||
system.cpu5: completed 10000 read accesses @370057
|
||||
system.cpu1: completed 10000 read accesses @372602
|
||||
system.cpu0: completed 10000 read accesses @380072
|
||||
system.cpu3: completed 10000 read accesses @380676
|
||||
system.cpu4: completed 10000 read accesses @383371
|
||||
system.cpu2: completed 10000 read accesses @385679
|
||||
system.cpu6: completed 10000 read accesses @386340
|
||||
system.cpu7: completed 10000 read accesses @389231
|
||||
system.cpu5: completed 20000 read accesses @746317
|
||||
system.cpu0: completed 20000 read accesses @748763
|
||||
system.cpu3: completed 20000 read accesses @752788
|
||||
system.cpu1: completed 20000 read accesses @753263
|
||||
system.cpu4: completed 20000 read accesses @763818
|
||||
system.cpu6: completed 20000 read accesses @765866
|
||||
system.cpu2: completed 20000 read accesses @771677
|
||||
system.cpu7: completed 20000 read accesses @772771
|
||||
system.cpu0: completed 30000 read accesses @1112242
|
||||
system.cpu1: completed 30000 read accesses @1129327
|
||||
system.cpu3: completed 30000 read accesses @1129794
|
||||
system.cpu5: completed 30000 read accesses @1131833
|
||||
system.cpu2: completed 30000 read accesses @1142425
|
||||
system.cpu4: completed 30000 read accesses @1144628
|
||||
system.cpu6: completed 30000 read accesses @1153431
|
||||
system.cpu7: completed 30000 read accesses @1154016
|
||||
system.cpu0: completed 40000 read accesses @1484294
|
||||
system.cpu1: completed 40000 read accesses @1505996
|
||||
system.cpu3: completed 40000 read accesses @1507887
|
||||
system.cpu2: completed 40000 read accesses @1512800
|
||||
system.cpu4: completed 40000 read accesses @1520410
|
||||
system.cpu5: completed 40000 read accesses @1522723
|
||||
system.cpu6: completed 40000 read accesses @1538655
|
||||
system.cpu7: completed 40000 read accesses @1539216
|
||||
system.cpu0: completed 50000 read accesses @1860160
|
||||
system.cpu3: completed 50000 read accesses @1882708
|
||||
system.cpu1: completed 50000 read accesses @1883329
|
||||
system.cpu2: completed 50000 read accesses @1891575
|
||||
system.cpu4: completed 50000 read accesses @1896200
|
||||
system.cpu5: completed 50000 read accesses @1912575
|
||||
system.cpu6: completed 50000 read accesses @1917985
|
||||
system.cpu7: completed 50000 read accesses @1929708
|
||||
system.cpu0: completed 60000 read accesses @2233080
|
||||
system.cpu1: completed 60000 read accesses @2253689
|
||||
system.cpu3: completed 60000 read accesses @2259715
|
||||
system.cpu2: completed 60000 read accesses @2264515
|
||||
system.cpu4: completed 60000 read accesses @2278281
|
||||
system.cpu5: completed 60000 read accesses @2291280
|
||||
system.cpu6: completed 60000 read accesses @2305718
|
||||
system.cpu7: completed 60000 read accesses @2318114
|
||||
system.cpu0: completed 70000 read accesses @2615296
|
||||
system.cpu1: completed 70000 read accesses @2621479
|
||||
system.cpu2: completed 70000 read accesses @2635267
|
||||
system.cpu3: completed 70000 read accesses @2642310
|
||||
system.cpu4: completed 70000 read accesses @2659144
|
||||
system.cpu5: completed 70000 read accesses @2668163
|
||||
system.cpu6: completed 70000 read accesses @2691243
|
||||
system.cpu7: completed 70000 read accesses @2706192
|
||||
system.cpu0: completed 80000 read accesses @2986810
|
||||
system.cpu1: completed 80000 read accesses @2994418
|
||||
system.cpu2: completed 80000 read accesses @3009400
|
||||
system.cpu3: completed 80000 read accesses @3028789
|
||||
system.cpu4: completed 80000 read accesses @3033010
|
||||
system.cpu5: completed 80000 read accesses @3042800
|
||||
system.cpu6: completed 80000 read accesses @3071603
|
||||
system.cpu7: completed 80000 read accesses @3108423
|
||||
system.cpu0: completed 90000 read accesses @3351259
|
||||
system.cpu1: completed 90000 read accesses @3361381
|
||||
system.cpu2: completed 90000 read accesses @3381198
|
||||
system.cpu4: completed 90000 read accesses @3406636
|
||||
system.cpu3: completed 90000 read accesses @3411857
|
||||
system.cpu5: completed 90000 read accesses @3424074
|
||||
system.cpu6: completed 90000 read accesses @3457139
|
||||
system.cpu7: completed 90000 read accesses @3490206
|
||||
system.cpu0: completed 100000 read accesses @3725190
|
||||
system.cpu0: completed 10000 read accesses @371396
|
||||
system.cpu2: completed 10000 read accesses @374647
|
||||
system.cpu7: completed 10000 read accesses @377314
|
||||
system.cpu1: completed 10000 read accesses @379478
|
||||
system.cpu3: completed 10000 read accesses @380787
|
||||
system.cpu5: completed 10000 read accesses @386046
|
||||
system.cpu4: completed 10000 read accesses @386470
|
||||
system.cpu6: completed 10000 read accesses @394077
|
||||
system.cpu0: completed 20000 read accesses @748308
|
||||
system.cpu2: completed 20000 read accesses @750148
|
||||
system.cpu1: completed 20000 read accesses @752701
|
||||
system.cpu3: completed 20000 read accesses @761044
|
||||
system.cpu5: completed 20000 read accesses @762156
|
||||
system.cpu4: completed 20000 read accesses @766351
|
||||
system.cpu6: completed 20000 read accesses @775961
|
||||
system.cpu7: completed 20000 read accesses @776472
|
||||
system.cpu2: completed 30000 read accesses @1125160
|
||||
system.cpu1: completed 30000 read accesses @1125369
|
||||
system.cpu0: completed 30000 read accesses @1130636
|
||||
system.cpu3: completed 30000 read accesses @1139985
|
||||
system.cpu5: completed 30000 read accesses @1141453
|
||||
system.cpu4: completed 30000 read accesses @1142264
|
||||
system.cpu6: completed 30000 read accesses @1154957
|
||||
system.cpu7: completed 30000 read accesses @1163543
|
||||
system.cpu2: completed 40000 read accesses @1501376
|
||||
system.cpu1: completed 40000 read accesses @1506717
|
||||
system.cpu0: completed 40000 read accesses @1507617
|
||||
system.cpu3: completed 40000 read accesses @1521033
|
||||
system.cpu4: completed 40000 read accesses @1523666
|
||||
system.cpu5: completed 40000 read accesses @1527373
|
||||
system.cpu6: completed 40000 read accesses @1547890
|
||||
system.cpu7: completed 40000 read accesses @1551332
|
||||
system.cpu2: completed 50000 read accesses @1879261
|
||||
system.cpu0: completed 50000 read accesses @1879360
|
||||
system.cpu1: completed 50000 read accesses @1885794
|
||||
system.cpu3: completed 50000 read accesses @1900931
|
||||
system.cpu4: completed 50000 read accesses @1902181
|
||||
system.cpu5: completed 50000 read accesses @1910820
|
||||
system.cpu6: completed 50000 read accesses @1931247
|
||||
system.cpu7: completed 50000 read accesses @1940656
|
||||
system.cpu0: completed 60000 read accesses @2246405
|
||||
system.cpu1: completed 60000 read accesses @2255112
|
||||
system.cpu2: completed 60000 read accesses @2258276
|
||||
system.cpu3: completed 60000 read accesses @2284120
|
||||
system.cpu4: completed 60000 read accesses @2284604
|
||||
system.cpu5: completed 60000 read accesses @2293116
|
||||
system.cpu6: completed 60000 read accesses @2311203
|
||||
system.cpu7: completed 60000 read accesses @2336896
|
||||
system.cpu0: completed 70000 read accesses @2626542
|
||||
system.cpu1: completed 70000 read accesses @2633209
|
||||
system.cpu2: completed 70000 read accesses @2638509
|
||||
system.cpu4: completed 70000 read accesses @2659805
|
||||
system.cpu3: completed 70000 read accesses @2663605
|
||||
system.cpu5: completed 70000 read accesses @2671213
|
||||
system.cpu6: completed 70000 read accesses @2693680
|
||||
system.cpu7: completed 70000 read accesses @2725734
|
||||
system.cpu0: completed 80000 read accesses @2999116
|
||||
system.cpu1: completed 80000 read accesses @3008858
|
||||
system.cpu2: completed 80000 read accesses @3014566
|
||||
system.cpu3: completed 80000 read accesses @3028069
|
||||
system.cpu4: completed 80000 read accesses @3040014
|
||||
system.cpu5: completed 80000 read accesses @3055346
|
||||
system.cpu6: completed 80000 read accesses @3080851
|
||||
system.cpu7: completed 80000 read accesses @3115153
|
||||
system.cpu0: completed 90000 read accesses @3374370
|
||||
system.cpu1: completed 90000 read accesses @3384044
|
||||
system.cpu2: completed 90000 read accesses @3385035
|
||||
system.cpu3: completed 90000 read accesses @3412877
|
||||
system.cpu4: completed 90000 read accesses @3422171
|
||||
system.cpu5: completed 90000 read accesses @3435207
|
||||
system.cpu6: completed 90000 read accesses @3466955
|
||||
system.cpu7: completed 90000 read accesses @3499833
|
||||
system.cpu0: completed 100000 read accesses @3750455
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 1 2010 14:38:07
|
||||
M5 revision acd9f15a9c7c 7493 default qtip tip simobj-parent-fix-stats-udpate
|
||||
M5 started Jul 1 2010 14:39:45
|
||||
M5 executing on phenom
|
||||
command line: build/ALPHA_SE_MESI_CMP_directory/m5.opt -d build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory
|
||||
M5 compiled Aug 20 2010 12:04:46
|
||||
M5 revision c4b5df973361 7570 default qtip tip brad/regress_updates
|
||||
M5 started Aug 20 2010 12:05:10
|
||||
M5 executing on SC2B0629
|
||||
command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 3725190 because maximum number of loads reached
|
||||
Exiting @ tick 3750455 because maximum number of loads reached
|
||||
|
|
|
|||
|
|
@ -1,34 +1,34 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_mem_usage 332596 # Number of bytes of host memory used
|
||||
host_seconds 35.19 # Real time elapsed on the host
|
||||
host_tick_rate 105869 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 341480 # Number of bytes of host memory used
|
||||
host_seconds 39.63 # Real time elapsed on the host
|
||||
host_tick_rate 94625 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_seconds 0.003725 # Number of seconds simulated
|
||||
sim_ticks 3725190 # Number of ticks simulated
|
||||
sim_seconds 0.003750 # Number of seconds simulated
|
||||
sim_ticks 3750455 # Number of ticks simulated
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
system.cpu0.num_reads 100000 # number of read accesses completed
|
||||
system.cpu0.num_writes 53802 # number of write accesses completed
|
||||
system.cpu0.num_writes 54108 # number of write accesses completed
|
||||
system.cpu1.num_copies 0 # number of copy accesses completed
|
||||
system.cpu1.num_reads 99730 # number of read accesses completed
|
||||
system.cpu1.num_writes 53651 # number of write accesses completed
|
||||
system.cpu1.num_reads 99918 # number of read accesses completed
|
||||
system.cpu1.num_writes 53757 # number of write accesses completed
|
||||
system.cpu2.num_copies 0 # number of copy accesses completed
|
||||
system.cpu2.num_reads 99194 # number of read accesses completed
|
||||
system.cpu2.num_writes 53071 # number of write accesses completed
|
||||
system.cpu2.num_reads 99521 # number of read accesses completed
|
||||
system.cpu2.num_writes 53948 # number of write accesses completed
|
||||
system.cpu3.num_copies 0 # number of copy accesses completed
|
||||
system.cpu3.num_reads 98275 # number of read accesses completed
|
||||
system.cpu3.num_writes 53108 # number of write accesses completed
|
||||
system.cpu3.num_reads 98786 # number of read accesses completed
|
||||
system.cpu3.num_writes 53362 # number of write accesses completed
|
||||
system.cpu4.num_copies 0 # number of copy accesses completed
|
||||
system.cpu4.num_reads 98291 # number of read accesses completed
|
||||
system.cpu4.num_writes 52851 # number of write accesses completed
|
||||
system.cpu4.num_reads 98631 # number of read accesses completed
|
||||
system.cpu4.num_writes 52746 # number of write accesses completed
|
||||
system.cpu5.num_copies 0 # number of copy accesses completed
|
||||
system.cpu5.num_reads 97729 # number of read accesses completed
|
||||
system.cpu5.num_writes 52263 # number of write accesses completed
|
||||
system.cpu5.num_reads 98242 # number of read accesses completed
|
||||
system.cpu5.num_writes 52924 # number of write accesses completed
|
||||
system.cpu6.num_copies 0 # number of copy accesses completed
|
||||
system.cpu6.num_reads 97202 # number of read accesses completed
|
||||
system.cpu6.num_writes 51897 # number of write accesses completed
|
||||
system.cpu6.num_reads 97407 # number of read accesses completed
|
||||
system.cpu6.num_writes 52658 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
system.cpu7.num_reads 96111 # number of read accesses completed
|
||||
system.cpu7.num_writes 51731 # number of write accesses completed
|
||||
system.cpu7.num_reads 96638 # number of read accesses completed
|
||||
system.cpu7.num_writes 51757 # number of write accesses completed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -5,13 +5,14 @@ dummy=0
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcmem physmem ruby
|
||||
children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 physmem ruby
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
|
||||
[system.cpu0]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -27,6 +28,7 @@ test=system.ruby.cpu_ruby_ports0.port[0]
|
|||
[system.cpu1]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -42,6 +44,7 @@ test=system.ruby.cpu_ruby_ports1.port[0]
|
|||
[system.cpu2]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -57,6 +60,7 @@ test=system.ruby.cpu_ruby_ports2.port[0]
|
|||
[system.cpu3]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -72,6 +76,7 @@ test=system.ruby.cpu_ruby_ports3.port[0]
|
|||
[system.cpu4]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -87,6 +92,7 @@ test=system.ruby.cpu_ruby_ports4.port[0]
|
|||
[system.cpu5]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -102,6 +108,7 @@ test=system.ruby.cpu_ruby_ports5.port[0]
|
|||
[system.cpu6]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -117,6 +124,7 @@ test=system.ruby.cpu_ruby_ports6.port[0]
|
|||
[system.cpu7]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -129,6 +137,47 @@ trace_addr=0
|
|||
functional=system.funcmem.port[7]
|
||||
test=system.ruby.cpu_ruby_ports7.port[0]
|
||||
|
||||
[system.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
directory=system.dir_cntrl0.directory
|
||||
directory_latency=6
|
||||
memBuffer=system.dir_cntrl0.memBuffer
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=6
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.funcmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
|
|
@ -139,6 +188,266 @@ range=0:134217727
|
|||
zero=false
|
||||
port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
|
||||
|
||||
[system.l1_cntrl0]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
sequencer=system.ruby.cpu_ruby_ports0
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl1]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.l1_cntrl1.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl1.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
sequencer=system.ruby.cpu_ruby_ports1
|
||||
transitions_per_cycle=32
|
||||
version=1
|
||||
|
||||
[system.l1_cntrl1.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl1.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl2]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.l1_cntrl2.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl2.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
sequencer=system.ruby.cpu_ruby_ports2
|
||||
transitions_per_cycle=32
|
||||
version=2
|
||||
|
||||
[system.l1_cntrl2.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl2.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl3]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.l1_cntrl3.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl3.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
sequencer=system.ruby.cpu_ruby_ports3
|
||||
transitions_per_cycle=32
|
||||
version=3
|
||||
|
||||
[system.l1_cntrl3.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl3.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl4]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.l1_cntrl4.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl4.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
sequencer=system.ruby.cpu_ruby_ports4
|
||||
transitions_per_cycle=32
|
||||
version=4
|
||||
|
||||
[system.l1_cntrl4.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl4.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl5]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.l1_cntrl5.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl5.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
sequencer=system.ruby.cpu_ruby_ports5
|
||||
transitions_per_cycle=32
|
||||
version=5
|
||||
|
||||
[system.l1_cntrl5.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl5.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl6]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.l1_cntrl6.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl6.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
sequencer=system.ruby.cpu_ruby_ports6
|
||||
transitions_per_cycle=32
|
||||
version=6
|
||||
|
||||
[system.l1_cntrl6.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl6.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl7]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.l1_cntrl7.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl7.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
sequencer=system.ruby.cpu_ruby_ports7
|
||||
transitions_per_cycle=32
|
||||
version=7
|
||||
|
||||
[system.l1_cntrl7.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl7.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l2_cntrl0]
|
||||
type=L2Cache_Controller
|
||||
children=L2cacheMemory
|
||||
L2cacheMemory=system.l2_cntrl0.L2cacheMemory
|
||||
buffer_size=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
response_latency=2
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l2_cntrl0.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=15
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
start_index_bit=6
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
|
|
@ -166,9 +475,9 @@ tracer=system.ruby.tracer
|
|||
|
||||
[system.ruby.cpu_ruby_ports0]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory
|
||||
dcache=system.l1_cntrl0.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory
|
||||
icache=system.l1_cntrl0.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
|
|
@ -178,9 +487,9 @@ port=system.cpu0.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports1]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory
|
||||
dcache=system.l1_cntrl1.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory
|
||||
icache=system.l1_cntrl1.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
|
|
@ -190,9 +499,9 @@ port=system.cpu1.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports2]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory
|
||||
dcache=system.l1_cntrl2.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory
|
||||
icache=system.l1_cntrl2.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
|
|
@ -202,9 +511,9 @@ port=system.cpu2.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports3]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory
|
||||
dcache=system.l1_cntrl3.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory
|
||||
icache=system.l1_cntrl3.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
|
|
@ -214,9 +523,9 @@ port=system.cpu3.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports4]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory
|
||||
dcache=system.l1_cntrl4.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory
|
||||
icache=system.l1_cntrl4.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
|
|
@ -226,9 +535,9 @@ port=system.cpu4.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports5]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory
|
||||
dcache=system.l1_cntrl5.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory
|
||||
icache=system.l1_cntrl5.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
|
|
@ -238,9 +547,9 @@ port=system.cpu5.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports6]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory
|
||||
dcache=system.l1_cntrl6.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory
|
||||
icache=system.l1_cntrl6.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
|
|
@ -250,9 +559,9 @@ port=system.cpu6.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports7]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory
|
||||
dcache=system.l1_cntrl7.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory
|
||||
icache=system.l1_cntrl7.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
|
|
@ -282,6 +591,7 @@ topology=system.ruby.network.topology
|
|||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 ext_links9 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 int_links9
|
||||
description=Crossbar
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8 system.ruby.network.topology.ext_links9
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8 system.ruby.network.topology.int_links9
|
||||
num_int_nodes=11
|
||||
|
|
@ -289,378 +599,84 @@ print_config=false
|
|||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links0.ext_node
|
||||
ext_node=system.l1_cntrl0
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
sequencer=system.ruby.cpu_ruby_ports0
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links1.ext_node
|
||||
ext_node=system.l1_cntrl1
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
sequencer=system.ruby.cpu_ruby_ports1
|
||||
transitions_per_cycle=32
|
||||
version=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links2]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links2.ext_node
|
||||
ext_node=system.l1_cntrl2
|
||||
int_node=2
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
sequencer=system.ruby.cpu_ruby_ports2
|
||||
transitions_per_cycle=32
|
||||
version=2
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links3]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links3.ext_node
|
||||
ext_node=system.l1_cntrl3
|
||||
int_node=3
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links3.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
sequencer=system.ruby.cpu_ruby_ports3
|
||||
transitions_per_cycle=32
|
||||
version=3
|
||||
|
||||
[system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links4]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links4.ext_node
|
||||
ext_node=system.l1_cntrl4
|
||||
int_node=4
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links4.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
sequencer=system.ruby.cpu_ruby_ports4
|
||||
transitions_per_cycle=32
|
||||
version=4
|
||||
|
||||
[system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links5]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links5.ext_node
|
||||
ext_node=system.l1_cntrl5
|
||||
int_node=5
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links5.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
sequencer=system.ruby.cpu_ruby_ports5
|
||||
transitions_per_cycle=32
|
||||
version=5
|
||||
|
||||
[system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links6]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links6.ext_node
|
||||
ext_node=system.l1_cntrl6
|
||||
int_node=6
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links6.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
sequencer=system.ruby.cpu_ruby_ports6
|
||||
transitions_per_cycle=32
|
||||
version=6
|
||||
|
||||
[system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links7]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links7.ext_node
|
||||
ext_node=system.l1_cntrl7
|
||||
int_node=7
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links7.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
sequencer=system.ruby.cpu_ruby_ports7
|
||||
transitions_per_cycle=32
|
||||
version=7
|
||||
|
||||
[system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links8]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links8.ext_node
|
||||
ext_node=system.l2_cntrl0
|
||||
int_node=8
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links8.ext_node]
|
||||
type=L2Cache_Controller
|
||||
children=L2cacheMemory
|
||||
L2cacheMemory=system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory
|
||||
buffer_size=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
response_latency=2
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=15
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
||||
[system.ruby.network.topology.ext_links9]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links9.ext_node
|
||||
ext_node=system.dir_cntrl0
|
||||
int_node=9
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links9.ext_node]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
directory=system.ruby.network.topology.ext_links9.ext_node.directory
|
||||
directory_latency=6
|
||||
memBuffer=system.ruby.network.topology.ext_links9.ext_node.memBuffer
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links9.ext_node.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=0
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links9.ext_node.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.int_links0]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,74 +1,74 @@
|
|||
system.cpu6: completed 10000 read accesses @325901
|
||||
system.cpu4: completed 10000 read accesses @333477
|
||||
system.cpu2: completed 10000 read accesses @337264
|
||||
system.cpu7: completed 10000 read accesses @338212
|
||||
system.cpu0: completed 10000 read accesses @341315
|
||||
system.cpu5: completed 10000 read accesses @343794
|
||||
system.cpu1: completed 10000 read accesses @347258
|
||||
system.cpu3: completed 10000 read accesses @349679
|
||||
system.cpu6: completed 20000 read accesses @662679
|
||||
system.cpu7: completed 20000 read accesses @663435
|
||||
system.cpu4: completed 20000 read accesses @670972
|
||||
system.cpu1: completed 20000 read accesses @674886
|
||||
system.cpu2: completed 20000 read accesses @675526
|
||||
system.cpu0: completed 20000 read accesses @687421
|
||||
system.cpu5: completed 20000 read accesses @695852
|
||||
system.cpu3: completed 20000 read accesses @698570
|
||||
system.cpu6: completed 30000 read accesses @1001408
|
||||
system.cpu1: completed 30000 read accesses @1004487
|
||||
system.cpu2: completed 30000 read accesses @1007345
|
||||
system.cpu4: completed 30000 read accesses @1009967
|
||||
system.cpu0: completed 30000 read accesses @1021321
|
||||
system.cpu7: completed 30000 read accesses @1025248
|
||||
system.cpu3: completed 30000 read accesses @1040400
|
||||
system.cpu5: completed 30000 read accesses @1042444
|
||||
system.cpu6: completed 40000 read accesses @1335158
|
||||
system.cpu1: completed 40000 read accesses @1341837
|
||||
system.cpu4: completed 40000 read accesses @1347757
|
||||
system.cpu2: completed 40000 read accesses @1348137
|
||||
system.cpu3: completed 40000 read accesses @1370930
|
||||
system.cpu0: completed 40000 read accesses @1372862
|
||||
system.cpu7: completed 40000 read accesses @1374480
|
||||
system.cpu5: completed 40000 read accesses @1395059
|
||||
system.cpu6: completed 50000 read accesses @1663756
|
||||
system.cpu2: completed 50000 read accesses @1676262
|
||||
system.cpu1: completed 50000 read accesses @1676376
|
||||
system.cpu4: completed 50000 read accesses @1689367
|
||||
system.cpu3: completed 50000 read accesses @1707722
|
||||
system.cpu7: completed 50000 read accesses @1715376
|
||||
system.cpu0: completed 50000 read accesses @1719053
|
||||
system.cpu5: completed 50000 read accesses @1756410
|
||||
system.cpu2: completed 60000 read accesses @1996507
|
||||
system.cpu6: completed 60000 read accesses @2009287
|
||||
system.cpu1: completed 60000 read accesses @2021631
|
||||
system.cpu4: completed 60000 read accesses @2032125
|
||||
system.cpu3: completed 60000 read accesses @2046121
|
||||
system.cpu7: completed 60000 read accesses @2054305
|
||||
system.cpu0: completed 60000 read accesses @2067865
|
||||
system.cpu5: completed 60000 read accesses @2103289
|
||||
system.cpu2: completed 70000 read accesses @2336053
|
||||
system.cpu6: completed 70000 read accesses @2351727
|
||||
system.cpu1: completed 70000 read accesses @2362242
|
||||
system.cpu3: completed 70000 read accesses @2365041
|
||||
system.cpu4: completed 70000 read accesses @2374894
|
||||
system.cpu7: completed 70000 read accesses @2393230
|
||||
system.cpu0: completed 70000 read accesses @2409417
|
||||
system.cpu5: completed 70000 read accesses @2444673
|
||||
system.cpu2: completed 80000 read accesses @2681751
|
||||
system.cpu1: completed 80000 read accesses @2695221
|
||||
system.cpu6: completed 80000 read accesses @2701603
|
||||
system.cpu3: completed 80000 read accesses @2708122
|
||||
system.cpu4: completed 80000 read accesses @2715599
|
||||
system.cpu7: completed 80000 read accesses @2739434
|
||||
system.cpu0: completed 80000 read accesses @2743943
|
||||
system.cpu5: completed 80000 read accesses @2780520
|
||||
system.cpu2: completed 90000 read accesses @3022424
|
||||
system.cpu1: completed 90000 read accesses @3030742
|
||||
system.cpu3: completed 90000 read accesses @3042635
|
||||
system.cpu6: completed 90000 read accesses @3050919
|
||||
system.cpu4: completed 90000 read accesses @3054095
|
||||
system.cpu0: completed 90000 read accesses @3084803
|
||||
system.cpu7: completed 90000 read accesses @3091274
|
||||
system.cpu5: completed 90000 read accesses @3116487
|
||||
system.cpu2: completed 100000 read accesses @3358188
|
||||
system.cpu3: completed 10000 read accesses @323743
|
||||
system.cpu2: completed 10000 read accesses @336402
|
||||
system.cpu1: completed 10000 read accesses @338132
|
||||
system.cpu0: completed 10000 read accesses @340751
|
||||
system.cpu5: completed 10000 read accesses @341263
|
||||
system.cpu4: completed 10000 read accesses @346558
|
||||
system.cpu7: completed 10000 read accesses @346738
|
||||
system.cpu6: completed 10000 read accesses @348135
|
||||
system.cpu3: completed 20000 read accesses @670303
|
||||
system.cpu0: completed 20000 read accesses @670934
|
||||
system.cpu2: completed 20000 read accesses @675651
|
||||
system.cpu1: completed 20000 read accesses @679374
|
||||
system.cpu6: completed 20000 read accesses @683883
|
||||
system.cpu7: completed 20000 read accesses @684999
|
||||
system.cpu4: completed 20000 read accesses @688475
|
||||
system.cpu5: completed 20000 read accesses @691089
|
||||
system.cpu3: completed 30000 read accesses @1012754
|
||||
system.cpu2: completed 30000 read accesses @1013014
|
||||
system.cpu5: completed 30000 read accesses @1015303
|
||||
system.cpu0: completed 30000 read accesses @1018359
|
||||
system.cpu1: completed 30000 read accesses @1021563
|
||||
system.cpu4: completed 30000 read accesses @1024489
|
||||
system.cpu6: completed 30000 read accesses @1024945
|
||||
system.cpu7: completed 30000 read accesses @1026805
|
||||
system.cpu3: completed 40000 read accesses @1337640
|
||||
system.cpu4: completed 40000 read accesses @1353749
|
||||
system.cpu5: completed 40000 read accesses @1355921
|
||||
system.cpu2: completed 40000 read accesses @1358297
|
||||
system.cpu0: completed 40000 read accesses @1365879
|
||||
system.cpu7: completed 40000 read accesses @1368402
|
||||
system.cpu6: completed 40000 read accesses @1369510
|
||||
system.cpu1: completed 40000 read accesses @1372174
|
||||
system.cpu3: completed 50000 read accesses @1687319
|
||||
system.cpu4: completed 50000 read accesses @1694511
|
||||
system.cpu7: completed 50000 read accesses @1696243
|
||||
system.cpu2: completed 50000 read accesses @1699794
|
||||
system.cpu5: completed 50000 read accesses @1700188
|
||||
system.cpu6: completed 50000 read accesses @1703368
|
||||
system.cpu0: completed 50000 read accesses @1704599
|
||||
system.cpu1: completed 50000 read accesses @1716501
|
||||
system.cpu4: completed 60000 read accesses @2030412
|
||||
system.cpu3: completed 60000 read accesses @2034929
|
||||
system.cpu2: completed 60000 read accesses @2036378
|
||||
system.cpu7: completed 60000 read accesses @2036726
|
||||
system.cpu0: completed 60000 read accesses @2038738
|
||||
system.cpu5: completed 60000 read accesses @2046852
|
||||
system.cpu1: completed 60000 read accesses @2050784
|
||||
system.cpu6: completed 60000 read accesses @2058109
|
||||
system.cpu3: completed 70000 read accesses @2359493
|
||||
system.cpu4: completed 70000 read accesses @2365063
|
||||
system.cpu2: completed 70000 read accesses @2371739
|
||||
system.cpu0: completed 70000 read accesses @2373666
|
||||
system.cpu7: completed 70000 read accesses @2373767
|
||||
system.cpu5: completed 70000 read accesses @2395804
|
||||
system.cpu1: completed 70000 read accesses @2404686
|
||||
system.cpu6: completed 70000 read accesses @2406335
|
||||
system.cpu2: completed 80000 read accesses @2701352
|
||||
system.cpu7: completed 80000 read accesses @2705729
|
||||
system.cpu3: completed 80000 read accesses @2707362
|
||||
system.cpu4: completed 80000 read accesses @2711169
|
||||
system.cpu0: completed 80000 read accesses @2718197
|
||||
system.cpu1: completed 80000 read accesses @2736476
|
||||
system.cpu6: completed 80000 read accesses @2746379
|
||||
system.cpu5: completed 80000 read accesses @2751740
|
||||
system.cpu2: completed 90000 read accesses @3041770
|
||||
system.cpu3: completed 90000 read accesses @3048359
|
||||
system.cpu7: completed 90000 read accesses @3049406
|
||||
system.cpu0: completed 90000 read accesses @3052026
|
||||
system.cpu4: completed 90000 read accesses @3061142
|
||||
system.cpu1: completed 90000 read accesses @3064341
|
||||
system.cpu6: completed 90000 read accesses @3079121
|
||||
system.cpu5: completed 90000 read accesses @3089679
|
||||
system.cpu2: completed 100000 read accesses @3377485
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 1 2010 14:38:10
|
||||
M5 revision acd9f15a9c7c 7493 default qtip tip simobj-parent-fix-stats-udpate
|
||||
M5 started Jul 1 2010 14:39:45
|
||||
M5 executing on phenom
|
||||
command line: build/ALPHA_SE_MOESI_CMP_directory/m5.opt -d build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory
|
||||
M5 compiled Aug 20 2010 12:10:28
|
||||
M5 revision c4b5df973361+ 7570+ default qtip tip brad/regress_updates
|
||||
M5 started Aug 20 2010 12:10:38
|
||||
M5 executing on SC2B0629
|
||||
command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 3358188 because maximum number of loads reached
|
||||
Exiting @ tick 3377485 because maximum number of loads reached
|
||||
|
|
|
|||
|
|
@ -1,34 +1,34 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_mem_usage 332872 # Number of bytes of host memory used
|
||||
host_seconds 24.53 # Real time elapsed on the host
|
||||
host_tick_rate 136908 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 341856 # Number of bytes of host memory used
|
||||
host_seconds 29.56 # Real time elapsed on the host
|
||||
host_tick_rate 114257 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_seconds 0.003358 # Number of seconds simulated
|
||||
sim_ticks 3358188 # Number of ticks simulated
|
||||
sim_seconds 0.003377 # Number of seconds simulated
|
||||
sim_ticks 3377485 # Number of ticks simulated
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
system.cpu0.num_reads 98036 # number of read accesses completed
|
||||
system.cpu0.num_writes 52677 # number of write accesses completed
|
||||
system.cpu0.num_reads 99116 # number of read accesses completed
|
||||
system.cpu0.num_writes 53019 # number of write accesses completed
|
||||
system.cpu1.num_copies 0 # number of copy accesses completed
|
||||
system.cpu1.num_reads 99903 # number of read accesses completed
|
||||
system.cpu1.num_writes 53671 # number of write accesses completed
|
||||
system.cpu1.num_reads 99151 # number of read accesses completed
|
||||
system.cpu1.num_writes 53486 # number of write accesses completed
|
||||
system.cpu2.num_copies 0 # number of copy accesses completed
|
||||
system.cpu2.num_reads 100000 # number of read accesses completed
|
||||
system.cpu2.num_writes 53360 # number of write accesses completed
|
||||
system.cpu2.num_writes 53183 # number of write accesses completed
|
||||
system.cpu3.num_copies 0 # number of copy accesses completed
|
||||
system.cpu3.num_reads 99545 # number of read accesses completed
|
||||
system.cpu3.num_writes 53578 # number of write accesses completed
|
||||
system.cpu3.num_reads 99632 # number of read accesses completed
|
||||
system.cpu3.num_writes 54001 # number of write accesses completed
|
||||
system.cpu4.num_copies 0 # number of copy accesses completed
|
||||
system.cpu4.num_reads 99118 # number of read accesses completed
|
||||
system.cpu4.num_writes 53226 # number of write accesses completed
|
||||
system.cpu4.num_reads 99186 # number of read accesses completed
|
||||
system.cpu4.num_writes 53590 # number of write accesses completed
|
||||
system.cpu5.num_copies 0 # number of copy accesses completed
|
||||
system.cpu5.num_reads 96991 # number of read accesses completed
|
||||
system.cpu5.num_writes 52753 # number of write accesses completed
|
||||
system.cpu5.num_reads 98345 # number of read accesses completed
|
||||
system.cpu5.num_writes 53268 # number of write accesses completed
|
||||
system.cpu6.num_copies 0 # number of copy accesses completed
|
||||
system.cpu6.num_reads 98713 # number of read accesses completed
|
||||
system.cpu6.num_writes 52958 # number of write accesses completed
|
||||
system.cpu6.num_reads 99155 # number of read accesses completed
|
||||
system.cpu6.num_writes 53749 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
system.cpu7.num_reads 97919 # number of read accesses completed
|
||||
system.cpu7.num_writes 52935 # number of write accesses completed
|
||||
system.cpu7.num_reads 99644 # number of read accesses completed
|
||||
system.cpu7.num_writes 53528 # number of write accesses completed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -5,13 +5,14 @@ dummy=0
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcmem physmem ruby
|
||||
children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 physmem ruby
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
|
||||
[system.cpu0]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -27,6 +28,7 @@ test=system.ruby.cpu_ruby_ports0.port[0]
|
|||
[system.cpu1]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -42,6 +44,7 @@ test=system.ruby.cpu_ruby_ports1.port[0]
|
|||
[system.cpu2]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -57,6 +60,7 @@ test=system.ruby.cpu_ruby_ports2.port[0]
|
|||
[system.cpu3]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -72,6 +76,7 @@ test=system.ruby.cpu_ruby_ports3.port[0]
|
|||
[system.cpu4]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -87,6 +92,7 @@ test=system.ruby.cpu_ruby_ports4.port[0]
|
|||
[system.cpu5]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -102,6 +108,7 @@ test=system.ruby.cpu_ruby_ports5.port[0]
|
|||
[system.cpu6]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -117,6 +124,7 @@ test=system.ruby.cpu_ruby_ports6.port[0]
|
|||
[system.cpu7]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -129,6 +137,50 @@ trace_addr=0
|
|||
functional=system.funcmem.port[7]
|
||||
test=system.ruby.cpu_ruby_ports7.port[0]
|
||||
|
||||
[system.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
directory=system.dir_cntrl0.directory
|
||||
directory_latency=5
|
||||
distributed_persistent=true
|
||||
fixed_timeout_latency=100
|
||||
l2_select_num_bits=0
|
||||
memBuffer=system.dir_cntrl0.memBuffer
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=6
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.funcmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
|
|
@ -139,6 +191,316 @@ range=0:134217727
|
|||
zero=false
|
||||
port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
|
||||
|
||||
[system.l1_cntrl0]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
|
||||
N_tokens=9
|
||||
buffer_size=0
|
||||
dynamic_timeout_enabled=true
|
||||
fixed_timeout_latency=300
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
sequencer=system.ruby.cpu_ruby_ports0
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl1]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.l1_cntrl1.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl1.L1IcacheMemory
|
||||
N_tokens=9
|
||||
buffer_size=0
|
||||
dynamic_timeout_enabled=true
|
||||
fixed_timeout_latency=300
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
sequencer=system.ruby.cpu_ruby_ports1
|
||||
transitions_per_cycle=32
|
||||
version=1
|
||||
|
||||
[system.l1_cntrl1.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl1.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl2]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.l1_cntrl2.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl2.L1IcacheMemory
|
||||
N_tokens=9
|
||||
buffer_size=0
|
||||
dynamic_timeout_enabled=true
|
||||
fixed_timeout_latency=300
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
sequencer=system.ruby.cpu_ruby_ports2
|
||||
transitions_per_cycle=32
|
||||
version=2
|
||||
|
||||
[system.l1_cntrl2.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl2.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl3]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.l1_cntrl3.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl3.L1IcacheMemory
|
||||
N_tokens=9
|
||||
buffer_size=0
|
||||
dynamic_timeout_enabled=true
|
||||
fixed_timeout_latency=300
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
sequencer=system.ruby.cpu_ruby_ports3
|
||||
transitions_per_cycle=32
|
||||
version=3
|
||||
|
||||
[system.l1_cntrl3.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl3.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl4]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.l1_cntrl4.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl4.L1IcacheMemory
|
||||
N_tokens=9
|
||||
buffer_size=0
|
||||
dynamic_timeout_enabled=true
|
||||
fixed_timeout_latency=300
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
sequencer=system.ruby.cpu_ruby_ports4
|
||||
transitions_per_cycle=32
|
||||
version=4
|
||||
|
||||
[system.l1_cntrl4.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl4.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl5]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.l1_cntrl5.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl5.L1IcacheMemory
|
||||
N_tokens=9
|
||||
buffer_size=0
|
||||
dynamic_timeout_enabled=true
|
||||
fixed_timeout_latency=300
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
sequencer=system.ruby.cpu_ruby_ports5
|
||||
transitions_per_cycle=32
|
||||
version=5
|
||||
|
||||
[system.l1_cntrl5.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl5.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl6]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.l1_cntrl6.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl6.L1IcacheMemory
|
||||
N_tokens=9
|
||||
buffer_size=0
|
||||
dynamic_timeout_enabled=true
|
||||
fixed_timeout_latency=300
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
sequencer=system.ruby.cpu_ruby_ports6
|
||||
transitions_per_cycle=32
|
||||
version=6
|
||||
|
||||
[system.l1_cntrl6.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl6.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl7]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.l1_cntrl7.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl7.L1IcacheMemory
|
||||
N_tokens=9
|
||||
buffer_size=0
|
||||
dynamic_timeout_enabled=true
|
||||
fixed_timeout_latency=300
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
sequencer=system.ruby.cpu_ruby_ports7
|
||||
transitions_per_cycle=32
|
||||
version=7
|
||||
|
||||
[system.l1_cntrl7.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl7.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l2_cntrl0]
|
||||
type=L2Cache_Controller
|
||||
children=L2cacheMemory
|
||||
L2cacheMemory=system.l2_cntrl0.L2cacheMemory
|
||||
N_tokens=9
|
||||
buffer_size=0
|
||||
filtering_enabled=true
|
||||
l2_request_latency=5
|
||||
l2_response_latency=5
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l2_cntrl0.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=10
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
start_index_bit=0
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
|
|
@ -166,9 +528,9 @@ tracer=system.ruby.tracer
|
|||
|
||||
[system.ruby.cpu_ruby_ports0]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory
|
||||
dcache=system.l1_cntrl0.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory
|
||||
icache=system.l1_cntrl0.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
|
|
@ -178,9 +540,9 @@ port=system.cpu0.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports1]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory
|
||||
dcache=system.l1_cntrl1.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory
|
||||
icache=system.l1_cntrl1.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
|
|
@ -190,9 +552,9 @@ port=system.cpu1.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports2]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory
|
||||
dcache=system.l1_cntrl2.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory
|
||||
icache=system.l1_cntrl2.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
|
|
@ -202,9 +564,9 @@ port=system.cpu2.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports3]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory
|
||||
dcache=system.l1_cntrl3.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory
|
||||
icache=system.l1_cntrl3.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
|
|
@ -214,9 +576,9 @@ port=system.cpu3.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports4]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory
|
||||
dcache=system.l1_cntrl4.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory
|
||||
icache=system.l1_cntrl4.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
|
|
@ -226,9 +588,9 @@ port=system.cpu4.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports5]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory
|
||||
dcache=system.l1_cntrl5.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory
|
||||
icache=system.l1_cntrl5.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
|
|
@ -238,9 +600,9 @@ port=system.cpu5.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports6]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory
|
||||
dcache=system.l1_cntrl6.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory
|
||||
icache=system.l1_cntrl6.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
|
|
@ -250,9 +612,9 @@ port=system.cpu6.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports7]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory
|
||||
dcache=system.l1_cntrl7.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory
|
||||
icache=system.l1_cntrl7.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
|
|
@ -282,6 +644,7 @@ topology=system.ruby.network.topology
|
|||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 ext_links9 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 int_links9
|
||||
description=Crossbar
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8 system.ruby.network.topology.ext_links9
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8 system.ruby.network.topology.int_links9
|
||||
num_int_nodes=11
|
||||
|
|
@ -289,423 +652,84 @@ print_config=false
|
|||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links0.ext_node
|
||||
ext_node=system.l1_cntrl0
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory
|
||||
N_tokens=9
|
||||
buffer_size=0
|
||||
dynamic_timeout_enabled=true
|
||||
fixed_timeout_latency=300
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
sequencer=system.ruby.cpu_ruby_ports0
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links1.ext_node
|
||||
ext_node=system.l1_cntrl1
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory
|
||||
N_tokens=9
|
||||
buffer_size=0
|
||||
dynamic_timeout_enabled=true
|
||||
fixed_timeout_latency=300
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
sequencer=system.ruby.cpu_ruby_ports1
|
||||
transitions_per_cycle=32
|
||||
version=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links2]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links2.ext_node
|
||||
ext_node=system.l1_cntrl2
|
||||
int_node=2
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory
|
||||
N_tokens=9
|
||||
buffer_size=0
|
||||
dynamic_timeout_enabled=true
|
||||
fixed_timeout_latency=300
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
sequencer=system.ruby.cpu_ruby_ports2
|
||||
transitions_per_cycle=32
|
||||
version=2
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links3]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links3.ext_node
|
||||
ext_node=system.l1_cntrl3
|
||||
int_node=3
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links3.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory
|
||||
N_tokens=9
|
||||
buffer_size=0
|
||||
dynamic_timeout_enabled=true
|
||||
fixed_timeout_latency=300
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
sequencer=system.ruby.cpu_ruby_ports3
|
||||
transitions_per_cycle=32
|
||||
version=3
|
||||
|
||||
[system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links4]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links4.ext_node
|
||||
ext_node=system.l1_cntrl4
|
||||
int_node=4
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links4.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory
|
||||
N_tokens=9
|
||||
buffer_size=0
|
||||
dynamic_timeout_enabled=true
|
||||
fixed_timeout_latency=300
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
sequencer=system.ruby.cpu_ruby_ports4
|
||||
transitions_per_cycle=32
|
||||
version=4
|
||||
|
||||
[system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links5]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links5.ext_node
|
||||
ext_node=system.l1_cntrl5
|
||||
int_node=5
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links5.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory
|
||||
N_tokens=9
|
||||
buffer_size=0
|
||||
dynamic_timeout_enabled=true
|
||||
fixed_timeout_latency=300
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
sequencer=system.ruby.cpu_ruby_ports5
|
||||
transitions_per_cycle=32
|
||||
version=5
|
||||
|
||||
[system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links6]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links6.ext_node
|
||||
ext_node=system.l1_cntrl6
|
||||
int_node=6
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links6.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory
|
||||
N_tokens=9
|
||||
buffer_size=0
|
||||
dynamic_timeout_enabled=true
|
||||
fixed_timeout_latency=300
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
sequencer=system.ruby.cpu_ruby_ports6
|
||||
transitions_per_cycle=32
|
||||
version=6
|
||||
|
||||
[system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links7]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links7.ext_node
|
||||
ext_node=system.l1_cntrl7
|
||||
int_node=7
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links7.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory
|
||||
N_tokens=9
|
||||
buffer_size=0
|
||||
dynamic_timeout_enabled=true
|
||||
fixed_timeout_latency=300
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
sequencer=system.ruby.cpu_ruby_ports7
|
||||
transitions_per_cycle=32
|
||||
version=7
|
||||
|
||||
[system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links8]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links8.ext_node
|
||||
ext_node=system.l2_cntrl0
|
||||
int_node=8
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links8.ext_node]
|
||||
type=L2Cache_Controller
|
||||
children=L2cacheMemory
|
||||
L2cacheMemory=system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory
|
||||
N_tokens=9
|
||||
buffer_size=0
|
||||
filtering_enabled=true
|
||||
l2_request_latency=10
|
||||
l2_response_latency=10
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=15
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
||||
[system.ruby.network.topology.ext_links9]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links9.ext_node
|
||||
ext_node=system.dir_cntrl0
|
||||
int_node=9
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links9.ext_node]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
directory=system.ruby.network.topology.ext_links9.ext_node.directory
|
||||
directory_latency=6
|
||||
distributed_persistent=true
|
||||
fixed_timeout_latency=300
|
||||
l2_select_num_bits=0
|
||||
memBuffer=system.ruby.network.topology.ext_links9.ext_node.memBuffer
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links9.ext_node.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=0
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links9.ext_node.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.int_links0]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,74 +1,74 @@
|
|||
system.cpu2: completed 10000 read accesses @322194
|
||||
system.cpu0: completed 10000 read accesses @322719
|
||||
system.cpu5: completed 10000 read accesses @330050
|
||||
system.cpu7: completed 10000 read accesses @330574
|
||||
system.cpu6: completed 10000 read accesses @330892
|
||||
system.cpu4: completed 10000 read accesses @331172
|
||||
system.cpu1: completed 10000 read accesses @333911
|
||||
system.cpu3: completed 10000 read accesses @335019
|
||||
system.cpu0: completed 20000 read accesses @641579
|
||||
system.cpu2: completed 20000 read accesses @642932
|
||||
system.cpu6: completed 20000 read accesses @660969
|
||||
system.cpu4: completed 20000 read accesses @661309
|
||||
system.cpu5: completed 20000 read accesses @662083
|
||||
system.cpu7: completed 20000 read accesses @664047
|
||||
system.cpu1: completed 20000 read accesses @664884
|
||||
system.cpu3: completed 20000 read accesses @668081
|
||||
system.cpu0: completed 30000 read accesses @964302
|
||||
system.cpu2: completed 30000 read accesses @967590
|
||||
system.cpu4: completed 30000 read accesses @990023
|
||||
system.cpu7: completed 30000 read accesses @990043
|
||||
system.cpu6: completed 30000 read accesses @991961
|
||||
system.cpu5: completed 30000 read accesses @993160
|
||||
system.cpu1: completed 30000 read accesses @996431
|
||||
system.cpu3: completed 30000 read accesses @1001054
|
||||
system.cpu2: completed 40000 read accesses @1287629
|
||||
system.cpu0: completed 40000 read accesses @1291802
|
||||
system.cpu4: completed 40000 read accesses @1317065
|
||||
system.cpu7: completed 40000 read accesses @1322312
|
||||
system.cpu6: completed 40000 read accesses @1324580
|
||||
system.cpu5: completed 40000 read accesses @1326928
|
||||
system.cpu1: completed 40000 read accesses @1328485
|
||||
system.cpu3: completed 40000 read accesses @1330568
|
||||
system.cpu2: completed 50000 read accesses @1610807
|
||||
system.cpu0: completed 50000 read accesses @1611621
|
||||
system.cpu4: completed 50000 read accesses @1645302
|
||||
system.cpu7: completed 50000 read accesses @1650899
|
||||
system.cpu6: completed 50000 read accesses @1654396
|
||||
system.cpu5: completed 50000 read accesses @1657056
|
||||
system.cpu1: completed 50000 read accesses @1661586
|
||||
system.cpu3: completed 50000 read accesses @1662920
|
||||
system.cpu0: completed 60000 read accesses @1928533
|
||||
system.cpu2: completed 60000 read accesses @1935763
|
||||
system.cpu4: completed 60000 read accesses @1973168
|
||||
system.cpu7: completed 60000 read accesses @1985073
|
||||
system.cpu6: completed 60000 read accesses @1987312
|
||||
system.cpu1: completed 60000 read accesses @1992182
|
||||
system.cpu5: completed 60000 read accesses @1992692
|
||||
system.cpu3: completed 60000 read accesses @1994120
|
||||
system.cpu0: completed 70000 read accesses @2251425
|
||||
system.cpu2: completed 70000 read accesses @2258967
|
||||
system.cpu4: completed 70000 read accesses @2302588
|
||||
system.cpu6: completed 70000 read accesses @2314337
|
||||
system.cpu7: completed 70000 read accesses @2315937
|
||||
system.cpu5: completed 70000 read accesses @2322183
|
||||
system.cpu1: completed 70000 read accesses @2323330
|
||||
system.cpu3: completed 70000 read accesses @2326357
|
||||
system.cpu0: completed 80000 read accesses @2576249
|
||||
system.cpu2: completed 80000 read accesses @2582991
|
||||
system.cpu4: completed 80000 read accesses @2630111
|
||||
system.cpu6: completed 80000 read accesses @2644662
|
||||
system.cpu7: completed 80000 read accesses @2648201
|
||||
system.cpu1: completed 80000 read accesses @2650725
|
||||
system.cpu5: completed 80000 read accesses @2653106
|
||||
system.cpu3: completed 80000 read accesses @2653877
|
||||
system.cpu2: completed 90000 read accesses @2907948
|
||||
system.cpu0: completed 90000 read accesses @2917526
|
||||
system.cpu4: completed 90000 read accesses @2951732
|
||||
system.cpu6: completed 90000 read accesses @2969846
|
||||
system.cpu1: completed 90000 read accesses @2970686
|
||||
system.cpu3: completed 90000 read accesses @2978760
|
||||
system.cpu5: completed 90000 read accesses @2981622
|
||||
system.cpu7: completed 90000 read accesses @2987871
|
||||
system.cpu2: completed 100000 read accesses @3229931
|
||||
system.cpu0: completed 10000 read accesses @257947
|
||||
system.cpu1: completed 10000 read accesses @260311
|
||||
system.cpu3: completed 10000 read accesses @264703
|
||||
system.cpu7: completed 10000 read accesses @266036
|
||||
system.cpu5: completed 10000 read accesses @266378
|
||||
system.cpu4: completed 10000 read accesses @267169
|
||||
system.cpu2: completed 10000 read accesses @267625
|
||||
system.cpu6: completed 10000 read accesses @271366
|
||||
system.cpu0: completed 20000 read accesses @515410
|
||||
system.cpu1: completed 20000 read accesses @519078
|
||||
system.cpu7: completed 20000 read accesses @528562
|
||||
system.cpu3: completed 20000 read accesses @529556
|
||||
system.cpu5: completed 20000 read accesses @531753
|
||||
system.cpu4: completed 20000 read accesses @536204
|
||||
system.cpu6: completed 20000 read accesses @537031
|
||||
system.cpu2: completed 20000 read accesses @537314
|
||||
system.cpu0: completed 30000 read accesses @772994
|
||||
system.cpu1: completed 30000 read accesses @780923
|
||||
system.cpu3: completed 30000 read accesses @794263
|
||||
system.cpu7: completed 30000 read accesses @796675
|
||||
system.cpu4: completed 30000 read accesses @797063
|
||||
system.cpu5: completed 30000 read accesses @800026
|
||||
system.cpu2: completed 30000 read accesses @802601
|
||||
system.cpu6: completed 30000 read accesses @805267
|
||||
system.cpu0: completed 40000 read accesses @1033304
|
||||
system.cpu1: completed 40000 read accesses @1040457
|
||||
system.cpu3: completed 40000 read accesses @1058903
|
||||
system.cpu7: completed 40000 read accesses @1062178
|
||||
system.cpu5: completed 40000 read accesses @1064117
|
||||
system.cpu4: completed 40000 read accesses @1065423
|
||||
system.cpu6: completed 40000 read accesses @1066744
|
||||
system.cpu2: completed 40000 read accesses @1068649
|
||||
system.cpu0: completed 50000 read accesses @1292512
|
||||
system.cpu1: completed 50000 read accesses @1299935
|
||||
system.cpu3: completed 50000 read accesses @1324981
|
||||
system.cpu5: completed 50000 read accesses @1327818
|
||||
system.cpu7: completed 50000 read accesses @1328780
|
||||
system.cpu4: completed 50000 read accesses @1329164
|
||||
system.cpu6: completed 50000 read accesses @1332786
|
||||
system.cpu2: completed 50000 read accesses @1334645
|
||||
system.cpu0: completed 60000 read accesses @1550153
|
||||
system.cpu1: completed 60000 read accesses @1559435
|
||||
system.cpu7: completed 60000 read accesses @1591474
|
||||
system.cpu3: completed 60000 read accesses @1593078
|
||||
system.cpu4: completed 60000 read accesses @1594642
|
||||
system.cpu5: completed 60000 read accesses @1595392
|
||||
system.cpu2: completed 60000 read accesses @1600002
|
||||
system.cpu6: completed 60000 read accesses @1600595
|
||||
system.cpu0: completed 70000 read accesses @1802423
|
||||
system.cpu1: completed 70000 read accesses @1829858
|
||||
system.cpu7: completed 70000 read accesses @1853648
|
||||
system.cpu5: completed 70000 read accesses @1854214
|
||||
system.cpu3: completed 70000 read accesses @1854818
|
||||
system.cpu4: completed 70000 read accesses @1855726
|
||||
system.cpu6: completed 70000 read accesses @1868528
|
||||
system.cpu2: completed 70000 read accesses @1875446
|
||||
system.cpu0: completed 80000 read accesses @2061056
|
||||
system.cpu1: completed 80000 read accesses @2090957
|
||||
system.cpu7: completed 80000 read accesses @2119055
|
||||
system.cpu4: completed 80000 read accesses @2119432
|
||||
system.cpu5: completed 80000 read accesses @2121677
|
||||
system.cpu3: completed 80000 read accesses @2123217
|
||||
system.cpu6: completed 80000 read accesses @2133942
|
||||
system.cpu2: completed 80000 read accesses @2139530
|
||||
system.cpu0: completed 90000 read accesses @2322313
|
||||
system.cpu1: completed 90000 read accesses @2351193
|
||||
system.cpu4: completed 90000 read accesses @2382901
|
||||
system.cpu7: completed 90000 read accesses @2384445
|
||||
system.cpu5: completed 90000 read accesses @2387842
|
||||
system.cpu3: completed 90000 read accesses @2390630
|
||||
system.cpu6: completed 90000 read accesses @2400244
|
||||
system.cpu2: completed 90000 read accesses @2403389
|
||||
system.cpu0: completed 100000 read accesses @2583072
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 1 2010 14:39:47
|
||||
M5 revision acd9f15a9c7c 7493 default qtip tip simobj-parent-fix-stats-udpate
|
||||
M5 started Jul 1 2010 14:40:13
|
||||
M5 executing on phenom
|
||||
command line: build/ALPHA_SE_MOESI_CMP_token/m5.opt -d build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token
|
||||
M5 compiled Aug 20 2010 12:14:24
|
||||
M5 revision c4b5df973361+ 7570+ default qtip tip brad/regress_updates
|
||||
M5 started Aug 20 2010 12:14:33
|
||||
M5 executing on SC2B0629
|
||||
command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 3229931 because maximum number of loads reached
|
||||
Exiting @ tick 2583072 because maximum number of loads reached
|
||||
|
|
|
|||
|
|
@ -1,34 +1,34 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_mem_usage 332852 # Number of bytes of host memory used
|
||||
host_seconds 26.21 # Real time elapsed on the host
|
||||
host_tick_rate 123225 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 341980 # Number of bytes of host memory used
|
||||
host_seconds 25.58 # Real time elapsed on the host
|
||||
host_tick_rate 100993 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_seconds 0.003230 # Number of seconds simulated
|
||||
sim_ticks 3229931 # Number of ticks simulated
|
||||
sim_seconds 0.002583 # Number of seconds simulated
|
||||
sim_ticks 2583072 # Number of ticks simulated
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
system.cpu0.num_reads 99664 # number of read accesses completed
|
||||
system.cpu0.num_writes 53551 # number of write accesses completed
|
||||
system.cpu0.num_reads 100000 # number of read accesses completed
|
||||
system.cpu0.num_writes 53663 # number of write accesses completed
|
||||
system.cpu1.num_copies 0 # number of copy accesses completed
|
||||
system.cpu1.num_reads 97847 # number of read accesses completed
|
||||
system.cpu1.num_writes 52926 # number of write accesses completed
|
||||
system.cpu1.num_reads 98827 # number of read accesses completed
|
||||
system.cpu1.num_writes 53487 # number of write accesses completed
|
||||
system.cpu2.num_copies 0 # number of copy accesses completed
|
||||
system.cpu2.num_reads 100000 # number of read accesses completed
|
||||
system.cpu2.num_writes 54081 # number of write accesses completed
|
||||
system.cpu2.num_reads 96775 # number of read accesses completed
|
||||
system.cpu2.num_writes 51846 # number of write accesses completed
|
||||
system.cpu3.num_copies 0 # number of copy accesses completed
|
||||
system.cpu3.num_reads 97548 # number of read accesses completed
|
||||
system.cpu3.num_writes 52843 # number of write accesses completed
|
||||
system.cpu3.num_reads 97235 # number of read accesses completed
|
||||
system.cpu3.num_writes 52295 # number of write accesses completed
|
||||
system.cpu4.num_copies 0 # number of copy accesses completed
|
||||
system.cpu4.num_reads 98335 # number of read accesses completed
|
||||
system.cpu4.num_writes 52557 # number of write accesses completed
|
||||
system.cpu4.num_reads 97597 # number of read accesses completed
|
||||
system.cpu4.num_writes 52429 # number of write accesses completed
|
||||
system.cpu5.num_copies 0 # number of copy accesses completed
|
||||
system.cpu5.num_reads 97595 # number of read accesses completed
|
||||
system.cpu5.num_writes 52679 # number of write accesses completed
|
||||
system.cpu5.num_reads 97329 # number of read accesses completed
|
||||
system.cpu5.num_writes 52105 # number of write accesses completed
|
||||
system.cpu6.num_copies 0 # number of copy accesses completed
|
||||
system.cpu6.num_reads 97889 # number of read accesses completed
|
||||
system.cpu6.num_writes 52461 # number of write accesses completed
|
||||
system.cpu6.num_reads 96958 # number of read accesses completed
|
||||
system.cpu6.num_writes 52281 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
system.cpu7.num_reads 97463 # number of read accesses completed
|
||||
system.cpu7.num_writes 51981 # number of write accesses completed
|
||||
system.cpu7.num_reads 97500 # number of read accesses completed
|
||||
system.cpu7.num_writes 52109 # number of write accesses completed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -5,13 +5,14 @@ dummy=0
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcmem physmem ruby
|
||||
children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 physmem ruby
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
|
||||
[system.cpu0]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -27,6 +28,7 @@ test=system.ruby.cpu_ruby_ports0.port[0]
|
|||
[system.cpu1]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -42,6 +44,7 @@ test=system.ruby.cpu_ruby_ports1.port[0]
|
|||
[system.cpu2]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -57,6 +60,7 @@ test=system.ruby.cpu_ruby_ports2.port[0]
|
|||
[system.cpu3]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -72,6 +76,7 @@ test=system.ruby.cpu_ruby_ports3.port[0]
|
|||
[system.cpu4]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -87,6 +92,7 @@ test=system.ruby.cpu_ruby_ports4.port[0]
|
|||
[system.cpu5]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -102,6 +108,7 @@ test=system.ruby.cpu_ruby_ports5.port[0]
|
|||
[system.cpu6]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -117,6 +124,7 @@ test=system.ruby.cpu_ruby_ports6.port[0]
|
|||
[system.cpu7]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -129,6 +137,57 @@ trace_addr=0
|
|||
functional=system.funcmem.port[7]
|
||||
test=system.ruby.cpu_ruby_ports7.port[0]
|
||||
|
||||
[system.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer probeFilter
|
||||
buffer_size=0
|
||||
directory=system.dir_cntrl0.directory
|
||||
memBuffer=system.dir_cntrl0.memBuffer
|
||||
memory_controller_latency=2
|
||||
number_of_TBEs=256
|
||||
probeFilter=system.dir_cntrl0.probeFilter
|
||||
probe_filter_enabled=false
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=6
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.dir_cntrl0.probeFilter]
|
||||
type=RubyCache
|
||||
assoc=4
|
||||
latency=1
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=1024
|
||||
start_index_bit=6
|
||||
|
||||
[system.funcmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
|
|
@ -139,6 +198,334 @@ range=0:134217727
|
|||
zero=false
|
||||
port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
|
||||
|
||||
[system.l1_cntrl0]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory L2cacheMemory
|
||||
L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
|
||||
L2cacheMemory=system.l1_cntrl0.L2cacheMemory
|
||||
buffer_size=0
|
||||
cache_response_latency=10
|
||||
issue_latency=2
|
||||
l2_cache_hit_latency=10
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports0
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=10
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl1]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory L2cacheMemory
|
||||
L1DcacheMemory=system.l1_cntrl1.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl1.L1IcacheMemory
|
||||
L2cacheMemory=system.l1_cntrl1.L2cacheMemory
|
||||
buffer_size=0
|
||||
cache_response_latency=10
|
||||
issue_latency=2
|
||||
l2_cache_hit_latency=10
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports1
|
||||
transitions_per_cycle=32
|
||||
version=1
|
||||
|
||||
[system.l1_cntrl1.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl1.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl1.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=10
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl2]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory L2cacheMemory
|
||||
L1DcacheMemory=system.l1_cntrl2.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl2.L1IcacheMemory
|
||||
L2cacheMemory=system.l1_cntrl2.L2cacheMemory
|
||||
buffer_size=0
|
||||
cache_response_latency=10
|
||||
issue_latency=2
|
||||
l2_cache_hit_latency=10
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports2
|
||||
transitions_per_cycle=32
|
||||
version=2
|
||||
|
||||
[system.l1_cntrl2.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl2.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl2.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=10
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl3]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory L2cacheMemory
|
||||
L1DcacheMemory=system.l1_cntrl3.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl3.L1IcacheMemory
|
||||
L2cacheMemory=system.l1_cntrl3.L2cacheMemory
|
||||
buffer_size=0
|
||||
cache_response_latency=10
|
||||
issue_latency=2
|
||||
l2_cache_hit_latency=10
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports3
|
||||
transitions_per_cycle=32
|
||||
version=3
|
||||
|
||||
[system.l1_cntrl3.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl3.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl3.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=10
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl4]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory L2cacheMemory
|
||||
L1DcacheMemory=system.l1_cntrl4.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl4.L1IcacheMemory
|
||||
L2cacheMemory=system.l1_cntrl4.L2cacheMemory
|
||||
buffer_size=0
|
||||
cache_response_latency=10
|
||||
issue_latency=2
|
||||
l2_cache_hit_latency=10
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports4
|
||||
transitions_per_cycle=32
|
||||
version=4
|
||||
|
||||
[system.l1_cntrl4.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl4.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl4.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=10
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl5]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory L2cacheMemory
|
||||
L1DcacheMemory=system.l1_cntrl5.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl5.L1IcacheMemory
|
||||
L2cacheMemory=system.l1_cntrl5.L2cacheMemory
|
||||
buffer_size=0
|
||||
cache_response_latency=10
|
||||
issue_latency=2
|
||||
l2_cache_hit_latency=10
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports5
|
||||
transitions_per_cycle=32
|
||||
version=5
|
||||
|
||||
[system.l1_cntrl5.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl5.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl5.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=10
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl6]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory L2cacheMemory
|
||||
L1DcacheMemory=system.l1_cntrl6.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl6.L1IcacheMemory
|
||||
L2cacheMemory=system.l1_cntrl6.L2cacheMemory
|
||||
buffer_size=0
|
||||
cache_response_latency=10
|
||||
issue_latency=2
|
||||
l2_cache_hit_latency=10
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports6
|
||||
transitions_per_cycle=32
|
||||
version=6
|
||||
|
||||
[system.l1_cntrl6.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl6.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl6.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=10
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl7]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory L2cacheMemory
|
||||
L1DcacheMemory=system.l1_cntrl7.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl7.L1IcacheMemory
|
||||
L2cacheMemory=system.l1_cntrl7.L2cacheMemory
|
||||
buffer_size=0
|
||||
cache_response_latency=10
|
||||
issue_latency=2
|
||||
l2_cache_hit_latency=10
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports7
|
||||
transitions_per_cycle=32
|
||||
version=7
|
||||
|
||||
[system.l1_cntrl7.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl7.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl7.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=10
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
start_index_bit=6
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
|
|
@ -166,9 +553,9 @@ tracer=system.ruby.tracer
|
|||
|
||||
[system.ruby.cpu_ruby_ports0]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory
|
||||
dcache=system.l1_cntrl0.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory
|
||||
icache=system.l1_cntrl0.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
|
|
@ -178,9 +565,9 @@ port=system.cpu0.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports1]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory
|
||||
dcache=system.l1_cntrl1.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory
|
||||
icache=system.l1_cntrl1.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
|
|
@ -190,9 +577,9 @@ port=system.cpu1.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports2]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory
|
||||
dcache=system.l1_cntrl2.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory
|
||||
icache=system.l1_cntrl2.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
|
|
@ -202,9 +589,9 @@ port=system.cpu2.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports3]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory
|
||||
dcache=system.l1_cntrl3.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory
|
||||
icache=system.l1_cntrl3.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
|
|
@ -214,9 +601,9 @@ port=system.cpu3.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports4]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory
|
||||
dcache=system.l1_cntrl4.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory
|
||||
icache=system.l1_cntrl4.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
|
|
@ -226,9 +613,9 @@ port=system.cpu4.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports5]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory
|
||||
dcache=system.l1_cntrl5.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory
|
||||
icache=system.l1_cntrl5.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
|
|
@ -238,9 +625,9 @@ port=system.cpu5.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports6]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory
|
||||
dcache=system.l1_cntrl6.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory
|
||||
icache=system.l1_cntrl6.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
|
|
@ -250,9 +637,9 @@ port=system.cpu6.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports7]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory
|
||||
dcache=system.l1_cntrl7.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory
|
||||
icache=system.l1_cntrl7.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
|
|
@ -282,6 +669,7 @@ topology=system.ruby.network.topology
|
|||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8
|
||||
description=Crossbar
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8
|
||||
num_int_nodes=10
|
||||
|
|
@ -289,414 +677,76 @@ print_config=false
|
|||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links0.ext_node
|
||||
ext_node=system.l1_cntrl0
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory L2cacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory
|
||||
L2cacheMemory=system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory
|
||||
buffer_size=0
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports0
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=15
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links1.ext_node
|
||||
ext_node=system.l1_cntrl1
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory L2cacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory
|
||||
L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
|
||||
buffer_size=0
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports1
|
||||
transitions_per_cycle=32
|
||||
version=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=15
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
||||
[system.ruby.network.topology.ext_links2]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links2.ext_node
|
||||
ext_node=system.l1_cntrl2
|
||||
int_node=2
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory L2cacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory
|
||||
L2cacheMemory=system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory
|
||||
buffer_size=0
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports2
|
||||
transitions_per_cycle=32
|
||||
version=2
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=15
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
||||
[system.ruby.network.topology.ext_links3]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links3.ext_node
|
||||
ext_node=system.l1_cntrl3
|
||||
int_node=3
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links3.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory L2cacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory
|
||||
L2cacheMemory=system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory
|
||||
buffer_size=0
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports3
|
||||
transitions_per_cycle=32
|
||||
version=3
|
||||
|
||||
[system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=15
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
||||
[system.ruby.network.topology.ext_links4]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links4.ext_node
|
||||
ext_node=system.l1_cntrl4
|
||||
int_node=4
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links4.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory L2cacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory
|
||||
L2cacheMemory=system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory
|
||||
buffer_size=0
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports4
|
||||
transitions_per_cycle=32
|
||||
version=4
|
||||
|
||||
[system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=15
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
||||
[system.ruby.network.topology.ext_links5]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links5.ext_node
|
||||
ext_node=system.l1_cntrl5
|
||||
int_node=5
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links5.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory L2cacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory
|
||||
L2cacheMemory=system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory
|
||||
buffer_size=0
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports5
|
||||
transitions_per_cycle=32
|
||||
version=5
|
||||
|
||||
[system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=15
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
||||
[system.ruby.network.topology.ext_links6]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links6.ext_node
|
||||
ext_node=system.l1_cntrl6
|
||||
int_node=6
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links6.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory L2cacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory
|
||||
L2cacheMemory=system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory
|
||||
buffer_size=0
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports6
|
||||
transitions_per_cycle=32
|
||||
version=6
|
||||
|
||||
[system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=15
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
||||
[system.ruby.network.topology.ext_links7]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links7.ext_node
|
||||
ext_node=system.l1_cntrl7
|
||||
int_node=7
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links7.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=L1DcacheMemory L1IcacheMemory L2cacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory
|
||||
L2cacheMemory=system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory
|
||||
buffer_size=0
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports7
|
||||
transitions_per_cycle=32
|
||||
version=7
|
||||
|
||||
[system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=15
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
||||
[system.ruby.network.topology.ext_links8]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links8.ext_node
|
||||
ext_node=system.dir_cntrl0
|
||||
int_node=8
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links8.ext_node]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
directory=system.ruby.network.topology.ext_links8.ext_node.directory
|
||||
memBuffer=system.ruby.network.topology.ext_links8.ext_node.memBuffer
|
||||
memory_controller_latency=12
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links8.ext_node.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=0
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links8.ext_node.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.int_links0]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,74 +1,74 @@
|
|||
system.cpu5: completed 10000 read accesses @427588
|
||||
system.cpu7: completed 10000 read accesses @431412
|
||||
system.cpu2: completed 10000 read accesses @431662
|
||||
system.cpu0: completed 10000 read accesses @436404
|
||||
system.cpu6: completed 10000 read accesses @437826
|
||||
system.cpu3: completed 10000 read accesses @441295
|
||||
system.cpu4: completed 10000 read accesses @446537
|
||||
system.cpu1: completed 10000 read accesses @454121
|
||||
system.cpu6: completed 20000 read accesses @860243
|
||||
system.cpu5: completed 20000 read accesses @863931
|
||||
system.cpu0: completed 20000 read accesses @870865
|
||||
system.cpu7: completed 20000 read accesses @874151
|
||||
system.cpu2: completed 20000 read accesses @878670
|
||||
system.cpu1: completed 20000 read accesses @880979
|
||||
system.cpu3: completed 20000 read accesses @881568
|
||||
system.cpu4: completed 20000 read accesses @885967
|
||||
system.cpu6: completed 30000 read accesses @1296805
|
||||
system.cpu7: completed 30000 read accesses @1298533
|
||||
system.cpu0: completed 30000 read accesses @1301793
|
||||
system.cpu5: completed 30000 read accesses @1305764
|
||||
system.cpu3: completed 30000 read accesses @1313209
|
||||
system.cpu1: completed 30000 read accesses @1317956
|
||||
system.cpu4: completed 30000 read accesses @1322397
|
||||
system.cpu2: completed 30000 read accesses @1327680
|
||||
system.cpu7: completed 40000 read accesses @1724327
|
||||
system.cpu6: completed 40000 read accesses @1741883
|
||||
system.cpu3: completed 40000 read accesses @1743341
|
||||
system.cpu0: completed 40000 read accesses @1746338
|
||||
system.cpu5: completed 40000 read accesses @1749918
|
||||
system.cpu4: completed 40000 read accesses @1756944
|
||||
system.cpu1: completed 40000 read accesses @1758785
|
||||
system.cpu2: completed 40000 read accesses @1766923
|
||||
system.cpu7: completed 50000 read accesses @2153101
|
||||
system.cpu3: completed 50000 read accesses @2174455
|
||||
system.cpu6: completed 50000 read accesses @2175676
|
||||
system.cpu0: completed 50000 read accesses @2176642
|
||||
system.cpu1: completed 50000 read accesses @2195626
|
||||
system.cpu5: completed 50000 read accesses @2196192
|
||||
system.cpu4: completed 50000 read accesses @2206329
|
||||
system.cpu2: completed 50000 read accesses @2212172
|
||||
system.cpu7: completed 60000 read accesses @2597994
|
||||
system.cpu3: completed 60000 read accesses @2607264
|
||||
system.cpu6: completed 60000 read accesses @2608871
|
||||
system.cpu0: completed 60000 read accesses @2617931
|
||||
system.cpu1: completed 60000 read accesses @2626417
|
||||
system.cpu5: completed 60000 read accesses @2627919
|
||||
system.cpu2: completed 60000 read accesses @2649345
|
||||
system.cpu4: completed 60000 read accesses @2649516
|
||||
system.cpu7: completed 70000 read accesses @3041950
|
||||
system.cpu6: completed 70000 read accesses @3046421
|
||||
system.cpu3: completed 70000 read accesses @3055853
|
||||
system.cpu0: completed 70000 read accesses @3057789
|
||||
system.cpu1: completed 70000 read accesses @3060703
|
||||
system.cpu5: completed 70000 read accesses @3069601
|
||||
system.cpu4: completed 70000 read accesses @3076345
|
||||
system.cpu2: completed 70000 read accesses @3079487
|
||||
system.cpu7: completed 80000 read accesses @3472996
|
||||
system.cpu6: completed 80000 read accesses @3475066
|
||||
system.cpu3: completed 80000 read accesses @3481511
|
||||
system.cpu0: completed 80000 read accesses @3498566
|
||||
system.cpu1: completed 80000 read accesses @3506662
|
||||
system.cpu2: completed 80000 read accesses @3515589
|
||||
system.cpu5: completed 80000 read accesses @3522207
|
||||
system.cpu4: completed 80000 read accesses @3524696
|
||||
system.cpu6: completed 90000 read accesses @3905962
|
||||
system.cpu7: completed 90000 read accesses @3913222
|
||||
system.cpu3: completed 90000 read accesses @3920060
|
||||
system.cpu0: completed 90000 read accesses @3930216
|
||||
system.cpu2: completed 90000 read accesses @3948853
|
||||
system.cpu1: completed 90000 read accesses @3953559
|
||||
system.cpu5: completed 90000 read accesses @3960654
|
||||
system.cpu4: completed 90000 read accesses @3965634
|
||||
system.cpu6: completed 100000 read accesses @4329426
|
||||
system.cpu2: completed 10000 read accesses @332309
|
||||
system.cpu0: completed 10000 read accesses @332762
|
||||
system.cpu3: completed 10000 read accesses @333275
|
||||
system.cpu7: completed 10000 read accesses @334660
|
||||
system.cpu4: completed 10000 read accesses @336400
|
||||
system.cpu6: completed 10000 read accesses @336827
|
||||
system.cpu1: completed 10000 read accesses @336833
|
||||
system.cpu5: completed 10000 read accesses @339345
|
||||
system.cpu3: completed 20000 read accesses @659139
|
||||
system.cpu0: completed 20000 read accesses @662762
|
||||
system.cpu2: completed 20000 read accesses @662918
|
||||
system.cpu4: completed 20000 read accesses @663822
|
||||
system.cpu6: completed 20000 read accesses @664214
|
||||
system.cpu7: completed 20000 read accesses @673557
|
||||
system.cpu1: completed 20000 read accesses @673720
|
||||
system.cpu5: completed 20000 read accesses @675222
|
||||
system.cpu3: completed 30000 read accesses @990404
|
||||
system.cpu6: completed 30000 read accesses @991868
|
||||
system.cpu0: completed 30000 read accesses @993980
|
||||
system.cpu2: completed 30000 read accesses @994621
|
||||
system.cpu4: completed 30000 read accesses @995936
|
||||
system.cpu5: completed 30000 read accesses @1005609
|
||||
system.cpu1: completed 30000 read accesses @1008145
|
||||
system.cpu7: completed 30000 read accesses @1008840
|
||||
system.cpu6: completed 40000 read accesses @1322251
|
||||
system.cpu0: completed 40000 read accesses @1324139
|
||||
system.cpu3: completed 40000 read accesses @1324341
|
||||
system.cpu2: completed 40000 read accesses @1325019
|
||||
system.cpu4: completed 40000 read accesses @1328462
|
||||
system.cpu5: completed 40000 read accesses @1335869
|
||||
system.cpu1: completed 40000 read accesses @1336407
|
||||
system.cpu7: completed 40000 read accesses @1342910
|
||||
system.cpu6: completed 50000 read accesses @1654106
|
||||
system.cpu0: completed 50000 read accesses @1654925
|
||||
system.cpu3: completed 50000 read accesses @1657897
|
||||
system.cpu2: completed 50000 read accesses @1658205
|
||||
system.cpu1: completed 50000 read accesses @1668347
|
||||
system.cpu5: completed 50000 read accesses @1668465
|
||||
system.cpu4: completed 50000 read accesses @1670315
|
||||
system.cpu7: completed 50000 read accesses @1681232
|
||||
system.cpu6: completed 60000 read accesses @1984633
|
||||
system.cpu0: completed 60000 read accesses @1986549
|
||||
system.cpu2: completed 60000 read accesses @1989981
|
||||
system.cpu3: completed 60000 read accesses @1993690
|
||||
system.cpu1: completed 60000 read accesses @2001694
|
||||
system.cpu4: completed 60000 read accesses @2002313
|
||||
system.cpu5: completed 60000 read accesses @2005561
|
||||
system.cpu7: completed 60000 read accesses @2014675
|
||||
system.cpu6: completed 70000 read accesses @2317222
|
||||
system.cpu0: completed 70000 read accesses @2318277
|
||||
system.cpu2: completed 70000 read accesses @2322048
|
||||
system.cpu3: completed 70000 read accesses @2324750
|
||||
system.cpu4: completed 70000 read accesses @2332151
|
||||
system.cpu1: completed 70000 read accesses @2332386
|
||||
system.cpu5: completed 70000 read accesses @2332911
|
||||
system.cpu7: completed 70000 read accesses @2343337
|
||||
system.cpu0: completed 80000 read accesses @2646207
|
||||
system.cpu6: completed 80000 read accesses @2646561
|
||||
system.cpu3: completed 80000 read accesses @2652685
|
||||
system.cpu2: completed 80000 read accesses @2655532
|
||||
system.cpu5: completed 80000 read accesses @2662477
|
||||
system.cpu4: completed 80000 read accesses @2665813
|
||||
system.cpu7: completed 80000 read accesses @2668350
|
||||
system.cpu1: completed 80000 read accesses @2668666
|
||||
system.cpu6: completed 90000 read accesses @2976982
|
||||
system.cpu0: completed 90000 read accesses @2982010
|
||||
system.cpu2: completed 90000 read accesses @2983845
|
||||
system.cpu3: completed 90000 read accesses @2993125
|
||||
system.cpu5: completed 90000 read accesses @2995492
|
||||
system.cpu4: completed 90000 read accesses @2998220
|
||||
system.cpu7: completed 90000 read accesses @3003787
|
||||
system.cpu1: completed 90000 read accesses @3004322
|
||||
system.cpu6: completed 100000 read accesses @3305503
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 1 2010 14:37:50
|
||||
M5 revision acd9f15a9c7c 7493 default qtip tip simobj-parent-fix-stats-udpate
|
||||
M5 started Jul 1 2010 14:38:54
|
||||
M5 executing on phenom
|
||||
command line: build/ALPHA_SE_MOESI_hammer/m5.opt -d build/ALPHA_SE_MOESI_hammer/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer
|
||||
M5 compiled Aug 20 2010 12:17:38
|
||||
M5 revision c4b5df973361+ 7570+ default qtip tip brad/regress_updates
|
||||
M5 started Aug 20 2010 12:17:55
|
||||
M5 executing on SC2B0629
|
||||
command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 4329426 because maximum number of loads reached
|
||||
Exiting @ tick 3305503 because maximum number of loads reached
|
||||
|
|
|
|||
|
|
@ -1,34 +1,34 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_mem_usage 332624 # Number of bytes of host memory used
|
||||
host_seconds 32.19 # Real time elapsed on the host
|
||||
host_tick_rate 134514 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 341640 # Number of bytes of host memory used
|
||||
host_seconds 37.52 # Real time elapsed on the host
|
||||
host_tick_rate 88100 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_seconds 0.004329 # Number of seconds simulated
|
||||
sim_ticks 4329426 # Number of ticks simulated
|
||||
sim_seconds 0.003306 # Number of seconds simulated
|
||||
sim_ticks 3305503 # Number of ticks simulated
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
system.cpu0.num_reads 99342 # number of read accesses completed
|
||||
system.cpu0.num_writes 53020 # number of write accesses completed
|
||||
system.cpu0.num_reads 99692 # number of read accesses completed
|
||||
system.cpu0.num_writes 53673 # number of write accesses completed
|
||||
system.cpu1.num_copies 0 # number of copy accesses completed
|
||||
system.cpu1.num_reads 98745 # number of read accesses completed
|
||||
system.cpu1.num_writes 53384 # number of write accesses completed
|
||||
system.cpu1.num_reads 99062 # number of read accesses completed
|
||||
system.cpu1.num_writes 53374 # number of write accesses completed
|
||||
system.cpu2.num_copies 0 # number of copy accesses completed
|
||||
system.cpu2.num_reads 98624 # number of read accesses completed
|
||||
system.cpu2.num_writes 53313 # number of write accesses completed
|
||||
system.cpu2.num_reads 99665 # number of read accesses completed
|
||||
system.cpu2.num_writes 53906 # number of write accesses completed
|
||||
system.cpu3.num_copies 0 # number of copy accesses completed
|
||||
system.cpu3.num_reads 99274 # number of read accesses completed
|
||||
system.cpu3.num_writes 53327 # number of write accesses completed
|
||||
system.cpu3.num_reads 99457 # number of read accesses completed
|
||||
system.cpu3.num_writes 53389 # number of write accesses completed
|
||||
system.cpu4.num_copies 0 # number of copy accesses completed
|
||||
system.cpu4.num_reads 98083 # number of read accesses completed
|
||||
system.cpu4.num_writes 52520 # number of write accesses completed
|
||||
system.cpu4.num_reads 99209 # number of read accesses completed
|
||||
system.cpu4.num_writes 53779 # number of write accesses completed
|
||||
system.cpu5.num_copies 0 # number of copy accesses completed
|
||||
system.cpu5.num_reads 98306 # number of read accesses completed
|
||||
system.cpu5.num_writes 52893 # number of write accesses completed
|
||||
system.cpu5.num_reads 99375 # number of read accesses completed
|
||||
system.cpu5.num_writes 53528 # number of write accesses completed
|
||||
system.cpu6.num_copies 0 # number of copy accesses completed
|
||||
system.cpu6.num_reads 100000 # number of read accesses completed
|
||||
system.cpu6.num_writes 53622 # number of write accesses completed
|
||||
system.cpu6.num_writes 53388 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
system.cpu7.num_reads 99389 # number of read accesses completed
|
||||
system.cpu7.num_writes 53486 # number of write accesses completed
|
||||
system.cpu7.num_reads 99219 # number of read accesses completed
|
||||
system.cpu7.num_writes 53946 # number of write accesses completed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -5,13 +5,14 @@ dummy=0
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcmem physmem ruby
|
||||
children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 physmem ruby
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
|
||||
[system.cpu0]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -22,11 +23,12 @@ percent_uncacheable=0
|
|||
progress_interval=10000
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[0]
|
||||
test=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
|
||||
test=system.ruby.cpu_ruby_ports0.port[0]
|
||||
|
||||
[system.cpu1]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -37,11 +39,12 @@ percent_uncacheable=0
|
|||
progress_interval=10000
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[1]
|
||||
test=system.ruby.network.topology.ext_links1.ext_node.sequencer.port[0]
|
||||
test=system.ruby.cpu_ruby_ports1.port[0]
|
||||
|
||||
[system.cpu2]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -52,11 +55,12 @@ percent_uncacheable=0
|
|||
progress_interval=10000
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[2]
|
||||
test=system.ruby.network.topology.ext_links2.ext_node.sequencer.port[0]
|
||||
test=system.ruby.cpu_ruby_ports2.port[0]
|
||||
|
||||
[system.cpu3]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -67,11 +71,12 @@ percent_uncacheable=0
|
|||
progress_interval=10000
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[3]
|
||||
test=system.ruby.network.topology.ext_links3.ext_node.sequencer.port[0]
|
||||
test=system.ruby.cpu_ruby_ports3.port[0]
|
||||
|
||||
[system.cpu4]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -82,11 +87,12 @@ percent_uncacheable=0
|
|||
progress_interval=10000
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[4]
|
||||
test=system.ruby.network.topology.ext_links4.ext_node.sequencer.port[0]
|
||||
test=system.ruby.cpu_ruby_ports4.port[0]
|
||||
|
||||
[system.cpu5]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -97,11 +103,12 @@ percent_uncacheable=0
|
|||
progress_interval=10000
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[5]
|
||||
test=system.ruby.network.topology.ext_links5.ext_node.sequencer.port[0]
|
||||
test=system.ruby.cpu_ruby_ports5.port[0]
|
||||
|
||||
[system.cpu6]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -112,11 +119,12 @@ percent_uncacheable=0
|
|||
progress_interval=10000
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[6]
|
||||
test=system.ruby.network.topology.ext_links6.ext_node.sequencer.port[0]
|
||||
test=system.ruby.cpu_ruby_ports6.port[0]
|
||||
|
||||
[system.cpu7]
|
||||
type=MemTest
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -127,7 +135,48 @@ percent_uncacheable=0
|
|||
progress_interval=10000
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[7]
|
||||
test=system.ruby.network.topology.ext_links7.ext_node.sequencer.port[0]
|
||||
test=system.ruby.cpu_ruby_ports7.port[0]
|
||||
|
||||
[system.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
directory=system.dir_cntrl0.directory
|
||||
directory_latency=12
|
||||
memBuffer=system.dir_cntrl0.memBuffer
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=6
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.funcmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -139,6 +188,174 @@ range=0:134217727
|
|||
zero=false
|
||||
port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
|
||||
|
||||
[system.l1_cntrl0]
|
||||
type=L1Cache_Controller
|
||||
children=cacheMemory
|
||||
buffer_size=0
|
||||
cacheMemory=system.l1_cntrl0.cacheMemory
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports0
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0.cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl1]
|
||||
type=L1Cache_Controller
|
||||
children=cacheMemory
|
||||
buffer_size=0
|
||||
cacheMemory=system.l1_cntrl1.cacheMemory
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports1
|
||||
transitions_per_cycle=32
|
||||
version=1
|
||||
|
||||
[system.l1_cntrl1.cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl2]
|
||||
type=L1Cache_Controller
|
||||
children=cacheMemory
|
||||
buffer_size=0
|
||||
cacheMemory=system.l1_cntrl2.cacheMemory
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports2
|
||||
transitions_per_cycle=32
|
||||
version=2
|
||||
|
||||
[system.l1_cntrl2.cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl3]
|
||||
type=L1Cache_Controller
|
||||
children=cacheMemory
|
||||
buffer_size=0
|
||||
cacheMemory=system.l1_cntrl3.cacheMemory
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports3
|
||||
transitions_per_cycle=32
|
||||
version=3
|
||||
|
||||
[system.l1_cntrl3.cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl4]
|
||||
type=L1Cache_Controller
|
||||
children=cacheMemory
|
||||
buffer_size=0
|
||||
cacheMemory=system.l1_cntrl4.cacheMemory
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports4
|
||||
transitions_per_cycle=32
|
||||
version=4
|
||||
|
||||
[system.l1_cntrl4.cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl5]
|
||||
type=L1Cache_Controller
|
||||
children=cacheMemory
|
||||
buffer_size=0
|
||||
cacheMemory=system.l1_cntrl5.cacheMemory
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports5
|
||||
transitions_per_cycle=32
|
||||
version=5
|
||||
|
||||
[system.l1_cntrl5.cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl6]
|
||||
type=L1Cache_Controller
|
||||
children=cacheMemory
|
||||
buffer_size=0
|
||||
cacheMemory=system.l1_cntrl6.cacheMemory
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports6
|
||||
transitions_per_cycle=32
|
||||
version=6
|
||||
|
||||
[system.l1_cntrl6.cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl7]
|
||||
type=L1Cache_Controller
|
||||
children=cacheMemory
|
||||
buffer_size=0
|
||||
cacheMemory=system.l1_cntrl7.cacheMemory
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports7
|
||||
transitions_per_cycle=32
|
||||
version=7
|
||||
|
||||
[system.l1_cntrl7.cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
|
|
@ -147,11 +364,11 @@ latency_var=0
|
|||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links1.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links2.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links3.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links4.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links5.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links6.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links7.ext_node.sequencer.physMemPort
|
||||
port=system.ruby.cpu_ruby_ports0.physMemPort system.ruby.cpu_ruby_ports1.physMemPort system.ruby.cpu_ruby_ports2.physMemPort system.ruby.cpu_ruby_ports3.physMemPort system.ruby.cpu_ruby_ports4.physMemPort system.ruby.cpu_ruby_ports5.physMemPort system.ruby.cpu_ruby_ports6.physMemPort system.ruby.cpu_ruby_ports7.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
children=cpu_ruby_ports0 cpu_ruby_ports1 cpu_ruby_ports2 cpu_ruby_ports3 cpu_ruby_ports4 cpu_ruby_ports5 cpu_ruby_ports6 cpu_ruby_ports7 debug network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
|
|
@ -164,6 +381,102 @@ randomization=false
|
|||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.cpu_ruby_ports0]
|
||||
type=RubySequencer
|
||||
dcache=system.l1_cntrl0.cacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.cacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu0.test
|
||||
|
||||
[system.ruby.cpu_ruby_ports1]
|
||||
type=RubySequencer
|
||||
dcache=system.l1_cntrl1.cacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl1.cacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=1
|
||||
physMemPort=system.physmem.port[1]
|
||||
port=system.cpu1.test
|
||||
|
||||
[system.ruby.cpu_ruby_ports2]
|
||||
type=RubySequencer
|
||||
dcache=system.l1_cntrl2.cacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl2.cacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=2
|
||||
physMemPort=system.physmem.port[2]
|
||||
port=system.cpu2.test
|
||||
|
||||
[system.ruby.cpu_ruby_ports3]
|
||||
type=RubySequencer
|
||||
dcache=system.l1_cntrl3.cacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl3.cacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=3
|
||||
physMemPort=system.physmem.port[3]
|
||||
port=system.cpu3.test
|
||||
|
||||
[system.ruby.cpu_ruby_ports4]
|
||||
type=RubySequencer
|
||||
dcache=system.l1_cntrl4.cacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl4.cacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=4
|
||||
physMemPort=system.physmem.port[4]
|
||||
port=system.cpu4.test
|
||||
|
||||
[system.ruby.cpu_ruby_ports5]
|
||||
type=RubySequencer
|
||||
dcache=system.l1_cntrl5.cacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl5.cacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=5
|
||||
physMemPort=system.physmem.port[5]
|
||||
port=system.cpu5.test
|
||||
|
||||
[system.ruby.cpu_ruby_ports6]
|
||||
type=RubySequencer
|
||||
dcache=system.l1_cntrl6.cacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl6.cacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=6
|
||||
physMemPort=system.physmem.port[6]
|
||||
port=system.cpu6.test
|
||||
|
||||
[system.ruby.cpu_ruby_ports7]
|
||||
type=RubySequencer
|
||||
dcache=system.l1_cntrl7.cacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl7.cacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=7
|
||||
physMemPort=system.physmem.port[7]
|
||||
port=system.cpu7.test
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
|
|
@ -186,6 +499,7 @@ topology=system.ruby.network.topology
|
|||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8
|
||||
description=Crossbar
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8
|
||||
num_int_nodes=10
|
||||
|
|
@ -193,390 +507,76 @@ print_config=false
|
|||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links0.ext_node
|
||||
ext_node=system.l1_cntrl0
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
buffer_size=0
|
||||
cacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=icache
|
||||
dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu0.test
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links1.ext_node
|
||||
ext_node=system.l1_cntrl1
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
buffer_size=0
|
||||
cacheMemory=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.network.topology.ext_links1.ext_node.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=icache
|
||||
dcache=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=1
|
||||
physMemPort=system.physmem.port[1]
|
||||
port=system.cpu1.test
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links2]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links2.ext_node
|
||||
ext_node=system.l1_cntrl2
|
||||
int_node=2
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
buffer_size=0
|
||||
cacheMemory=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.network.topology.ext_links2.ext_node.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=2
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=icache
|
||||
dcache=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=2
|
||||
physMemPort=system.physmem.port[2]
|
||||
port=system.cpu2.test
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links3]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links3.ext_node
|
||||
ext_node=system.l1_cntrl3
|
||||
int_node=3
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links3.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
buffer_size=0
|
||||
cacheMemory=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.network.topology.ext_links3.ext_node.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=3
|
||||
|
||||
[system.ruby.network.topology.ext_links3.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=icache
|
||||
dcache=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=3
|
||||
physMemPort=system.physmem.port[3]
|
||||
port=system.cpu3.test
|
||||
|
||||
[system.ruby.network.topology.ext_links3.ext_node.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links4]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links4.ext_node
|
||||
ext_node=system.l1_cntrl4
|
||||
int_node=4
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links4.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
buffer_size=0
|
||||
cacheMemory=system.ruby.network.topology.ext_links4.ext_node.sequencer.icache
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.network.topology.ext_links4.ext_node.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=4
|
||||
|
||||
[system.ruby.network.topology.ext_links4.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=icache
|
||||
dcache=system.ruby.network.topology.ext_links4.ext_node.sequencer.icache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links4.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=4
|
||||
physMemPort=system.physmem.port[4]
|
||||
port=system.cpu4.test
|
||||
|
||||
[system.ruby.network.topology.ext_links4.ext_node.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links5]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links5.ext_node
|
||||
ext_node=system.l1_cntrl5
|
||||
int_node=5
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links5.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
buffer_size=0
|
||||
cacheMemory=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.network.topology.ext_links5.ext_node.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=5
|
||||
|
||||
[system.ruby.network.topology.ext_links5.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=icache
|
||||
dcache=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=5
|
||||
physMemPort=system.physmem.port[5]
|
||||
port=system.cpu5.test
|
||||
|
||||
[system.ruby.network.topology.ext_links5.ext_node.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links6]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links6.ext_node
|
||||
ext_node=system.l1_cntrl6
|
||||
int_node=6
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links6.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
buffer_size=0
|
||||
cacheMemory=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.network.topology.ext_links6.ext_node.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=6
|
||||
|
||||
[system.ruby.network.topology.ext_links6.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=icache
|
||||
dcache=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=6
|
||||
physMemPort=system.physmem.port[6]
|
||||
port=system.cpu6.test
|
||||
|
||||
[system.ruby.network.topology.ext_links6.ext_node.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links7]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links7.ext_node
|
||||
ext_node=system.l1_cntrl7
|
||||
int_node=7
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links7.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
buffer_size=0
|
||||
cacheMemory=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.network.topology.ext_links7.ext_node.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=7
|
||||
|
||||
[system.ruby.network.topology.ext_links7.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=icache
|
||||
dcache=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=7
|
||||
physMemPort=system.physmem.port[7]
|
||||
port=system.cpu7.test
|
||||
|
||||
[system.ruby.network.topology.ext_links7.ext_node.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links8]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links8.ext_node
|
||||
ext_node=system.dir_cntrl0
|
||||
int_node=8
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links8.ext_node]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
directory=system.ruby.network.topology.ext_links8.ext_node.directory
|
||||
directory_latency=12
|
||||
memBuffer=system.ruby.network.topology.ext_links8.ext_node.memBuffer
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links8.ext_node.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=0
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links8.ext_node.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.int_links0]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
|
|
|
|||
|
|
@ -34,29 +34,29 @@ periodic_stats_period: 1000000
|
|||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Mar/18/2010 15:36:18
|
||||
Real time: Aug/20/2010 13:39:31
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 77
|
||||
Elapsed_time_in_minutes: 1.28333
|
||||
Elapsed_time_in_hours: 0.0213889
|
||||
Elapsed_time_in_days: 0.000891204
|
||||
Elapsed_time_in_seconds: 69
|
||||
Elapsed_time_in_minutes: 1.15
|
||||
Elapsed_time_in_hours: 0.0191667
|
||||
Elapsed_time_in_days: 0.000798611
|
||||
|
||||
Virtual_time_in_seconds: 76.96
|
||||
Virtual_time_in_minutes: 1.28267
|
||||
Virtual_time_in_hours: 0.0213778
|
||||
Virtual_time_in_days: 0.000890741
|
||||
Virtual_time_in_seconds: 68.75
|
||||
Virtual_time_in_minutes: 1.14583
|
||||
Virtual_time_in_hours: 0.0190972
|
||||
Virtual_time_in_days: 0.000795718
|
||||
|
||||
Ruby_current_time: 11048357
|
||||
Ruby_current_time: 11059012
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 11048357
|
||||
Ruby_cycles: 11059012
|
||||
|
||||
mbytes_resident: 30.7461
|
||||
mbytes_total: 331.699
|
||||
resident_ratio: 0.0927045
|
||||
mbytes_resident: 32.25
|
||||
mbytes_total: 333.105
|
||||
resident_ratio: 0.0968279
|
||||
|
||||
ruby_cycles_executed: [ 11048358 11048358 11048358 11048358 11048358 11048358 11048358 11048358 ]
|
||||
ruby_cycles_executed: [ 11059013 11059013 11059013 11059013 11059013 11059013 11059013 11059013 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0
|
||||
|
|
@ -66,13 +66,31 @@ Directory-0:0
|
|||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1227589 average: 1.875 | standard deviation: 0.330723 | 0 153452 1074137 ]
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1228772 average: 1.9375 | standard deviation: 0.242071 | 0 76804 1151968 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 4 max: 549 count: 1227573 average: 141.876 | standard deviation: 1.82074 | 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25 294 5125 80867 1141231 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_2: [binsize: 4 max: 549 count: 798072 average: 141.875 | standard deviation: 1.78629 | 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 192 3318 52570 741960 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_3: [binsize: 4 max: 531 count: 429501 average: 141.879 | standard deviation: 1.88309 | 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 102 1807 28297 399271 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency: [binsize: 4 max: 548 count: 1228757 average: 141.941 | standard deviation: 1.79768 | 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21 272 4811 76194 1147428 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 4 max: 548 count: 798474 average: 141.942 | standard deviation: 1.87927 | 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18 174 3144 49367 745750 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 4 max: 459 count: 430283 average: 141.94 | standard deviation: 1.63553 | 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 98 1667 26827 401678 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_L1Cache: [binsize: 1 max: 3 count: 14 average: 3 | standard deviation: 0 | 0 0 0 14 ]
|
||||
miss_latency_Directory: [binsize: 2 max: 359 count: 2 average: 304 | standard deviation: 77.7817 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_L1Cache_wCC: [binsize: 4 max: 548 count: 1228741 average: 141.942 | standard deviation: 1.72165 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21 272 4811 76194 1147428 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 6 average: 0 | standard deviation: 0 | 6 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 6 average: 0 | standard deviation: 0 | 6 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 6 average: 0 | standard deviation: 0 | 6 ]
|
||||
miss_latency_wCC_first_response_to_completion: [binsize: 4 max: 495 count: 6 average: 412.667 | standard deviation: 76.4147 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
imcomplete_wCC_Times: 1228735
|
||||
miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 2 average: 0 | standard deviation: 0 | 2 ]
|
||||
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 2 average: 0 | standard deviation: 0 | 2 ]
|
||||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 2 average: 0 | standard deviation: 0 | 2 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 2 max: 359 count: 2 average: 304 | standard deviation: 77.7817 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
imcomplete_dir_Times: 0
|
||||
miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 7 average: 3 | standard deviation: 0 | 0 0 0 7 ]
|
||||
miss_latency_LD_Directory: [binsize: 2 max: 359 count: 2 average: 304 | standard deviation: 77.7817 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_LD_L1Cache_wCC: [binsize: 4 max: 548 count: 798465 average: 141.943 | standard deviation: 1.81358 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18 174 3144 49367 745750 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 7 average: 3 | standard deviation: 0 | 0 0 0 7 ]
|
||||
miss_latency_ST_L1Cache_wCC: [binsize: 4 max: 459 count: 430276 average: 141.942 | standard deviation: 1.53653 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 98 1667 26827 401678 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
|
|
@ -86,11 +104,11 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN
|
|||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
Total_delay_cycles: [binsize: 4 max: 152 count: 2455118 average: 47.4372 | standard deviation: 47.4484 | 1227560 0 1 0 0 0 0 1 0 0 0 1 0 1 0 1 1 0 0 9 138 2625 40347 646958 537470 2 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 4 max: 152 count: 2455118 average: 47.4372 | standard deviation: 47.4484 | 1227560 0 1 0 0 0 0 1 0 0 0 1 0 1 0 1 1 0 0 9 138 2625 40347 646958 537470 2 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 ]
|
||||
Total_delay_cycles: [binsize: 4 max: 151 count: 2457486 average: 47.4696 | standard deviation: 47.4806 | 1228745 0 0 0 1 0 0 1 0 0 0 1 0 0 0 2 0 0 0 7 145 2397 38169 611708 576306 0 0 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 4 max: 151 count: 2457486 average: 47.4696 | standard deviation: 47.4806 | 1228745 0 0 0 1 0 0 1 0 0 0 1 0 0 0 2 0 0 0 7 145 2397 38169 611708 576306 0 0 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 1227559 average: 0 | standard deviation: 0 | 1227559 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 4 max: 152 count: 1227559 average: 94.8743 | standard deviation: 1.46213 | 1 0 1 0 0 0 0 1 0 0 0 1 0 1 0 1 1 0 0 9 138 2625 40347 646958 537470 2 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 1228743 average: 0 | standard deviation: 0 | 1228743 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 4 max: 151 count: 1228743 average: 94.9391 | standard deviation: 1.44451 | 2 0 0 0 1 0 0 1 0 0 0 1 0 0 0 2 0 0 0 7 145 2397 38169 611708 576306 0 0 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
|
@ -102,9 +120,9 @@ Total_nonPF_delay_cycles: [binsize: 4 max: 152 count: 2455118 average: 47.4372 |
|
|||
Resource Usage
|
||||
--------------
|
||||
page_size: 4096
|
||||
user_time: 76
|
||||
user_time: 68
|
||||
system_time: 0
|
||||
page_reclaims: 8851
|
||||
page_reclaims: 9322
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
|
|
@ -113,49 +131,54 @@ block_outputs: 0
|
|||
Network Stats
|
||||
-------------
|
||||
|
||||
total_msg_count_Control: 3686271 29490168
|
||||
total_msg_count_Response_Data: 3686229 265408488
|
||||
total_msg_count_Writeback_Control: 3686259 29490072
|
||||
total_msgs: 11058759 total_bytes: 324388728
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 0.434016
|
||||
links_utilized_percent_switch_0_link_0: 0.173607 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.694425 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_0: 0.173606 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.694426 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 153446 11048112 [ 0 0 0 0 153446 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 153446 1227568 [ 0 0 0 153446 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 153447 1227576 [ 0 0 153447 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 153595 1228760 [ 0 0 153595 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 0.434016
|
||||
links_utilized_percent_switch_1_link_0: 0.173606 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.694425 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.694426 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 153447 1227576 [ 0 0 0 153447 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Control: 153447 1227576 [ 0 0 153447 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Control: 153595 1228760 [ 0 0 153595 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 0.434016
|
||||
links_utilized_percent_switch_2_link_0: 0.173606 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.694425 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.694426 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 153447 1227576 [ 0 0 0 153447 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Control: 153447 1227576 [ 0 0 153447 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 153595 1228760 [ 0 0 0 153595 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Control: 153595 1228760 [ 0 0 153595 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_3_inlinks: 2
|
||||
switch_3_outlinks: 2
|
||||
links_utilized_percent_switch_3: 0.434016
|
||||
links_utilized_percent_switch_3_link_0: 0.173606 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 0.694425 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 0.694426 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Writeback_Control: 153446 1227568 [ 0 0 0 153446 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Control: 153447 1227576 [ 0 0 153447 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Control: 153595 1228760 [ 0 0 153595 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_4_inlinks: 2
|
||||
switch_4_outlinks: 2
|
||||
|
|
@ -163,32 +186,32 @@ links_utilized_percent_switch_4: 0.434014
|
|||
links_utilized_percent_switch_4_link_0: 0.173606 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_4_link_1: 0.694421 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_4_link_0_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_0_Writeback_Control: 153446 1227568 [ 0 0 0 153446 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_1_Control: 153446 1227568 [ 0 0 153446 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_1_Response_Data: 153444 11047968 [ 0 0 0 0 153444 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_0_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_0_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_1_Control: 153594 1228752 [ 0 0 153594 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_1_Response_Data: 153592 11058624 [ 0 0 0 0 153592 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_5_inlinks: 2
|
||||
switch_5_outlinks: 2
|
||||
links_utilized_percent_switch_5: 0.434016
|
||||
links_utilized_percent_switch_5_link_0: 0.173606 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_5_link_1: 0.694425 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_5_link_1: 0.694426 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_5_link_0_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_0_Writeback_Control: 153446 1227568 [ 0 0 0 153446 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Control: 153447 1227576 [ 0 0 153447 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_0_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_0_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Control: 153595 1228760 [ 0 0 153595 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_6_inlinks: 2
|
||||
switch_6_outlinks: 2
|
||||
links_utilized_percent_switch_6: 0.434013
|
||||
links_utilized_percent_switch_6_link_0: 0.173605 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_6: 0.434014
|
||||
links_utilized_percent_switch_6_link_0: 0.173606 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_6_link_1: 0.694421 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_6_link_0_Response_Data: 153444 11047968 [ 0 0 0 0 153444 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_0_Writeback_Control: 153446 1227568 [ 0 0 0 153446 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_1_Control: 153446 1227568 [ 0 0 153446 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_1_Response_Data: 153444 11047968 [ 0 0 0 0 153444 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_0_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_0_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_1_Control: 153594 1228752 [ 0 0 153594 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_1_Response_Data: 153592 11058624 [ 0 0 0 0 153592 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_7_inlinks: 2
|
||||
switch_7_outlinks: 2
|
||||
|
|
@ -196,10 +219,10 @@ links_utilized_percent_switch_7: 0.434013
|
|||
links_utilized_percent_switch_7_link_0: 0.173605 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_7_link_1: 0.694421 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_7_link_0_Response_Data: 153444 11047968 [ 0 0 0 0 153444 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_0_Writeback_Control: 153445 1227560 [ 0 0 0 153445 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_1_Control: 153446 1227568 [ 0 0 153446 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_1_Response_Data: 153444 11047968 [ 0 0 0 0 153444 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_0_Response_Data: 153592 11058624 [ 0 0 0 0 153592 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_0_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_1_Control: 153594 1228752 [ 0 0 153594 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_1_Response_Data: 153592 11058624 [ 0 0 0 0 153592 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_8_inlinks: 2
|
||||
switch_8_outlinks: 2
|
||||
|
|
@ -207,458 +230,177 @@ links_utilized_percent_switch_8: 0.347219
|
|||
links_utilized_percent_switch_8_link_0: 0.138886 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_8_link_1: 0.555552 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_8_link_0_Control: 1227573 9820584 [ 0 0 1227573 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_0_Control: 1228757 9830056 [ 0 0 1228757 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_1_Response_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_1_Writeback_Control: 1227569 9820552 [ 0 0 0 1227569 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_1_Writeback_Control: 1228753 9830024 [ 0 0 0 1228753 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_9_inlinks: 9
|
||||
switch_9_outlinks: 9
|
||||
links_utilized_percent_switch_9: 0.678994
|
||||
links_utilized_percent_switch_9_link_0: 0.694429 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_0: 0.694425 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_1: 0.694425 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_2: 0.694425 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_2: 0.694426 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_3: 0.694425 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_4: 0.694425 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_5: 0.694425 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_6: 0.694421 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_7: 0.69442 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_8: 0.555545 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_6: 0.694425 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_7: 0.694421 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_8: 0.555546 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_9_link_0_Response_Data: 153446 11048112 [ 0 0 0 0 153446 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_0_Writeback_Control: 153446 1227568 [ 0 0 0 153446 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_1_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_1_Writeback_Control: 153447 1227576 [ 0 0 0 153447 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_2_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_2_Writeback_Control: 153447 1227576 [ 0 0 0 153447 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_3_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_3_Writeback_Control: 153446 1227568 [ 0 0 0 153446 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_4_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_4_Writeback_Control: 153446 1227568 [ 0 0 0 153446 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_5_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_5_Writeback_Control: 153446 1227568 [ 0 0 0 153446 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_6_Response_Data: 153444 11047968 [ 0 0 0 0 153444 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_6_Writeback_Control: 153446 1227568 [ 0 0 0 153446 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_7_Response_Data: 153444 11047968 [ 0 0 0 0 153444 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_7_Writeback_Control: 153445 1227560 [ 0 0 0 153445 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_8_Control: 1227573 9820584 [ 0 0 1227573 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_0_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_0_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_1_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_1_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_2_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_2_Writeback_Control: 153595 1228760 [ 0 0 0 153595 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_3_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_3_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_4_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_4_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_5_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_5_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_6_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_6_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_7_Response_Data: 153592 11058624 [ 0 0 0 0 153592 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_7_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_8_Control: 1228757 9830056 [ 0 0 1228757 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 153447
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 153447
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
|
||||
Cache Stats: system.l1_cntrl0.cacheMemory
|
||||
system.l1_cntrl0.cacheMemory_total_misses: 153595
|
||||
system.l1_cntrl0.cacheMemory_total_demand_misses: 153595
|
||||
system.l1_cntrl0.cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_LD: 65.0211%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_ST: 34.9789%
|
||||
system.l1_cntrl0.cacheMemory_request_type_LD: 64.8608%
|
||||
system.l1_cntrl0.cacheMemory_request_type_ST: 35.1392%
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153447 100%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153447 average: 1 | standard deviation: 0 | 0 153447 ]
|
||||
system.l1_cntrl0.cacheMemory_access_mode_type_SupervisorMode: 153595 100%
|
||||
|
||||
--- L1Cache 0 ---
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load 99774
|
||||
Ifetch 0
|
||||
Store 53675
|
||||
Data 153446
|
||||
Fwd_GETX 153446
|
||||
Inv 0
|
||||
Replacement 0
|
||||
Writeback_Ack 0
|
||||
Writeback_Nack 0
|
||||
Load [100001 99948 99718 99978 99623 99719 99984 99512 ] 798483
|
||||
Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
Store [53593 53647 53876 53616 53974 53880 53619 54083 ] 430288
|
||||
Data [153593 153593 153593 153592 153593 153593 153593 153593 ] 1228743
|
||||
Fwd_GETX [153593 153593 153593 153592 153593 153593 153593 153593 ] 1228743
|
||||
Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
Writeback_Ack [0 0 0 0 0 0 0 0 ] 0
|
||||
Writeback_Nack [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
- Transitions -
|
||||
I Load 99773
|
||||
I Ifetch 0 <--
|
||||
I Store 53674
|
||||
I Inv 0 <--
|
||||
I Replacement 0 <--
|
||||
I Load [100001 99948 99718 99978 99623 99718 99978 99512 ] 798476
|
||||
I Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
I Store [53593 53647 53876 53616 53972 53877 53617 54083 ] 430281
|
||||
I Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
I Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
II Writeback_Nack 0 <--
|
||||
II Writeback_Nack [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
M Load 1
|
||||
M Ifetch 0 <--
|
||||
M Store 1
|
||||
M Fwd_GETX 153446
|
||||
M Inv 0 <--
|
||||
M Replacement 0 <--
|
||||
M Load [0 0 0 0 0 1 6 0 ] 7
|
||||
M Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
M Store [0 0 0 0 2 3 2 0 ] 7
|
||||
M Fwd_GETX [153593 153593 153593 153592 153593 153593 153593 153593 ] 1228743
|
||||
M Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
M Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
MI Fwd_GETX 0 <--
|
||||
MI Inv 0 <--
|
||||
MI Writeback_Ack 0 <--
|
||||
MI Writeback_Nack 0 <--
|
||||
MI Fwd_GETX [0 0 0 0 0 0 0 0 ] 0
|
||||
MI Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
MI Writeback_Ack [0 0 0 0 0 0 0 0 ] 0
|
||||
MI Writeback_Nack [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
MII Fwd_GETX 0 <--
|
||||
MII Fwd_GETX [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
IS Data 99773
|
||||
IS Data [100000 99946 99718 99976 99622 99716 99977 99512 ] 798467
|
||||
|
||||
IM Data 53673
|
||||
IM Data [53593 53647 53875 53616 53971 53877 53616 54081 ] 430276
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links1.ext_node.sequencer.icache
|
||||
system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_misses: 153447
|
||||
system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_demand_misses: 153447
|
||||
system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_hw_prefetches: 0
|
||||
Cache Stats: system.l1_cntrl1.cacheMemory
|
||||
system.l1_cntrl1.cacheMemory_total_misses: 153595
|
||||
system.l1_cntrl1.cacheMemory_total_demand_misses: 153595
|
||||
system.l1_cntrl1.cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl1.cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl1.cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_request_type_LD: 64.6816%
|
||||
system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_request_type_ST: 35.3184%
|
||||
system.l1_cntrl1.cacheMemory_request_type_LD: 64.9227%
|
||||
system.l1_cntrl1.cacheMemory_request_type_ST: 35.0773%
|
||||
|
||||
system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153447 100%
|
||||
system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153447 average: 1 | standard deviation: 0 | 0 153447 ]
|
||||
system.l1_cntrl1.cacheMemory_access_mode_type_SupervisorMode: 153595 100%
|
||||
|
||||
--- L1Cache 1 ---
|
||||
- Event Counts -
|
||||
Load 99260
|
||||
Ifetch 0
|
||||
Store 54199
|
||||
Data 153445
|
||||
Fwd_GETX 153445
|
||||
Inv 0
|
||||
Replacement 0
|
||||
Writeback_Ack 0
|
||||
Writeback_Nack 0
|
||||
Cache Stats: system.l1_cntrl2.cacheMemory
|
||||
system.l1_cntrl2.cacheMemory_total_misses: 153595
|
||||
system.l1_cntrl2.cacheMemory_total_demand_misses: 153595
|
||||
system.l1_cntrl2.cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl2.cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl2.cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
- Transitions -
|
||||
I Load 99252
|
||||
I Ifetch 0 <--
|
||||
I Store 54195
|
||||
I Inv 0 <--
|
||||
I Replacement 0 <--
|
||||
system.l1_cntrl2.cacheMemory_request_type_LD: 65.092%
|
||||
system.l1_cntrl2.cacheMemory_request_type_ST: 34.908%
|
||||
|
||||
II Writeback_Nack 0 <--
|
||||
system.l1_cntrl2.cacheMemory_access_mode_type_SupervisorMode: 153595 100%
|
||||
|
||||
M Load 8
|
||||
M Ifetch 0 <--
|
||||
M Store 4
|
||||
M Fwd_GETX 153445
|
||||
M Inv 0 <--
|
||||
M Replacement 0 <--
|
||||
Cache Stats: system.l1_cntrl3.cacheMemory
|
||||
system.l1_cntrl3.cacheMemory_total_misses: 153595
|
||||
system.l1_cntrl3.cacheMemory_total_demand_misses: 153595
|
||||
system.l1_cntrl3.cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl3.cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl3.cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
MI Fwd_GETX 0 <--
|
||||
MI Inv 0 <--
|
||||
MI Writeback_Ack 0 <--
|
||||
MI Writeback_Nack 0 <--
|
||||
system.l1_cntrl3.cacheMemory_request_type_LD: 64.7886%
|
||||
system.l1_cntrl3.cacheMemory_request_type_ST: 35.2114%
|
||||
|
||||
MII Fwd_GETX 0 <--
|
||||
system.l1_cntrl3.cacheMemory_access_mode_type_SupervisorMode: 153595 100%
|
||||
|
||||
IS Data 99251
|
||||
Cache Stats: system.l1_cntrl4.cacheMemory
|
||||
system.l1_cntrl4.cacheMemory_total_misses: 153594
|
||||
system.l1_cntrl4.cacheMemory_total_demand_misses: 153594
|
||||
system.l1_cntrl4.cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl4.cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl4.cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
IM Data 54194
|
||||
system.l1_cntrl4.cacheMemory_request_type_LD: 65.1074%
|
||||
system.l1_cntrl4.cacheMemory_request_type_ST: 34.8926%
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links2.ext_node.sequencer.icache
|
||||
system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_misses: 153447
|
||||
system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_demand_misses: 153447
|
||||
system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_hw_prefetches: 0
|
||||
system.l1_cntrl4.cacheMemory_access_mode_type_SupervisorMode: 153594 100%
|
||||
|
||||
system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_request_type_LD: 64.8804%
|
||||
system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_request_type_ST: 35.1196%
|
||||
Cache Stats: system.l1_cntrl5.cacheMemory
|
||||
system.l1_cntrl5.cacheMemory_total_misses: 153595
|
||||
system.l1_cntrl5.cacheMemory_total_demand_misses: 153595
|
||||
system.l1_cntrl5.cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl5.cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl5.cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153447 100%
|
||||
system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153447 average: 1 | standard deviation: 0 | 0 153447 ]
|
||||
system.l1_cntrl5.cacheMemory_request_type_LD: 65.0724%
|
||||
system.l1_cntrl5.cacheMemory_request_type_ST: 34.9276%
|
||||
|
||||
--- L1Cache 2 ---
|
||||
- Event Counts -
|
||||
Load 99557
|
||||
Ifetch 0
|
||||
Store 53890
|
||||
Data 153445
|
||||
Fwd_GETX 153445
|
||||
Inv 0
|
||||
Replacement 0
|
||||
Writeback_Ack 0
|
||||
Writeback_Nack 0
|
||||
system.l1_cntrl5.cacheMemory_access_mode_type_SupervisorMode: 153595 100%
|
||||
|
||||
- Transitions -
|
||||
I Load 99557
|
||||
I Ifetch 0 <--
|
||||
I Store 53890
|
||||
I Inv 0 <--
|
||||
I Replacement 0 <--
|
||||
Cache Stats: system.l1_cntrl6.cacheMemory
|
||||
system.l1_cntrl6.cacheMemory_total_misses: 153594
|
||||
system.l1_cntrl6.cacheMemory_total_demand_misses: 153594
|
||||
system.l1_cntrl6.cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl6.cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl6.cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
II Writeback_Nack 0 <--
|
||||
system.l1_cntrl6.cacheMemory_request_type_LD: 64.9231%
|
||||
system.l1_cntrl6.cacheMemory_request_type_ST: 35.0769%
|
||||
|
||||
M Load 0 <--
|
||||
M Ifetch 0 <--
|
||||
M Store 0 <--
|
||||
M Fwd_GETX 153445
|
||||
M Inv 0 <--
|
||||
M Replacement 0 <--
|
||||
system.l1_cntrl6.cacheMemory_access_mode_type_SupervisorMode: 153594 100%
|
||||
|
||||
MI Fwd_GETX 0 <--
|
||||
MI Inv 0 <--
|
||||
MI Writeback_Ack 0 <--
|
||||
MI Writeback_Nack 0 <--
|
||||
Cache Stats: system.l1_cntrl7.cacheMemory
|
||||
system.l1_cntrl7.cacheMemory_total_misses: 153594
|
||||
system.l1_cntrl7.cacheMemory_total_demand_misses: 153594
|
||||
system.l1_cntrl7.cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl7.cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl7.cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
MII Fwd_GETX 0 <--
|
||||
system.l1_cntrl7.cacheMemory_request_type_LD: 65.0924%
|
||||
system.l1_cntrl7.cacheMemory_request_type_ST: 34.9076%
|
||||
|
||||
IS Data 99555
|
||||
system.l1_cntrl7.cacheMemory_access_mode_type_SupervisorMode: 153594 100%
|
||||
|
||||
IM Data 53890
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links3.ext_node.sequencer.icache
|
||||
system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_misses: 153447
|
||||
system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_demand_misses: 153447
|
||||
system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_hw_prefetches: 0
|
||||
|
||||
system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_request_type_LD: 65.1254%
|
||||
system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_request_type_ST: 34.8746%
|
||||
|
||||
system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153447 100%
|
||||
system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153447 average: 1 | standard deviation: 0 | 0 153447 ]
|
||||
|
||||
--- L1Cache 3 ---
|
||||
- Event Counts -
|
||||
Load 99933
|
||||
Ifetch 0
|
||||
Store 53514
|
||||
Data 153445
|
||||
Fwd_GETX 153445
|
||||
Inv 0
|
||||
Replacement 0
|
||||
Writeback_Ack 0
|
||||
Writeback_Nack 0
|
||||
|
||||
- Transitions -
|
||||
I Load 99933
|
||||
I Ifetch 0 <--
|
||||
I Store 53514
|
||||
I Inv 0 <--
|
||||
I Replacement 0 <--
|
||||
|
||||
II Writeback_Nack 0 <--
|
||||
|
||||
M Load 0 <--
|
||||
M Ifetch 0 <--
|
||||
M Store 0 <--
|
||||
M Fwd_GETX 153445
|
||||
M Inv 0 <--
|
||||
M Replacement 0 <--
|
||||
|
||||
MI Fwd_GETX 0 <--
|
||||
MI Inv 0 <--
|
||||
MI Writeback_Ack 0 <--
|
||||
MI Writeback_Nack 0 <--
|
||||
|
||||
MII Fwd_GETX 0 <--
|
||||
|
||||
IS Data 99932
|
||||
|
||||
IM Data 53513
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links4.ext_node.sequencer.icache
|
||||
system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_misses: 153446
|
||||
system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_demand_misses: 153446
|
||||
system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_hw_prefetches: 0
|
||||
|
||||
system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_request_type_LD: 65.1702%
|
||||
system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_request_type_ST: 34.8298%
|
||||
|
||||
system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153446 100%
|
||||
system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153446 average: 1 | standard deviation: 0 | 0 153446 ]
|
||||
|
||||
--- L1Cache 4 ---
|
||||
- Event Counts -
|
||||
Load 100001
|
||||
Ifetch 0
|
||||
Store 53445
|
||||
Data 153445
|
||||
Fwd_GETX 153445
|
||||
Inv 0
|
||||
Replacement 0
|
||||
Writeback_Ack 0
|
||||
Writeback_Nack 0
|
||||
|
||||
- Transitions -
|
||||
I Load 100001
|
||||
I Ifetch 0 <--
|
||||
I Store 53445
|
||||
I Inv 0 <--
|
||||
I Replacement 0 <--
|
||||
|
||||
II Writeback_Nack 0 <--
|
||||
|
||||
M Load 0 <--
|
||||
M Ifetch 0 <--
|
||||
M Store 0 <--
|
||||
M Fwd_GETX 153445
|
||||
M Inv 0 <--
|
||||
M Replacement 0 <--
|
||||
|
||||
MI Fwd_GETX 0 <--
|
||||
MI Inv 0 <--
|
||||
MI Writeback_Ack 0 <--
|
||||
MI Writeback_Nack 0 <--
|
||||
|
||||
MII Fwd_GETX 0 <--
|
||||
|
||||
IS Data 100000
|
||||
|
||||
IM Data 53445
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links5.ext_node.sequencer.icache
|
||||
system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_misses: 153447
|
||||
system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_demand_misses: 153447
|
||||
system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_hw_prefetches: 0
|
||||
|
||||
system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_request_type_LD: 65.1137%
|
||||
system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_request_type_ST: 34.8863%
|
||||
|
||||
system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153447 100%
|
||||
system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153447 average: 1 | standard deviation: 0 | 0 153447 ]
|
||||
|
||||
--- L1Cache 5 ---
|
||||
- Event Counts -
|
||||
Load 99915
|
||||
Ifetch 0
|
||||
Store 53532
|
||||
Data 153445
|
||||
Fwd_GETX 153445
|
||||
Inv 0
|
||||
Replacement 0
|
||||
Writeback_Ack 0
|
||||
Writeback_Nack 0
|
||||
|
||||
- Transitions -
|
||||
I Load 99915
|
||||
I Ifetch 0 <--
|
||||
I Store 53532
|
||||
I Inv 0 <--
|
||||
I Replacement 0 <--
|
||||
|
||||
II Writeback_Nack 0 <--
|
||||
|
||||
M Load 0 <--
|
||||
M Ifetch 0 <--
|
||||
M Store 0 <--
|
||||
M Fwd_GETX 153445
|
||||
M Inv 0 <--
|
||||
M Replacement 0 <--
|
||||
|
||||
MI Fwd_GETX 0 <--
|
||||
MI Inv 0 <--
|
||||
MI Writeback_Ack 0 <--
|
||||
MI Writeback_Nack 0 <--
|
||||
|
||||
MII Fwd_GETX 0 <--
|
||||
|
||||
IS Data 99914
|
||||
|
||||
IM Data 53531
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links6.ext_node.sequencer.icache
|
||||
system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_misses: 153446
|
||||
system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_demand_misses: 153446
|
||||
system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_hw_prefetches: 0
|
||||
|
||||
system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_request_type_LD: 65.0203%
|
||||
system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_request_type_ST: 34.9797%
|
||||
|
||||
system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153446 100%
|
||||
system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153446 average: 1 | standard deviation: 0 | 0 153446 ]
|
||||
|
||||
--- L1Cache 6 ---
|
||||
- Event Counts -
|
||||
Load 99771
|
||||
Ifetch 0
|
||||
Store 53675
|
||||
Data 153444
|
||||
Fwd_GETX 153444
|
||||
Inv 0
|
||||
Replacement 0
|
||||
Writeback_Ack 0
|
||||
Writeback_Nack 0
|
||||
|
||||
- Transitions -
|
||||
I Load 99771
|
||||
I Ifetch 0 <--
|
||||
I Store 53675
|
||||
I Inv 0 <--
|
||||
I Replacement 0 <--
|
||||
|
||||
II Writeback_Nack 0 <--
|
||||
|
||||
M Load 0 <--
|
||||
M Ifetch 0 <--
|
||||
M Store 0 <--
|
||||
M Fwd_GETX 153444
|
||||
M Inv 0 <--
|
||||
M Replacement 0 <--
|
||||
|
||||
MI Fwd_GETX 0 <--
|
||||
MI Inv 0 <--
|
||||
MI Writeback_Ack 0 <--
|
||||
MI Writeback_Nack 0 <--
|
||||
|
||||
MII Fwd_GETX 0 <--
|
||||
|
||||
IS Data 99770
|
||||
|
||||
IM Data 53674
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links7.ext_node.sequencer.icache
|
||||
system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_misses: 153446
|
||||
system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_demand_misses: 153446
|
||||
system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_hw_prefetches: 0
|
||||
|
||||
system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_request_type_LD: 65.0841%
|
||||
system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_request_type_ST: 34.9159%
|
||||
|
||||
system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153446 100%
|
||||
system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153446 average: 1 | standard deviation: 0 | 0 153446 ]
|
||||
|
||||
--- L1Cache 7 ---
|
||||
- Event Counts -
|
||||
Load 99869
|
||||
Ifetch 0
|
||||
Store 53577
|
||||
Data 153444
|
||||
Fwd_GETX 153444
|
||||
Inv 0
|
||||
Replacement 0
|
||||
Writeback_Ack 0
|
||||
Writeback_Nack 0
|
||||
|
||||
- Transitions -
|
||||
I Load 99869
|
||||
I Ifetch 0 <--
|
||||
I Store 53577
|
||||
I Inv 0 <--
|
||||
I Replacement 0 <--
|
||||
|
||||
II Writeback_Nack 0 <--
|
||||
|
||||
M Load 0 <--
|
||||
M Ifetch 0 <--
|
||||
M Store 0 <--
|
||||
M Fwd_GETX 153444
|
||||
M Inv 0 <--
|
||||
M Replacement 0 <--
|
||||
|
||||
MI Fwd_GETX 0 <--
|
||||
MI Inv 0 <--
|
||||
MI Writeback_Ack 0 <--
|
||||
MI Writeback_Nack 0 <--
|
||||
|
||||
MII Fwd_GETX 0 <--
|
||||
|
||||
IS Data 99868
|
||||
|
||||
IM Data 53576
|
||||
|
||||
Memory controller: system.ruby.network.topology.ext_links8.ext_node.memBuffer:
|
||||
Memory controller: system.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 2
|
||||
memory_reads: 2
|
||||
memory_writes: 0
|
||||
|
|
@ -678,70 +420,69 @@ Memory controller: system.ruby.network.topology.ext_links8.ext_node.memBuffer:
|
|||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
|
||||
|
||||
--- Directory 0 ---
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
GETX 1227984
|
||||
GETS 0
|
||||
PUTX 0
|
||||
PUTX_NotOwner 0
|
||||
DMA_READ 0
|
||||
DMA_WRITE 0
|
||||
Memory_Data 2
|
||||
Memory_Ack 0
|
||||
GETX [1229168 ] 1229168
|
||||
GETS [0 ] 0
|
||||
PUTX [0 ] 0
|
||||
PUTX_NotOwner [0 ] 0
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
Memory_Data [2 ] 2
|
||||
Memory_Ack [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
I GETX 2
|
||||
I PUTX_NotOwner 0 <--
|
||||
I DMA_READ 0 <--
|
||||
I DMA_WRITE 0 <--
|
||||
I GETX [2 ] 2
|
||||
I PUTX_NotOwner [0 ] 0
|
||||
I DMA_READ [0 ] 0
|
||||
I DMA_WRITE [0 ] 0
|
||||
|
||||
M GETX 1227571
|
||||
M PUTX 0 <--
|
||||
M PUTX_NotOwner 0 <--
|
||||
M DMA_READ 0 <--
|
||||
M DMA_WRITE 0 <--
|
||||
M GETX [1228755 ] 1228755
|
||||
M PUTX [0 ] 0
|
||||
M PUTX_NotOwner [0 ] 0
|
||||
M DMA_READ [0 ] 0
|
||||
M DMA_WRITE [0 ] 0
|
||||
|
||||
M_DRD GETX 0 <--
|
||||
M_DRD PUTX 0 <--
|
||||
M_DRD GETX [0 ] 0
|
||||
M_DRD PUTX [0 ] 0
|
||||
|
||||
M_DWR GETX 0 <--
|
||||
M_DWR PUTX 0 <--
|
||||
M_DWR GETX [0 ] 0
|
||||
M_DWR PUTX [0 ] 0
|
||||
|
||||
M_DWRI GETX 0 <--
|
||||
M_DWRI Memory_Ack 0 <--
|
||||
M_DWRI GETX [0 ] 0
|
||||
M_DWRI Memory_Ack [0 ] 0
|
||||
|
||||
M_DRDI GETX 0 <--
|
||||
M_DRDI Memory_Ack 0 <--
|
||||
M_DRDI GETX [0 ] 0
|
||||
M_DRDI Memory_Ack [0 ] 0
|
||||
|
||||
IM GETX 411
|
||||
IM GETS 0 <--
|
||||
IM PUTX 0 <--
|
||||
IM PUTX_NotOwner 0 <--
|
||||
IM DMA_READ 0 <--
|
||||
IM DMA_WRITE 0 <--
|
||||
IM Memory_Data 2
|
||||
IM GETX [411 ] 411
|
||||
IM GETS [0 ] 0
|
||||
IM PUTX [0 ] 0
|
||||
IM PUTX_NotOwner [0 ] 0
|
||||
IM DMA_READ [0 ] 0
|
||||
IM DMA_WRITE [0 ] 0
|
||||
IM Memory_Data [2 ] 2
|
||||
|
||||
MI GETX 0 <--
|
||||
MI GETS 0 <--
|
||||
MI PUTX 0 <--
|
||||
MI PUTX_NotOwner 0 <--
|
||||
MI DMA_READ 0 <--
|
||||
MI DMA_WRITE 0 <--
|
||||
MI Memory_Ack 0 <--
|
||||
MI GETX [0 ] 0
|
||||
MI GETS [0 ] 0
|
||||
MI PUTX [0 ] 0
|
||||
MI PUTX_NotOwner [0 ] 0
|
||||
MI DMA_READ [0 ] 0
|
||||
MI DMA_WRITE [0 ] 0
|
||||
MI Memory_Ack [0 ] 0
|
||||
|
||||
ID GETX 0 <--
|
||||
ID GETS 0 <--
|
||||
ID PUTX 0 <--
|
||||
ID PUTX_NotOwner 0 <--
|
||||
ID DMA_READ 0 <--
|
||||
ID DMA_WRITE 0 <--
|
||||
ID Memory_Data 0 <--
|
||||
|
||||
ID_W GETX 0 <--
|
||||
ID_W GETS 0 <--
|
||||
ID_W PUTX 0 <--
|
||||
ID_W PUTX_NotOwner 0 <--
|
||||
ID_W DMA_READ 0 <--
|
||||
ID_W DMA_WRITE 0 <--
|
||||
ID_W Memory_Ack 0 <--
|
||||
ID GETX [0 ] 0
|
||||
ID GETS [0 ] 0
|
||||
ID PUTX [0 ] 0
|
||||
ID PUTX_NotOwner [0 ] 0
|
||||
ID DMA_READ [0 ] 0
|
||||
ID DMA_WRITE [0 ] 0
|
||||
ID Memory_Data [0 ] 0
|
||||
|
||||
ID_W GETX [0 ] 0
|
||||
ID_W GETS [0 ] 0
|
||||
ID_W PUTX [0 ] 0
|
||||
ID_W PUTX_NotOwner [0 ] 0
|
||||
ID_W DMA_READ [0 ] 0
|
||||
ID_W DMA_WRITE [0 ] 0
|
||||
ID_W Memory_Ack
|
||||
|
|
@ -1,74 +1,74 @@
|
|||
system.cpu5: completed 10000 read accesses @1097795
|
||||
system.cpu1: completed 10000 read accesses @1101449
|
||||
system.cpu4: completed 10000 read accesses @1103861
|
||||
system.cpu3: completed 10000 read accesses @1104689
|
||||
system.cpu6: completed 10000 read accesses @1107767
|
||||
system.cpu2: completed 10000 read accesses @1108955
|
||||
system.cpu0: completed 10000 read accesses @1109315
|
||||
system.cpu7: completed 10000 read accesses @1115237
|
||||
system.cpu5: completed 20000 read accesses @2202527
|
||||
system.cpu4: completed 20000 read accesses @2207405
|
||||
system.cpu3: completed 20000 read accesses @2212049
|
||||
system.cpu2: completed 20000 read accesses @2212140
|
||||
system.cpu6: completed 20000 read accesses @2216495
|
||||
system.cpu1: completed 20000 read accesses @2218601
|
||||
system.cpu7: completed 20000 read accesses @2229041
|
||||
system.cpu0: completed 20000 read accesses @2229203
|
||||
system.cpu5: completed 30000 read accesses @3306575
|
||||
system.cpu4: completed 30000 read accesses @3307925
|
||||
system.cpu3: completed 30000 read accesses @3308753
|
||||
system.cpu7: completed 30000 read accesses @3318869
|
||||
system.cpu6: completed 30000 read accesses @3328247
|
||||
system.cpu2: completed 30000 read accesses @3331884
|
||||
system.cpu1: completed 30000 read accesses @3338201
|
||||
system.cpu0: completed 30000 read accesses @3340343
|
||||
system.cpu5: completed 40000 read accesses @4410227
|
||||
system.cpu4: completed 40000 read accesses @4410389
|
||||
system.cpu3: completed 40000 read accesses @4424177
|
||||
system.cpu7: completed 40000 read accesses @4429973
|
||||
system.cpu0: completed 40000 read accesses @4435175
|
||||
system.cpu6: completed 40000 read accesses @4438199
|
||||
system.cpu2: completed 40000 read accesses @4444715
|
||||
system.cpu1: completed 40000 read accesses @4450313
|
||||
system.cpu5: completed 50000 read accesses @5504627
|
||||
system.cpu4: completed 50000 read accesses @5519333
|
||||
system.cpu3: completed 50000 read accesses @5526785
|
||||
system.cpu7: completed 50000 read accesses @5529377
|
||||
system.cpu0: completed 50000 read accesses @5532419
|
||||
system.cpu6: completed 50000 read accesses @5546639
|
||||
system.cpu2: completed 50000 read accesses @5560715
|
||||
system.cpu1: completed 50000 read accesses @5569193
|
||||
system.cpu5: completed 60000 read accesses @6620303
|
||||
system.cpu4: completed 60000 read accesses @6630005
|
||||
system.cpu3: completed 60000 read accesses @6637745
|
||||
system.cpu7: completed 60000 read accesses @6639905
|
||||
system.cpu0: completed 60000 read accesses @6649463
|
||||
system.cpu6: completed 60000 read accesses @6652055
|
||||
system.cpu2: completed 60000 read accesses @6667068
|
||||
system.cpu1: completed 60000 read accesses @6690378
|
||||
system.cpu5: completed 70000 read accesses @7728671
|
||||
system.cpu3: completed 70000 read accesses @7729265
|
||||
system.cpu4: completed 70000 read accesses @7729373
|
||||
system.cpu7: completed 70000 read accesses @7748849
|
||||
system.cpu6: completed 70000 read accesses @7751423
|
||||
system.cpu0: completed 70000 read accesses @7760099
|
||||
system.cpu2: completed 70000 read accesses @7781196
|
||||
system.cpu1: completed 70000 read accesses @7788377
|
||||
system.cpu4: completed 80000 read accesses @8833637
|
||||
system.cpu3: completed 80000 read accesses @8841377
|
||||
system.cpu5: completed 80000 read accesses @8845283
|
||||
system.cpu7: completed 80000 read accesses @8850647
|
||||
system.cpu0: completed 80000 read accesses @8859269
|
||||
system.cpu6: completed 80000 read accesses @8861015
|
||||
system.cpu2: completed 80000 read accesses @8880203
|
||||
system.cpu1: completed 80000 read accesses @8893866
|
||||
system.cpu4: completed 90000 read accesses @9931349
|
||||
system.cpu7: completed 90000 read accesses @9951959
|
||||
system.cpu5: completed 90000 read accesses @9952175
|
||||
system.cpu3: completed 90000 read accesses @9957341
|
||||
system.cpu6: completed 90000 read accesses @9967079
|
||||
system.cpu0: completed 90000 read accesses @9971795
|
||||
system.cpu2: completed 90000 read accesses @9992027
|
||||
system.cpu1: completed 90000 read accesses @10012745
|
||||
system.cpu4: completed 100000 read accesses @11048357
|
||||
system.cpu5: completed 10000 read accesses @1097056
|
||||
system.cpu4: completed 10000 read accesses @1101790
|
||||
system.cpu2: completed 10000 read accesses @1104058
|
||||
system.cpu0: completed 10000 read accesses @1107910
|
||||
system.cpu7: completed 10000 read accesses @1111870
|
||||
system.cpu1: completed 10000 read accesses @1114192
|
||||
system.cpu6: completed 10000 read accesses @1114876
|
||||
system.cpu3: completed 10000 read accesses @1117090
|
||||
system.cpu5: completed 20000 read accesses @2192968
|
||||
system.cpu0: completed 20000 read accesses @2201554
|
||||
system.cpu2: completed 20000 read accesses @2213290
|
||||
system.cpu4: completed 20000 read accesses @2213470
|
||||
system.cpu6: completed 20000 read accesses @2213812
|
||||
system.cpu7: completed 20000 read accesses @2222758
|
||||
system.cpu1: completed 20000 read accesses @2232856
|
||||
system.cpu3: completed 20000 read accesses @2238562
|
||||
system.cpu5: completed 30000 read accesses @3309256
|
||||
system.cpu6: completed 30000 read accesses @3313180
|
||||
system.cpu0: completed 30000 read accesses @3314566
|
||||
system.cpu4: completed 30000 read accesses @3316942
|
||||
system.cpu2: completed 30000 read accesses @3324682
|
||||
system.cpu7: completed 30000 read accesses @3331702
|
||||
system.cpu1: completed 30000 read accesses @3337912
|
||||
system.cpu3: completed 30000 read accesses @3342322
|
||||
system.cpu5: completed 40000 read accesses @4420792
|
||||
system.cpu7: completed 40000 read accesses @4420990
|
||||
system.cpu6: completed 40000 read accesses @4421692
|
||||
system.cpu4: completed 40000 read accesses @4422430
|
||||
system.cpu0: completed 40000 read accesses @4424770
|
||||
system.cpu2: completed 40000 read accesses @4424842
|
||||
system.cpu3: completed 40000 read accesses @4446316
|
||||
system.cpu1: completed 40000 read accesses @4448440
|
||||
system.cpu5: completed 50000 read accesses @5519584
|
||||
system.cpu4: completed 50000 read accesses @5528980
|
||||
system.cpu0: completed 50000 read accesses @5530150
|
||||
system.cpu2: completed 50000 read accesses @5533210
|
||||
system.cpu7: completed 50000 read accesses @5537782
|
||||
system.cpu6: completed 50000 read accesses @5538916
|
||||
system.cpu3: completed 50000 read accesses @5549410
|
||||
system.cpu1: completed 50000 read accesses @5549536
|
||||
system.cpu7: completed 60000 read accesses @6629734
|
||||
system.cpu5: completed 60000 read accesses @6636160
|
||||
system.cpu4: completed 60000 read accesses @6637060
|
||||
system.cpu2: completed 60000 read accesses @6637402
|
||||
system.cpu0: completed 60000 read accesses @6644710
|
||||
system.cpu1: completed 60000 read accesses @6651352
|
||||
system.cpu6: completed 60000 read accesses @6651892
|
||||
system.cpu3: completed 60000 read accesses @6661234
|
||||
system.cpu7: completed 70000 read accesses @7727014
|
||||
system.cpu4: completed 70000 read accesses @7730110
|
||||
system.cpu5: completed 70000 read accesses @7736608
|
||||
system.cpu2: completed 70000 read accesses @7742746
|
||||
system.cpu6: completed 70000 read accesses @7757092
|
||||
system.cpu0: completed 70000 read accesses @7759378
|
||||
system.cpu1: completed 70000 read accesses @7770088
|
||||
system.cpu3: completed 70000 read accesses @7773058
|
||||
system.cpu5: completed 80000 read accesses @8842240
|
||||
system.cpu7: completed 80000 read accesses @8843086
|
||||
system.cpu4: completed 80000 read accesses @8844580
|
||||
system.cpu2: completed 80000 read accesses @8853131
|
||||
system.cpu0: completed 80000 read accesses @8863426
|
||||
system.cpu6: completed 80000 read accesses @8876836
|
||||
system.cpu1: completed 80000 read accesses @8878960
|
||||
system.cpu3: completed 80000 read accesses @8885602
|
||||
system.cpu5: completed 90000 read accesses @9955126
|
||||
system.cpu7: completed 90000 read accesses @9956782
|
||||
system.cpu4: completed 90000 read accesses @9957844
|
||||
system.cpu2: completed 90000 read accesses @9967690
|
||||
system.cpu1: completed 90000 read accesses @9973576
|
||||
system.cpu0: completed 90000 read accesses @9976024
|
||||
system.cpu6: completed 90000 read accesses @9981604
|
||||
system.cpu3: completed 90000 read accesses @9999874
|
||||
system.cpu4: completed 100000 read accesses @11059012
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Mar 18 2010 15:34:55
|
||||
M5 revision 6a6bb24e484f+ 7041+ default qtip tip brad/regress_updates
|
||||
M5 started Mar 18 2010 15:35:01
|
||||
M5 executing on cabr0210
|
||||
M5 compiled Aug 20 2010 12:21:09
|
||||
M5 revision c4b5df973361+ 7570+ default qtip tip brad/regress_updates
|
||||
M5 started Aug 20 2010 13:38:22
|
||||
M5 executing on SC2B0629
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 11048357 because maximum number of loads reached
|
||||
Exiting @ tick 11059012 because maximum number of loads reached
|
||||
|
|
|
|||
|
|
@ -1,34 +1,34 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_mem_usage 339664 # Number of bytes of host memory used
|
||||
host_seconds 76.81 # Real time elapsed on the host
|
||||
host_tick_rate 143842 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 341104 # Number of bytes of host memory used
|
||||
host_seconds 68.57 # Real time elapsed on the host
|
||||
host_tick_rate 161272 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_seconds 0.011048 # Number of seconds simulated
|
||||
sim_ticks 11048357 # Number of ticks simulated
|
||||
sim_seconds 0.011059 # Number of seconds simulated
|
||||
sim_ticks 11059012 # Number of ticks simulated
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
system.cpu0.num_reads 99774 # number of read accesses completed
|
||||
system.cpu0.num_writes 53674 # number of write accesses completed
|
||||
system.cpu0.num_reads 99622 # number of read accesses completed
|
||||
system.cpu0.num_writes 53973 # number of write accesses completed
|
||||
system.cpu1.num_copies 0 # number of copy accesses completed
|
||||
system.cpu1.num_reads 99259 # number of read accesses completed
|
||||
system.cpu1.num_writes 54198 # number of write accesses completed
|
||||
system.cpu1.num_reads 99717 # number of read accesses completed
|
||||
system.cpu1.num_writes 53880 # number of write accesses completed
|
||||
system.cpu2.num_copies 0 # number of copy accesses completed
|
||||
system.cpu2.num_reads 99555 # number of read accesses completed
|
||||
system.cpu2.num_writes 53890 # number of write accesses completed
|
||||
system.cpu2.num_reads 99983 # number of read accesses completed
|
||||
system.cpu2.num_writes 53618 # number of write accesses completed
|
||||
system.cpu3.num_copies 0 # number of copy accesses completed
|
||||
system.cpu3.num_reads 99932 # number of read accesses completed
|
||||
system.cpu3.num_writes 53513 # number of write accesses completed
|
||||
system.cpu3.num_reads 99512 # number of read accesses completed
|
||||
system.cpu3.num_writes 54081 # number of write accesses completed
|
||||
system.cpu4.num_copies 0 # number of copy accesses completed
|
||||
system.cpu4.num_reads 100000 # number of read accesses completed
|
||||
system.cpu4.num_writes 53445 # number of write accesses completed
|
||||
system.cpu4.num_writes 53593 # number of write accesses completed
|
||||
system.cpu5.num_copies 0 # number of copy accesses completed
|
||||
system.cpu5.num_reads 99914 # number of read accesses completed
|
||||
system.cpu5.num_writes 53531 # number of write accesses completed
|
||||
system.cpu5.num_reads 99946 # number of read accesses completed
|
||||
system.cpu5.num_writes 53647 # number of write accesses completed
|
||||
system.cpu6.num_copies 0 # number of copy accesses completed
|
||||
system.cpu6.num_reads 99770 # number of read accesses completed
|
||||
system.cpu6.num_writes 53674 # number of write accesses completed
|
||||
system.cpu6.num_reads 99718 # number of read accesses completed
|
||||
system.cpu6.num_writes 53875 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
system.cpu7.num_reads 99868 # number of read accesses completed
|
||||
system.cpu7.num_writes 53576 # number of write accesses completed
|
||||
system.cpu7.num_reads 99976 # number of read accesses completed
|
||||
system.cpu7.num_writes 53616 # number of write accesses completed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@ physmem=system.physmem
|
|||
type=MemTest
|
||||
children=l1c
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -60,6 +61,7 @@ mem_side=system.toL2Bus.port[1]
|
|||
type=MemTest
|
||||
children=l1c
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -107,6 +109,7 @@ mem_side=system.toL2Bus.port[2]
|
|||
type=MemTest
|
||||
children=l1c
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -154,6 +157,7 @@ mem_side=system.toL2Bus.port[3]
|
|||
type=MemTest
|
||||
children=l1c
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -201,6 +205,7 @@ mem_side=system.toL2Bus.port[4]
|
|||
type=MemTest
|
||||
children=l1c
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -248,6 +253,7 @@ mem_side=system.toL2Bus.port[5]
|
|||
type=MemTest
|
||||
children=l1c
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -295,6 +301,7 @@ mem_side=system.toL2Bus.port[6]
|
|||
type=MemTest
|
||||
children=l1c
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
@ -342,6 +349,7 @@ mem_side=system.toL2Bus.port[7]
|
|||
type=MemTest
|
||||
children=l1c
|
||||
atomic=false
|
||||
issue_dmas=false
|
||||
max_loads=100000
|
||||
memory_size=65536
|
||||
percent_dest_unaligned=50
|
||||
|
|
|
|||
|
|
@ -1,74 +1,74 @@
|
|||
system.cpu4: completed 10000 read accesses @26226880
|
||||
system.cpu0: completed 10000 read accesses @26416342
|
||||
system.cpu3: completed 10000 read accesses @26427251
|
||||
system.cpu2: completed 10000 read accesses @26798889
|
||||
system.cpu5: completed 10000 read accesses @26886521
|
||||
system.cpu7: completed 10000 read accesses @27109446
|
||||
system.cpu6: completed 10000 read accesses @27197408
|
||||
system.cpu1: completed 10000 read accesses @27318359
|
||||
system.cpu4: completed 20000 read accesses @53279230
|
||||
system.cpu0: completed 20000 read accesses @53417084
|
||||
system.cpu3: completed 20000 read accesses @53757092
|
||||
system.cpu5: completed 20000 read accesses @53888320
|
||||
system.cpu2: completed 20000 read accesses @53947132
|
||||
system.cpu1: completed 20000 read accesses @54390092
|
||||
system.cpu6: completed 20000 read accesses @54397720
|
||||
system.cpu7: completed 20000 read accesses @54632966
|
||||
system.cpu0: completed 30000 read accesses @80144176
|
||||
system.cpu4: completed 30000 read accesses @80518264
|
||||
system.cpu5: completed 30000 read accesses @80638600
|
||||
system.cpu2: completed 30000 read accesses @80869702
|
||||
system.cpu6: completed 30000 read accesses @81289158
|
||||
system.cpu3: completed 30000 read accesses @81358716
|
||||
system.cpu7: completed 30000 read accesses @81981296
|
||||
system.cpu1: completed 30000 read accesses @82043104
|
||||
system.cpu0: completed 40000 read accesses @107087547
|
||||
system.cpu5: completed 40000 read accesses @107662142
|
||||
system.cpu4: completed 40000 read accesses @107722516
|
||||
system.cpu2: completed 40000 read accesses @107884124
|
||||
system.cpu6: completed 40000 read accesses @107981413
|
||||
system.cpu7: completed 40000 read accesses @108415286
|
||||
system.cpu3: completed 40000 read accesses @108655120
|
||||
system.cpu1: completed 40000 read accesses @109427858
|
||||
system.cpu0: completed 50000 read accesses @133583246
|
||||
system.cpu5: completed 50000 read accesses @133832383
|
||||
system.cpu2: completed 50000 read accesses @134755386
|
||||
system.cpu6: completed 50000 read accesses @134792594
|
||||
system.cpu7: completed 50000 read accesses @134914312
|
||||
system.cpu4: completed 50000 read accesses @134993978
|
||||
system.cpu3: completed 50000 read accesses @135362549
|
||||
system.cpu1: completed 50000 read accesses @135394370
|
||||
system.cpu5: completed 60000 read accesses @160410176
|
||||
system.cpu0: completed 60000 read accesses @160667590
|
||||
system.cpu7: completed 60000 read accesses @161466346
|
||||
system.cpu6: completed 60000 read accesses @161592434
|
||||
system.cpu2: completed 60000 read accesses @161656374
|
||||
system.cpu1: completed 60000 read accesses @161882626
|
||||
system.cpu3: completed 60000 read accesses @162062631
|
||||
system.cpu4: completed 60000 read accesses @162154299
|
||||
system.cpu0: completed 70000 read accesses @187592265
|
||||
system.cpu6: completed 70000 read accesses @188138542
|
||||
system.cpu7: completed 70000 read accesses @188373105
|
||||
system.cpu5: completed 70000 read accesses @188690782
|
||||
system.cpu4: completed 70000 read accesses @189309687
|
||||
system.cpu3: completed 70000 read accesses @189360790
|
||||
system.cpu1: completed 70000 read accesses @189391126
|
||||
system.cpu2: completed 70000 read accesses @189902895
|
||||
system.cpu0: completed 80000 read accesses @214739574
|
||||
system.cpu6: completed 80000 read accesses @215665444
|
||||
system.cpu5: completed 80000 read accesses @216021457
|
||||
system.cpu7: completed 80000 read accesses @216394344
|
||||
system.cpu4: completed 80000 read accesses @216537382
|
||||
system.cpu1: completed 80000 read accesses @216775798
|
||||
system.cpu3: completed 80000 read accesses @216868662
|
||||
system.cpu2: completed 80000 read accesses @217401619
|
||||
system.cpu0: completed 90000 read accesses @241415090
|
||||
system.cpu6: completed 90000 read accesses @242558992
|
||||
system.cpu5: completed 90000 read accesses @242897388
|
||||
system.cpu7: completed 90000 read accesses @243372191
|
||||
system.cpu4: completed 90000 read accesses @243630762
|
||||
system.cpu2: completed 90000 read accesses @243633950
|
||||
system.cpu1: completed 90000 read accesses @243710816
|
||||
system.cpu3: completed 90000 read accesses @243974160
|
||||
system.cpu0: completed 100000 read accesses @268915439
|
||||
system.cpu2: completed 10000 read accesses @26695905
|
||||
system.cpu6: completed 10000 read accesses @26791606
|
||||
system.cpu5: completed 10000 read accesses @26792650
|
||||
system.cpu1: completed 10000 read accesses @26942582
|
||||
system.cpu7: completed 10000 read accesses @27101805
|
||||
system.cpu3: completed 10000 read accesses @27218798
|
||||
system.cpu0: completed 10000 read accesses @27391241
|
||||
system.cpu4: completed 10000 read accesses @27569488
|
||||
system.cpu6: completed 20000 read accesses @53349763
|
||||
system.cpu2: completed 20000 read accesses @53503744
|
||||
system.cpu5: completed 20000 read accesses @53714174
|
||||
system.cpu7: completed 20000 read accesses @53950546
|
||||
system.cpu3: completed 20000 read accesses @54185930
|
||||
system.cpu0: completed 20000 read accesses @54225484
|
||||
system.cpu1: completed 20000 read accesses @54276231
|
||||
system.cpu4: completed 20000 read accesses @54597598
|
||||
system.cpu0: completed 30000 read accesses @80866924
|
||||
system.cpu7: completed 30000 read accesses @80945592
|
||||
system.cpu6: completed 30000 read accesses @81027764
|
||||
system.cpu2: completed 30000 read accesses @81035060
|
||||
system.cpu4: completed 30000 read accesses @81318103
|
||||
system.cpu5: completed 30000 read accesses @81377684
|
||||
system.cpu3: completed 30000 read accesses @81429000
|
||||
system.cpu1: completed 30000 read accesses @81820011
|
||||
system.cpu2: completed 40000 read accesses @106813760
|
||||
system.cpu3: completed 40000 read accesses @106974444
|
||||
system.cpu6: completed 40000 read accesses @106993530
|
||||
system.cpu7: completed 40000 read accesses @107261306
|
||||
system.cpu5: completed 40000 read accesses @107310319
|
||||
system.cpu0: completed 40000 read accesses @107652944
|
||||
system.cpu1: completed 40000 read accesses @107852182
|
||||
system.cpu4: completed 40000 read accesses @108023308
|
||||
system.cpu2: completed 50000 read accesses @133853751
|
||||
system.cpu6: completed 50000 read accesses @134086054
|
||||
system.cpu3: completed 50000 read accesses @134273902
|
||||
system.cpu7: completed 50000 read accesses @134574750
|
||||
system.cpu0: completed 50000 read accesses @134577823
|
||||
system.cpu1: completed 50000 read accesses @134778033
|
||||
system.cpu5: completed 50000 read accesses @134896821
|
||||
system.cpu4: completed 50000 read accesses @135759299
|
||||
system.cpu2: completed 60000 read accesses @161211555
|
||||
system.cpu3: completed 60000 read accesses @161581369
|
||||
system.cpu6: completed 60000 read accesses @161831828
|
||||
system.cpu0: completed 60000 read accesses @161942121
|
||||
system.cpu1: completed 60000 read accesses @162215822
|
||||
system.cpu7: completed 60000 read accesses @162487402
|
||||
system.cpu5: completed 60000 read accesses @162758928
|
||||
system.cpu4: completed 60000 read accesses @162827113
|
||||
system.cpu2: completed 70000 read accesses @188493937
|
||||
system.cpu1: completed 70000 read accesses @189035964
|
||||
system.cpu3: completed 70000 read accesses @189157397
|
||||
system.cpu6: completed 70000 read accesses @189252661
|
||||
system.cpu0: completed 70000 read accesses @189257028
|
||||
system.cpu7: completed 70000 read accesses @189348164
|
||||
system.cpu5: completed 70000 read accesses @189769120
|
||||
system.cpu4: completed 70000 read accesses @191028989
|
||||
system.cpu2: completed 80000 read accesses @215328997
|
||||
system.cpu7: completed 80000 read accesses @216072978
|
||||
system.cpu1: completed 80000 read accesses @216240482
|
||||
system.cpu6: completed 80000 read accesses @216413258
|
||||
system.cpu3: completed 80000 read accesses @216551338
|
||||
system.cpu5: completed 80000 read accesses @216884718
|
||||
system.cpu0: completed 80000 read accesses @216894493
|
||||
system.cpu4: completed 80000 read accesses @218108705
|
||||
system.cpu2: completed 90000 read accesses @242508064
|
||||
system.cpu7: completed 90000 read accesses @242698389
|
||||
system.cpu1: completed 90000 read accesses @242967798
|
||||
system.cpu5: completed 90000 read accesses @243529194
|
||||
system.cpu3: completed 90000 read accesses @243598064
|
||||
system.cpu6: completed 90000 read accesses @243621284
|
||||
system.cpu0: completed 90000 read accesses @244529131
|
||||
system.cpu4: completed 90000 read accesses @246008618
|
||||
system.cpu2: completed 100000 read accesses @269223994
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 1 2010 14:37:40
|
||||
M5 revision acd9f15a9c7c 7493 default qtip tip simobj-parent-fix-stats-udpate
|
||||
M5 started Jul 1 2010 14:37:50
|
||||
M5 executing on phenom
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest
|
||||
M5 compiled Aug 20 2010 12:21:09
|
||||
M5 revision c4b5df973361+ 7570+ default qtip tip brad/regress_updates
|
||||
M5 started Aug 20 2010 12:21:31
|
||||
M5 executing on SC2B0629
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 268915439 because maximum number of loads reached
|
||||
Exiting @ tick 269223994 because maximum number of loads reached
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -5,10 +5,118 @@ dummy=0
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=physmem ruby
|
||||
children=dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
|
||||
[system.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
directory=system.dir_cntrl0.directory
|
||||
directory_latency=6
|
||||
memBuffer=system.dir_cntrl0.memBuffer
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
to_mem_ctrl_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=6
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
|
||||
L1IcacheMemory=system.l1_cntrl0.sequencer.icache
|
||||
buffer_size=0
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.l1_cntrl0.sequencer
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.l1_cntrl0.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=true
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=root.cpuPort[0]
|
||||
|
||||
[system.l1_cntrl0.sequencer.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l2_cntrl0]
|
||||
type=L2Cache_Controller
|
||||
children=L2cacheMemory
|
||||
L2cacheMemory=system.l2_cntrl0.L2cacheMemory
|
||||
buffer_size=0
|
||||
l2_request_latency=2
|
||||
l2_response_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
to_l1_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l2_cntrl0.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=15
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
start_index_bit=6
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
|
|
@ -17,7 +125,7 @@ latency_var=0
|
|||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
|
||||
port=system.l1_cntrl0.sequencer.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
|
|
@ -56,6 +164,7 @@ topology=system.ruby.network.topology
|
|||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
|
||||
description=Crossbar
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
|
||||
num_int_nodes=4
|
||||
|
|
@ -63,136 +172,28 @@ print_config=false
|
|||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links0.ext_node
|
||||
ext_node=system.l1_cntrl0
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
buffer_size=0
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=true
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=root.cpuPort[0]
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links1.ext_node
|
||||
ext_node=system.l2_cntrl0
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node]
|
||||
type=L2Cache_Controller
|
||||
children=L2cacheMemory
|
||||
L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
|
||||
buffer_size=0
|
||||
l2_request_latency=2
|
||||
l2_response_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
to_l1_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=15
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
||||
[system.ruby.network.topology.ext_links2]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links2.ext_node
|
||||
ext_node=system.dir_cntrl0
|
||||
int_node=2
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
directory=system.ruby.network.topology.ext_links2.ext_node.directory
|
||||
directory_latency=6
|
||||
memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
to_mem_ctrl_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=0
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.int_links0]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Mar 18 2010 14:36:48
|
||||
M5 revision 6a6bb24e484f+ 7041+ default qtip tip brad/regress_updates
|
||||
M5 started Mar 18 2010 14:37:00
|
||||
M5 executing on cabr0210
|
||||
M5 compiled Aug 20 2010 11:26:07
|
||||
M5 revision 7074a6fb3b4f 7537 default qtip tip brad/regress_updates
|
||||
M5 started Aug 20 2010 11:29:00
|
||||
M5 executing on SC2B0629
|
||||
command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 385311 because Ruby Tester completed
|
||||
Exiting @ tick 362171 because Ruby Tester completed
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_mem_usage 208556 # Number of bytes of host memory used
|
||||
host_seconds 0.90 # Real time elapsed on the host
|
||||
host_tick_rate 429636 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 209424 # Number of bytes of host memory used
|
||||
host_seconds 0.56 # Real time elapsed on the host
|
||||
host_tick_rate 645865 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_seconds 0.000385 # Number of seconds simulated
|
||||
sim_ticks 385311 # Number of ticks simulated
|
||||
sim_seconds 0.000362 # Number of seconds simulated
|
||||
sim_ticks 362171 # Number of ticks simulated
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -5,10 +5,114 @@ dummy=0
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=physmem ruby
|
||||
children=dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
|
||||
[system.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
directory=system.dir_cntrl0.directory
|
||||
directory_latency=6
|
||||
memBuffer=system.dir_cntrl0.memBuffer
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=6
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
|
||||
L1IcacheMemory=system.l1_cntrl0.sequencer.icache
|
||||
buffer_size=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
sequencer=system.l1_cntrl0.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.l1_cntrl0.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=true
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=root.cpuPort[0]
|
||||
|
||||
[system.l1_cntrl0.sequencer.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l2_cntrl0]
|
||||
type=L2Cache_Controller
|
||||
children=L2cacheMemory
|
||||
L2cacheMemory=system.l2_cntrl0.L2cacheMemory
|
||||
buffer_size=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
response_latency=2
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l2_cntrl0.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=15
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
start_index_bit=6
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
|
|
@ -17,7 +121,7 @@ latency_var=0
|
|||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
|
||||
port=system.l1_cntrl0.sequencer.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
|
|
@ -58,137 +162,34 @@ type=Topology
|
|||
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
|
||||
name=Crossbar
|
||||
num_int_nodes=4
|
||||
print_config=false
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links0.ext_node
|
||||
ext_node=system.l1_cntrl0
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
buffer_size=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=true
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=root.cpuPort[0]
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links1.ext_node
|
||||
ext_node=system.l2_cntrl0
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node]
|
||||
type=L2Cache_Controller
|
||||
children=L2cacheMemory
|
||||
L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
|
||||
buffer_size=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
response_latency=2
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=15
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
||||
[system.ruby.network.topology.ext_links2]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links2.ext_node
|
||||
ext_node=system.dir_cntrl0
|
||||
int_node=2
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
directory=system.ruby.network.topology.ext_links2.ext_node.directory
|
||||
directory_latency=6
|
||||
memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=0
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.int_links0]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Mar 18 2010 14:39:50
|
||||
M5 revision 6a6bb24e484f+ 7041+ default qtip tip brad/regress_updates
|
||||
M5 started Mar 18 2010 14:40:19
|
||||
M5 executing on cabr0210
|
||||
M5 compiled Aug 5 2010 10:34:54
|
||||
M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip
|
||||
M5 started Aug 5 2010 10:40:24
|
||||
M5 executing on svvint09
|
||||
command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 382981 because Ruby Tester completed
|
||||
Exiting @ tick 372291 because Ruby Tester completed
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_mem_usage 208684 # Number of bytes of host memory used
|
||||
host_seconds 6.96 # Real time elapsed on the host
|
||||
host_tick_rate 55013 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 210064 # Number of bytes of host memory used
|
||||
host_seconds 0.80 # Real time elapsed on the host
|
||||
host_tick_rate 465329 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_seconds 0.000383 # Number of seconds simulated
|
||||
sim_ticks 382981 # Number of ticks simulated
|
||||
sim_seconds 0.000372 # Number of seconds simulated
|
||||
sim_ticks 372291 # Number of ticks simulated
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -5,10 +5,125 @@ dummy=0
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=physmem ruby
|
||||
children=dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
|
||||
[system.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
directory=system.dir_cntrl0.directory
|
||||
directory_latency=5
|
||||
distributed_persistent=true
|
||||
fixed_timeout_latency=100
|
||||
l2_select_num_bits=0
|
||||
memBuffer=system.dir_cntrl0.memBuffer
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=6
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
|
||||
L1IcacheMemory=system.l1_cntrl0.sequencer.icache
|
||||
N_tokens=2
|
||||
buffer_size=0
|
||||
dynamic_timeout_enabled=true
|
||||
fixed_timeout_latency=300
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
sequencer=system.l1_cntrl0.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.l1_cntrl0.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=true
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=root.cpuPort[0]
|
||||
|
||||
[system.l1_cntrl0.sequencer.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l2_cntrl0]
|
||||
type=L2Cache_Controller
|
||||
children=L2cacheMemory
|
||||
L2cacheMemory=system.l2_cntrl0.L2cacheMemory
|
||||
N_tokens=2
|
||||
buffer_size=0
|
||||
filtering_enabled=true
|
||||
l2_request_latency=5
|
||||
l2_response_latency=5
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l2_cntrl0.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=10
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
start_index_bit=0
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
|
|
@ -17,7 +132,7 @@ latency_var=0
|
|||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
|
||||
port=system.l1_cntrl0.sequencer.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
|
|
@ -58,147 +173,34 @@ type=Topology
|
|||
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
|
||||
name=Crossbar
|
||||
num_int_nodes=4
|
||||
print_config=false
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links0.ext_node
|
||||
ext_node=system.l1_cntrl0
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
N_tokens=2
|
||||
buffer_size=0
|
||||
dynamic_timeout_enabled=true
|
||||
fixed_timeout_latency=300
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=true
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=root.cpuPort[0]
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links1.ext_node
|
||||
ext_node=system.l2_cntrl0
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node]
|
||||
type=L2Cache_Controller
|
||||
children=L2cacheMemory
|
||||
L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
|
||||
N_tokens=2
|
||||
buffer_size=0
|
||||
filtering_enabled=true
|
||||
l2_request_latency=10
|
||||
l2_response_latency=10
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=15
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
||||
[system.ruby.network.topology.ext_links2]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links2.ext_node
|
||||
ext_node=system.dir_cntrl0
|
||||
int_node=2
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
directory=system.ruby.network.topology.ext_links2.ext_node.directory
|
||||
directory_latency=6
|
||||
distributed_persistent=true
|
||||
fixed_timeout_latency=300
|
||||
l2_select_num_bits=0
|
||||
memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=0
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.int_links0]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Mar 18 2010 14:58:42
|
||||
M5 revision 6a6bb24e484f+ 7041+ default qtip tip brad/regress_updates
|
||||
M5 started Mar 18 2010 14:58:52
|
||||
M5 executing on cabr0210
|
||||
M5 compiled Aug 5 2010 10:41:36
|
||||
M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip
|
||||
M5 started Aug 5 2010 10:45:27
|
||||
M5 executing on svvint09
|
||||
command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 275491 because Ruby Tester completed
|
||||
Exiting @ tick 273851 because Ruby Tester completed
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_mem_usage 208544 # Number of bytes of host memory used
|
||||
host_mem_usage 210052 # Number of bytes of host memory used
|
||||
host_seconds 0.53 # Real time elapsed on the host
|
||||
host_tick_rate 518969 # Simulator tick rate (ticks/s)
|
||||
host_tick_rate 516678 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_seconds 0.000275 # Number of seconds simulated
|
||||
sim_ticks 275491 # Number of ticks simulated
|
||||
sim_seconds 0.000274 # Number of seconds simulated
|
||||
sim_ticks 273851 # Number of ticks simulated
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -5,10 +5,114 @@ dummy=0
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=physmem ruby
|
||||
children=dir_cntrl0 l1_cntrl0 physmem ruby
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
|
||||
[system.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer probeFilter
|
||||
buffer_size=0
|
||||
directory=system.dir_cntrl0.directory
|
||||
memBuffer=system.dir_cntrl0.memBuffer
|
||||
memory_controller_latency=2
|
||||
number_of_TBEs=256
|
||||
probeFilter=system.dir_cntrl0.probeFilter
|
||||
probe_filter_enabled=false
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=6
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.dir_cntrl0.probeFilter]
|
||||
type=RubyCache
|
||||
assoc=4
|
||||
latency=1
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=1024
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0]
|
||||
type=L1Cache_Controller
|
||||
children=L2cacheMemory sequencer
|
||||
L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
|
||||
L1IcacheMemory=system.l1_cntrl0.sequencer.icache
|
||||
L2cacheMemory=system.l1_cntrl0.L2cacheMemory
|
||||
buffer_size=0
|
||||
cache_response_latency=10
|
||||
issue_latency=2
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.l1_cntrl0.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=10
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.l1_cntrl0.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=true
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=root.cpuPort[0]
|
||||
|
||||
[system.l1_cntrl0.sequencer.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
|
|
@ -17,7 +121,7 @@ latency_var=0
|
|||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
|
||||
port=system.l1_cntrl0.sequencer.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
|
|
@ -58,117 +162,26 @@ type=Topology
|
|||
children=ext_links0 ext_links1 int_links0 int_links1
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
|
||||
name=Crossbar
|
||||
num_int_nodes=3
|
||||
print_config=false
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links0.ext_node
|
||||
ext_node=system.l1_cntrl0
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=L2cacheMemory sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
L2cacheMemory=system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory
|
||||
buffer_size=0
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=15
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=true
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=root.cpuPort[0]
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links1.ext_node
|
||||
ext_node=system.dir_cntrl0
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
directory=system.ruby.network.topology.ext_links1.ext_node.directory
|
||||
memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer
|
||||
memory_controller_latency=12
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=0
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.int_links0]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Mar 18 2010 14:59:19
|
||||
M5 revision 6a6bb24e484f+ 7041+ default qtip tip brad/regress_updates
|
||||
M5 started Mar 18 2010 14:59:22
|
||||
M5 executing on cabr0210
|
||||
M5 compiled Aug 5 2010 14:43:33
|
||||
M5 revision c5f5b5533e96+ 7536+ default qtip tip brad/regress_updates
|
||||
M5 started Aug 5 2010 14:46:32
|
||||
M5 executing on svvint09
|
||||
command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 222961 because Ruby Tester completed
|
||||
Exiting @ tick 213851 because Ruby Tester completed
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_mem_usage 208348 # Number of bytes of host memory used
|
||||
host_seconds 0.53 # Real time elapsed on the host
|
||||
host_tick_rate 420464 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 209796 # Number of bytes of host memory used
|
||||
host_seconds 0.44 # Real time elapsed on the host
|
||||
host_tick_rate 485996 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_seconds 0.000223 # Number of seconds simulated
|
||||
sim_ticks 222961 # Number of ticks simulated
|
||||
sim_seconds 0.000214 # Number of seconds simulated
|
||||
sim_ticks 213851 # Number of ticks simulated
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -5,10 +5,85 @@ dummy=0
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=physmem ruby
|
||||
children=dir_cntrl0 l1_cntrl0 physmem ruby
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
|
||||
[system.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
directory=system.dir_cntrl0.directory
|
||||
directory_latency=12
|
||||
memBuffer=system.dir_cntrl0.memBuffer
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=6
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
buffer_size=0
|
||||
cacheMemory=system.l1_cntrl0.sequencer.icache
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.l1_cntrl0.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
children=icache
|
||||
dcache=system.l1_cntrl0.sequencer.icache
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=true
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=root.cpuPort[0]
|
||||
|
||||
[system.l1_cntrl0.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
|
|
@ -17,7 +92,7 @@ latency_var=0
|
|||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
|
||||
port=system.l1_cntrl0.sequencer.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
|
|
@ -58,101 +133,26 @@ type=Topology
|
|||
children=ext_links0 ext_links1 int_links0 int_links1
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
|
||||
name=Crossbar
|
||||
num_int_nodes=3
|
||||
print_config=false
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links0.ext_node
|
||||
ext_node=system.l1_cntrl0
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
buffer_size=0
|
||||
cacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=icache
|
||||
dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=true
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=root.cpuPort[0]
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links1.ext_node
|
||||
ext_node=system.dir_cntrl0
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
directory=system.ruby.network.topology.ext_links1.ext_node.directory
|
||||
directory_latency=12
|
||||
memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=0
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.int_links0]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@ RubySystem config:
|
|||
Network Configuration
|
||||
---------------------
|
||||
network: SIMPLE_NETWORK
|
||||
topology:
|
||||
topology: Crossbar
|
||||
|
||||
virtual_net_0: active, ordered
|
||||
virtual_net_1: active, ordered
|
||||
|
|
@ -34,27 +34,27 @@ periodic_stats_period: 1000000
|
|||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Mar/18/2010 13:52:47
|
||||
Real time: Aug/05/2010 10:10:57
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 1
|
||||
Elapsed_time_in_minutes: 0.0166667
|
||||
Elapsed_time_in_hours: 0.000277778
|
||||
Elapsed_time_in_days: 1.15741e-05
|
||||
Elapsed_time_in_seconds: 0
|
||||
Elapsed_time_in_minutes: 0
|
||||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.27
|
||||
Virtual_time_in_minutes: 0.0045
|
||||
Virtual_time_in_hours: 7.5e-05
|
||||
Virtual_time_in_days: 3.125e-06
|
||||
Virtual_time_in_seconds: 0.29
|
||||
Virtual_time_in_minutes: 0.00483333
|
||||
Virtual_time_in_hours: 8.05556e-05
|
||||
Virtual_time_in_days: 3.35648e-06
|
||||
|
||||
Ruby_current_time: 281031
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 281031
|
||||
|
||||
mbytes_resident: 30.418
|
||||
mbytes_total: 203.402
|
||||
resident_ratio: 0.149584
|
||||
mbytes_resident: 30.9531
|
||||
mbytes_total: 203.703
|
||||
resident_ratio: 0.15199
|
||||
|
||||
ruby_cycles_executed: [ 281032 ]
|
||||
|
||||
|
|
@ -70,8 +70,27 @@ sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1014 average: 15.7801
|
|||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 32 max: 6068 count: 999 average: 4453.7 | standard deviation: 529.325 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 1 0 0 0 0 1 1 1 0 1 0 1 1 2 5 0 4 1 2 6 3 6 5 6 4 7 8 11 10 20 9 19 17 13 22 23 30 23 21 22 25 31 27 31 39 35 22 20 39 25 30 27 25 23 23 19 22 10 24 20 22 19 19 12 21 14 12 11 5 8 6 0 3 2 0 2 0 2 0 1 0 0 0 0 2 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 ]
|
||||
miss_latency_2: [binsize: 32 max: 5702 count: 100 average: 4601.67 | standard deviation: 400.66 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 2 0 3 1 1 3 4 5 2 3 1 2 2 1 1 5 2 0 2 2 2 5 2 2 3 1 3 3 1 5 4 4 2 3 3 1 1 3 3 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_3: [binsize: 32 max: 6068 count: 899 average: 4437.24 | standard deviation: 539.424 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 1 0 0 0 0 1 1 1 0 1 0 1 1 2 5 0 4 1 2 6 3 6 4 6 4 7 7 11 9 18 9 16 16 12 19 19 25 21 18 21 23 29 26 30 34 33 22 18 37 23 25 25 23 20 22 16 19 9 19 16 18 17 16 9 20 13 9 8 4 7 6 0 3 2 0 1 0 2 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 32 max: 5702 count: 52 average: 4674.27 | standard deviation: 454.241 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 0 2 0 0 1 3 4 0 0 0 0 1 0 1 1 1 0 0 1 0 1 0 2 2 0 3 2 0 3 0 3 1 3 3 1 1 3 2 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_LD: [binsize: 32 max: 5245 count: 48 average: 4523.02 | standard deviation: 319.516 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 2 1 1 2 3 1 2 1 1 0 4 1 0 2 1 2 4 2 0 1 1 0 1 1 2 4 1 1 0 0 0 0 0 1 0 1 ]
|
||||
miss_latency_ST: [binsize: 32 max: 6068 count: 899 average: 4437.24 | standard deviation: 539.424 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 1 0 0 0 0 1 1 1 0 1 0 1 1 2 5 0 4 1 2 6 3 6 4 6 4 7 7 11 9 18 9 16 16 12 19 19 25 21 18 21 23 29 26 30 34 33 22 18 37 23 25 25 23 20 22 16 19 9 19 16 18 17 16 9 20 13 9 8 4 7 6 0 3 2 0 1 0 2 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 ]
|
||||
miss_latency_L1Cache: [binsize: 32 max: 4572 count: 43 average: 3768.3 | standard deviation: 359.401 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 0 1 0 2 2 0 3 1 0 2 2 1 1 3 1 2 1 1 0 4 1 3 0 2 0 0 1 0 0 0 0 0 0 0 2 0 0 0 2 ]
|
||||
miss_latency_Directory: [binsize: 32 max: 6068 count: 956 average: 4484.53 | standard deviation: 514.797 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 0 1 0 2 4 1 5 4 3 3 5 7 10 10 16 8 16 17 11 22 23 29 23 21 22 25 31 27 31 37 35 22 20 37 25 30 27 25 23 23 19 22 10 24 20 22 19 19 12 21 14 12 11 5 8 6 0 3 2 0 2 0 2 0 1 0 0 0 0 2 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_wCC_Times: 0
|
||||
miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_dir_Times: 956
|
||||
miss_latency_IFETCH_L1Cache: [binsize: 32 max: 4022 count: 1 average: 4022 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 32 max: 5702 count: 51 average: 4687.06 | standard deviation: 449.206 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 0 1 0 0 1 3 4 0 0 0 0 1 0 1 1 1 0 0 1 0 1 0 2 2 0 3 2 0 3 0 3 1 3 3 1 1 3 2 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_LD_L1Cache: [binsize: 32 max: 3964 count: 1 average: 3964 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_LD_Directory: [binsize: 32 max: 5245 count: 47 average: 4534.91 | standard deviation: 312.044 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 2 1 1 2 3 1 2 1 1 0 4 1 0 2 1 2 4 2 0 1 1 0 1 1 2 4 1 1 0 0 0 0 0 1 0 1 ]
|
||||
miss_latency_ST_L1Cache: [binsize: 32 max: 4572 count: 41 average: 3757.34 | standard deviation: 364.607 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 0 1 0 2 2 0 3 1 0 2 2 1 1 3 1 2 1 1 0 3 1 2 0 2 0 0 1 0 0 0 0 0 0 0 2 0 0 0 2 ]
|
||||
miss_latency_ST_Directory: [binsize: 32 max: 6068 count: 858 average: 4469.73 | standard deviation: 524.902 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 0 1 0 2 4 1 5 3 3 3 5 6 10 9 15 8 14 16 10 19 19 24 21 18 21 23 29 26 30 32 33 22 18 35 23 25 25 23 20 22 16 19 9 19 16 18 17 16 9 20 13 9 8 4 7 6 0 3 2 0 1 0 2 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
|
|
@ -103,7 +122,7 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 8779
|
||||
page_reclaims: 9003
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
|
|
@ -112,6 +131,12 @@ block_outputs: 0
|
|||
Network Stats
|
||||
-------------
|
||||
|
||||
total_msg_count_Control: 2871 22968
|
||||
total_msg_count_Data: 2862 206064
|
||||
total_msg_count_Response_Data: 2870 206640
|
||||
total_msg_count_Writeback_Control: 2861 22888
|
||||
total_msgs: 11464 total_bytes: 458560
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 0.106147
|
||||
|
|
@ -145,59 +170,59 @@ links_utilized_percent_switch_2: 0.169999
|
|||
outgoing_messages_switch_2_link_1_Control: 957 7656 [ 0 0 957 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Data: 954 68688 [ 0 0 954 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 957
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 957
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
|
||||
Cache Stats: system.l1_cntrl0.sequencer.icache
|
||||
system.l1_cntrl0.sequencer.icache_total_misses: 957
|
||||
system.l1_cntrl0.sequencer.icache_total_demand_misses: 957
|
||||
system.l1_cntrl0.sequencer.icache_total_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_LD: 10.2403%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_ST: 89.7597%
|
||||
system.l1_cntrl0.sequencer.icache_request_type_LD: 4.91118%
|
||||
system.l1_cntrl0.sequencer.icache_request_type_ST: 89.7597%
|
||||
system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 5.32915%
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 957 100%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 4 count: 957 average: 1.30721 | standard deviation: 0.910193 | 0 859 0 0 98 ]
|
||||
system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 957 100%
|
||||
|
||||
--- L1Cache 0 ---
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load 100
|
||||
Ifetch 0
|
||||
Store 900
|
||||
Data 956
|
||||
Fwd_GETX 0
|
||||
Inv 0
|
||||
Replacement 954
|
||||
Writeback_Ack 953
|
||||
Writeback_Nack 0
|
||||
Load [48 ] 48
|
||||
Ifetch [52 ] 52
|
||||
Store [900 ] 900
|
||||
Data [956 ] 956
|
||||
Fwd_GETX [0 ] 0
|
||||
Inv [0 ] 0
|
||||
Replacement [954 ] 954
|
||||
Writeback_Ack [953 ] 953
|
||||
Writeback_Nack [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
I Load 98
|
||||
I Ifetch 0 <--
|
||||
I Store 859
|
||||
I Inv 0 <--
|
||||
I Replacement 0 <--
|
||||
I Load [47 ] 47
|
||||
I Ifetch [51 ] 51
|
||||
I Store [859 ] 859
|
||||
I Inv [0 ] 0
|
||||
I Replacement [0 ] 0
|
||||
|
||||
II Writeback_Nack 0 <--
|
||||
II Writeback_Nack [0 ] 0
|
||||
|
||||
M Load 2
|
||||
M Ifetch 0 <--
|
||||
M Store 41
|
||||
M Fwd_GETX 0 <--
|
||||
M Inv 0 <--
|
||||
M Replacement 954
|
||||
M Load [1 ] 1
|
||||
M Ifetch [1 ] 1
|
||||
M Store [41 ] 41
|
||||
M Fwd_GETX [0 ] 0
|
||||
M Inv [0 ] 0
|
||||
M Replacement [954 ] 954
|
||||
|
||||
MI Fwd_GETX 0 <--
|
||||
MI Inv 0 <--
|
||||
MI Writeback_Ack 953
|
||||
MI Writeback_Nack 0 <--
|
||||
MI Fwd_GETX [0 ] 0
|
||||
MI Inv [0 ] 0
|
||||
MI Writeback_Ack [953 ] 953
|
||||
MI Writeback_Nack [0 ] 0
|
||||
|
||||
MII Fwd_GETX 0 <--
|
||||
MII Fwd_GETX [0 ] 0
|
||||
|
||||
IS Data 98
|
||||
IS Data [98 ] 98
|
||||
|
||||
IM Data 858
|
||||
IM Data [858 ] 858
|
||||
|
||||
Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer:
|
||||
Memory controller: system.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 1911
|
||||
memory_reads: 957
|
||||
memory_writes: 954
|
||||
|
|
@ -217,70 +242,69 @@ Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer:
|
|||
memory_stalls_for_read_read_turnaround: 112
|
||||
accesses_per_bank: 52 59 44 109 131 76 66 52 64 66 66 44 56 54 54 52 52 48 76 50 48 60 56 48 50 62 66 48 36 64 48 54
|
||||
|
||||
--- Directory 0 ---
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
GETX 957
|
||||
GETS 0
|
||||
PUTX 954
|
||||
PUTX_NotOwner 0
|
||||
DMA_READ 0
|
||||
DMA_WRITE 0
|
||||
Memory_Data 957
|
||||
Memory_Ack 954
|
||||
GETX [957 ] 957
|
||||
GETS [0 ] 0
|
||||
PUTX [954 ] 954
|
||||
PUTX_NotOwner [0 ] 0
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
Memory_Data [957 ] 957
|
||||
Memory_Ack [954 ] 954
|
||||
|
||||
- Transitions -
|
||||
I GETX 957
|
||||
I PUTX_NotOwner 0 <--
|
||||
I DMA_READ 0 <--
|
||||
I DMA_WRITE 0 <--
|
||||
I GETX [957 ] 957
|
||||
I PUTX_NotOwner [0 ] 0
|
||||
I DMA_READ [0 ] 0
|
||||
I DMA_WRITE [0 ] 0
|
||||
|
||||
M GETX 0 <--
|
||||
M PUTX 954
|
||||
M PUTX_NotOwner 0 <--
|
||||
M DMA_READ 0 <--
|
||||
M DMA_WRITE 0 <--
|
||||
M GETX [0 ] 0
|
||||
M PUTX [954 ] 954
|
||||
M PUTX_NotOwner [0 ] 0
|
||||
M DMA_READ [0 ] 0
|
||||
M DMA_WRITE [0 ] 0
|
||||
|
||||
M_DRD GETX 0 <--
|
||||
M_DRD PUTX 0 <--
|
||||
M_DRD GETX [0 ] 0
|
||||
M_DRD PUTX [0 ] 0
|
||||
|
||||
M_DWR GETX 0 <--
|
||||
M_DWR PUTX 0 <--
|
||||
M_DWR GETX [0 ] 0
|
||||
M_DWR PUTX [0 ] 0
|
||||
|
||||
M_DWRI GETX 0 <--
|
||||
M_DWRI Memory_Ack 0 <--
|
||||
M_DWRI GETX [0 ] 0
|
||||
M_DWRI Memory_Ack [0 ] 0
|
||||
|
||||
M_DRDI GETX 0 <--
|
||||
M_DRDI Memory_Ack 0 <--
|
||||
M_DRDI GETX [0 ] 0
|
||||
M_DRDI Memory_Ack [0 ] 0
|
||||
|
||||
IM GETX 0 <--
|
||||
IM GETS 0 <--
|
||||
IM PUTX 0 <--
|
||||
IM PUTX_NotOwner 0 <--
|
||||
IM DMA_READ 0 <--
|
||||
IM DMA_WRITE 0 <--
|
||||
IM Memory_Data 957
|
||||
IM GETX [0 ] 0
|
||||
IM GETS [0 ] 0
|
||||
IM PUTX [0 ] 0
|
||||
IM PUTX_NotOwner [0 ] 0
|
||||
IM DMA_READ [0 ] 0
|
||||
IM DMA_WRITE [0 ] 0
|
||||
IM Memory_Data [957 ] 957
|
||||
|
||||
MI GETX 0 <--
|
||||
MI GETS 0 <--
|
||||
MI PUTX 0 <--
|
||||
MI PUTX_NotOwner 0 <--
|
||||
MI DMA_READ 0 <--
|
||||
MI DMA_WRITE 0 <--
|
||||
MI Memory_Ack 954
|
||||
MI GETX [0 ] 0
|
||||
MI GETS [0 ] 0
|
||||
MI PUTX [0 ] 0
|
||||
MI PUTX_NotOwner [0 ] 0
|
||||
MI DMA_READ [0 ] 0
|
||||
MI DMA_WRITE [0 ] 0
|
||||
MI Memory_Ack [954 ] 954
|
||||
|
||||
ID GETX 0 <--
|
||||
ID GETS 0 <--
|
||||
ID PUTX 0 <--
|
||||
ID PUTX_NotOwner 0 <--
|
||||
ID DMA_READ 0 <--
|
||||
ID DMA_WRITE 0 <--
|
||||
ID Memory_Data 0 <--
|
||||
|
||||
ID_W GETX 0 <--
|
||||
ID_W GETS 0 <--
|
||||
ID_W PUTX 0 <--
|
||||
ID_W PUTX_NotOwner 0 <--
|
||||
ID_W DMA_READ 0 <--
|
||||
ID_W DMA_WRITE 0 <--
|
||||
ID_W Memory_Ack 0 <--
|
||||
ID GETX [0 ] 0
|
||||
ID GETS [0 ] 0
|
||||
ID PUTX [0 ] 0
|
||||
ID PUTX_NotOwner [0 ] 0
|
||||
ID DMA_READ [0 ] 0
|
||||
ID DMA_WRITE [0 ] 0
|
||||
ID Memory_Data [0 ] 0
|
||||
|
||||
ID_W GETX [0 ] 0
|
||||
ID_W GETS [0 ] 0
|
||||
ID_W PUTX [0 ] 0
|
||||
ID_W PUTX_NotOwner [0 ] 0
|
||||
ID_W DMA_READ [0 ] 0
|
||||
ID_W DMA_WRITE [0 ] 0
|
||||
ID_W Memory_Ack
|
||||
|
|
@ -1,3 +1,5 @@
|
|||
Redirecting stdout to build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby/simout
|
||||
Redirecting stderr to build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -5,10 +7,10 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Mar 18 2010 13:52:42
|
||||
M5 revision 6a6bb24e484f 7041 default qtip tip brad/regress_updates
|
||||
M5 started Mar 18 2010 13:52:46
|
||||
M5 executing on cabr0210
|
||||
M5 compiled Aug 4 2010 17:29:21
|
||||
M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip
|
||||
M5 started Aug 5 2010 10:10:57
|
||||
M5 executing on SC2B0617
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_mem_usage 208288 # Number of bytes of host memory used
|
||||
host_seconds 0.10 # Real time elapsed on the host
|
||||
host_tick_rate 2919378 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 208596 # Number of bytes of host memory used
|
||||
host_seconds 0.09 # Real time elapsed on the host
|
||||
host_tick_rate 3195386 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_seconds 0.000281 # Number of seconds simulated
|
||||
sim_ticks 281031 # Number of ticks simulated
|
||||
|
|
|
|||
Loading…
Reference in a new issue