Regression tester updates required by the following patches: brad/moved_python_protocol_files: config: moved python protocol config files brad/ruby_options_movement: config: reorganized how ruby specifies command-line options brad/config_token_bcast: ruby: added token broadcast config params to cmd options brad/topology_name: config: Added the topology description to m5 config.ini brad/ruby_system_names: config: Improve ruby simobject names brad/consolidated_protocol_stats: slicc: Consolidated the protocol stats printing brad/ruby_request_type_ostream_fix: ruby: Added ruby_request_type ostream def to libruby.hh brad/memtest_dma_extension: memtest: Memtester support for DMA brad/token_dma_lockdown_fix: MOESI_CMP_token: Fixed dma persistent lockdown bugs brad/profile_generic_mach_type: ruby: Reincarnated the responding machine profiling brad/network_msg_consolidated_stats: ruby: Added consolidated network msg stats brad/bcast_msg_profiling: ruby: Added bcast msg profiling to hammer and token brad/l2cache_profiling_fix: ruby: Fixed L2 cache miss profiling brad/llsc_ruby_m5_fix: ruby: fix ruby llsc support to sync sc outcomes brad/ruby_latency_fixes: ruby: Reduced ruby latencies brad/hammer_l2_cache_latency: ruby: Updated MOESI_hammer L2 latency behavior brad/deterministic_resurrection: ruby: Resurrected Ruby's deterministic tests brad/token_dma_fixes: ruby: MOESI_CMP_token dma fixes brad/ruby_cmd_options: config: added cmd options to control ruby debug brad/token_owner_fixes: ruby: fixed token bugs associated with owner token counts brad/ruby_remove_try_except: ruby: Improved try except blocks in ruby creation brad/ruby_port_callback_fix: ruby: Fixed RubyPort sendTiming callbacks brad/interrupt_drain_fix: devices: Fixed periodic interrupts to work with draining brad/llsc_trace_profile: ruby: Added SC fail indication to trace profiling brad/no_migrate_atomic: ruby: Disable migratory sharing for token and hammer brad/ruby_start_time_fix: ruby: Reset ruby stats in RubySystem unserialize brad/numa_bit_select_fix: ruby: fixed DirectoryMemory's numa_high_bit configuration brad/hammer_probe_filter: ruby: added probe filter support to hammer brad/miss_latency_detail_profile: MOESI_hammer: break down miss latency stalled cycles brad/recycle_latency_fix: ruby: Recycle latency fix for hammer brad/stall_and_wait: ruby: Stall and wait input messages instead of recycling brad/rubytest_request_flag_fix: ruby: Fixed minor bug in ruby test for setting the request type brad/hammer_merge_gets: ruby: Added merge GETS optimization to hammer brad/regress_updates: regress: Regression tester updates
621 lines
22 KiB
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621 lines
22 KiB
Plaintext
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================ Begin RubySystem Configuration Print ================
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RubySystem config:
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random_seed: 1234
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randomization: 1
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cycle_period: 1
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block_size_bytes: 64
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block_size_bits: 6
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memory_size_bytes: 134217728
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memory_size_bits: 27
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Network Configuration
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---------------------
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network: SIMPLE_NETWORK
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topology:
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virtual_net_0: active, unordered
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virtual_net_1: active, unordered
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virtual_net_2: active, unordered
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virtual_net_3: inactive
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virtual_net_4: inactive
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virtual_net_5: inactive
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virtual_net_6: inactive
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virtual_net_7: inactive
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virtual_net_8: inactive
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virtual_net_9: inactive
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Profiler Configuration
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----------------------
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periodic_stats_period: 1000000
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================ End RubySystem Configuration Print ================
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Real time: Aug/20/2010 11:29:01
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Profiler Stats
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--------------
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Elapsed_time_in_seconds: 1
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Elapsed_time_in_minutes: 0.0166667
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Elapsed_time_in_hours: 0.000277778
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Elapsed_time_in_days: 1.15741e-05
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Virtual_time_in_seconds: 0.73
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Virtual_time_in_minutes: 0.0121667
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Virtual_time_in_hours: 0.000202778
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Virtual_time_in_days: 8.44907e-06
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Ruby_current_time: 362171
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Ruby_start_time: 0
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Ruby_cycles: 362171
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mbytes_resident: 31.3438
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mbytes_total: 204.512
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resident_ratio: 0.153319
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ruby_cycles_executed: [ 362172 ]
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Busy Controller Counts:
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L1Cache-0:0
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L2Cache-0:0
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Directory-0:0
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Busy Bank Count:0
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sequencer_requests_outstanding: [binsize: 1 max: 16 count: 989 average: 15.8261 | standard deviation: 1.13064 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 53 922 ]
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All Non-Zero Cycle Demand Cache Accesses
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----------------------------------------
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miss_latency: [binsize: 256 max: 32770 count: 974 average: 5848.35 | standard deviation: 7643.86 | 78 21 56 74 77 80 49 39 35 30 33 25 16 19 17 15 6 9 8 7 4 5 5 5 4 3 8 3 5 6 5 7 0 3 1 6 1 3 3 1 1 1 2 1 1 1 3 2 0 1 2 3 2 6 3 3 2 3 2 4 3 6 2 3 6 5 3 3 3 2 4 2 3 5 10 4 1 3 4 9 3 4 3 2 2 3 7 1 2 2 2 2 3 3 2 1 4 2 0 3 1 2 2 2 1 1 3 0 1 1 3 0 1 0 2 1 0 1 0 0 0 0 1 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_IFETCH: [binsize: 16 max: 2239 count: 47 average: 995.638 | standard deviation: 452.716 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 1 1 1 0 1 1 1 0 0 0 1 1 2 0 0 0 1 0 2 2 1 0 0 0 0 2 1 0 0 0 1 0 2 1 0 0 0 2 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 2 0 2 1 0 2 0 0 1 0 2 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_LD: [binsize: 128 max: 21145 count: 53 average: 4245.77 | standard deviation: 5383.1 | 5 0 0 0 1 1 4 2 1 2 1 6 3 2 1 0 1 1 0 0 0 1 3 0 0 1 0 1 0 2 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_ST: [binsize: 256 max: 32770 count: 874 average: 6206.49 | standard deviation: 7863.36 | 73 14 42 60 69 63 42 36 32 30 32 22 15 18 15 14 6 9 8 6 4 5 4 5 4 3 7 3 5 6 5 7 0 3 1 4 1 2 3 1 1 1 2 1 1 0 3 2 0 1 2 3 2 6 3 3 2 2 1 4 3 6 2 2 6 5 3 2 3 2 4 2 3 4 10 4 1 3 4 9 3 4 2 2 2 3 7 1 2 2 2 2 3 3 2 1 4 2 0 3 1 2 2 2 1 1 3 0 1 1 3 0 1 0 2 1 0 1 0 0 0 0 1 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_NULL: [binsize: 256 max: 32770 count: 974 average: 5848.35 | standard deviation: 7643.86 | 78 21 56 74 77 80 49 39 35 30 33 25 16 19 17 15 6 9 8 7 4 5 5 5 4 3 8 3 5 6 5 7 0 3 1 6 1 3 3 1 1 1 2 1 1 1 3 2 0 1 2 3 2 6 3 3 2 3 2 4 3 6 2 3 6 5 3 3 3 2 4 2 3 5 10 4 1 3 4 9 3 4 3 2 2 3 7 1 2 2 2 2 3 3 2 1 4 2 0 3 1 2 2 2 1 1 3 0 1 1 3 0 1 0 2 1 0 1 0 0 0 0 1 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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imcomplete_wCC_Times: 0
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miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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imcomplete_dir_Times: 0
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miss_latency_IFETCH_NULL: [binsize: 16 max: 2239 count: 47 average: 995.638 | standard deviation: 452.716 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 1 1 1 0 1 1 1 0 0 0 1 1 2 0 0 0 1 0 2 2 1 0 0 0 0 2 1 0 0 0 1 0 2 1 0 0 0 2 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 2 0 2 1 0 2 0 0 1 0 2 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_LD_NULL: [binsize: 128 max: 21145 count: 53 average: 4245.77 | standard deviation: 5383.1 | 5 0 0 0 1 1 4 2 1 2 1 6 3 2 1 0 1 1 0 0 0 1 3 0 0 1 0 1 0 2 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_ST_NULL: [binsize: 256 max: 32770 count: 874 average: 6206.49 | standard deviation: 7863.36 | 73 14 42 60 69 63 42 36 32 30 32 22 15 18 15 14 6 9 8 6 4 5 4 5 4 3 7 3 5 6 5 7 0 3 1 4 1 2 3 1 1 1 2 1 1 0 3 2 0 1 2 3 2 6 3 3 2 2 1 4 3 6 2 2 6 5 3 2 3 2 4 2 3 4 10 4 1 3 4 9 3 4 2 2 2 3 7 1 2 2 2 2 3 3 2 1 4 2 0 3 1 2 2 2 1 1 3 0 1 1 3 0 1 0 2 1 0 1 0 0 0 0 1 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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All Non-Zero Cycle SW Prefetch Requests
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------------------------------------
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prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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Request vs. RubySystem State Profile
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--------------------------------
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filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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Message Delayed Cycles
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----------------------
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Total_delay_cycles: [binsize: 32 max: 1370 count: 6560 average: 27.1387 | standard deviation: 120.504 | 6041 13 41 130 8 21 48 8 12 22 20 4 19 15 5 14 23 3 9 21 22 3 9 6 3 6 6 3 1 2 5 1 3 4 2 0 3 1 1 1 0 0 1 0 0 0 0 0 ]
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Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 4028 average: 0 | standard deviation: 0 | 4028 ]
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virtual_network_0_delay_cycles: [binsize: 32 max: 1370 count: 2532 average: 70.312 | standard deviation: 185.996 | 2013 13 41 130 8 21 48 8 12 22 20 4 19 15 5 14 23 3 9 21 22 3 9 6 3 6 6 3 1 2 5 1 3 4 2 0 3 1 1 1 0 0 1 0 0 0 0 0 ]
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virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 512 average: 0 | standard deviation: 0 | 512 ]
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virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 3516 average: 0 | standard deviation: 0 | 3516 ]
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virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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Resource Usage
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--------------
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page_size: 4096
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user_time: 0
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system_time: 0
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page_reclaims: 9085
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page_faults: 0
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swaps: 0
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block_inputs: 0
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block_outputs: 0
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Network Stats
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-------------
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total_msg_count_Control: 5304 42432
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total_msg_count_Request_Control: 1537 12296
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total_msg_count_Response_Data: 7619 548568
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total_msg_count_Response_Control: 6666 53328
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total_msg_count_Writeback_Data: 3615 260280
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total_msg_count_Writeback_Control: 132 1056
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total_msgs: 24873 total_bytes: 917960
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switch_0_inlinks: 2
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switch_0_outlinks: 2
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links_utilized_percent_switch_0: 0.103063
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links_utilized_percent_switch_0_link_0: 0.0310005 bw: 640000 base_latency: 1
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links_utilized_percent_switch_0_link_1: 0.175124 bw: 160000 base_latency: 1
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outgoing_messages_switch_0_link_0_Request_Control: 512 4096 [ 512 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_0_Response_Data: 899 64728 [ 0 899 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_0_Response_Control: 379 3032 [ 0 379 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_1_Control: 901 7208 [ 901 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_1_Response_Control: 895 7160 [ 0 43 852 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_1_Writeback_Data: 1205 86760 [ 736 469 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_1_Writeback_Control: 44 352 [ 44 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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switch_1_inlinks: 2
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switch_1_outlinks: 2
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links_utilized_percent_switch_1: 0.153567
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links_utilized_percent_switch_1_link_0: 0.0736531 bw: 640000 base_latency: 1
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links_utilized_percent_switch_1_link_1: 0.233481 bw: 160000 base_latency: 1
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outgoing_messages_switch_1_link_0_Control: 901 7208 [ 901 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_0_Response_Data: 866 62352 [ 0 866 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_0_Response_Control: 1756 14048 [ 0 904 852 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_0_Writeback_Data: 1205 86760 [ 736 469 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_0_Writeback_Control: 44 352 [ 44 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_1_Control: 867 6936 [ 867 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_1_Request_Control: 513 4104 [ 513 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_1_Response_Data: 1674 120528 [ 0 1674 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_1_Response_Control: 466 3728 [ 0 466 0 0 0 0 0 0 0 0 ] base_latency: 1
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switch_2_inlinks: 2
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switch_2_outlinks: 2
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links_utilized_percent_switch_2: 0.0734115
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links_utilized_percent_switch_2_link_0: 0.0273352 bw: 640000 base_latency: 1
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links_utilized_percent_switch_2_link_1: 0.119488 bw: 160000 base_latency: 1
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outgoing_messages_switch_2_link_0_Control: 867 6936 [ 867 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_2_link_0_Response_Data: 774 55728 [ 0 774 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_2_link_0_Response_Control: 87 696 [ 0 87 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_2_link_1_Response_Data: 866 62352 [ 0 866 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_2_link_1_Response_Control: 861 6888 [ 0 861 0 0 0 0 0 0 0 0 ] base_latency: 1
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switch_3_inlinks: 3
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switch_3_outlinks: 3
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links_utilized_percent_switch_3: 0.176026
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links_utilized_percent_switch_3_link_0: 0.124002 bw: 160000 base_latency: 1
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links_utilized_percent_switch_3_link_1: 0.294612 bw: 160000 base_latency: 1
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links_utilized_percent_switch_3_link_2: 0.109465 bw: 160000 base_latency: 1
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outgoing_messages_switch_3_link_0_Request_Control: 512 4096 [ 512 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_3_link_0_Response_Data: 899 64728 [ 0 899 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_3_link_0_Response_Control: 379 3032 [ 0 379 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_3_link_1_Control: 901 7208 [ 901 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_3_link_1_Response_Data: 866 62352 [ 0 866 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_3_link_1_Response_Control: 1756 14048 [ 0 904 852 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_3_link_1_Writeback_Data: 1205 86760 [ 736 469 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_3_link_1_Writeback_Control: 44 352 [ 44 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_3_link_2_Control: 867 6936 [ 867 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_3_link_2_Response_Data: 775 55800 [ 0 775 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_3_link_2_Response_Control: 87 696 [ 0 87 0 0 0 0 0 0 0 0 ] base_latency: 1
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Cache Stats: system.l1_cntrl0.sequencer.icache
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system.l1_cntrl0.sequencer.icache_total_misses: 0
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system.l1_cntrl0.sequencer.icache_total_demand_misses: 0
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system.l1_cntrl0.sequencer.icache_total_prefetches: 0
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system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
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system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
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Cache Stats: system.l1_cntrl0.sequencer.dcache
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system.l1_cntrl0.sequencer.dcache_total_misses: 0
|
|
system.l1_cntrl0.sequencer.dcache_total_demand_misses: 0
|
|
system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
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system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
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system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
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--- L1Cache ---
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- Event Counts -
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Load [53 ] 53
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Ifetch [260 ] 260
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Store [877 ] 877
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Inv [512 ] 512
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L1_Replacement [510484 ] 510484
|
|
Fwd_GETX [0 ] 0
|
|
Fwd_GETS [0 ] 0
|
|
Fwd_GET_INSTR [0 ] 0
|
|
Data [0 ] 0
|
|
Data_Exclusive [48 ] 48
|
|
DataS_fromL1 [0 ] 0
|
|
Data_all_Acks [851 ] 851
|
|
Ack [0 ] 0
|
|
Ack_all [0 ] 0
|
|
WB_Ack [379 ] 379
|
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|
|
- Transitions -
|
|
NP Load [48 ] 48
|
|
NP Ifetch [47 ] 47
|
|
NP Store [806 ] 806
|
|
NP Inv [1 ] 1
|
|
NP L1_Replacement [0 ] 0
|
|
|
|
I Load [0 ] 0
|
|
I Ifetch [0 ] 0
|
|
I Store [0 ] 0
|
|
I Inv [0 ] 0
|
|
I L1_Replacement [110 ] 110
|
|
|
|
S Load [0 ] 0
|
|
S Ifetch [0 ] 0
|
|
S Store [0 ] 0
|
|
S Inv [26 ] 26
|
|
S L1_Replacement [6 ] 6
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|
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E Load [0 ] 0
|
|
E Ifetch [0 ] 0
|
|
E Store [0 ] 0
|
|
E Inv [3 ] 3
|
|
E L1_Replacement [45 ] 45
|
|
E Fwd_GETX [0 ] 0
|
|
E Fwd_GETS [0 ] 0
|
|
E Fwd_GET_INSTR [0 ] 0
|
|
|
|
M Load [5 ] 5
|
|
M Ifetch [0 ] 0
|
|
M Store [70 ] 70
|
|
M Inv [68 ] 68
|
|
M L1_Replacement [735 ] 735
|
|
M Fwd_GETX [0 ] 0
|
|
M Fwd_GETS [0 ] 0
|
|
M Fwd_GET_INSTR [0 ] 0
|
|
|
|
IS Load [0 ] 0
|
|
IS Ifetch [0 ] 0
|
|
IS Store [0 ] 0
|
|
IS Inv [13 ] 13
|
|
IS L1_Replacement [28783 ] 28783
|
|
IS Data_Exclusive [48 ] 48
|
|
IS DataS_fromL1 [0 ] 0
|
|
IS Data_all_Acks [34 ] 34
|
|
|
|
IM Load [0 ] 0
|
|
IM Ifetch [0 ] 0
|
|
IM Store [0 ] 0
|
|
IM Inv [0 ] 0
|
|
IM L1_Replacement [480805 ] 480805
|
|
IM Data [0 ] 0
|
|
IM Data_all_Acks [804 ] 804
|
|
IM Ack [0 ] 0
|
|
|
|
SM Load [0 ] 0
|
|
SM Ifetch [0 ] 0
|
|
SM Store [0 ] 0
|
|
SM Inv [0 ] 0
|
|
SM L1_Replacement [0 ] 0
|
|
SM Ack [0 ] 0
|
|
SM Ack_all [0 ] 0
|
|
|
|
IS_I Load [0 ] 0
|
|
IS_I Ifetch [0 ] 0
|
|
IS_I Store [0 ] 0
|
|
IS_I Inv [0 ] 0
|
|
IS_I L1_Replacement [0 ] 0
|
|
IS_I Data_Exclusive [0 ] 0
|
|
IS_I DataS_fromL1 [0 ] 0
|
|
IS_I Data_all_Acks [13 ] 13
|
|
|
|
M_I Load [0 ] 0
|
|
M_I Ifetch [213 ] 213
|
|
M_I Store [1 ] 1
|
|
M_I Inv [401 ] 401
|
|
M_I L1_Replacement [0 ] 0
|
|
M_I Fwd_GETX [0 ] 0
|
|
M_I Fwd_GETS [0 ] 0
|
|
M_I Fwd_GET_INSTR [0 ] 0
|
|
M_I WB_Ack [379 ] 379
|
|
|
|
E_I Load [0 ] 0
|
|
E_I Ifetch [0 ] 0
|
|
E_I Store [0 ] 0
|
|
E_I L1_Replacement [0 ] 0
|
|
|
|
Cache Stats: system.l2_cntrl0.L2cacheMemory
|
|
system.l2_cntrl0.L2cacheMemory_total_misses: 0
|
|
system.l2_cntrl0.L2cacheMemory_total_demand_misses: 0
|
|
system.l2_cntrl0.L2cacheMemory_total_prefetches: 0
|
|
system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
|
|
system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
|
|
|
|
|
|
--- L2Cache ---
|
|
- Event Counts -
|
|
L1_GET_INSTR [48 ] 48
|
|
L1_GETS [48 ] 48
|
|
L1_GETX [807 ] 807
|
|
L1_UPGRADE [0 ] 0
|
|
L1_PUTX [568 ] 568
|
|
L1_PUTX_old [1966 ] 1966
|
|
Fwd_L1_GETX [0 ] 0
|
|
Fwd_L1_GETS [0 ] 0
|
|
Fwd_L1_GET_INSTR [0 ] 0
|
|
L2_Replacement [328 ] 328
|
|
L2_Replacement_clean [16621 ] 16621
|
|
Mem_Data [865 ] 865
|
|
Mem_Ack [861 ] 861
|
|
WB_Data [447 ] 447
|
|
WB_Data_clean [22 ] 22
|
|
Ack [0 ] 0
|
|
Ack_all [43 ] 43
|
|
Unblock [0 ] 0
|
|
Unblock_Cancel [0 ] 0
|
|
Exclusive_Unblock [852 ] 852
|
|
MEM_Inv [0 ] 0
|
|
|
|
- Transitions -
|
|
NP L1_GET_INSTR [41 ] 41
|
|
NP L1_GETS [47 ] 47
|
|
NP L1_GETX [779 ] 779
|
|
NP L1_PUTX [0 ] 0
|
|
NP L1_PUTX_old [93 ] 93
|
|
|
|
SS L1_GET_INSTR [0 ] 0
|
|
SS L1_GETS [0 ] 0
|
|
SS L1_GETX [5 ] 5
|
|
SS L1_UPGRADE [0 ] 0
|
|
SS L1_PUTX [0 ] 0
|
|
SS L1_PUTX_old [0 ] 0
|
|
SS L2_Replacement [0 ] 0
|
|
SS L2_Replacement_clean [41 ] 41
|
|
SS MEM_Inv [0 ] 0
|
|
|
|
M L1_GET_INSTR [6 ] 6
|
|
M L1_GETS [1 ] 1
|
|
M L1_GETX [22 ] 22
|
|
M L1_PUTX [0 ] 0
|
|
M L1_PUTX_old [0 ] 0
|
|
M L2_Replacement [328 ] 328
|
|
M L2_Replacement_clean [22 ] 22
|
|
M MEM_Inv [0 ] 0
|
|
|
|
MT L1_GET_INSTR [0 ] 0
|
|
MT L1_GETS [0 ] 0
|
|
MT L1_GETX [0 ] 0
|
|
MT L1_PUTX [379 ] 379
|
|
MT L1_PUTX_old [0 ] 0
|
|
MT L2_Replacement [0 ] 0
|
|
MT L2_Replacement_clean [472 ] 472
|
|
MT MEM_Inv [0 ] 0
|
|
|
|
M_I L1_GET_INSTR [1 ] 1
|
|
M_I L1_GETS [0 ] 0
|
|
M_I L1_GETX [1 ] 1
|
|
M_I L1_UPGRADE [0 ] 0
|
|
M_I L1_PUTX [0 ] 0
|
|
M_I L1_PUTX_old [140 ] 140
|
|
M_I Mem_Ack [861 ] 861
|
|
M_I MEM_Inv [0 ] 0
|
|
|
|
MT_I L1_GET_INSTR [0 ] 0
|
|
MT_I L1_GETS [0 ] 0
|
|
MT_I L1_GETX [0 ] 0
|
|
MT_I L1_UPGRADE [0 ] 0
|
|
MT_I L1_PUTX [0 ] 0
|
|
MT_I L1_PUTX_old [0 ] 0
|
|
MT_I WB_Data [0 ] 0
|
|
MT_I WB_Data_clean [0 ] 0
|
|
MT_I Ack_all [0 ] 0
|
|
MT_I MEM_Inv [0 ] 0
|
|
|
|
MCT_I L1_GET_INSTR [0 ] 0
|
|
MCT_I L1_GETS [0 ] 0
|
|
MCT_I L1_GETX [0 ] 0
|
|
MCT_I L1_UPGRADE [0 ] 0
|
|
MCT_I L1_PUTX [0 ] 0
|
|
MCT_I L1_PUTX_old [167 ] 167
|
|
MCT_I WB_Data [447 ] 447
|
|
MCT_I WB_Data_clean [22 ] 22
|
|
MCT_I Ack_all [3 ] 3
|
|
|
|
I_I L1_GET_INSTR [0 ] 0
|
|
I_I L1_GETS [0 ] 0
|
|
I_I L1_GETX [0 ] 0
|
|
I_I L1_UPGRADE [0 ] 0
|
|
I_I L1_PUTX [0 ] 0
|
|
I_I L1_PUTX_old [0 ] 0
|
|
I_I Ack [0 ] 0
|
|
I_I Ack_all [40 ] 40
|
|
|
|
S_I L1_GET_INSTR [0 ] 0
|
|
S_I L1_GETS [0 ] 0
|
|
S_I L1_GETX [0 ] 0
|
|
S_I L1_UPGRADE [0 ] 0
|
|
S_I L1_PUTX [0 ] 0
|
|
S_I L1_PUTX_old [0 ] 0
|
|
S_I Ack [0 ] 0
|
|
S_I Ack_all [0 ] 0
|
|
S_I MEM_Inv [0 ] 0
|
|
|
|
ISS L1_GET_INSTR [0 ] 0
|
|
ISS L1_GETS [0 ] 0
|
|
ISS L1_GETX [0 ] 0
|
|
ISS L1_PUTX [0 ] 0
|
|
ISS L1_PUTX_old [0 ] 0
|
|
ISS L2_Replacement [0 ] 0
|
|
ISS L2_Replacement_clean [376 ] 376
|
|
ISS Mem_Data [47 ] 47
|
|
ISS MEM_Inv [0 ] 0
|
|
|
|
IS L1_GET_INSTR [0 ] 0
|
|
IS L1_GETS [0 ] 0
|
|
IS L1_GETX [0 ] 0
|
|
IS L1_PUTX [0 ] 0
|
|
IS L1_PUTX_old [0 ] 0
|
|
IS L2_Replacement [0 ] 0
|
|
IS L2_Replacement_clean [1234 ] 1234
|
|
IS Mem_Data [41 ] 41
|
|
IS MEM_Inv [0 ] 0
|
|
|
|
IM L1_GET_INSTR [0 ] 0
|
|
IM L1_GETS [0 ] 0
|
|
IM L1_GETX [0 ] 0
|
|
IM L1_PUTX [0 ] 0
|
|
IM L1_PUTX_old [0 ] 0
|
|
IM L2_Replacement [0 ] 0
|
|
IM L2_Replacement_clean [5858 ] 5858
|
|
IM Mem_Data [777 ] 777
|
|
IM MEM_Inv [0 ] 0
|
|
|
|
SS_MB L1_GET_INSTR [0 ] 0
|
|
SS_MB L1_GETS [0 ] 0
|
|
SS_MB L1_GETX [0 ] 0
|
|
SS_MB L1_UPGRADE [0 ] 0
|
|
SS_MB L1_PUTX [0 ] 0
|
|
SS_MB L1_PUTX_old [0 ] 0
|
|
SS_MB L2_Replacement [0 ] 0
|
|
SS_MB L2_Replacement_clean [0 ] 0
|
|
SS_MB Unblock_Cancel [0 ] 0
|
|
SS_MB Exclusive_Unblock [5 ] 5
|
|
SS_MB MEM_Inv [0 ] 0
|
|
|
|
MT_MB L1_GET_INSTR [0 ] 0
|
|
MT_MB L1_GETS [0 ] 0
|
|
MT_MB L1_GETX [0 ] 0
|
|
MT_MB L1_UPGRADE [0 ] 0
|
|
MT_MB L1_PUTX [189 ] 189
|
|
MT_MB L1_PUTX_old [1566 ] 1566
|
|
MT_MB L2_Replacement [0 ] 0
|
|
MT_MB L2_Replacement_clean [8618 ] 8618
|
|
MT_MB Unblock_Cancel [0 ] 0
|
|
MT_MB Exclusive_Unblock [847 ] 847
|
|
MT_MB MEM_Inv [0 ] 0
|
|
|
|
M_MB L1_GET_INSTR [0 ] 0
|
|
M_MB L1_GETS [0 ] 0
|
|
M_MB L1_GETX [0 ] 0
|
|
M_MB L1_UPGRADE [0 ] 0
|
|
M_MB L1_PUTX [0 ] 0
|
|
M_MB L1_PUTX_old [0 ] 0
|
|
M_MB L2_Replacement [0 ] 0
|
|
M_MB L2_Replacement_clean [0 ] 0
|
|
M_MB Exclusive_Unblock [0 ] 0
|
|
M_MB MEM_Inv [0 ] 0
|
|
|
|
MT_IIB L1_GET_INSTR [0 ] 0
|
|
MT_IIB L1_GETS [0 ] 0
|
|
MT_IIB L1_GETX [0 ] 0
|
|
MT_IIB L1_UPGRADE [0 ] 0
|
|
MT_IIB L1_PUTX [0 ] 0
|
|
MT_IIB L1_PUTX_old [0 ] 0
|
|
MT_IIB L2_Replacement [0 ] 0
|
|
MT_IIB L2_Replacement_clean [0 ] 0
|
|
MT_IIB WB_Data [0 ] 0
|
|
MT_IIB WB_Data_clean [0 ] 0
|
|
MT_IIB Unblock [0 ] 0
|
|
MT_IIB MEM_Inv [0 ] 0
|
|
|
|
MT_IB L1_GET_INSTR [0 ] 0
|
|
MT_IB L1_GETS [0 ] 0
|
|
MT_IB L1_GETX [0 ] 0
|
|
MT_IB L1_UPGRADE [0 ] 0
|
|
MT_IB L1_PUTX [0 ] 0
|
|
MT_IB L1_PUTX_old [0 ] 0
|
|
MT_IB L2_Replacement [0 ] 0
|
|
MT_IB L2_Replacement_clean [0 ] 0
|
|
MT_IB WB_Data [0 ] 0
|
|
MT_IB WB_Data_clean [0 ] 0
|
|
MT_IB Unblock_Cancel [0 ] 0
|
|
MT_IB MEM_Inv [0 ] 0
|
|
|
|
MT_SB L1_GET_INSTR [0 ] 0
|
|
MT_SB L1_GETS [0 ] 0
|
|
MT_SB L1_GETX [0 ] 0
|
|
MT_SB L1_UPGRADE [0 ] 0
|
|
MT_SB L1_PUTX [0 ] 0
|
|
MT_SB L1_PUTX_old [0 ] 0
|
|
MT_SB L2_Replacement [0 ] 0
|
|
MT_SB L2_Replacement_clean [0 ] 0
|
|
MT_SB Unblock [0 ] 0
|
|
MT_SB MEM_Inv [0 ] 0
|
|
|
|
Memory controller: system.dir_cntrl0.memBuffer:
|
|
memory_total_requests: 1641
|
|
memory_reads: 867
|
|
memory_writes: 774
|
|
memory_refreshes: 755
|
|
memory_total_request_delays: 1219
|
|
memory_delays_per_request: 0.74284
|
|
memory_delays_in_input_queue: 205
|
|
memory_delays_behind_head_of_bank_queue: 0
|
|
memory_delays_stalled_at_head_of_bank_queue: 1014
|
|
memory_stalls_for_bank_busy: 156
|
|
memory_stalls_for_random_busy: 0
|
|
memory_stalls_for_anti_starvation: 0
|
|
memory_stalls_for_arbitration: 89
|
|
memory_stalls_for_bus: 403
|
|
memory_stalls_for_tfaw: 0
|
|
memory_stalls_for_read_write_turnaround: 288
|
|
memory_stalls_for_read_read_turnaround: 78
|
|
accesses_per_bank: 54 61 46 85 55 63 50 44 52 43 42 47 32 53 58 44 49 60 55 44 56 46 52 48 42 68 40 47 41 48 61 55
|
|
|
|
--- Directory ---
|
|
- Event Counts -
|
|
Fetch [867 ] 867
|
|
Data [774 ] 774
|
|
Memory_Data [866 ] 866
|
|
Memory_Ack [774 ] 774
|
|
DMA_READ [0 ] 0
|
|
DMA_WRITE [0 ] 0
|
|
CleanReplacement [87 ] 87
|
|
|
|
- Transitions -
|
|
I Fetch [867 ] 867
|
|
I DMA_READ [0 ] 0
|
|
I DMA_WRITE [0 ] 0
|
|
|
|
ID Fetch [0 ] 0
|
|
ID Data [0 ] 0
|
|
ID Memory_Data [0 ] 0
|
|
ID DMA_READ [0 ] 0
|
|
ID DMA_WRITE [0 ] 0
|
|
|
|
ID_W Fetch [0 ] 0
|
|
ID_W Data [0 ] 0
|
|
ID_W Memory_Ack [0 ] 0
|
|
ID_W DMA_READ [0 ] 0
|
|
ID_W DMA_WRITE [0 ] 0
|
|
|
|
M Data [774 ] 774
|
|
M DMA_READ [0 ] 0
|
|
M DMA_WRITE [0 ] 0
|
|
M CleanReplacement [87 ] 87
|
|
|
|
IM Fetch [0 ] 0
|
|
IM Data [0 ] 0
|
|
IM Memory_Data [866 ] 866
|
|
IM DMA_READ [0 ] 0
|
|
IM DMA_WRITE [0 ] 0
|
|
|
|
MI Fetch [0 ] 0
|
|
MI Data [0 ] 0
|
|
MI Memory_Ack [774 ] 774
|
|
MI DMA_READ [0 ] 0
|
|
MI DMA_WRITE [0 ] 0
|
|
|
|
M_DRD Data [0 ] 0
|
|
M_DRD DMA_READ [0 ] 0
|
|
M_DRD DMA_WRITE [0 ] 0
|
|
|
|
M_DRDI Fetch [0 ] 0
|
|
M_DRDI Data [0 ] 0
|
|
M_DRDI Memory_Ack [0 ] 0
|
|
M_DRDI DMA_READ [0 ] 0
|
|
M_DRDI DMA_WRITE [0 ] 0
|
|
|
|
M_DWR Data [0 ] 0
|
|
M_DWR DMA_READ [0 ] 0
|
|
M_DWR DMA_WRITE [0 ] 0
|
|
|
|
M_DWRI Fetch [0 ] 0
|
|
M_DWRI Data [0 ] 0
|
|
M_DWRI Memory_Ack [0 ] 0
|
|
M_DWRI DMA_READ [0 ] 0
|
|
M_DWRI DMA_WRITE |