Update statistics for the last three revisions

--HG--
extra : convert_revision : 117e2a40bd6e0867d013a3a6076fb758ac526d24

tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt

@@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect                4207318                       # Nu
 global.BPredUnit.condPredicted               70088985                       # Number of conditional branches predicted
 global.BPredUnit.lookups                     76017379                       # Number of BP lookups
 global.BPredUnit.usedRAS                      1692882                       # Number of times the RAS was used to get a target.
-host_inst_rate                                 211348                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 182448                       # Number of bytes of host memory used
-host_seconds                                  2675.93                       # Real time elapsed on the host
-host_tick_rate                               60738573                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 209676                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 200632                       # Number of bytes of host memory used
+host_seconds                                  2697.27                       # Real time elapsed on the host
+host_tick_rate                               60257939                       # Simulator tick rate (ticks/s)
 memdepunit.memDep.conflictingLoads           16721732                       # Number of conflicting loads.
 memdepunit.memDep.conflictingStores          11866335                       # Number of conflicting stores.
 memdepunit.memDep.insertedLoads             126743752                       # Number of loads inserted to the mem dependence unit.
@@ -157,7 +157,7 @@ system.cpu.fetch.SquashCycles                 4233156                       # Nu
 system.cpu.fetch.branchRate                  0.233854                       # Number of branch fetches per cycle
 system.cpu.fetch.icacheStallCycles           65923007                       # Number of cycles fetch is stalled on an Icache miss
 system.cpu.fetch.predictedBranches           67369318                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        2.146836                       # Number of inst fetches per cycle
+system.cpu.fetch.rate                        2.146834                       # Number of inst fetches per cycle
 system.cpu.fetch.rateDist.start_dist                           # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist.samples           325063615                      
 system.cpu.fetch.rateDist.min_value                 0                      
@@ -236,10 +236,10 @@ system.cpu.icache.tagsinuse                770.534444                       # Cy
 system.cpu.icache.total_refs                 65922018                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                          190397                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles                             278                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.iew.EXEC:branches                 67319692                       # Number of branches executed
 system.cpu.iew.EXEC:nop                      42991424                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     1.842347                       # Inst execution rate
+system.cpu.iew.EXEC:rate                     1.842345                       # Inst execution rate
 system.cpu.iew.EXEC:refs                    163918711                       # number of memory reference insts executed
 system.cpu.iew.EXEC:stores                   41167815                       # Number of stores executed
 system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
@@ -249,7 +249,7 @@ system.cpu.iew.WB:fanout                     0.805927                       # av
 system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.iew.WB:producers                 395691865                       # num instructions producing a value
-system.cpu.iew.WB:rate                       1.832664                       # insts written-back per cycle
+system.cpu.iew.WB:rate                       1.832662                       # insts written-back per cycle
 system.cpu.iew.WB:sent                      596897738                       # cumulative count of insts sent to commit
 system.cpu.iew.branchMispredicts              4671822                       # Number of branch mispredicts detected at execute
 system.cpu.iew.iewBlockCycles                  211982                       # Number of cycles IEW is blocking
@@ -279,8 +279,8 @@ system.cpu.iew.lsq.thread.0.squashedStores      3229074                       #
 system.cpu.iew.memOrderViolationEvents          28955                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect       540642                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect        4131180                       # Number of branches that were predicted taken incorrectly
-system.cpu.ipc                               1.739821                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.739821                       # IPC: Total IPC of All Threads
+system.cpu.ipc                               1.739819                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.739819                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0               605296760                       # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0.start_dist
                       No_OpClass            0      0.00%            # Type of FU issued
@@ -331,7 +331,7 @@ system.cpu.iq.ISSUE:issued_per_cycle.min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle.max_value            8                      
 system.cpu.iq.ISSUE:issued_per_cycle.end_dist
 
-system.cpu.iq.ISSUE:rate                     1.862087                       # Inst issue rate
+system.cpu.iq.ISSUE:rate                     1.862085                       # Inst issue rate
 system.cpu.iq.iqInstsAdded                  619382498                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                 605296760                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded                  22                       # Number of non-speculative instructions added to the IQ
@@ -428,7 +428,7 @@ system.cpu.l2cache.tagsinuse              8150.643180                       # Cy
 system.cpu.l2cache.total_refs                   66110                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.numCycles                        325063615                       # number of cpu cycles simulated
+system.cpu.numCycles                        325063893                       # number of cpu cycles simulated
 system.cpu.rename.RENAME:BlockCycles         11040699                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps      463854889                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IQFullEvents        31586100                       # Number of times rename has blocked due to IQ full

tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt

@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1730291                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 181616                       # Number of bytes of host memory used
-host_seconds                                   347.84                       # Real time elapsed on the host
-host_tick_rate                             2208778962                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1400395                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 199872                       # Number of bytes of host memory used
+host_seconds                                   429.78                       # Real time elapsed on the host
+host_tick_rate                             1787654853                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   601856964                       # Number of instructions simulated
 sim_seconds                                  0.768293                       # Number of seconds simulated
@@ -245,7 +245,7 @@ system.cpu.l2cache.total_refs                   52084                       # To
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                     768292872000                       # number of cpu cycles simulated
+system.cpu.numCycles                       1536585744                       # number of cpu cycles simulated
 system.cpu.num_insts                        601856964                       # Number of instructions executed
 system.cpu.num_refs                         154866966                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              17                       # Number of system calls

tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt

@@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect               84447535                       # Nu
 global.BPredUnit.condPredicted              256528366                       # Number of conditional branches predicted
 global.BPredUnit.lookups                    256528366                       # Number of BP lookups
 global.BPredUnit.usedRAS                            0                       # Number of times the RAS was used to get a target.
-host_inst_rate                                  94020                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 184848                       # Number of bytes of host memory used
-host_seconds                                 14950.16                       # Real time elapsed on the host
-host_tick_rate                               73409017                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 101903                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 202864                       # Number of bytes of host memory used
+host_seconds                                 13793.57                       # Real time elapsed on the host
+host_tick_rate                               79564409                       # Simulator tick rate (ticks/s)
 memdepunit.memDep.conflictingLoads          458856790                       # Number of conflicting loads.
 memdepunit.memDep.conflictingStores         141228058                       # Number of conflicting stores.
 memdepunit.memDep.insertedLoads             745627925                       # Number of loads inserted to the mem dependence unit.
@@ -229,7 +229,7 @@ system.cpu.icache.tagsinuse               1042.348080                       # Cy
 system.cpu.icache.total_refs                355014725                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                           94965                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles                             155                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.iew.EXEC:branches                128778452                       # Number of branches executed
 system.cpu.iew.EXEC:nop                     354384689                       # number of nop insts executed
 system.cpu.iew.EXEC:rate                     0.865881                       # Inst execution rate
@@ -242,7 +242,7 @@ system.cpu.iew.WB:fanout                     0.963032                       # av
 system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.iew.WB:producers                1442442170                       # num instructions producing a value
-system.cpu.iew.WB:rate                       0.850638                       # insts written-back per cycle
+system.cpu.iew.WB:rate                       0.850637                       # insts written-back per cycle
 system.cpu.iew.WB:sent                     1877161076                       # cumulative count of insts sent to commit
 system.cpu.iew.branchMispredicts             91327681                       # Number of branch mispredicts detected at execute
 system.cpu.iew.iewBlockCycles                  454443                       # Number of cycles IEW is blocking
@@ -417,7 +417,7 @@ system.cpu.l2cache.tagsinuse              8527.413561                       # Cy
 system.cpu.l2cache.total_refs                   96715                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.numCycles                       2194953627                       # number of cpu cycles simulated
+system.cpu.numCycles                       2194953782                       # number of cpu cycles simulated
 system.cpu.rename.RENAME:BlockCycles         13000888                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps     1244771057                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:FullRegisterEvents            9                       # Number of times there has been no free registers

tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr

@@ -1,6 +1,2 @@
-warn: More than two loadable segments in ELF object.
-warn: Ignoring segment @ 0xb4000 length 0x10.
-warn: More than two loadable segments in ELF object.
-warn: Ignoring segment @ 0x0 length 0x0.
 warn: Entering event queue @ 0.  Starting simulation...
 warn: Ignoring request to flush register windows.

tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr

@@ -1,6 +1,2 @@
-warn: More than two loadable segments in ELF object.
-warn: Ignoring segment @ 0xb4000 length 0x10.
-warn: More than two loadable segments in ELF object.
-warn: Ignoring segment @ 0x0 length 0x0.
 warn: Entering event queue @ 0.  Starting simulation...
 warn: Ignoring request to flush register windows.

tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt

@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1120793                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 183848                       # Number of bytes of host memory used
-host_seconds                                  1328.98                       # Real time elapsed on the host
-host_tick_rate                             1558243449                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1001521                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 201940                       # Number of bytes of host memory used
+host_seconds                                  1487.25                       # Real time elapsed on the host
+host_tick_rate                             1392419330                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1489514761                       # Number of instructions simulated
 sim_seconds                                  2.070880                       # Number of seconds simulated
@@ -239,7 +239,7 @@ system.cpu.l2cache.total_refs                   62289                       # To
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                     2070879986000                       # number of cpu cycles simulated
+system.cpu.numCycles                       4141759972                       # number of cpu cycles simulated
 system.cpu.num_insts                       1489514761                       # Number of instructions executed
 system.cpu.num_refs                         569364430                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              19                       # Number of system calls

tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr

@@ -1,6 +1,2 @@
-warn: More than two loadable segments in ELF object.
-warn: Ignoring segment @ 0xb4000 length 0x10.
-warn: More than two loadable segments in ELF object.
-warn: Ignoring segment @ 0x0 length 0x0.
 warn: Entering event queue @ 0.  Starting simulation...
 warn: Ignoring request to flush register windows.

tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr

@@ -1,6 +1,2 @@
-warn: More than two loadable segments in ELF object.
-warn: Ignoring segment @ 0xa2000 length 0x10.
-warn: More than two loadable segments in ELF object.
-warn: Ignoring segment @ 0x0 length 0x0.
 warn: Entering event queue @ 0.  Starting simulation...
 warn: Ignoring request to flush register windows.

tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt

@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1059302                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 184256                       # Number of bytes of host memory used
-host_seconds                                   230.18                       # Real time elapsed on the host
-host_tick_rate                             1578613892                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 981553                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 203224                       # Number of bytes of host memory used
+host_seconds                                   248.41                       # Real time elapsed on the host
+host_tick_rate                             1462749007                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   243829010                       # Number of instructions simulated
 sim_seconds                                  0.363364                       # Number of seconds simulated
@@ -239,7 +239,7 @@ system.cpu.l2cache.total_refs                  553407                       # To
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                     363364127000                       # number of cpu cycles simulated
+system.cpu.numCycles                        726728254                       # number of cpu cycles simulated
 system.cpu.num_insts                        243829010                       # Number of instructions executed
 system.cpu.num_refs                         105710359                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls             428                       # Number of system calls

tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr

@@ -1,6 +1,2 @@
-warn: More than two loadable segments in ELF object.
-warn: Ignoring segment @ 0xa2000 length 0x10.
-warn: More than two loadable segments in ELF object.
-warn: Ignoring segment @ 0x0 length 0x0.
 warn: Entering event queue @ 0.  Starting simulation...
 warn: Ignoring request to flush register windows.

tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt

@@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect                5797485                       # Nu
 global.BPredUnit.condPredicted               35586107                       # Number of conditional branches predicted
 global.BPredUnit.lookups                     62816866                       # Number of BP lookups
 global.BPredUnit.usedRAS                     12584281                       # Number of times the RAS was used to get a target.
-host_inst_rate                                 159982                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 190068                       # Number of bytes of host memory used
-host_seconds                                  2347.61                       # Real time elapsed on the host
-host_tick_rate                               55593251                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 162238                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 208244                       # Number of bytes of host memory used
+host_seconds                                  2314.96                       # Real time elapsed on the host
+host_tick_rate                               56377317                       # Simulator tick rate (ticks/s)
 memdepunit.memDep.conflictingLoads           72605768                       # Number of conflicting loads.
 memdepunit.memDep.conflictingStores          52678550                       # Number of conflicting stores.
 memdepunit.memDep.insertedLoads             125601766                       # Number of loads inserted to the mem dependence unit.
@@ -49,8 +49,8 @@ system.cpu.commit.commitNonSpecStalls             215                       # Th
 system.cpu.commit.commitSquashedInsts        97412298                       # The number of squashed insts skipped by commit
 system.cpu.committedInsts                   375574833                       # Number of Instructions Simulated
 system.cpu.committedInsts_total             375574833                       # Number of Instructions Simulated
-system.cpu.cpi                               0.694992                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.694992                       # CPI: Total CPI of All Threads
+system.cpu.cpi                               0.694995                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.694995                       # CPI: Total CPI of All Threads
 system.cpu.dcache.LoadLockedReq_accesses            1                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_hits                1                       # number of LoadLockedReq hits
 system.cpu.dcache.ReadReq_accesses           96463931                       # number of ReadReq accesses(hits+misses)
@@ -154,10 +154,10 @@ system.cpu.fetch.Cycles                     169349894                       # Nu
 system.cpu.fetch.IcacheSquashes               1380085                       # Number of outstanding Icache misses that were squashed
 system.cpu.fetch.Insts                      550063393                       # Number of instructions fetch has processed
 system.cpu.fetch.SquashCycles                 6176073                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate                  0.240658                       # Number of branch fetches per cycle
+system.cpu.fetch.branchRate                  0.240657                       # Number of branch fetches per cycle
 system.cpu.fetch.icacheStallCycles           64526365                       # Number of cycles fetch is stalled on an Icache miss
 system.cpu.fetch.predictedBranches           49445851                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        2.107348                       # Number of inst fetches per cycle
+system.cpu.fetch.rate                        2.107339                       # Number of inst fetches per cycle
 system.cpu.fetch.rateDist.start_dist                           # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist.samples           261021562                      
 system.cpu.fetch.rateDist.min_value                 0                      
@@ -236,10 +236,10 @@ system.cpu.icache.tagsinuse               1827.041992                       # Cy
 system.cpu.icache.total_refs                 64522273                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                          787561                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles                            1138                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.iew.EXEC:branches                 51184181                       # Number of branches executed
 system.cpu.iew.EXEC:nop                      27521515                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     1.613810                       # Inst execution rate
+system.cpu.iew.EXEC:rate                     1.613803                       # Inst execution rate
 system.cpu.iew.EXEC:refs                    192783461                       # number of memory reference insts executed
 system.cpu.iew.EXEC:stores                   80743835                       # Number of stores executed
 system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
@@ -249,7 +249,7 @@ system.cpu.iew.WB:fanout                     0.706015                       # av
 system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.iew.WB:producers                 200824371                       # num instructions producing a value
-system.cpu.iew.WB:rate                       1.598292                       # insts written-back per cycle
+system.cpu.iew.WB:rate                       1.598285                       # insts written-back per cycle
 system.cpu.iew.WB:sent                      418096768                       # cumulative count of insts sent to commit
 system.cpu.iew.branchMispredicts              6170690                       # Number of branch mispredicts detected at execute
 system.cpu.iew.iewBlockCycles                 1426561                       # Number of cycles IEW is blocking
@@ -279,8 +279,8 @@ system.cpu.iew.lsq.thread.0.squashedStores     19324087                       #
 system.cpu.iew.memOrderViolationEvents         574238                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect       908757                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect        5261933                       # Number of branches that were predicted taken incorrectly
-system.cpu.ipc                               1.438865                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.438865                       # IPC: Total IPC of All Threads
+system.cpu.ipc                               1.438859                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.438859                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0               431234771                       # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0.start_dist
                       No_OpClass        33581      0.01%            # Type of FU issued
@@ -331,7 +331,7 @@ system.cpu.iq.ISSUE:issued_per_cycle.min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle.max_value            8                      
 system.cpu.iq.ISSUE:issued_per_cycle.end_dist
 
-system.cpu.iq.ISSUE:rate                     1.652104                       # Inst issue rate
+system.cpu.iq.ISSUE:rate                     1.652097                       # Inst issue rate
 system.cpu.iq.iqInstsAdded                  468556087                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                 431234771                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded                 239                       # Number of non-speculative instructions added to the IQ
@@ -428,7 +428,7 @@ system.cpu.l2cache.tagsinuse              3522.085649                       # Cy
 system.cpu.l2cache.total_refs                     573                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.numCycles                        261021562                       # number of cpu cycles simulated
+system.cpu.numCycles                        261022700                       # number of cpu cycles simulated
 system.cpu.rename.RENAME:BlockCycles          4632657                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps      259532351                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IQFullEvents          371371                       # Number of times rename has blocked due to IQ full

tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt

@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1404632                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 189192                       # Number of bytes of host memory used
-host_seconds                                   283.82                       # Real time elapsed on the host
-host_tick_rate                             1998169503                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1238026                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 207368                       # Number of bytes of host memory used
+host_seconds                                   322.02                       # Real time elapsed on the host
+host_tick_rate                             1761163764                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   398664609                       # Number of instructions simulated
 sim_seconds                                  0.567124                       # Number of seconds simulated
@@ -245,7 +245,7 @@ system.cpu.l2cache.total_refs                     510                       # To
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                     567124013000                       # number of cpu cycles simulated
+system.cpu.numCycles                       1134248026                       # number of cpu cycles simulated
 system.cpu.num_insts                        398664609                       # Number of instructions executed
 system.cpu.num_refs                         174183455                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls             215                       # Number of system calls

tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt

@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1524477                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 188336                       # Number of bytes of host memory used
-host_seconds                                  1317.82                       # Real time elapsed on the host
-host_tick_rate                             2100501698                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1159414                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 206548                       # Number of bytes of host memory used
+host_seconds                                  1732.76                       # Real time elapsed on the host
+host_tick_rate                             1597499589                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  2008987605                       # Number of instructions simulated
 sim_seconds                                  2.768086                       # Number of seconds simulated
@@ -245,7 +245,7 @@ system.cpu.l2cache.total_refs                   22612                       # To
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                     2768085828000                       # number of cpu cycles simulated
+system.cpu.numCycles                       5536171656                       # number of cpu cycles simulated
 system.cpu.num_insts                       2008987605                       # Number of instructions executed
 system.cpu.num_refs                         722823898                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              39                       # Number of system calls

tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt

@@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect                 455902                       # Nu
 global.BPredUnit.condPredicted               10551273                       # Number of conditional branches predicted
 global.BPredUnit.lookups                     16246333                       # Number of BP lookups
 global.BPredUnit.usedRAS                      1941036                       # Number of times the RAS was used to get a target.
-host_inst_rate                                 173213                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 193376                       # Number of bytes of host memory used
-host_seconds                                   459.50                       # Real time elapsed on the host
-host_tick_rate                               54150958                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 178455                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 211564                       # Number of bytes of host memory used
+host_seconds                                   446.00                       # Real time elapsed on the host
+host_tick_rate                               55789781                       # Simulator tick rate (ticks/s)
 memdepunit.memDep.conflictingLoads           12304370                       # Number of conflicting loads.
 memdepunit.memDep.conflictingStores          10964244                       # Number of conflicting stores.
 memdepunit.memDep.insertedLoads              22974359                       # Number of loads inserted to the mem dependence unit.
@@ -49,8 +49,8 @@ system.cpu.commit.commitNonSpecStalls            4583                       # Th
 system.cpu.commit.commitSquashedInsts         8051078                       # The number of squashed insts skipped by commit
 system.cpu.committedInsts                    79591756                       # Number of Instructions Simulated
 system.cpu.committedInsts_total              79591756                       # Number of Instructions Simulated
-system.cpu.cpi                               0.625230                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.625230                       # CPI: Total CPI of All Threads
+system.cpu.cpi                               0.625252                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.625252                       # CPI: Total CPI of All Threads
 system.cpu.dcache.LoadLockedReq_accesses           44                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_hits               44                       # number of LoadLockedReq hits
 system.cpu.dcache.ReadReq_accesses           20377695                       # number of ReadReq accesses(hits+misses)
@@ -154,10 +154,10 @@ system.cpu.fetch.Cycles                      33194597                       # Nu
 system.cpu.fetch.IcacheSquashes                152184                       # Number of outstanding Icache misses that were squashed
 system.cpu.fetch.Insts                      103251284                       # Number of instructions fetch has processed
 system.cpu.fetch.SquashCycles                  572846                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate                  0.326473                       # Number of branch fetches per cycle
+system.cpu.fetch.branchRate                  0.326461                       # Number of branch fetches per cycle
 system.cpu.fetch.icacheStallCycles           13375683                       # Number of cycles fetch is stalled on an Icache miss
 system.cpu.fetch.predictedBranches            9942709                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        2.074854                       # Number of inst fetches per cycle
+system.cpu.fetch.rate                        2.074780                       # Number of inst fetches per cycle
 system.cpu.fetch.rateDist.start_dist                           # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist.samples            49763148                      
 system.cpu.fetch.rateDist.min_value                 0                      
@@ -236,10 +236,10 @@ system.cpu.icache.tagsinuse               1922.769682                       # Cy
 system.cpu.icache.total_refs                 13289333                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle            21643859000                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                         1231826                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles                            1791                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.iew.EXEC:branches                 14739683                       # Number of branches executed
 system.cpu.iew.EXEC:nop                       9380523                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     1.704450                       # Inst execution rate
+system.cpu.iew.EXEC:rate                     1.704389                       # Inst execution rate
 system.cpu.iew.EXEC:refs                     36969776                       # number of memory reference insts executed
 system.cpu.iew.EXEC:stores                   15295559                       # Number of stores executed
 system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
@@ -249,7 +249,7 @@ system.cpu.iew.WB:fanout                     0.765386                       # av
 system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.iew.WB:producers                  32456867                       # num instructions producing a value
-system.cpu.iew.WB:rate                       1.694688                       # insts written-back per cycle
+system.cpu.iew.WB:rate                       1.694627                       # insts written-back per cycle
 system.cpu.iew.WB:sent                       84566644                       # cumulative count of insts sent to commit
 system.cpu.iew.branchMispredicts               400717                       # Number of branch mispredicts detected at execute
 system.cpu.iew.iewBlockCycles                   20492                       # Number of cycles IEW is blocking
@@ -279,8 +279,8 @@ system.cpu.iew.lsq.thread.0.squashedStores      1453767                       #
 system.cpu.iew.memOrderViolationEvents          19531                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect       108348                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect         292369                       # Number of branches that were predicted taken incorrectly
-system.cpu.ipc                               1.599412                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.599412                       # IPC: Total IPC of All Threads
+system.cpu.ipc                               1.599354                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.599354                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0                85364731                       # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0.start_dist
                       No_OpClass            0      0.00%            # Type of FU issued
@@ -331,7 +331,7 @@ system.cpu.iq.ISSUE:issued_per_cycle.min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle.max_value            8                      
 system.cpu.iq.ISSUE:issued_per_cycle.end_dist
 
-system.cpu.iq.ISSUE:rate                     1.715421                       # Inst issue rate
+system.cpu.iq.ISSUE:rate                     1.715359                       # Inst issue rate
 system.cpu.iq.iqInstsAdded                   89442204                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                  85364731                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded                4987                       # Number of non-speculative instructions added to the IQ
@@ -428,7 +428,7 @@ system.cpu.l2cache.tagsinuse              4581.530519                       # Cy
 system.cpu.l2cache.total_refs                  102503                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.numCycles                         49763148                       # number of cpu cycles simulated
+system.cpu.numCycles                         49764939                       # number of cpu cycles simulated
 system.cpu.rename.RENAME:BlockCycles           263435                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps       52546881                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IQFullEvents           34724                       # Number of times rename has blocked due to IQ full

tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt

@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1453070                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 191752                       # Number of bytes of host memory used
-host_seconds                                    60.80                       # Real time elapsed on the host
-host_tick_rate                             2124138006                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1210019                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 209960                       # Number of bytes of host memory used
+host_seconds                                    73.01                       # Real time elapsed on the host
+host_tick_rate                             1768843958                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    88340673                       # Number of instructions simulated
 sim_seconds                                  0.129140                       # Number of seconds simulated
@@ -245,7 +245,7 @@ system.cpu.l2cache.total_refs                   93692                       # To
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                     129139604000                       # number of cpu cycles simulated
+system.cpu.numCycles                        258279208                       # number of cpu cycles simulated
 system.cpu.num_insts                         88340673                       # Number of instructions executed
 system.cpu.num_refs                          35321418                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls            4583                       # Number of system calls

tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr

@@ -1,7 +1,3 @@
-warn: More than two loadable segments in ELF object.
-warn: Ignoring segment @ 0x1838c0 length 0x10.
-warn: More than two loadable segments in ELF object.
-warn: Ignoring segment @ 0x0 length 0x0.
 warn: Entering event queue @ 0.  Starting simulation...
 warn: Ignoring request to flush register windows.
 warn: ignoring syscall time(4026527856, 4026528256, ...)

tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt

@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 960220                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 192724                       # Number of bytes of host memory used
-host_seconds                                   141.78                       # Real time elapsed on the host
-host_tick_rate                             1412855280                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 941673                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 210848                       # Number of bytes of host memory used
+host_seconds                                   144.57                       # Real time elapsed on the host
+host_tick_rate                             1385565564                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   136141055                       # Number of instructions simulated
 sim_seconds                                  0.200317                       # Number of seconds simulated
@@ -239,7 +239,7 @@ system.cpu.l2cache.total_refs                  193951                       # To
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                     200316584000                       # number of cpu cycles simulated
+system.cpu.numCycles                        400633168                       # number of cpu cycles simulated
 system.cpu.num_insts                        136141055                       # Number of instructions executed
 system.cpu.num_refs                          58160249                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls            1946                       # Number of system calls

tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr

@@ -1,7 +1,3 @@
-warn: More than two loadable segments in ELF object.
-warn: Ignoring segment @ 0x1838c0 length 0x10.
-warn: More than two loadable segments in ELF object.
-warn: Ignoring segment @ 0x0 length 0x0.
 warn: Entering event queue @ 0.  Starting simulation...
 warn: Ignoring request to flush register windows.
 warn: ignoring syscall time(4026527856, 4026528256, ...)

tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt

@@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect               19407214                       # Nu
 global.BPredUnit.condPredicted              254124044                       # Number of conditional branches predicted
 global.BPredUnit.lookups                    329654644                       # Number of BP lookups
 global.BPredUnit.usedRAS                     23321143                       # Number of times the RAS was used to get a target.
-host_inst_rate                                 153530                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 182552                       # Number of bytes of host memory used
-host_seconds                                 11307.49                       # Real time elapsed on the host
-host_tick_rate                               57851122                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 162413                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 200732                       # Number of bytes of host memory used
+host_seconds                                 10689.07                       # Real time elapsed on the host
+host_tick_rate                               61198134                       # Simulator tick rate (ticks/s)
 memdepunit.memDep.conflictingLoads           71970991                       # Number of conflicting loads.
 memdepunit.memDep.conflictingStores          36581423                       # Number of conflicting stores.
 memdepunit.memDep.insertedLoads             594992654                       # Number of loads inserted to the mem dependence unit.
@@ -244,10 +244,10 @@ system.cpu.icache.tagsinuse                710.981871                       # Cy
 system.cpu.icache.total_refs                338458990                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                          287621                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles                             197                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.iew.EXEC:branches                270496646                       # Number of branches executed
 system.cpu.iew.EXEC:nop                     123104849                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     1.690527                       # Inst execution rate
+system.cpu.iew.EXEC:rate                     1.690526                       # Inst execution rate
 system.cpu.iew.EXEC:refs                    759555990                       # number of memory reference insts executed
 system.cpu.iew.EXEC:stores                  199980185                       # Number of stores executed
 system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
@@ -436,7 +436,7 @@ system.cpu.l2cache.tagsinuse             18802.772660                       # Cy
 system.cpu.l2cache.total_refs                 5868601                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle          505903232000                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.numCycles                       1308302031                       # number of cpu cycles simulated
+system.cpu.numCycles                       1308302228                       # number of cpu cycles simulated
 system.cpu.rename.RENAME:BlockCycles          9337867                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps     1376202963                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IQFullEvents         3445352                       # Number of times rename has blocked due to IQ full

tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt

@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1514723                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 181532                       # Number of bytes of host memory used
-host_seconds                                  1201.39                       # Real time elapsed on the host
-host_tick_rate                             2161875158                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1279505                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 199716                       # Number of bytes of host memory used
+host_seconds                                  1422.25                       # Real time elapsed on the host
+host_tick_rate                             1826162604                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1819780127                       # Number of instructions simulated
 sim_seconds                                  2.597265                       # Number of seconds simulated
@@ -245,7 +245,7 @@ system.cpu.l2cache.total_refs                 5824390                       # To
 system.cpu.l2cache.warmup_cycle          2034930554000                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                     2597265186000                       # number of cpu cycles simulated
+system.cpu.numCycles                       5194530372                       # number of cpu cycles simulated
 system.cpu.num_insts                       1819780127                       # Number of instructions executed
 system.cpu.num_refs                         613169725                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              29                       # Number of system calls

tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt

@@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect                1944478                       # Nu
 global.BPredUnit.condPredicted               14575632                       # Number of conditional branches predicted
 global.BPredUnit.lookups                     19422613                       # Number of BP lookups
 global.BPredUnit.usedRAS                      1713685                       # Number of times the RAS was used to get a target.
-host_inst_rate                                 134486                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 187512                       # Number of bytes of host memory used
-host_seconds                                   625.94                       # Real time elapsed on the host
-host_tick_rate                               64866574                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 135551                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 205692                       # Number of bytes of host memory used
+host_seconds                                   621.02                       # Real time elapsed on the host
+host_tick_rate                               65380263                       # Simulator tick rate (ticks/s)
 memdepunit.memDep.conflictingLoads           17216912                       # Number of conflicting loads.
 memdepunit.memDep.conflictingStores           5017487                       # Number of conflicting stores.
 memdepunit.memDep.insertedLoads              33831723                       # Number of loads inserted to the mem dependence unit.
@@ -49,8 +49,8 @@ system.cpu.commit.commitNonSpecStalls             389                       # Th
 system.cpu.commit.commitSquashedInsts        55442802                       # The number of squashed insts skipped by commit
 system.cpu.committedInsts                    84179709                       # Number of Instructions Simulated
 system.cpu.committedInsts_total              84179709                       # Number of Instructions Simulated
-system.cpu.cpi                               0.964650                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.964650                       # CPI: Total CPI of All Threads
+system.cpu.cpi                               0.964659                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.964659                       # CPI: Total CPI of All Threads
 system.cpu.dcache.LoadLockedReq_accesses            7                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_hits                7                       # number of LoadLockedReq hits
 system.cpu.dcache.ReadReq_accesses           23305151                       # number of ReadReq accesses(hits+misses)
@@ -154,10 +154,10 @@ system.cpu.fetch.Cycles                      50102609                       # Nu
 system.cpu.fetch.IcacheSquashes                509210                       # Number of outstanding Icache misses that were squashed
 system.cpu.fetch.Insts                      167066208                       # Number of instructions fetch has processed
 system.cpu.fetch.SquashCycles                 2080138                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate                  0.239183                       # Number of branch fetches per cycle
+system.cpu.fetch.branchRate                  0.239181                       # Number of branch fetches per cycle
 system.cpu.fetch.icacheStallCycles           19195045                       # Number of cycles fetch is stalled on an Icache miss
 system.cpu.fetch.predictedBranches           14724343                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        2.057366                       # Number of inst fetches per cycle
+system.cpu.fetch.rate                        2.057346                       # Number of inst fetches per cycle
 system.cpu.fetch.rateDist.start_dist                           # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist.samples            81203929                      
 system.cpu.fetch.rateDist.min_value                 0                      
@@ -236,10 +236,10 @@ system.cpu.icache.tagsinuse               1547.586704                       # Cy
 system.cpu.icache.total_refs                 19184655                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                          554685                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles                             795                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.iew.EXEC:branches                 12760718                       # Number of branches executed
 system.cpu.iew.EXEC:nop                      12520368                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     1.249722                       # Inst execution rate
+system.cpu.iew.EXEC:rate                     1.249709                       # Inst execution rate
 system.cpu.iew.EXEC:refs                     31851627                       # number of memory reference insts executed
 system.cpu.iew.EXEC:stores                    7184817                       # Number of stores executed
 system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
@@ -249,7 +249,7 @@ system.cpu.iew.WB:fanout                     0.723301                       # av
 system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.iew.WB:producers                  65598879                       # num instructions producing a value
-system.cpu.iew.WB:rate                       1.226153                       # insts written-back per cycle
+system.cpu.iew.WB:rate                       1.226141                       # insts written-back per cycle
 system.cpu.iew.WB:sent                      100495413                       # cumulative count of insts sent to commit
 system.cpu.iew.branchMispredicts              2106580                       # Number of branch mispredicts detected at execute
 system.cpu.iew.iewBlockCycles                  285272                       # Number of cycles IEW is blocking
@@ -279,8 +279,8 @@ system.cpu.iew.lsq.thread.0.squashedStores      4054272                       #
 system.cpu.iew.memOrderViolationEvents         250644                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect       202889                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect        1903691                       # Number of branches that were predicted taken incorrectly
-system.cpu.ipc                               1.036646                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.036646                       # IPC: Total IPC of All Threads
+system.cpu.ipc                               1.036636                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.036636                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0               103670386                       # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0.start_dist
                       No_OpClass            7      0.00%            # Type of FU issued
@@ -331,7 +331,7 @@ system.cpu.iq.ISSUE:issued_per_cycle.min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle.max_value            8                      
 system.cpu.iq.ISSUE:issued_per_cycle.end_dist
 
-system.cpu.iq.ISSUE:rate                     1.276667                       # Inst issue rate
+system.cpu.iq.ISSUE:rate                     1.276655                       # Inst issue rate
 system.cpu.iq.iqInstsAdded                  134823640                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                 103670386                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded                 429                       # Number of non-speculative instructions added to the IQ
@@ -428,7 +428,7 @@ system.cpu.l2cache.tagsinuse              2248.754865                       # Cy
 system.cpu.l2cache.total_refs                    7137                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.numCycles                         81203929                       # number of cpu cycles simulated
+system.cpu.numCycles                         81204724                       # number of cpu cycles simulated
 system.cpu.rename.RENAME:BlockCycles          1670922                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps       68427361                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IQFullEvents         1021107                       # Number of times rename has blocked due to IQ full

tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt

@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1574277                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 186464                       # Number of bytes of host memory used
-host_seconds                                    58.38                       # Real time elapsed on the host
-host_tick_rate                             2031398471                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1354641                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 204632                       # Number of bytes of host memory used
+host_seconds                                    67.84                       # Real time elapsed on the host
+host_tick_rate                             1747991543                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    91903056                       # Number of instructions simulated
 sim_seconds                                  0.118590                       # Number of seconds simulated
@@ -245,7 +245,7 @@ system.cpu.l2cache.total_refs                    5916                       # To
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                     118589630000                       # number of cpu cycles simulated
+system.cpu.numCycles                        237179260                       # number of cpu cycles simulated
 system.cpu.num_insts                         91903056                       # Number of instructions executed
 system.cpu.num_refs                          26537141                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls             389                       # Number of system calls

tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr

@@ -1,7 +1,3 @@
-warn: More than two loadable segments in ELF object.
-warn: Ignoring segment @ 0x11e394 length 0x10.
-warn: More than two loadable segments in ELF object.
-warn: Ignoring segment @ 0x0 length 0x0.
 warn: Entering event queue @ 0.  Starting simulation...
 warn: Ignoring request to flush register windows.
 warn: Increasing stack size by one page.

tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt

@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1002711                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 188412                       # Number of bytes of host memory used
-host_seconds                                   192.91                       # Real time elapsed on the host
-host_tick_rate                             1401662479                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 958305                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 206472                       # Number of bytes of host memory used
+host_seconds                                   201.85                       # Real time elapsed on the host
+host_tick_rate                             1339588721                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   193435005                       # Number of instructions simulated
 sim_seconds                                  0.270398                       # Number of seconds simulated
@@ -239,7 +239,7 @@ system.cpu.l2cache.total_refs                    8679                       # To
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                     270397899000                       # number of cpu cycles simulated
+system.cpu.numCycles                        540795798                       # number of cpu cycles simulated
 system.cpu.num_insts                        193435005                       # Number of instructions executed
 system.cpu.num_refs                          76733003                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls             396                       # Number of system calls

tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr

@@ -1,7 +1,3 @@
-warn: More than two loadable segments in ELF object.
-warn: Ignoring segment @ 0x11e394 length 0x10.
-warn: More than two loadable segments in ELF object.
-warn: Ignoring segment @ 0x0 length 0x0.
 warn: Entering event queue @ 0.  Starting simulation...
 warn: Ignoring request to flush register windows.
 warn: Increasing stack size by one page.

tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt

@@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect                    409                       # Nu
 global.BPredUnit.condPredicted                   1184                       # Number of conditional branches predicted
 global.BPredUnit.lookups                         2029                       # Number of BP lookups
 global.BPredUnit.usedRAS                          277                       # Number of times the RAS was used to get a target.
-host_inst_rate                                   9351                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 180452                       # Number of bytes of host memory used
-host_seconds                                     0.60                       # Real time elapsed on the host
-host_tick_rate                                7988790                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  84357                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 197344                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
+host_tick_rate                               71887995                       # Simulator tick rate (ticks/s)
 memdepunit.memDep.conflictingLoads                 23                       # Number of conflicting loads.
 memdepunit.memDep.conflictingStores               124                       # Number of conflicting stores.
 memdepunit.memDep.insertedLoads                  2030                       # Number of loads inserted to the mem dependence unit.
@@ -49,8 +49,8 @@ system.cpu.commit.commitNonSpecStalls              17                       # Th
 system.cpu.commit.commitSquashedInsts            4234                       # The number of squashed insts skipped by commit
 system.cpu.committedInsts                        5623                       # Number of Instructions Simulated
 system.cpu.committedInsts_total                  5623                       # Number of Instructions Simulated
-system.cpu.cpi                               1.680420                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.680420                       # CPI: Total CPI of All Threads
+system.cpu.cpi                               1.709586                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.709586                       # CPI: Total CPI of All Threads
 system.cpu.dcache.ReadReq_accesses               1535                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_avg_miss_latency 10443.877551                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency  6357.142857                       # average ReadReq mshr miss latency
@@ -152,10 +152,10 @@ system.cpu.fetch.Cycles                          3746                       # Nu
 system.cpu.fetch.IcacheSquashes                   226                       # Number of outstanding Icache misses that were squashed
 system.cpu.fetch.Insts                          12519                       # Number of instructions fetch has processed
 system.cpu.fetch.SquashCycles                     469                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate                  0.214732                       # Number of branch fetches per cycle
+system.cpu.fetch.branchRate                  0.211068                       # Number of branch fetches per cycle
 system.cpu.fetch.icacheStallCycles               1542                       # Number of cycles fetch is stalled on an Icache miss
 system.cpu.fetch.predictedBranches                839                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        1.324902                       # Number of inst fetches per cycle
+system.cpu.fetch.rate                        1.302299                       # Number of inst fetches per cycle
 system.cpu.fetch.rateDist.start_dist                           # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist.samples                9449                      
 system.cpu.fetch.rateDist.min_value                 0                      
@@ -234,10 +234,10 @@ system.cpu.icache.tagsinuse                164.253671                       # Cy
 system.cpu.icache.total_refs                     1211                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                          110443                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles                             164                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.iew.EXEC:branches                     1199                       # Number of branches executed
 system.cpu.iew.EXEC:nop                            72                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     0.848450                       # Inst execution rate
+system.cpu.iew.EXEC:rate                     0.833975                       # Inst execution rate
 system.cpu.iew.EXEC:refs                         2660                       # number of memory reference insts executed
 system.cpu.iew.EXEC:stores                       1006                       # Number of stores executed
 system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
@@ -247,7 +247,7 @@ system.cpu.iew.WB:fanout                     0.742905                       # av
 system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.iew.WB:producers                      4031                       # num instructions producing a value
-system.cpu.iew.WB:rate                       0.811091                       # insts written-back per cycle
+system.cpu.iew.WB:rate                       0.797254                       # insts written-back per cycle
 system.cpu.iew.WB:sent                           7781                       # cumulative count of insts sent to commit
 system.cpu.iew.branchMispredicts                  401                       # Number of branch mispredicts detected at execute
 system.cpu.iew.iewBlockCycles                       4                       # Number of cycles IEW is blocking
@@ -277,8 +277,8 @@ system.cpu.iew.lsq.thread.0.squashedStores          424                       #
 system.cpu.iew.memOrderViolationEvents             68                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect          295                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect            106                       # Number of branches that were predicted taken incorrectly
-system.cpu.ipc                               0.595089                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.595089                       # IPC: Total IPC of All Threads
+system.cpu.ipc                               0.584937                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.584937                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0                    8383                       # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0.start_dist
                       No_OpClass            2      0.02%            # Type of FU issued
@@ -329,7 +329,7 @@ system.cpu.iq.ISSUE:issued_per_cycle.min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle.max_value            8                      
 system.cpu.iq.ISSUE:issued_per_cycle.end_dist
 
-system.cpu.iq.ISSUE:rate                     0.887184                       # Inst issue rate
+system.cpu.iq.ISSUE:rate                     0.872048                       # Inst issue rate
 system.cpu.iq.iqInstsAdded                       9901                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                      8383                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded                  23                       # Number of non-speculative instructions added to the IQ
@@ -421,7 +421,7 @@ system.cpu.l2cache.tagsinuse               218.025629                       # Cy
 system.cpu.l2cache.total_refs                       1                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.numCycles                             9449                       # number of cpu cycles simulated
+system.cpu.numCycles                             9613                       # number of cpu cycles simulated
 system.cpu.rename.RENAME:BlockCycles               50                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps           4051                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IdleCycles              6291                       # Number of cycles rename is idle

tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt

@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 243703                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 179944                       # Number of bytes of host memory used
+host_inst_rate                                 341217                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 196644                       # Number of bytes of host memory used
 host_seconds                                     0.02                       # Real time elapsed on the host
-host_tick_rate                              781539770                       # Simulator tick rate (ticks/s)
+host_tick_rate                             1094407052                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5641                       # Number of instructions simulated
 sim_seconds                                  0.000018                       # Number of seconds simulated
@@ -240,7 +240,7 @@ system.cpu.l2cache.total_refs                       1                       # To
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                         18374000                       # number of cpu cycles simulated
+system.cpu.numCycles                            36748                       # number of cpu cycles simulated
 system.cpu.num_insts                             5641                       # Number of instructions executed
 system.cpu.num_refs                              1801                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              17                       # Number of system calls

tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt

@@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect                    213                       # Nu
 global.BPredUnit.condPredicted                    401                       # Number of conditional branches predicted
 global.BPredUnit.lookups                          824                       # Number of BP lookups
 global.BPredUnit.usedRAS                          163                       # Number of times the RAS was used to get a target.
-host_inst_rate                                  31893                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 179460                       # Number of bytes of host memory used
-host_seconds                                     0.08                       # Real time elapsed on the host
-host_tick_rate                               32096529                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  66708                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 196356                       # Number of bytes of host memory used
+host_seconds                                     0.04                       # Real time elapsed on the host
+host_tick_rate                               66966767                       # Simulator tick rate (ticks/s)
 memdepunit.memDep.conflictingLoads                  7                       # Number of conflicting loads.
 memdepunit.memDep.conflictingStores                 7                       # Number of conflicting stores.
 memdepunit.memDep.insertedLoads                   698                       # Number of loads inserted to the mem dependence unit.
@@ -49,8 +49,8 @@ system.cpu.commit.commitNonSpecStalls               4                       # Th
 system.cpu.commit.commitSquashedInsts            1380                       # The number of squashed insts skipped by commit
 system.cpu.committedInsts                        2387                       # Number of Instructions Simulated
 system.cpu.committedInsts_total                  2387                       # Number of Instructions Simulated
-system.cpu.cpi                               1.984080                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.984080                       # CPI: Total CPI of All Threads
+system.cpu.cpi                               2.019690                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.019690                       # CPI: Total CPI of All Threads
 system.cpu.dcache.ReadReq_accesses                528                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_avg_miss_latency  8639.344262                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency  5655.737705                       # average ReadReq mshr miss latency
@@ -152,10 +152,10 @@ system.cpu.fetch.Cycles                          1626                       # Nu
 system.cpu.fetch.IcacheSquashes                   101                       # Number of outstanding Icache misses that were squashed
 system.cpu.fetch.Insts                           5268                       # Number of instructions fetch has processed
 system.cpu.fetch.SquashCycles                     242                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate                  0.173986                       # Number of branch fetches per cycle
+system.cpu.fetch.branchRate                  0.170919                       # Number of branch fetches per cycle
 system.cpu.fetch.icacheStallCycles                707                       # Number of cycles fetch is stalled on an Icache miss
 system.cpu.fetch.predictedBranches                319                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        1.112331                       # Number of inst fetches per cycle
+system.cpu.fetch.rate                        1.092719                       # Number of inst fetches per cycle
 system.cpu.fetch.rateDist.start_dist                           # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist.samples                4736                      
 system.cpu.fetch.rateDist.min_value                 0                      
@@ -234,10 +234,10 @@ system.cpu.icache.tagsinuse                 92.900452                       # Cy
 system.cpu.icache.total_refs                      510                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                           56472                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles                              85                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.iew.EXEC:branches                      538                       # Number of branches executed
 system.cpu.iew.EXEC:nop                           274                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     0.670608                       # Inst execution rate
+system.cpu.iew.EXEC:rate                     0.658784                       # Inst execution rate
 system.cpu.iew.EXEC:refs                          934                       # number of memory reference insts executed
 system.cpu.iew.EXEC:stores                        356                       # Number of stores executed
 system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
@@ -247,7 +247,7 @@ system.cpu.iew.WB:fanout                     0.794497                       # av
 system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.iew.WB:producers                      1415                       # num instructions producing a value
-system.cpu.iew.WB:rate                       0.651182                       # insts written-back per cycle
+system.cpu.iew.WB:rate                       0.639701                       # insts written-back per cycle
 system.cpu.iew.WB:sent                           3123                       # cumulative count of insts sent to commit
 system.cpu.iew.branchMispredicts                  149                       # Number of branch mispredicts detected at execute
 system.cpu.iew.iewBlockCycles                       0                       # Number of cycles IEW is blocking
@@ -277,8 +277,8 @@ system.cpu.iew.lsq.thread.0.squashedStores          118                       #
 system.cpu.iew.memOrderViolationEvents             11                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect           97                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect             52                       # Number of branches that were predicted taken incorrectly
-system.cpu.ipc                               0.504012                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.504012                       # IPC: Total IPC of All Threads
+system.cpu.ipc                               0.495125                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.495125                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0                    3281                       # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0.start_dist
                       No_OpClass            0      0.00%            # Type of FU issued
@@ -329,7 +329,7 @@ system.cpu.iq.ISSUE:issued_per_cycle.min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle.max_value            8                      
 system.cpu.iq.ISSUE:issued_per_cycle.end_dist
 
-system.cpu.iq.ISSUE:rate                     0.692779                       # Inst issue rate
+system.cpu.iq.ISSUE:rate                     0.680564                       # Inst issue rate
 system.cpu.iq.iqInstsAdded                       3776                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                      3281                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded                   6                       # Number of non-speculative instructions added to the IQ
@@ -420,7 +420,7 @@ system.cpu.l2cache.tagsinuse               115.687599                       # Cy
 system.cpu.l2cache.total_refs                       0                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.numCycles                             4736                       # number of cpu cycles simulated
+system.cpu.numCycles                             4821                       # number of cpu cycles simulated
 system.cpu.rename.RENAME:CommittedMaps           1768                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IdleCycles              3552                       # Number of cycles rename is idle
 system.cpu.rename.RENAME:LSQFullEvents              2                       # Number of times rename has blocked due to LSQ full

tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout

@@ -6,9 +6,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 14 2007 17:36:58
-M5 started Tue Aug 14 17:40:04 2007
-M5 executing on nacho
+M5 compiled Sep 27 2007 13:46:37
+M5 started Thu Sep 27 20:06:36 2007
+M5 executing on zeep
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic tests/run.py quick/00.hello/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 Exiting @ tick 1297500 because target called exit()

tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt

@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 123219                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 178996                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
-host_tick_rate                              443932267                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 178240                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 195696                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
+host_tick_rate                              641473527                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        2577                       # Number of instructions simulated
 sim_seconds                                  0.000009                       # Number of seconds simulated
@@ -239,7 +239,7 @@ system.cpu.l2cache.total_refs                       0                       # To
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                          9438000                       # number of cpu cycles simulated
+system.cpu.numCycles                            18876                       # number of cpu cycles simulated
 system.cpu.num_insts                             2577                       # Number of instructions executed
 system.cpu.num_refs                               717                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls               4                       # Number of system calls

tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt

@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 186969                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 180780                       # Number of bytes of host memory used
+host_inst_rate                                 192479                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 197496                       # Number of bytes of host memory used
 host_seconds                                     0.03                       # Real time elapsed on the host
-host_tick_rate                              602814418                       # Simulator tick rate (ticks/s)
+host_tick_rate                              618816195                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5656                       # Number of instructions simulated
 sim_seconds                                  0.000018                       # Number of seconds simulated
@@ -224,7 +224,7 @@ system.cpu.l2cache.total_refs                       2                       # To
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                         18463000                       # number of cpu cycles simulated
+system.cpu.numCycles                            36926                       # number of cpu cycles simulated
 system.cpu.num_insts                             5656                       # Number of instructions executed
 system.cpu.num_refs                              2055                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              13                       # Number of system calls

tests/quick/00.hello/ref/sparc/linux/simple-atomic/stderr

@@ -1,3 +1 @@
-warn: More than two loadable segments in ELF object.
-warn: Ignoring segment @ 0x0 length 0x0.
 warn: Entering event queue @ 0.  Starting simulation...

tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt

@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 198489                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 181156                       # Number of bytes of host memory used
+host_inst_rate                                 290934                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 197920                       # Number of bytes of host memory used
 host_seconds                                     0.02                       # Real time elapsed on the host
-host_tick_rate                              645076356                       # Simulator tick rate (ticks/s)
+host_tick_rate                              939694341                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        4833                       # Number of instructions simulated
 sim_seconds                                  0.000016                       # Number of seconds simulated
@@ -224,7 +224,7 @@ system.cpu.l2cache.total_refs                       3                       # To
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                         15925000                       # number of cpu cycles simulated
+system.cpu.numCycles                            31850                       # number of cpu cycles simulated
 system.cpu.num_insts                             4833                       # Number of instructions executed
 system.cpu.num_refs                              1282                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              11                       # Number of system calls

tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr

@@ -1,3 +1 @@
-warn: More than two loadable segments in ELF object.
-warn: Ignoring segment @ 0x0 length 0x0.
 warn: Entering event queue @ 0.  Starting simulation...

tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini

@@ -368,7 +368,7 @@ cwd=
 egid=100
 env=
 euid=100
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 output=cout
@@ -384,7 +384,7 @@ cwd=
 egid=100
 env=
 euid=100
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 output=cout

tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt

@@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect                   1092                       # Nu
 global.BPredUnit.condPredicted                   2350                       # Number of conditional branches predicted
 global.BPredUnit.lookups                         4075                       # Number of BP lookups
 global.BPredUnit.usedRAS                          561                       # Number of times the RAS was used to get a target.
-host_inst_rate                                  76336                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 181020                       # Number of bytes of host memory used
-host_seconds                                     0.15                       # Real time elapsed on the host
-host_tick_rate                               38800813                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  92493                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 197924                       # Number of bytes of host memory used
+host_seconds                                     0.12                       # Real time elapsed on the host
+host_tick_rate                               47019704                       # Simulator tick rate (ticks/s)
 memdepunit.memDep.conflictingLoads                 14                       # Number of conflicting loads.
 memdepunit.memDep.conflictingLoads                 12                       # Number of conflicting loads.
 memdepunit.memDep.conflictingStores                35                       # Number of conflicting stores.
@@ -68,9 +68,9 @@ system.cpu.commit.commitSquashedInsts            8053                       # Th
 system.cpu.committedInsts_0                      5623                       # Number of Instructions Simulated
 system.cpu.committedInsts_1                      5624                       # Number of Instructions Simulated
 system.cpu.committedInsts_total                 11247                       # Number of Instructions Simulated
-system.cpu.cpi_0                             2.035568                       # CPI: Cycles Per Instruction
-system.cpu.cpi_1                             2.035206                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.017694                       # CPI: Total CPI of All Threads
+system.cpu.cpi_0                             2.037169                       # CPI: Cycles Per Instruction
+system.cpu.cpi_1                             2.036807                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.018494                       # CPI: Total CPI of All Threads
 system.cpu.dcache.ReadReq_accesses               2934                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses_0             2934                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_avg_miss_latency_0 12119.897959                       # average ReadReq miss latency
@@ -244,10 +244,10 @@ system.cpu.fetch.Cycles                          7174                       # Nu
 system.cpu.fetch.IcacheSquashes                   439                       # Number of outstanding Icache misses that were squashed
 system.cpu.fetch.Insts                          24770                       # Number of instructions fetch has processed
 system.cpu.fetch.SquashCycles                    1207                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate                  0.356020                       # Number of branch fetches per cycle
+system.cpu.fetch.branchRate                  0.355740                       # Number of branch fetches per cycle
 system.cpu.fetch.icacheStallCycles               3019                       # Number of cycles fetch is stalled on an Icache miss
 system.cpu.fetch.predictedBranches               1267                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        2.164075                       # Number of inst fetches per cycle
+system.cpu.fetch.rate                        2.162375                       # Number of inst fetches per cycle
 system.cpu.fetch.rateDist.start_dist                           # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist.samples               11446                      
 system.cpu.fetch.rateDist.min_value                 0                      
@@ -391,14 +391,14 @@ system.cpu.icache.warmup_cycle                      0                       # Cy
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.icache.writebacks_0                      0                       # number of writebacks
 system.cpu.icache.writebacks_1                      0                       # number of writebacks
-system.cpu.idleCycles                            6496                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles                               9                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.iew.EXEC:branches                     2386                       # Number of branches executed
 system.cpu.iew.EXEC:branches_0                   1188                       # Number of branches executed
 system.cpu.iew.EXEC:branches_1                   1198                       # Number of branches executed
 system.cpu.iew.EXEC:nop                           127                       # number of nop insts executed
 system.cpu.iew.EXEC:nop_0                          66                       # number of nop insts executed
 system.cpu.iew.EXEC:nop_1                          61                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     1.378123                       # Inst execution rate
+system.cpu.iew.EXEC:rate                     1.377041                       # Inst execution rate
 system.cpu.iew.EXEC:refs                         5110                       # number of memory reference insts executed
 system.cpu.iew.EXEC:refs_0                       2531                       # number of memory reference insts executed
 system.cpu.iew.EXEC:refs_1                       2579                       # number of memory reference insts executed
@@ -426,9 +426,9 @@ system.cpu.iew.WB:penalized_rate_1                  0                       # fr
 system.cpu.iew.WB:producers                      7913                       # num instructions producing a value
 system.cpu.iew.WB:producers_0                    3958                       # num instructions producing a value
 system.cpu.iew.WB:producers_1                    3955                       # num instructions producing a value
-system.cpu.iew.WB:rate                       1.323170                       # insts written-back per cycle
-system.cpu.iew.WB:rate_0                     0.662590                       # insts written-back per cycle
-system.cpu.iew.WB:rate_1                     0.660580                       # insts written-back per cycle
+system.cpu.iew.WB:rate                       1.322130                       # insts written-back per cycle
+system.cpu.iew.WB:rate_0                     0.662069                       # insts written-back per cycle
+system.cpu.iew.WB:rate_1                     0.660061                       # insts written-back per cycle
 system.cpu.iew.WB:sent                          15343                       # cumulative count of insts sent to commit
 system.cpu.iew.WB:sent_0                         7675                       # cumulative count of insts sent to commit
 system.cpu.iew.WB:sent_1                         7668                       # cumulative count of insts sent to commit
@@ -472,9 +472,9 @@ system.cpu.iew.lsq.thread.1.squashedStores          328                       #
 system.cpu.iew.memOrderViolationEvents            125                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect          788                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect            203                       # Number of branches that were predicted taken incorrectly
-system.cpu.ipc_0                             0.491263                       # IPC: Instructions Per Cycle
-system.cpu.ipc_1                             0.491351                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.982614                       # IPC: Total IPC of All Threads
+system.cpu.ipc_0                             0.490877                       # IPC: Instructions Per Cycle
+system.cpu.ipc_1                             0.490965                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.981842                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0                    8365                       # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0.start_dist
                       No_OpClass            2      0.02%            # Type of FU issued
@@ -563,7 +563,7 @@ system.cpu.iq.ISSUE:issued_per_cycle.min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle.max_value            8                      
 system.cpu.iq.ISSUE:issued_per_cycle.end_dist
 
-system.cpu.iq.ISSUE:rate                     1.458763                       # Inst issue rate
+system.cpu.iq.ISSUE:rate                     1.457617                       # Inst issue rate
 system.cpu.iq.iqInstsAdded                      19328                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                     16697                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded                  46                       # Number of non-speculative instructions added to the IQ
@@ -729,7 +729,7 @@ system.cpu.l2cache.warmup_cycle                     0                       # Cy
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.l2cache.writebacks_0                     0                       # number of writebacks
 system.cpu.l2cache.writebacks_1                     0                       # number of writebacks
-system.cpu.numCycles                            11446                       # number of cpu cycles simulated
+system.cpu.numCycles                            11455                       # number of cpu cycles simulated
 system.cpu.rename.RENAME:BlockCycles              641                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps           8102                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IdleCycles             15417                       # Number of cycles rename is idle

tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt

@@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect                   2012                       # Nu
 global.BPredUnit.condPredicted                   7659                       # Number of conditional branches predicted
 global.BPredUnit.lookups                         7659                       # Number of BP lookups
 global.BPredUnit.usedRAS                            0                       # Number of times the RAS was used to get a target.
-host_inst_rate                                   7502                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 186228                       # Number of bytes of host memory used
-host_seconds                                     1.39                       # Real time elapsed on the host
-host_tick_rate                               10800438                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  64485                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 198296                       # Number of bytes of host memory used
+host_seconds                                     0.16                       # Real time elapsed on the host
+host_tick_rate                               92733729                       # Simulator tick rate (ticks/s)
 memdepunit.memDep.conflictingLoads                 15                       # Number of conflicting loads.
 memdepunit.memDep.conflictingStores                 0                       # Number of conflicting stores.
 memdepunit.memDep.insertedLoads                  3077                       # Number of loads inserted to the mem dependence unit.
@@ -49,8 +49,8 @@ system.cpu.commit.commitNonSpecStalls             329                       # Th
 system.cpu.commit.commitSquashedInsts           13198                       # The number of squashed insts skipped by commit
 system.cpu.committedInsts                       10411                       # Number of Instructions Simulated
 system.cpu.committedInsts_total                 10411                       # Number of Instructions Simulated
-system.cpu.cpi                               2.871770                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.871770                       # CPI: Total CPI of All Threads
+system.cpu.cpi                               2.879839                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.879839                       # CPI: Total CPI of All Threads
 system.cpu.dcache.ReadReq_accesses               2274                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_avg_miss_latency  9734.848485                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency  5560.606061                       # average ReadReq mshr miss latency
@@ -139,10 +139,10 @@ system.cpu.fetch.Cycles                         16219                       # Nu
 system.cpu.fetch.IcacheSquashes                   589                       # Number of outstanding Icache misses that were squashed
 system.cpu.fetch.Insts                          42202                       # Number of instructions fetch has processed
 system.cpu.fetch.SquashCycles                    2099                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate                  0.256171                       # Number of branch fetches per cycle
+system.cpu.fetch.branchRate                  0.255453                       # Number of branch fetches per cycle
 system.cpu.fetch.icacheStallCycles               4927                       # Number of cycles fetch is stalled on an Icache miss
 system.cpu.fetch.predictedBranches               2711                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        1.411533                       # Number of inst fetches per cycle
+system.cpu.fetch.rate                        1.407578                       # Number of inst fetches per cycle
 system.cpu.fetch.rateDist.start_dist                           # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist.samples               29898                      
 system.cpu.fetch.rateDist.min_value                 0                      
@@ -221,10 +221,10 @@ system.cpu.icache.tagsinuse                233.477311                       # Cy
 system.cpu.icache.total_refs                     4537                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                           51980                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles                              84                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.iew.EXEC:branches                     3086                       # Number of branches executed
 system.cpu.iew.EXEC:nop                          1794                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     0.576995                       # Inst execution rate
+system.cpu.iew.EXEC:rate                     0.575379                       # Inst execution rate
 system.cpu.iew.EXEC:refs                         4543                       # number of memory reference insts executed
 system.cpu.iew.EXEC:stores                       2116                       # Number of stores executed
 system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
@@ -234,7 +234,7 @@ system.cpu.iew.WB:fanout                     0.827620                       # av
 system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.iew.WB:producers                      7605                       # num instructions producing a value
-system.cpu.iew.WB:rate                       0.555823                       # insts written-back per cycle
+system.cpu.iew.WB:rate                       0.554266                       # insts written-back per cycle
 system.cpu.iew.WB:sent                          16830                       # cumulative count of insts sent to commit
 system.cpu.iew.branchMispredicts                 2216                       # Number of branch mispredicts detected at execute
 system.cpu.iew.iewBlockCycles                       0                       # Number of cycles IEW is blocking
@@ -264,8 +264,8 @@ system.cpu.iew.lsq.thread.0.squashedStores         1658                       #
 system.cpu.iew.memOrderViolationEvents             57                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect          695                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect           1521                       # Number of branches that were predicted taken incorrectly
-system.cpu.ipc                               0.348217                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.348217                       # IPC: Total IPC of All Threads
+system.cpu.ipc                               0.347242                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.347242                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0                   20089                       # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0.start_dist
                       No_OpClass            0      0.00%            # Type of FU issued
@@ -316,7 +316,7 @@ system.cpu.iq.ISSUE:issued_per_cycle.min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle.max_value            8                      
 system.cpu.iq.ISSUE:issued_per_cycle.end_dist
 
-system.cpu.iq.ISSUE:rate                     0.671918                       # Inst issue rate
+system.cpu.iq.ISSUE:rate                     0.670035                       # Inst issue rate
 system.cpu.iq.iqInstsAdded                      21924                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                     20089                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded                 612                       # Number of non-speculative instructions added to the IQ
@@ -404,7 +404,7 @@ system.cpu.l2cache.tagsinuse               259.708792                       # Cy
 system.cpu.l2cache.total_refs                       4                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.numCycles                            29898                       # number of cpu cycles simulated
+system.cpu.numCycles                            29982                       # number of cpu cycles simulated
 system.cpu.rename.RENAME:CommittedMaps           9868                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IdleCycles             14192                       # Number of cycles rename is idle
 system.cpu.rename.RENAME:RenameLookups          51924                       # Number of register rename lookups that rename has made

tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr

@@ -1,3 +1 @@
-warn: More than two loadable segments in ELF object.
-warn: Ignoring segment @ 0x0 length 0x0.
 warn: Entering event queue @ 0.  Starting simulation...

tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr

@@ -1,3 +1 @@
-warn: More than two loadable segments in ELF object.
-warn: Ignoring segment @ 0x0 length 0x0.
 warn: Entering event queue @ 0.  Starting simulation...

tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt

@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 343655                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 180816                       # Number of bytes of host memory used
-host_seconds                                     0.03                       # Real time elapsed on the host
-host_tick_rate                              753768067                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 472716                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 197656                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
+host_tick_rate                             1037354119                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                       10976                       # Number of instructions simulated
 sim_seconds                                  0.000024                       # Number of seconds simulated
@@ -226,7 +226,7 @@ system.cpu.l2cache.total_refs                       2                       # To
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                         24355000                       # number of cpu cycles simulated
+system.cpu.numCycles                            48710                       # number of cpu cycles simulated
 system.cpu.num_insts                            10976                       # Number of instructions executed
 system.cpu.num_refs                              2770                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls               8                       # Number of system calls

tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr

@@ -1,3 +1 @@
-warn: More than two loadable segments in ELF object.
-warn: Ignoring segment @ 0x0 length 0x0.
 warn: Entering event queue @ 0.  Starting simulation...

tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini

@@ -460,7 +460,7 @@ pio=system.toL2Bus.default
 
 [system.tsunami]
 type=Tsunami
-children=cchip console etherint ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
+children=cchip console ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
 intrctrl=system.intrctrl
 system=system
 
@@ -484,48 +484,8 @@ sim_console=system.sim_console
 system=system
 pio=system.iobus.port[25]
 
-[system.tsunami.etherint]
-type=NSGigEInt
-device=system.tsunami.ethernet
-peer=Null
-
 [system.tsunami.ethernet]
 type=NSGigE
-children=configdata
-clock=0
-config_latency=20000
-configdata=system.tsunami.ethernet.configdata
-dma_data_free=false
-dma_desc_free=false
-dma_no_allocate=true
-dma_read_delay=0
-dma_read_factor=0
-dma_write_delay=0
-dma_write_factor=0
-hardware_address=00:90:00:00:00:01
-intr_delay=10000000
-max_backoff_delay=10000000
-min_backoff_delay=4000
-pci_bus=0
-pci_dev=1
-pci_func=0
-pio_latency=1000
-platform=system.tsunami
-rss=false
-rx_delay=1000000
-rx_fifo_size=524288
-rx_filter=true
-rx_thread=false
-system=system
-tx_delay=1000000
-tx_fifo_size=524288
-tx_thread=false
-config=system.iobus.port[29]
-dma=system.iobus.port[30]
-pio=system.iobus.port[27]
-
-[system.tsunami.ethernet.configdata]
-type=PciConfigData
 BAR0=1
 BAR0Size=256
 BAR1=0
@@ -558,6 +518,36 @@ SubClassCode=0
 SubsystemID=0
 SubsystemVendorID=0
 VendorID=4107
+clock=0
+config_latency=20000
+dma_data_free=false
+dma_desc_free=false
+dma_no_allocate=true
+dma_read_delay=0
+dma_read_factor=0
+dma_write_delay=0
+dma_write_factor=0
+hardware_address=00:90:00:00:00:01
+intr_delay=10000000
+max_backoff_delay=10000000
+min_backoff_delay=4000
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=1000
+platform=system.tsunami
+rss=false
+rx_delay=1000000
+rx_fifo_size=524288
+rx_filter=true
+rx_thread=false
+system=system
+tx_delay=1000000
+tx_fifo_size=524288
+tx_thread=false
+config=system.iobus.port[29]
+dma=system.iobus.port[30]
+pio=system.iobus.port[27]
 
 [system.tsunami.fake_OROM]
 type=IsaFake
@@ -874,24 +864,6 @@ pio=system.iobus.port[22]
 
 [system.tsunami.ide]
 type=IdeController
-children=configdata
-config_latency=20000
-configdata=system.tsunami.ide.configdata
-disks=system.disk0 system.disk2
-max_backoff_delay=10000000
-min_backoff_delay=4000
-pci_bus=0
-pci_dev=0
-pci_func=0
-pio_latency=1000
-platform=system.tsunami
-system=system
-config=system.iobus.port[31]
-dma=system.iobus.port[32]
-pio=system.iobus.port[26]
-
-[system.tsunami.ide.configdata]
-type=PciConfigData
 BAR0=1
 BAR0Size=8
 BAR1=1
@@ -924,6 +896,19 @@ SubClassCode=1
 SubsystemID=0
 SubsystemVendorID=0
 VendorID=32902
+config_latency=20000
+disks=system.disk0 system.disk2
+max_backoff_delay=10000000
+min_backoff_delay=4000
+pci_bus=0
+pci_dev=0
+pci_func=0
+pio_latency=1000
+platform=system.tsunami
+system=system
+config=system.iobus.port[31]
+dma=system.iobus.port[32]
+pio=system.iobus.port[26]
 
 [system.tsunami.io]
 type=TsunamiIO

tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt

@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2322076                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 309268                       # Number of bytes of host memory used
-host_seconds                                    27.18                       # Real time elapsed on the host
-host_tick_rate                            68811889767                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2182924                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 325992                       # Number of bytes of host memory used
+host_seconds                                    28.91                       # Real time elapsed on the host
+host_tick_rate                            64688316336                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    63114079                       # Number of instructions simulated
 sim_seconds                                  1.870335                       # Number of seconds simulated
@@ -239,7 +239,7 @@ system.cpu0.kern.syscall_132                        2      0.88%     98.23% # nu
 system.cpu0.kern.syscall_144                        2      0.88%     99.12% # number of syscalls executed
 system.cpu0.kern.syscall_147                        2      0.88%    100.00% # number of syscalls executed
 system.cpu0.not_idle_fraction                0.015290                       # Percentage of non-idle cycles
-system.cpu0.numCycles                        57193784                       # number of cpu cycles simulated
+system.cpu0.numCycles                      3740670091                       # number of cpu cycles simulated
 system.cpu0.num_insts                        57182116                       # Number of instructions executed
 system.cpu0.num_refs                         15322419                       # Number of memory references
 system.cpu1.dcache.LoadLockedReq_accesses        16418                       # number of LoadLockedReq accesses(hits+misses)
@@ -456,7 +456,7 @@ system.cpu1.kern.syscall_74                         8      8.00%     97.00% # nu
 system.cpu1.kern.syscall_90                         1      1.00%     98.00% # number of syscalls executed
 system.cpu1.kern.syscall_132                        2      2.00%    100.00% # number of syscalls executed
 system.cpu1.not_idle_fraction                0.001587                       # Percentage of non-idle cycles
-system.cpu1.numCycles                         5937367                       # number of cpu cycles simulated
+system.cpu1.numCycles                      3740248039                       # number of cpu cycles simulated
 system.cpu1.num_insts                         5931963                       # Number of instructions executed
 system.cpu1.num_refs                          1926645                       # Number of memory references
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).

tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini

@@ -350,7 +350,7 @@ pio=system.toL2Bus.default
 
 [system.tsunami]
 type=Tsunami
-children=cchip console etherint ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
+children=cchip console ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
 intrctrl=system.intrctrl
 system=system
 
@@ -374,48 +374,8 @@ sim_console=system.sim_console
 system=system
 pio=system.iobus.port[25]
 
-[system.tsunami.etherint]
-type=NSGigEInt
-device=system.tsunami.ethernet
-peer=Null
-
 [system.tsunami.ethernet]
 type=NSGigE
-children=configdata
-clock=0
-config_latency=20000
-configdata=system.tsunami.ethernet.configdata
-dma_data_free=false
-dma_desc_free=false
-dma_no_allocate=true
-dma_read_delay=0
-dma_read_factor=0
-dma_write_delay=0
-dma_write_factor=0
-hardware_address=00:90:00:00:00:01
-intr_delay=10000000
-max_backoff_delay=10000000
-min_backoff_delay=4000
-pci_bus=0
-pci_dev=1
-pci_func=0
-pio_latency=1000
-platform=system.tsunami
-rss=false
-rx_delay=1000000
-rx_fifo_size=524288
-rx_filter=true
-rx_thread=false
-system=system
-tx_delay=1000000
-tx_fifo_size=524288
-tx_thread=false
-config=system.iobus.port[29]
-dma=system.iobus.port[30]
-pio=system.iobus.port[27]
-
-[system.tsunami.ethernet.configdata]
-type=PciConfigData
 BAR0=1
 BAR0Size=256
 BAR1=0
@@ -448,6 +408,36 @@ SubClassCode=0
 SubsystemID=0
 SubsystemVendorID=0
 VendorID=4107
+clock=0
+config_latency=20000
+dma_data_free=false
+dma_desc_free=false
+dma_no_allocate=true
+dma_read_delay=0
+dma_read_factor=0
+dma_write_delay=0
+dma_write_factor=0
+hardware_address=00:90:00:00:00:01
+intr_delay=10000000
+max_backoff_delay=10000000
+min_backoff_delay=4000
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=1000
+platform=system.tsunami
+rss=false
+rx_delay=1000000
+rx_fifo_size=524288
+rx_filter=true
+rx_thread=false
+system=system
+tx_delay=1000000
+tx_fifo_size=524288
+tx_thread=false
+config=system.iobus.port[29]
+dma=system.iobus.port[30]
+pio=system.iobus.port[27]
 
 [system.tsunami.fake_OROM]
 type=IsaFake
@@ -764,24 +754,6 @@ pio=system.iobus.port[22]
 
 [system.tsunami.ide]
 type=IdeController
-children=configdata
-config_latency=20000
-configdata=system.tsunami.ide.configdata
-disks=system.disk0 system.disk2
-max_backoff_delay=10000000
-min_backoff_delay=4000
-pci_bus=0
-pci_dev=0
-pci_func=0
-pio_latency=1000
-platform=system.tsunami
-system=system
-config=system.iobus.port[31]
-dma=system.iobus.port[32]
-pio=system.iobus.port[26]
-
-[system.tsunami.ide.configdata]
-type=PciConfigData
 BAR0=1
 BAR0Size=8
 BAR1=1
@@ -814,6 +786,19 @@ SubClassCode=1
 SubsystemID=0
 SubsystemVendorID=0
 VendorID=32902
+config_latency=20000
+disks=system.disk0 system.disk2
+max_backoff_delay=10000000
+min_backoff_delay=4000
+pci_bus=0
+pci_dev=0
+pci_func=0
+pio_latency=1000
+platform=system.tsunami
+system=system
+config=system.iobus.port[31]
+dma=system.iobus.port[32]
+pio=system.iobus.port[26]
 
 [system.tsunami.io]
 type=TsunamiIO

tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt

@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2191272                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 308228                       # Number of bytes of host memory used
-host_seconds                                    27.38                       # Real time elapsed on the host
-host_tick_rate                            66777888282                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2454439                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 324968                       # Number of bytes of host memory used
+host_seconds                                    24.44                       # Real time elapsed on the host
+host_tick_rate                            74797977378                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    59995479                       # Number of instructions simulated
 sim_seconds                                  1.828355                       # Number of seconds simulated
@@ -234,7 +234,7 @@ system.cpu.kern.syscall_132                         4      1.23%     98.77% # nu
 system.cpu.kern.syscall_144                         2      0.61%     99.39% # number of syscalls executed
 system.cpu.kern.syscall_147                         2      0.61%    100.00% # number of syscalls executed
 system.cpu.not_idle_fraction                 0.016412                       # Percentage of non-idle cycles
-system.cpu.numCycles                         60012507                       # number of cpu cycles simulated
+system.cpu.numCycles                       3656710843                       # number of cpu cycles simulated
 system.cpu.num_insts                         59995479                       # Number of instructions executed
 system.cpu.num_refs                          16302129                       # Number of memory references
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).

tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini

@@ -456,7 +456,7 @@ pio=system.toL2Bus.default
 
 [system.tsunami]
 type=Tsunami
-children=cchip console etherint ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
+children=cchip console ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
 intrctrl=system.intrctrl
 system=system
 
@@ -480,48 +480,8 @@ sim_console=system.sim_console
 system=system
 pio=system.iobus.port[25]
 
-[system.tsunami.etherint]
-type=NSGigEInt
-device=system.tsunami.ethernet
-peer=Null
-
 [system.tsunami.ethernet]
 type=NSGigE
-children=configdata
-clock=0
-config_latency=20000
-configdata=system.tsunami.ethernet.configdata
-dma_data_free=false
-dma_desc_free=false
-dma_no_allocate=true
-dma_read_delay=0
-dma_read_factor=0
-dma_write_delay=0
-dma_write_factor=0
-hardware_address=00:90:00:00:00:01
-intr_delay=10000000
-max_backoff_delay=10000000
-min_backoff_delay=4000
-pci_bus=0
-pci_dev=1
-pci_func=0
-pio_latency=1000
-platform=system.tsunami
-rss=false
-rx_delay=1000000
-rx_fifo_size=524288
-rx_filter=true
-rx_thread=false
-system=system
-tx_delay=1000000
-tx_fifo_size=524288
-tx_thread=false
-config=system.iobus.port[29]
-dma=system.iobus.port[30]
-pio=system.iobus.port[27]
-
-[system.tsunami.ethernet.configdata]
-type=PciConfigData
 BAR0=1
 BAR0Size=256
 BAR1=0
@@ -554,6 +514,36 @@ SubClassCode=0
 SubsystemID=0
 SubsystemVendorID=0
 VendorID=4107
+clock=0
+config_latency=20000
+dma_data_free=false
+dma_desc_free=false
+dma_no_allocate=true
+dma_read_delay=0
+dma_read_factor=0
+dma_write_delay=0
+dma_write_factor=0
+hardware_address=00:90:00:00:00:01
+intr_delay=10000000
+max_backoff_delay=10000000
+min_backoff_delay=4000
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=1000
+platform=system.tsunami
+rss=false
+rx_delay=1000000
+rx_fifo_size=524288
+rx_filter=true
+rx_thread=false
+system=system
+tx_delay=1000000
+tx_fifo_size=524288
+tx_thread=false
+config=system.iobus.port[29]
+dma=system.iobus.port[30]
+pio=system.iobus.port[27]
 
 [system.tsunami.fake_OROM]
 type=IsaFake
@@ -870,24 +860,6 @@ pio=system.iobus.port[22]
 
 [system.tsunami.ide]
 type=IdeController
-children=configdata
-config_latency=20000
-configdata=system.tsunami.ide.configdata
-disks=system.disk0 system.disk2
-max_backoff_delay=10000000
-min_backoff_delay=4000
-pci_bus=0
-pci_dev=0
-pci_func=0
-pio_latency=1000
-platform=system.tsunami
-system=system
-config=system.iobus.port[31]
-dma=system.iobus.port[32]
-pio=system.iobus.port[26]
-
-[system.tsunami.ide.configdata]
-type=PciConfigData
 BAR0=1
 BAR0Size=8
 BAR1=1
@@ -920,6 +892,19 @@ SubClassCode=1
 SubsystemID=0
 SubsystemVendorID=0
 VendorID=32902
+config_latency=20000
+disks=system.disk0 system.disk2
+max_backoff_delay=10000000
+min_backoff_delay=4000
+pci_bus=0
+pci_dev=0
+pci_func=0
+pio_latency=1000
+platform=system.tsunami
+system=system
+config=system.iobus.port[31]
+dma=system.iobus.port[32]
+pio=system.iobus.port[26]
 
 [system.tsunami.io]
 type=TsunamiIO

tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt

@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 979093                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 278732                       # Number of bytes of host memory used
-host_seconds                                    66.19                       # Real time elapsed on the host
-host_tick_rate                            29741162851                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1027363                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 295468                       # Number of bytes of host memory used
+host_seconds                                    63.08                       # Real time elapsed on the host
+host_tick_rate                            31207407187                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    64810685                       # Number of instructions simulated
 sim_seconds                                  1.968714                       # Number of seconds simulated
@@ -273,7 +273,7 @@ system.cpu0.kern.syscall_132                        2      0.94%     98.58% # nu
 system.cpu0.kern.syscall_144                        1      0.47%     99.06% # number of syscalls executed
 system.cpu0.kern.syscall_147                        2      0.94%    100.00% # number of syscalls executed
 system.cpu0.not_idle_fraction                0.057929                       # Percentage of non-idle cycles
-system.cpu0.numCycles                    1967810461000                       # number of cpu cycles simulated
+system.cpu0.numCycles                      3935620922                       # number of cpu cycles simulated
 system.cpu0.num_insts                        50990937                       # Number of instructions executed
 system.cpu0.num_refs                         13220047                       # Number of memory references
 system.cpu1.dcache.LoadLockedReq_accesses        60083                       # number of LoadLockedReq accesses(hits+misses)
@@ -528,7 +528,7 @@ system.cpu1.kern.syscall_92                         2      1.75%     97.37% # nu
 system.cpu1.kern.syscall_132                        2      1.75%     99.12% # number of syscalls executed
 system.cpu1.kern.syscall_144                        1      0.88%    100.00% # number of syscalls executed
 system.cpu1.not_idle_fraction                0.013720                       # Percentage of non-idle cycles
-system.cpu1.numCycles                    1968713509000                       # number of cpu cycles simulated
+system.cpu1.numCycles                      3937427018                       # number of cpu cycles simulated
 system.cpu1.num_insts                        13819748                       # Number of instructions executed
 system.cpu1.num_refs                          4429865                       # Number of memory references
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).

tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini

@@ -348,7 +348,7 @@ pio=system.toL2Bus.default
 
 [system.tsunami]
 type=Tsunami
-children=cchip console etherint ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
+children=cchip console ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
 intrctrl=system.intrctrl
 system=system
 
@@ -372,48 +372,8 @@ sim_console=system.sim_console
 system=system
 pio=system.iobus.port[25]
 
-[system.tsunami.etherint]
-type=NSGigEInt
-device=system.tsunami.ethernet
-peer=Null
-
 [system.tsunami.ethernet]
 type=NSGigE
-children=configdata
-clock=0
-config_latency=20000
-configdata=system.tsunami.ethernet.configdata
-dma_data_free=false
-dma_desc_free=false
-dma_no_allocate=true
-dma_read_delay=0
-dma_read_factor=0
-dma_write_delay=0
-dma_write_factor=0
-hardware_address=00:90:00:00:00:01
-intr_delay=10000000
-max_backoff_delay=10000000
-min_backoff_delay=4000
-pci_bus=0
-pci_dev=1
-pci_func=0
-pio_latency=1000
-platform=system.tsunami
-rss=false
-rx_delay=1000000
-rx_fifo_size=524288
-rx_filter=true
-rx_thread=false
-system=system
-tx_delay=1000000
-tx_fifo_size=524288
-tx_thread=false
-config=system.iobus.port[29]
-dma=system.iobus.port[30]
-pio=system.iobus.port[27]
-
-[system.tsunami.ethernet.configdata]
-type=PciConfigData
 BAR0=1
 BAR0Size=256
 BAR1=0
@@ -446,6 +406,36 @@ SubClassCode=0
 SubsystemID=0
 SubsystemVendorID=0
 VendorID=4107
+clock=0
+config_latency=20000
+dma_data_free=false
+dma_desc_free=false
+dma_no_allocate=true
+dma_read_delay=0
+dma_read_factor=0
+dma_write_delay=0
+dma_write_factor=0
+hardware_address=00:90:00:00:00:01
+intr_delay=10000000
+max_backoff_delay=10000000
+min_backoff_delay=4000
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=1000
+platform=system.tsunami
+rss=false
+rx_delay=1000000
+rx_fifo_size=524288
+rx_filter=true
+rx_thread=false
+system=system
+tx_delay=1000000
+tx_fifo_size=524288
+tx_thread=false
+config=system.iobus.port[29]
+dma=system.iobus.port[30]
+pio=system.iobus.port[27]
 
 [system.tsunami.fake_OROM]
 type=IsaFake
@@ -762,24 +752,6 @@ pio=system.iobus.port[22]
 
 [system.tsunami.ide]
 type=IdeController
-children=configdata
-config_latency=20000
-configdata=system.tsunami.ide.configdata
-disks=system.disk0 system.disk2
-max_backoff_delay=10000000
-min_backoff_delay=4000
-pci_bus=0
-pci_dev=0
-pci_func=0
-pio_latency=1000
-platform=system.tsunami
-system=system
-config=system.iobus.port[31]
-dma=system.iobus.port[32]
-pio=system.iobus.port[26]
-
-[system.tsunami.ide.configdata]
-type=PciConfigData
 BAR0=1
 BAR0Size=8
 BAR1=1
@@ -812,6 +784,19 @@ SubClassCode=1
 SubsystemID=0
 SubsystemVendorID=0
 VendorID=32902
+config_latency=20000
+disks=system.disk0 system.disk2
+max_backoff_delay=10000000
+min_backoff_delay=4000
+pci_bus=0
+pci_dev=0
+pci_func=0
+pio_latency=1000
+platform=system.tsunami
+system=system
+config=system.iobus.port[31]
+dma=system.iobus.port[32]
+pio=system.iobus.port[26]
 
 [system.tsunami.io]
 type=TsunamiIO

tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt

@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 986602                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 268252                       # Number of bytes of host memory used
-host_seconds                                    60.87                       # Real time elapsed on the host
-host_tick_rate                            31682591808                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1046777                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 284980                       # Number of bytes of host memory used
+host_seconds                                    57.37                       # Real time elapsed on the host
+host_tick_rate                            33615024315                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    60057633                       # Number of instructions simulated
 sim_seconds                                  1.928634                       # Number of seconds simulated
@@ -268,7 +268,7 @@ system.cpu.kern.syscall_132                         4      1.23%     98.77% # nu
 system.cpu.kern.syscall_144                         2      0.61%     99.39% # number of syscalls executed
 system.cpu.kern.syscall_147                         2      0.61%    100.00% # number of syscalls executed
 system.cpu.not_idle_fraction                 0.069379                       # Percentage of non-idle cycles
-system.cpu.numCycles                     1928634086000                       # number of cpu cycles simulated
+system.cpu.numCycles                       3857268172                       # number of cpu cycles simulated
 system.cpu.num_insts                         60057633                       # Number of instructions executed
 system.cpu.num_refs                          16313038                       # Number of memory references
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).

tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt

@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2121237                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 171724                       # Number of bytes of host memory used
-host_seconds                                     0.24                       # Real time elapsed on the host
-host_tick_rate                             1058992833                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1676309                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 188356                       # Number of bytes of host memory used
+host_seconds                                     0.30                       # Real time elapsed on the host
+host_tick_rate                              837474668                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                      500001                       # Number of instructions simulated
 sim_seconds                                  0.000250                       # Number of seconds simulated

tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt

@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1285667                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 179016                       # Number of bytes of host memory used
-host_seconds                                     0.39                       # Real time elapsed on the host
-host_tick_rate                             1812257249                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1220265                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 195724                       # Number of bytes of host memory used
+host_seconds                                     0.41                       # Real time elapsed on the host
+host_tick_rate                             1720644367                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                      500001                       # Number of instructions simulated
 sim_seconds                                  0.000705                       # Number of seconds simulated
@@ -239,7 +239,7 @@ system.cpu.l2cache.total_refs                       0                       # To
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                        705490000                       # number of cpu cycles simulated
+system.cpu.numCycles                          1410980                       # number of cpu cycles simulated
 system.cpu.num_insts                           500001                       # Number of instructions executed
 system.cpu.num_refs                            182222                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              18                       # Number of system calls

tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini

@@ -14,7 +14,7 @@ kernel=/dist/m5/system/binaries/vmlinux
 mem_mode=atomic
 pal=/dist/m5/system/binaries/ts_osfpal
 physmem=drivesys.physmem
-readfile=/home/blackga/m5/repos/m5/configs/boot/netperf-server.rcS
+readfile=/z/saidi/work/m5.dev/configs/boot/netperf-server.rcS
 symbolfile=
 system_rev=1024
 system_type=34
@@ -694,7 +694,7 @@ kernel=/dist/m5/system/binaries/vmlinux
 mem_mode=atomic
 pal=/dist/m5/system/binaries/ts_osfpal
 physmem=testsys.physmem
-readfile=/home/blackga/m5/repos/m5/configs/boot/netperf-stream-client.rcS
+readfile=/z/saidi/work/m5.dev/configs/boot/netperf-stream-client.rcS
 symbolfile=
 system_rev=1024
 system_type=34

tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt

@@ -76,7 +76,7 @@ drivesys.cpu.kern.syscall_106                       1      4.55%     86.36% # nu
 drivesys.cpu.kern.syscall_118                       2      9.09%     95.45% # number of syscalls executed
 drivesys.cpu.kern.syscall_150                       1      4.55%    100.00% # number of syscalls executed
 drivesys.cpu.not_idle_fraction               0.000000                       # Percentage of non-idle cycles
-drivesys.cpu.numCycles                        1958954                       # number of cpu cycles simulated
+drivesys.cpu.numCycles                   199572412849                       # number of cpu cycles simulated
 drivesys.cpu.num_insts                        1958129                       # Number of instructions executed
 drivesys.cpu.num_refs                          626223                       # Number of memory references
 drivesys.disk0.dma_read_bytes                       0                       # Number of bytes transfered via DMA reads (not PRD).
@@ -139,10 +139,10 @@ drivesys.tsunami.ethernet.txPPS                    25                       # Pa
 drivesys.tsunami.ethernet.txPackets                 5                       # Number of Packets Transmitted
 drivesys.tsunami.ethernet.txTcpChecksums            2                       # Number of tx TCP Checksums done by device
 drivesys.tsunami.ethernet.txUdpChecksums            0                       # Number of tx UDP Checksums done by device
-host_inst_rate                              118863353                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 459784                       # Number of bytes of host memory used
-host_seconds                                     2.30                       # Real time elapsed on the host
-host_tick_rate                            86976188826                       # Simulator tick rate (ticks/s)
+host_inst_rate                              129173906                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 476620                       # Number of bytes of host memory used
+host_seconds                                     2.12                       # Real time elapsed on the host
+host_tick_rate                            94522664540                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   273294782                       # Number of instructions simulated
 sim_seconds                                  0.200001                       # Number of seconds simulated
@@ -233,7 +233,7 @@ testsys.cpu.kern.syscall_104                        1      1.20%     93.98% # nu
 testsys.cpu.kern.syscall_105                        3      3.61%     97.59% # number of syscalls executed
 testsys.cpu.kern.syscall_118                        2      2.41%    100.00% # number of syscalls executed
 testsys.cpu.not_idle_fraction                0.000001                       # Percentage of non-idle cycles
-testsys.cpu.numCycles                         3566060                       # number of cpu cycles simulated
+testsys.cpu.numCycles                    199570420361                       # number of cpu cycles simulated
 testsys.cpu.num_insts                         3560518                       # Number of instructions executed
 testsys.cpu.num_refs                          1173605                       # Number of memory references
 testsys.disk0.dma_read_bytes                        0                       # Number of bytes transfered via DMA reads (not PRD).
@@ -381,10 +381,10 @@ drivesys.tsunami.ethernet.totalSwi                  0                       # to
 drivesys.tsunami.ethernet.totalTxDesc               0                       # total number of TxDesc written to ISR
 drivesys.tsunami.ethernet.totalTxIdle               0                       # total number of TxIdle written to ISR
 drivesys.tsunami.ethernet.totalTxOk                 0                       # total number of TxOk written to ISR
-host_inst_rate                           116742751815                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 459784                       # Number of bytes of host memory used
+host_inst_rate                           134363216323                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 476620                       # Number of bytes of host memory used
 host_seconds                                     0.00                       # Real time elapsed on the host
-host_tick_rate                              317182405                       # Simulator tick rate (ticks/s)
+host_tick_rate                              362870729                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   273294782                       # Number of instructions simulated
 sim_seconds                                  0.000001                       # Number of seconds simulated