452 lines
48 KiB
Plaintext
452 lines
48 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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global.BPredUnit.BTBHits 13010658 # Number of BTB hits
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global.BPredUnit.BTBLookups 16925459 # Number of BTB lookups
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global.BPredUnit.RASInCorrect 1191 # Number of incorrect RAS predictions.
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global.BPredUnit.condIncorrect 1944478 # Number of conditional branches incorrect
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global.BPredUnit.condPredicted 14575632 # Number of conditional branches predicted
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global.BPredUnit.lookups 19422613 # Number of BP lookups
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global.BPredUnit.usedRAS 1713685 # Number of times the RAS was used to get a target.
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host_inst_rate 135551 # Simulator instruction rate (inst/s)
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host_mem_usage 205692 # Number of bytes of host memory used
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host_seconds 621.02 # Real time elapsed on the host
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host_tick_rate 65380263 # Simulator tick rate (ticks/s)
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memdepunit.memDep.conflictingLoads 17216912 # Number of conflicting loads.
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memdepunit.memDep.conflictingStores 5017487 # Number of conflicting stores.
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memdepunit.memDep.insertedLoads 33831723 # Number of loads inserted to the mem dependence unit.
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memdepunit.memDep.insertedStores 10556967 # Number of stores inserted to the mem dependence unit.
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 84179709 # Number of instructions simulated
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sim_seconds 0.040602 # Number of seconds simulated
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sim_ticks 40602361500 # Number of ticks simulated
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system.cpu.commit.COM:branches 10240685 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 2830089 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle.samples 73220545
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system.cpu.commit.COM:committed_per_cycle.min_value 0
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0 35958705 4911.01%
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1 18165534 2480.93%
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2 7495163 1023.64%
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3 3905368 533.37%
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4 2115499 288.92%
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5 1290804 176.29%
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6 741318 101.24%
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7 718065 98.07%
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8 2830089 386.52%
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system.cpu.commit.COM:committed_per_cycle.max_value 8
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system.cpu.commit.COM:committed_per_cycle.end_dist
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system.cpu.commit.COM:count 91903055 # Number of instructions committed
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system.cpu.commit.COM:loads 20034413 # Number of loads committed
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system.cpu.commit.COM:membars 0 # Number of memory barriers committed
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system.cpu.commit.COM:refs 26537108 # Number of memory references committed
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.branchMispredicts 1932029 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 55442802 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 84179709 # Number of Instructions Simulated
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system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated
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system.cpu.cpi 0.964659 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 0.964659 # CPI: Total CPI of All Threads
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system.cpu.dcache.LoadLockedReq_accesses 7 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_hits 7 # number of LoadLockedReq hits
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system.cpu.dcache.ReadReq_accesses 23305151 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 8854.743083 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5500 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 23304645 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 4480500 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.000022 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 506 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 115 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 2783000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 506 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 6494991 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 24985.167206 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5885.922330 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 6493137 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 46322500 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.000285 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 1854 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 6112 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 10912500 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.000285 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 1854 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 13302.637946 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 29800142 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 21526.694915 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 5803.177966 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 29797782 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 50803000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.000079 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 2360 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 6227 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 13695500 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.000079 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 2360 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 29800142 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 21526.694915 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 5803.177966 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 29797782 # number of overall hits
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system.cpu.dcache.overall_miss_latency 50803000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.000079 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 2360 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 6227 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 13695500 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.000079 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 2360 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.dcache.replacements 159 # number of replacements
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system.cpu.dcache.sampled_refs 2240 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 1459.011880 # Cycle average of tags in use
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system.cpu.dcache.total_refs 29797909 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 105 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 3766232 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:BranchMispred 12611 # Number of times decode detected a branch misprediction
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system.cpu.decode.DECODE:BranchResolved 3034294 # Number of times decode resolved a branch
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system.cpu.decode.DECODE:DecodedInsts 162205348 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 39405972 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 29900475 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 7983383 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:SquashedInsts 45169 # Number of squashed instructions handled by decode
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system.cpu.decode.DECODE:UnblockCycles 147867 # Number of cycles decode is unblocking
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system.cpu.dtb.accesses 31800987 # DTB accesses
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system.cpu.dtb.acv 0 # DTB access violations
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system.cpu.dtb.hits 31340580 # DTB hits
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system.cpu.dtb.misses 460407 # DTB misses
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system.cpu.dtb.read_accesses 24617799 # DTB read accesses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_hits 24158583 # DTB read hits
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system.cpu.dtb.read_misses 459216 # DTB read misses
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system.cpu.dtb.write_accesses 7183188 # DTB write accesses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_hits 7181997 # DTB write hits
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system.cpu.dtb.write_misses 1191 # DTB write misses
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system.cpu.fetch.Branches 19422613 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 19195045 # Number of cache lines fetched
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system.cpu.fetch.Cycles 50102609 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 509210 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 167066208 # Number of instructions fetch has processed
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system.cpu.fetch.SquashCycles 2080138 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.239181 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 19195045 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 14724343 # Number of branches that fetch has predicted taken
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system.cpu.fetch.rate 2.057346 # Number of inst fetches per cycle
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system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist.samples 81203929
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system.cpu.fetch.rateDist.min_value 0
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0 50296438 6193.84%
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1 3127485 385.14%
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2 2009190 247.43%
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3 3499443 430.95%
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4 4580392 564.06%
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5 1498651 184.55%
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6 2040206 251.24%
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7 1851037 227.95%
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8 12301087 1514.84%
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system.cpu.fetch.rateDist.max_value 8
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system.cpu.fetch.rateDist.end_dist
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system.cpu.icache.ReadReq_accesses 19194697 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 5285.401314 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 3152.011551 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 19184655 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 53076000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.000523 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 10042 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_hits 348 # number of ReadReq MSHR hits
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system.cpu.icache.ReadReq_mshr_miss_latency 31652500 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000523 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 10042 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 1910.441645 # Average number of references to valid blocks.
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system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 19194697 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 5285.401314 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 3152.011551 # average overall mshr miss latency
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system.cpu.icache.demand_hits 19184655 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 53076000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.000523 # miss rate for demand accesses
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system.cpu.icache.demand_misses 10042 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 348 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 31652500 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.000523 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 10042 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_accesses 19194697 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 5285.401314 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 3152.011551 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 19184655 # number of overall hits
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system.cpu.icache.overall_miss_latency 53076000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.000523 # miss rate for overall accesses
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system.cpu.icache.overall_misses 10042 # number of overall misses
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system.cpu.icache.overall_mshr_hits 348 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 31652500 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.000523 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 10042 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.icache.replacements 8129 # number of replacements
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system.cpu.icache.sampled_refs 10042 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 1547.586704 # Cycle average of tags in use
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system.cpu.icache.total_refs 19184655 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idleCycles 795 # Total number of cycles that the CPU has spent unscheduled due to idling
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system.cpu.iew.EXEC:branches 12760718 # Number of branches executed
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system.cpu.iew.EXEC:nop 12520368 # number of nop insts executed
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system.cpu.iew.EXEC:rate 1.249709 # Inst execution rate
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system.cpu.iew.EXEC:refs 31851627 # number of memory reference insts executed
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system.cpu.iew.EXEC:stores 7184817 # Number of stores executed
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system.cpu.iew.EXEC:swp 0 # number of swp insts executed
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system.cpu.iew.WB:consumers 90693698 # num instructions consuming a value
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system.cpu.iew.WB:count 99568419 # cumulative count of insts written-back
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system.cpu.iew.WB:fanout 0.723301 # average fanout of values written-back
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system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
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system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
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system.cpu.iew.WB:producers 65598879 # num instructions producing a value
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system.cpu.iew.WB:rate 1.226141 # insts written-back per cycle
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system.cpu.iew.WB:sent 100495413 # cumulative count of insts sent to commit
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system.cpu.iew.branchMispredicts 2106580 # Number of branch mispredicts detected at execute
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system.cpu.iew.iewBlockCycles 285272 # Number of cycles IEW is blocking
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system.cpu.iew.iewDispLoadInsts 33831723 # Number of dispatched load instructions
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system.cpu.iew.iewDispNonSpecInsts 429 # Number of dispatched non-speculative instructions
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system.cpu.iew.iewDispSquashedInsts 1731846 # Number of squashed instructions skipped by dispatch
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system.cpu.iew.iewDispStoreInsts 10556967 # Number of dispatched store instructions
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system.cpu.iew.iewDispatchedInsts 147344437 # Number of instructions dispatched to IQ
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system.cpu.iew.iewExecLoadInsts 24666810 # Number of load instructions executed
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system.cpu.iew.iewExecSquashedInsts 2188087 # Number of squashed instructions skipped in execute
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system.cpu.iew.iewExecutedInsts 101482299 # Number of executed instructions
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system.cpu.iew.iewIQFullEvents 133099 # Number of times the IQ has become full, causing a stall
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system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
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system.cpu.iew.iewLSQFullEvents 12 # Number of times the LSQ has become full, causing a stall
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system.cpu.iew.iewSquashCycles 7983383 # Number of cycles IEW is squashing
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system.cpu.iew.iewUnblockCycles 165893 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.lsq.thread.0.forwLoads 843499 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 1537 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 250644 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 9811 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 13797310 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread.0.squashedStores 4054272 # Number of stores squashed
|
|
system.cpu.iew.memOrderViolationEvents 250644 # Number of memory order violations
|
|
system.cpu.iew.predictedNotTakenIncorrect 202889 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.predictedTakenIncorrect 1903691 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.ipc 1.036636 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.036636 # IPC: Total IPC of All Threads
|
|
system.cpu.iq.ISSUE:FU_type_0 103670386 # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
|
No_OpClass 7 0.00% # Type of FU issued
|
|
IntAlu 64195239 61.92% # Type of FU issued
|
|
IntMult 473046 0.46% # Type of FU issued
|
|
IntDiv 0 0.00% # Type of FU issued
|
|
FloatAdd 2788829 2.69% # Type of FU issued
|
|
FloatCmp 115617 0.11% # Type of FU issued
|
|
FloatCvt 2372095 2.29% # Type of FU issued
|
|
FloatMult 305683 0.29% # Type of FU issued
|
|
FloatDiv 755148 0.73% # Type of FU issued
|
|
FloatSqrt 322 0.00% # Type of FU issued
|
|
MemRead 25353594 24.46% # Type of FU issued
|
|
MemWrite 7310806 7.05% # Type of FU issued
|
|
IprAccess 0 0.00% # Type of FU issued
|
|
InstPrefetch 0 0.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 1973729 # FU busy when requested
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.019039 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.ISSUE:fu_full.start_dist
|
|
No_OpClass 0 0.00% # attempts to use FU when none available
|
|
IntAlu 311847 15.80% # attempts to use FU when none available
|
|
IntMult 0 0.00% # attempts to use FU when none available
|
|
IntDiv 0 0.00% # attempts to use FU when none available
|
|
FloatAdd 478 0.02% # attempts to use FU when none available
|
|
FloatCmp 0 0.00% # attempts to use FU when none available
|
|
FloatCvt 2917 0.15% # attempts to use FU when none available
|
|
FloatMult 2390 0.12% # attempts to use FU when none available
|
|
FloatDiv 832522 42.18% # attempts to use FU when none available
|
|
FloatSqrt 0 0.00% # attempts to use FU when none available
|
|
MemRead 750992 38.05% # attempts to use FU when none available
|
|
MemWrite 72583 3.68% # attempts to use FU when none available
|
|
IprAccess 0 0.00% # attempts to use FU when none available
|
|
InstPrefetch 0 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full.end_dist
|
|
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle.samples 81203929
|
|
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
|
0 35188418 4333.34%
|
|
1 18662979 2298.29%
|
|
2 11625415 1431.63%
|
|
3 6937118 854.28%
|
|
4 4927347 606.79%
|
|
5 2234432 275.16%
|
|
6 1373348 169.12%
|
|
7 215389 26.52%
|
|
8 39483 4.86%
|
|
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
|
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
|
|
|
system.cpu.iq.ISSUE:rate 1.276655 # Inst issue rate
|
|
system.cpu.iq.iqInstsAdded 134823640 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqInstsIssued 103670386 # Number of instructions issued
|
|
system.cpu.iq.iqNonSpecInstsAdded 429 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqSquashedInstsExamined 50027749 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedInstsIssued 225448 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 40 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.iqSquashedOperandsExamined 46827412 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.itb.accesses 19195118 # ITB accesses
|
|
system.cpu.itb.acv 0 # ITB acv
|
|
system.cpu.itb.hits 19195045 # ITB hits
|
|
system.cpu.itb.misses 73 # ITB misses
|
|
system.cpu.l2cache.ReadExReq_accesses 1735 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 4523.342939 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2523.342939 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_miss_latency 7848000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_misses 1735 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 4378000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 1735 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_accesses 10547 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 4263.929619 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2263.929619 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_hits 7137 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_miss_latency 14540000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.323315 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_misses 3410 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 7720000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.323315 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_misses 3410 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_accesses 123 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 4430.894309 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2430.894309 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_miss_latency 545000 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_misses 123 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 299000 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 123 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.Writeback_accesses 105 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
|
|
system.cpu.l2cache.Writeback_misses 105 # number of Writeback misses
|
|
system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
|
|
system.cpu.l2cache.Writeback_mshr_misses 105 # number of Writeback MSHR misses
|
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_refs 2.172603 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.demand_accesses 12282 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_avg_miss_latency 4351.409135 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 2351.409135 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_hits 7137 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_miss_latency 22388000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_rate 0.418906 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_misses 5145 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_miss_latency 12098000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.418906 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_misses 5145 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.overall_accesses 12282 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_avg_miss_latency 4351.409135 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 2351.409135 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_hits 7137 # number of overall hits
|
|
system.cpu.l2cache.overall_miss_latency 22388000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_rate 0.418906 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_misses 5145 # number of overall misses
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_miss_latency 12098000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.418906 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_misses 5145 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.sampled_refs 3285 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.l2cache.tagsinuse 2248.754865 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 7137 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
|
system.cpu.numCycles 81204724 # number of cpu cycles simulated
|
|
system.cpu.rename.RENAME:BlockCycles 1670922 # Number of cycles rename is blocking
|
|
system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed
|
|
system.cpu.rename.RENAME:IQFullEvents 1021107 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.RENAME:IdleCycles 40689840 # Number of cycles rename is idle
|
|
system.cpu.rename.RENAME:LSQFullEvents 938076 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RENAME:RenameLookups 202669964 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.RENAME:RenamedInsts 157140698 # Number of instructions processed by rename
|
|
system.cpu.rename.RENAME:RenamedOperands 115798524 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RENAME:RunCycles 28770212 # Number of cycles rename is running
|
|
system.cpu.rename.RENAME:SquashCycles 7983383 # Number of cycles rename is squashing
|
|
system.cpu.rename.RENAME:UnblockCycles 2084846 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RENAME:UndoneMaps 47371163 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.RENAME:serializeStallCycles 4726 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RENAME:serializingInsts 465 # count of serializing insts renamed
|
|
system.cpu.rename.RENAME:skidInsts 4645791 # count of insts added to the skid buffer
|
|
system.cpu.rename.RENAME:tempSerializingInsts 454 # count of temporary serializing insts renamed
|
|
system.cpu.timesIdled 325 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
|
|
|
|
---------- End Simulation Statistics ----------
|