753 lines
81 KiB
Plaintext
753 lines
81 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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global.BPredUnit.BTBHits 706 # Number of BTB hits
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global.BPredUnit.BTBLookups 3499 # Number of BTB lookups
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global.BPredUnit.RASInCorrect 117 # Number of incorrect RAS predictions.
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global.BPredUnit.condIncorrect 1092 # Number of conditional branches incorrect
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global.BPredUnit.condPredicted 2350 # Number of conditional branches predicted
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global.BPredUnit.lookups 4075 # Number of BP lookups
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global.BPredUnit.usedRAS 561 # Number of times the RAS was used to get a target.
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host_inst_rate 92493 # Simulator instruction rate (inst/s)
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host_mem_usage 197924 # Number of bytes of host memory used
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host_seconds 0.12 # Real time elapsed on the host
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host_tick_rate 47019704 # Simulator tick rate (ticks/s)
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memdepunit.memDep.conflictingLoads 14 # Number of conflicting loads.
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memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads.
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memdepunit.memDep.conflictingStores 35 # Number of conflicting stores.
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memdepunit.memDep.conflictingStores 38 # Number of conflicting stores.
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memdepunit.memDep.insertedLoads 1959 # Number of loads inserted to the mem dependence unit.
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memdepunit.memDep.insertedLoads 1940 # Number of loads inserted to the mem dependence unit.
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memdepunit.memDep.insertedStores 1118 # Number of stores inserted to the mem dependence unit.
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memdepunit.memDep.insertedStores 1140 # Number of stores inserted to the mem dependence unit.
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 11247 # Number of instructions simulated
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sim_seconds 0.000006 # Number of seconds simulated
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sim_ticks 5727000 # Number of ticks simulated
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system.cpu.commit.COM:branches 1724 # Number of branches committed
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system.cpu.commit.COM:branches_0 862 # Number of branches committed
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system.cpu.commit.COM:branches_1 862 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 161 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:bw_limited_0 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:bw_limited_1 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle.samples 11403
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system.cpu.commit.COM:committed_per_cycle.min_value 0
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0 6781 5946.68%
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1 2144 1880.21%
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2 950 833.11%
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3 495 434.10%
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4 331 290.27%
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5 216 189.42%
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6 215 188.55%
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7 110 96.47%
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8 161 141.19%
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system.cpu.commit.COM:committed_per_cycle.max_value 8
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system.cpu.commit.COM:committed_per_cycle.end_dist
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system.cpu.commit.COM:count 11281 # Number of instructions committed
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system.cpu.commit.COM:count_0 5640 # Number of instructions committed
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system.cpu.commit.COM:count_1 5641 # Number of instructions committed
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system.cpu.commit.COM:loads 1958 # Number of loads committed
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system.cpu.commit.COM:loads_0 979 # Number of loads committed
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system.cpu.commit.COM:loads_1 979 # Number of loads committed
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system.cpu.commit.COM:membars 0 # Number of memory barriers committed
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system.cpu.commit.COM:membars_0 0 # Number of memory barriers committed
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system.cpu.commit.COM:membars_1 0 # Number of memory barriers committed
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system.cpu.commit.COM:refs 3582 # Number of memory references committed
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system.cpu.commit.COM:refs_0 1791 # Number of memory references committed
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system.cpu.commit.COM:refs_1 1791 # Number of memory references committed
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.COM:swp_count_0 0 # Number of s/w prefetches committed
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system.cpu.commit.COM:swp_count_1 0 # Number of s/w prefetches committed
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system.cpu.commit.branchMispredicts 854 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 11281 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 8053 # The number of squashed insts skipped by commit
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system.cpu.committedInsts_0 5623 # Number of Instructions Simulated
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system.cpu.committedInsts_1 5624 # Number of Instructions Simulated
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system.cpu.committedInsts_total 11247 # Number of Instructions Simulated
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system.cpu.cpi_0 2.037169 # CPI: Cycles Per Instruction
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system.cpu.cpi_1 2.036807 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 1.018494 # CPI: Total CPI of All Threads
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system.cpu.dcache.ReadReq_accesses 2934 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_accesses_0 2934 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency_0 12119.897959 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 7403.061224 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 2738 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits_0 2738 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 2375500 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_latency_0 2375500 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate_0 0.066803 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 196 # number of ReadReq misses
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system.cpu.dcache.ReadReq_misses_0 196 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 81 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_hits_0 81 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 1451000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_latency_0 1451000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.066803 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 196 # number of ReadReq MSHR misses
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system.cpu.dcache.ReadReq_mshr_misses_0 196 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 1240 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses_0 1240 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency_0 21692.528736 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 6310.344828 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 1066 # number of WriteReq hits
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system.cpu.dcache.WriteReq_hits_0 1066 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 3774500 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency_0 3774500 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate_0 0.140323 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 174 # number of WriteReq misses
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system.cpu.dcache.WriteReq_misses_0 174 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 384 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_hits_0 384 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 1098000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_latency_0 1098000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.140323 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 174 # number of WriteReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_misses_0 174 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 11.276471 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 4174 # number of demand (read+write) accesses
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system.cpu.dcache.demand_accesses_0 4174 # number of demand (read+write) accesses
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system.cpu.dcache.demand_accesses_1 0 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency <err: div-0> # average overall miss latency
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system.cpu.dcache.demand_avg_miss_latency_0 16621.621622 # average overall miss latency
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system.cpu.dcache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency_0 6889.189189 # average overall mshr miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
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system.cpu.dcache.demand_hits 3804 # number of demand (read+write) hits
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system.cpu.dcache.demand_hits_0 3804 # number of demand (read+write) hits
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system.cpu.dcache.demand_hits_1 0 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 6150000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_latency_0 6150000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate <err: div-0> # miss rate for demand accesses
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system.cpu.dcache.demand_miss_rate_0 0.088644 # miss rate for demand accesses
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system.cpu.dcache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses
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system.cpu.dcache.demand_misses 370 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses_0 370 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses_1 0 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 465 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_hits_0 465 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 2549000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_latency_0 2549000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_miss_rate_0 0.088644 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 370 # number of demand (read+write) MSHR misses
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system.cpu.dcache.demand_mshr_misses_0 370 # number of demand (read+write) MSHR misses
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system.cpu.dcache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.mshr_cap_events_0 0 # number of times MSHR cap was activated
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system.cpu.dcache.mshr_cap_events_1 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 4174 # number of overall (read+write) accesses
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system.cpu.dcache.overall_accesses_0 4174 # number of overall (read+write) accesses
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system.cpu.dcache.overall_accesses_1 0 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency <err: div-0> # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency_0 16621.621622 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency_0 6889.189189 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 3804 # number of overall hits
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system.cpu.dcache.overall_hits_0 3804 # number of overall hits
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system.cpu.dcache.overall_hits_1 0 # number of overall hits
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system.cpu.dcache.overall_miss_latency 6150000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_latency_0 6150000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_latency_1 0 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate <err: div-0> # miss rate for overall accesses
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system.cpu.dcache.overall_miss_rate_0 0.088644 # miss rate for overall accesses
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system.cpu.dcache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses
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system.cpu.dcache.overall_misses 370 # number of overall misses
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system.cpu.dcache.overall_misses_0 370 # number of overall misses
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system.cpu.dcache.overall_misses_1 0 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 465 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_hits_0 465 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_hits_1 0 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 2549000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency_0 2549000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_miss_rate_0 0.088644 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 370 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_misses_0 370 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_misses_1 0 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_latency_1 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.dcache.replacements 0 # number of replacements
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system.cpu.dcache.replacements_0 0 # number of replacements
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system.cpu.dcache.replacements_1 0 # number of replacements
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system.cpu.dcache.sampled_refs 340 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 215.589336 # Cycle average of tags in use
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system.cpu.dcache.total_refs 3834 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 0 # number of writebacks
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system.cpu.dcache.writebacks_0 0 # number of writebacks
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system.cpu.dcache.writebacks_1 0 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 1981 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:BranchMispred 247 # Number of times decode detected a branch misprediction
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system.cpu.decode.DECODE:BranchResolved 354 # Number of times decode resolved a branch
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system.cpu.decode.DECODE:DecodedInsts 22591 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 15034 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 3799 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 1569 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:SquashedInsts 329 # Number of squashed instructions handled by decode
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system.cpu.decode.DECODE:UnblockCycles 215 # Number of cycles decode is unblocking
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system.cpu.dtb.accesses 5095 # DTB accesses
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system.cpu.dtb.acv 0 # DTB access violations
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system.cpu.dtb.hits 4970 # DTB hits
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system.cpu.dtb.misses 125 # DTB misses
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system.cpu.dtb.read_accesses 3183 # DTB read accesses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_hits 3106 # DTB read hits
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system.cpu.dtb.read_misses 77 # DTB read misses
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system.cpu.dtb.write_accesses 1912 # DTB write accesses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_hits 1864 # DTB write hits
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system.cpu.dtb.write_misses 48 # DTB write misses
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system.cpu.fetch.Branches 4075 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 3019 # Number of cache lines fetched
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system.cpu.fetch.Cycles 7174 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 439 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 24770 # Number of instructions fetch has processed
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system.cpu.fetch.SquashCycles 1207 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.355740 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 3019 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 1267 # Number of branches that fetch has predicted taken
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system.cpu.fetch.rate 2.162375 # Number of inst fetches per cycle
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system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist.samples 11446
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system.cpu.fetch.rateDist.min_value 0
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0 7343 6415.34%
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1 306 267.34%
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2 243 212.30%
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3 264 230.65%
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4 343 299.67%
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5 290 253.36%
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6 316 276.08%
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7 260 227.15%
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8 2081 1818.10%
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system.cpu.fetch.rateDist.max_value 8
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system.cpu.fetch.rateDist.end_dist
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system.cpu.icache.ReadReq_accesses 2953 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses_0 2953 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency_0 8345.528455 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 5903.252033 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_hits 2338 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits_0 2338 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_miss_latency 5132500 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency_0 5132500 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_rate_0 0.208263 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_misses 615 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses_0 615 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_mshr_hits 66 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits_0 66 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 3630500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency_0 3630500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate_0 0.208263 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_misses 615 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses_0 615 # number of ReadReq MSHR misses
|
|
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_refs 3.801626 # Average number of references to valid blocks.
|
|
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.demand_accesses 2953 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses_0 2953 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses_1 0 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_avg_miss_latency <err: div-0> # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency_0 8345.528455 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency_0 5903.252033 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
|
|
system.cpu.icache.demand_hits 2338 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits_0 2338 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits_1 0 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_miss_latency 5132500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency_0 5132500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_rate <err: div-0> # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate_0 0.208263 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses
|
|
system.cpu.icache.demand_misses 615 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses_0 615 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses_1 0 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_mshr_hits 66 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits_0 66 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_miss_latency 3630500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency_0 3630500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate_0 0.208263 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_misses 615 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses_0 615 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.icache.mshr_cap_events_0 0 # number of times MSHR cap was activated
|
|
system.cpu.icache.mshr_cap_events_1 0 # number of times MSHR cap was activated
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.overall_accesses 2953 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses_0 2953 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses_1 0 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_avg_miss_latency <err: div-0> # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency_0 8345.528455 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency_0 5903.252033 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency
|
|
system.cpu.icache.overall_hits 2338 # number of overall hits
|
|
system.cpu.icache.overall_hits_0 2338 # number of overall hits
|
|
system.cpu.icache.overall_hits_1 0 # number of overall hits
|
|
system.cpu.icache.overall_miss_latency 5132500 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency_0 5132500 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency_1 0 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_rate <err: div-0> # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate_0 0.208263 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses
|
|
system.cpu.icache.overall_misses 615 # number of overall misses
|
|
system.cpu.icache.overall_misses_0 615 # number of overall misses
|
|
system.cpu.icache.overall_misses_1 0 # number of overall misses
|
|
system.cpu.icache.overall_mshr_hits 66 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits_0 66 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits_1 0 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_miss_latency 3630500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency_0 3630500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate_0 0.208263 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_misses 615 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses_0 615 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses_1 0 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_latency_1 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.icache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.icache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
system.cpu.icache.replacements 7 # number of replacements
|
|
system.cpu.icache.replacements_0 7 # number of replacements
|
|
system.cpu.icache.replacements_1 0 # number of replacements
|
|
system.cpu.icache.sampled_refs 615 # Sample count of references to valid blocks.
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.icache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.icache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.icache.tagsinuse 319.122278 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 2338 # Total number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
|
system.cpu.icache.writebacks_0 0 # number of writebacks
|
|
system.cpu.icache.writebacks_1 0 # number of writebacks
|
|
system.cpu.idleCycles 9 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.iew.EXEC:branches 2386 # Number of branches executed
|
|
system.cpu.iew.EXEC:branches_0 1188 # Number of branches executed
|
|
system.cpu.iew.EXEC:branches_1 1198 # Number of branches executed
|
|
system.cpu.iew.EXEC:nop 127 # number of nop insts executed
|
|
system.cpu.iew.EXEC:nop_0 66 # number of nop insts executed
|
|
system.cpu.iew.EXEC:nop_1 61 # number of nop insts executed
|
|
system.cpu.iew.EXEC:rate 1.377041 # Inst execution rate
|
|
system.cpu.iew.EXEC:refs 5110 # number of memory reference insts executed
|
|
system.cpu.iew.EXEC:refs_0 2531 # number of memory reference insts executed
|
|
system.cpu.iew.EXEC:refs_1 2579 # number of memory reference insts executed
|
|
system.cpu.iew.EXEC:stores 1925 # Number of stores executed
|
|
system.cpu.iew.EXEC:stores_0 958 # Number of stores executed
|
|
system.cpu.iew.EXEC:stores_1 967 # Number of stores executed
|
|
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
|
system.cpu.iew.EXEC:swp_0 0 # number of swp insts executed
|
|
system.cpu.iew.EXEC:swp_1 0 # number of swp insts executed
|
|
system.cpu.iew.WB:consumers 10281 # num instructions consuming a value
|
|
system.cpu.iew.WB:consumers_0 5147 # num instructions consuming a value
|
|
system.cpu.iew.WB:consumers_1 5134 # num instructions consuming a value
|
|
system.cpu.iew.WB:count 15145 # cumulative count of insts written-back
|
|
system.cpu.iew.WB:count_0 7584 # cumulative count of insts written-back
|
|
system.cpu.iew.WB:count_1 7561 # cumulative count of insts written-back
|
|
system.cpu.iew.WB:fanout 1.539346 # average fanout of values written-back
|
|
system.cpu.iew.WB:fanout_0 0.768992 # average fanout of values written-back
|
|
system.cpu.iew.WB:fanout_1 0.770354 # average fanout of values written-back
|
|
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.WB:penalized_0 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.WB:penalized_1 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.iew.WB:penalized_rate_0 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.iew.WB:penalized_rate_1 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.iew.WB:producers 7913 # num instructions producing a value
|
|
system.cpu.iew.WB:producers_0 3958 # num instructions producing a value
|
|
system.cpu.iew.WB:producers_1 3955 # num instructions producing a value
|
|
system.cpu.iew.WB:rate 1.322130 # insts written-back per cycle
|
|
system.cpu.iew.WB:rate_0 0.662069 # insts written-back per cycle
|
|
system.cpu.iew.WB:rate_1 0.660061 # insts written-back per cycle
|
|
system.cpu.iew.WB:sent 15343 # cumulative count of insts sent to commit
|
|
system.cpu.iew.WB:sent_0 7675 # cumulative count of insts sent to commit
|
|
system.cpu.iew.WB:sent_1 7668 # cumulative count of insts sent to commit
|
|
system.cpu.iew.branchMispredicts 991 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewBlockCycles 60 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewDispLoadInsts 3899 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 46 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewDispSquashedInsts 435 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispStoreInsts 2258 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispatchedInsts 19501 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewExecLoadInsts 3185 # Number of load instructions executed
|
|
system.cpu.iew.iewExecLoadInsts_0 1573 # Number of load instructions executed
|
|
system.cpu.iew.iewExecLoadInsts_1 1612 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 923 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.iewExecutedInsts 15774 # Number of executed instructions
|
|
system.cpu.iew.iewIQFullEvents 16 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.iewSquashCycles 1569 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.lsq.thread.0.forwLoads 39 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 62 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 980 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread.0.squashedStores 306 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread.1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread.1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.lsq.thread.1.forwLoads 50 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread.1.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.1.memOrderViolation 63 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread.1.squashedLoads 961 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread.1.squashedStores 328 # Number of stores squashed
|
|
system.cpu.iew.memOrderViolationEvents 125 # Number of memory order violations
|
|
system.cpu.iew.predictedNotTakenIncorrect 788 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.predictedTakenIncorrect 203 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.ipc_0 0.490877 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_1 0.490965 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.981842 # IPC: Total IPC of All Threads
|
|
system.cpu.iq.ISSUE:FU_type_0 8365 # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
|
No_OpClass 2 0.02% # Type of FU issued
|
|
IntAlu 5650 67.54% # Type of FU issued
|
|
IntMult 1 0.01% # Type of FU issued
|
|
IntDiv 0 0.00% # Type of FU issued
|
|
FloatAdd 2 0.02% # Type of FU issued
|
|
FloatCmp 0 0.00% # Type of FU issued
|
|
FloatCvt 0 0.00% # Type of FU issued
|
|
FloatMult 0 0.00% # Type of FU issued
|
|
FloatDiv 0 0.00% # Type of FU issued
|
|
FloatSqrt 0 0.00% # Type of FU issued
|
|
MemRead 1721 20.57% # Type of FU issued
|
|
MemWrite 989 11.82% # Type of FU issued
|
|
IprAccess 0 0.00% # Type of FU issued
|
|
InstPrefetch 0 0.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
|
system.cpu.iq.ISSUE:FU_type_1 8332 # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1.start_dist
|
|
No_OpClass 2 0.02% # Type of FU issued
|
|
IntAlu 5594 67.14% # Type of FU issued
|
|
IntMult 1 0.01% # Type of FU issued
|
|
IntDiv 0 0.00% # Type of FU issued
|
|
FloatAdd 2 0.02% # Type of FU issued
|
|
FloatCmp 0 0.00% # Type of FU issued
|
|
FloatCvt 0 0.00% # Type of FU issued
|
|
FloatMult 0 0.00% # Type of FU issued
|
|
FloatDiv 0 0.00% # Type of FU issued
|
|
FloatSqrt 0 0.00% # Type of FU issued
|
|
MemRead 1734 20.81% # Type of FU issued
|
|
MemWrite 999 11.99% # Type of FU issued
|
|
IprAccess 0 0.00% # Type of FU issued
|
|
InstPrefetch 0 0.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_1.end_dist
|
|
system.cpu.iq.ISSUE:FU_type 16697 # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type.start_dist
|
|
No_OpClass 4 0.02% # Type of FU issued
|
|
IntAlu 11244 67.34% # Type of FU issued
|
|
IntMult 2 0.01% # Type of FU issued
|
|
IntDiv 0 0.00% # Type of FU issued
|
|
FloatAdd 4 0.02% # Type of FU issued
|
|
FloatCmp 0 0.00% # Type of FU issued
|
|
FloatCvt 0 0.00% # Type of FU issued
|
|
FloatMult 0 0.00% # Type of FU issued
|
|
FloatDiv 0 0.00% # Type of FU issued
|
|
FloatSqrt 0 0.00% # Type of FU issued
|
|
MemRead 3455 20.69% # Type of FU issued
|
|
MemWrite 1988 11.91% # Type of FU issued
|
|
IprAccess 0 0.00% # Type of FU issued
|
|
InstPrefetch 0 0.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type.end_dist
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 193 # FU busy when requested
|
|
system.cpu.iq.ISSUE:fu_busy_cnt_0 88 # FU busy when requested
|
|
system.cpu.iq.ISSUE:fu_busy_cnt_1 105 # FU busy when requested
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.011559 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.ISSUE:fu_busy_rate_0 0.005270 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.ISSUE:fu_busy_rate_1 0.006289 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.ISSUE:fu_full.start_dist
|
|
No_OpClass 0 0.00% # attempts to use FU when none available
|
|
IntAlu 13 6.74% # attempts to use FU when none available
|
|
IntMult 0 0.00% # attempts to use FU when none available
|
|
IntDiv 0 0.00% # attempts to use FU when none available
|
|
FloatAdd 0 0.00% # attempts to use FU when none available
|
|
FloatCmp 0 0.00% # attempts to use FU when none available
|
|
FloatCvt 0 0.00% # attempts to use FU when none available
|
|
FloatMult 0 0.00% # attempts to use FU when none available
|
|
FloatDiv 0 0.00% # attempts to use FU when none available
|
|
FloatSqrt 0 0.00% # attempts to use FU when none available
|
|
MemRead 111 57.51% # attempts to use FU when none available
|
|
MemWrite 69 35.75% # attempts to use FU when none available
|
|
IprAccess 0 0.00% # attempts to use FU when none available
|
|
InstPrefetch 0 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full.end_dist
|
|
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle.samples 11446
|
|
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
|
0 5082 4439.98%
|
|
1 1881 1643.37%
|
|
2 1650 1441.55%
|
|
3 1151 1005.59%
|
|
4 829 724.27%
|
|
5 503 439.45%
|
|
6 239 208.81%
|
|
7 90 78.63%
|
|
8 21 18.35%
|
|
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
|
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
|
|
|
system.cpu.iq.ISSUE:rate 1.457617 # Inst issue rate
|
|
system.cpu.iq.iqInstsAdded 19328 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqInstsIssued 16697 # Number of instructions issued
|
|
system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqSquashedInstsExamined 7298 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.iqSquashedOperandsExamined 4495 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.itb.accesses 3071 # ITB accesses
|
|
system.cpu.itb.acv 0 # ITB acv
|
|
system.cpu.itb.hits 3019 # ITB hits
|
|
system.cpu.itb.misses 52 # ITB misses
|
|
system.cpu.l2cache.ReadExReq_accesses 144 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses_0 144 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency_0 4743.055556 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency_0 2743.055556 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_miss_latency 683000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency_0 683000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_rate_0 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_misses 144 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses_0 144 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 395000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency_0 395000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate_0 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 144 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses_0 144 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_accesses 811 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses_0 811 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency_0 4691.831683 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 2691.831683 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits_0 3 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_miss_latency 3791000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency_0 3791000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_rate_0 0.996301 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_misses 808 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses_0 808 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 2175000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency_0 2175000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.996301 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_misses 808 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses_0 808 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_accesses 30 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses_0 30 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency_0 4500 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency_0 2500 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_miss_latency 135000 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency_0 135000 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_rate_0 1 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_misses 30 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses_0 30 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 75000 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency_0 75000 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate_0 1 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 30 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses_0 30 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_refs 0.003856 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.demand_accesses 955 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses_0 955 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses_1 0 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_avg_miss_latency <err: div-0> # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency_0 4699.579832 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency_0 2699.579832 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits_0 3 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits_1 0 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_miss_latency 4474000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency_0 4474000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_rate <err: div-0> # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate_0 0.996859 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_misses 952 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses_0 952 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses_1 0 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits_0 0 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_miss_latency 2570000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency_0 2570000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate_0 0.996859 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_misses 952 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses_0 952 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.l2cache.mshr_cap_events_0 0 # number of times MSHR cap was activated
|
|
system.cpu.l2cache.mshr_cap_events_1 0 # number of times MSHR cap was activated
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.overall_accesses 955 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses_0 955 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses_1 0 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_avg_miss_latency <err: div-0> # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency_0 4699.579832 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency_0 2699.579832 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_hits 3 # number of overall hits
|
|
system.cpu.l2cache.overall_hits_0 3 # number of overall hits
|
|
system.cpu.l2cache.overall_hits_1 0 # number of overall hits
|
|
system.cpu.l2cache.overall_miss_latency 4474000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency_0 4474000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency_1 0 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_rate <err: div-0> # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate_0 0.996859 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_misses 952 # number of overall misses
|
|
system.cpu.l2cache.overall_misses_0 952 # number of overall misses
|
|
system.cpu.l2cache.overall_misses_1 0 # number of overall misses
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits_0 0 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits_1 0 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_miss_latency 2570000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency_0 2570000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate_0 0.996859 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_misses 952 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses_0 952 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses_1 0 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency_1 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.replacements_0 0 # number of replacements
|
|
system.cpu.l2cache.replacements_1 0 # number of replacements
|
|
system.cpu.l2cache.sampled_refs 778 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.l2cache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.l2cache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.l2cache.tagsinuse 424.676856 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
|
system.cpu.l2cache.writebacks_0 0 # number of writebacks
|
|
system.cpu.l2cache.writebacks_1 0 # number of writebacks
|
|
system.cpu.numCycles 11455 # number of cpu cycles simulated
|
|
system.cpu.rename.RENAME:BlockCycles 641 # Number of cycles rename is blocking
|
|
system.cpu.rename.RENAME:CommittedMaps 8102 # Number of HB maps that are committed
|
|
system.cpu.rename.RENAME:IdleCycles 15417 # Number of cycles rename is idle
|
|
system.cpu.rename.RENAME:LSQFullEvents 776 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RENAME:RenameLookups 27043 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.RENAME:RenamedInsts 21312 # Number of instructions processed by rename
|
|
system.cpu.rename.RENAME:RenamedOperands 15958 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RENAME:RunCycles 3623 # Number of cycles rename is running
|
|
system.cpu.rename.RENAME:SquashCycles 1569 # Number of cycles rename is squashing
|
|
system.cpu.rename.RENAME:UnblockCycles 844 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RENAME:UndoneMaps 7856 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.RENAME:serializeStallCycles 504 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed
|
|
system.cpu.rename.RENAME:skidInsts 2318 # count of insts added to the skid buffer
|
|
system.cpu.rename.RENAME:tempSerializingInsts 36 # count of temporary serializing insts renamed
|
|
system.cpu.timesIdled 4 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls
|
|
system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls
|
|
|
|
---------- End Simulation Statistics ----------
|