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Update stats for new single bad-address responder.

Browse source 
Mostly just config.ini updates, though the different response
latency for bad addresses caused very minor timing changes
in the O3 Linux boot tests.
This commit is contained in:
Steve Reinhardt 2009-04-22 01:55:52 -04:00
parent 6629d9b2bc
commit 7b40c36fbd
189 changed files with 1613 additions and 1937 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

13
tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
View file

@ -104,11 +104,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -277,11 +276,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -313,11 +311,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -356,12 +353,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing
cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/gzip
executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
gid=100
input=cin
max_stack_size=67108864

10
tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 14 2009 23:40:03
M5 revision 4208b24ee3ad 6033 default qtip tip new-thread-status-stats-update
M5 started Apr 14 2009 23:40:05
M5 executing on phenom
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing
M5 compiled Apr 21 2009 16:38:39
M5 revision e6dd09514462 6117 default qtip tip stats-update
M5 started Apr 21 2009 17:09:58
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

8
tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 252050 # Simulator instruction rate (inst/s)
host_mem_usage 207828 # Number of bytes of host memory used
host_seconds 2243.81 # Real time elapsed on the host
host_tick_rate 74461791 # Simulator tick rate (ticks/s)
host_inst_rate 211142 # Simulator instruction rate (inst/s)
host_mem_usage 204372 # Number of bytes of host memory used
host_seconds 2678.54 # Real time elapsed on the host
host_tick_rate 62376647 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 565552443 # Number of instructions simulated
sim_seconds 0.167078 # Number of seconds simulated

8
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:34:49
M5 executing on maize
M5 compiled Apr 21 2009 16:38:39
M5 revision e6dd09514462 6117 default qtip tip stats-update
M5 started Apr 21 2009 16:39:08
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

8
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 5975527 # Simulator instruction rate (inst/s)
host_mem_usage 197448 # Number of bytes of host memory used
host_seconds 100.72 # Real time elapsed on the host
host_tick_rate 2987780856 # Simulator tick rate (ticks/s)
host_inst_rate 3845310 # Simulator instruction rate (inst/s)
host_mem_usage 195720 # Number of bytes of host memory used
host_seconds 156.52 # Real time elapsed on the host
host_tick_rate 1922667398 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 601856964 # Number of instructions simulated
sim_seconds 0.300931 # Number of seconds simulated

9
tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
View file

@ -40,11 +40,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -76,11 +75,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -112,11 +110,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=10000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false

8
tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:34:42
M5 executing on maize
M5 compiled Apr 21 2009 16:38:39
M5 revision e6dd09514462 6117 default qtip tip stats-update
M5 started Apr 21 2009 17:10:28
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

8
tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 3011769 # Simulator instruction rate (inst/s)
host_mem_usage 204988 # Number of bytes of host memory used
host_seconds 199.84 # Real time elapsed on the host
host_tick_rate 3893225431 # Simulator tick rate (ticks/s)
host_inst_rate 1860782 # Simulator instruction rate (inst/s)
host_mem_usage 203344 # Number of bytes of host memory used
host_seconds 323.44 # Real time elapsed on the host
host_tick_rate 2405379783 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 601856964 # Number of instructions simulated
sim_seconds 0.778004 # Number of seconds simulated

13
tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
View file

@ -104,11 +104,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -277,11 +276,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -313,11 +311,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -356,12 +353,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing
cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/home/stever/m5/dist/cpu2000/binaries/sparc/linux/gzip
executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip
gid=100
input=cin
max_stack_size=67108864

10
tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 14 2009 21:09:22
M5 revision 4208b24ee3ad 6033 default qtip tip new-thread-status-stats-update
M5 started Apr 14 2009 23:40:01
M5 executing on phenom
command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing
M5 compiled Apr 21 2009 18:04:32
M5 revision e6dd09514462 6117 default qtip tip stats-update
M5 started Apr 21 2009 18:17:54
M5 executing on zizzer
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init

8
tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 120324 # Simulator instruction rate (inst/s)
host_mem_usage 213384 # Number of bytes of host memory used
host_seconds 11681.98 # Real time elapsed on the host
host_tick_rate 94389741 # Simulator tick rate (ticks/s)
host_inst_rate 110757 # Simulator instruction rate (inst/s)
host_mem_usage 206360 # Number of bytes of host memory used
host_seconds 12690.99 # Real time elapsed on the host
host_tick_rate 86885218 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1405618365 # Number of instructions simulated
sim_seconds 1.102659 # Number of seconds simulated

8
tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:31:00
M5 executing on maize
M5 compiled Apr 21 2009 18:04:32
M5 revision e6dd09514462 6117 default qtip tip stats-update
M5 started Apr 21 2009 18:04:58
M5 executing on zizzer
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

8
tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 3659022 # Simulator instruction rate (inst/s)
host_mem_usage 199544 # Number of bytes of host memory used
host_seconds 407.08 # Real time elapsed on the host
host_tick_rate 1829515892 # Simulator tick rate (ticks/s)
host_inst_rate 2585505 # Simulator instruction rate (inst/s)
host_mem_usage 197792 # Number of bytes of host memory used
host_seconds 576.11 # Real time elapsed on the host
host_tick_rate 1292756549 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1489523295 # Number of instructions simulated
sim_seconds 0.744764 # Number of seconds simulated

9
tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
View file

@ -40,11 +40,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -76,11 +75,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -112,11 +110,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=10000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false

8
tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:32:24
M5 executing on maize
M5 compiled Apr 21 2009 18:04:32
M5 revision e6dd09514462 6117 default qtip tip stats-update
M5 started Apr 21 2009 18:13:21
M5 executing on zizzer
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

8
tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1898996 # Simulator instruction rate (inst/s)
host_mem_usage 207084 # Number of bytes of host memory used
host_seconds 784.37 # Real time elapsed on the host
host_tick_rate 2646697045 # Simulator tick rate (ticks/s)
host_inst_rate 1263053 # Simulator instruction rate (inst/s)
host_mem_usage 205412 # Number of bytes of host memory used
host_seconds 1179.30 # Real time elapsed on the host
host_tick_rate 1760361196 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1489523295 # Number of instructions simulated
sim_seconds 2.076001 # Number of seconds simulated

8
tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 12 2009 13:26:17
M5 revision 8c874c02878a 6042 default qtip tip cpuidfixstats.patch
M5 started Apr 12 2009 13:32:20
M5 executing on tater
M5 compiled Apr 21 2009 19:00:07
M5 revision e6dd09514462 6117 default qtip tip stats-update
M5 started Apr 21 2009 19:00:32
M5 executing on zizzer
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

8
tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1453243 # Simulator instruction rate (inst/s)
host_mem_usage 197380 # Number of bytes of host memory used
host_seconds 1114.31 # Real time elapsed on the host
host_tick_rate 864146267 # Simulator tick rate (ticks/s)
host_inst_rate 2698152 # Simulator instruction rate (inst/s)
host_mem_usage 198060 # Number of bytes of host memory used
host_seconds 600.18 # Real time elapsed on the host
host_tick_rate 1604410387 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1619365954 # Number of instructions simulated
sim_seconds 0.962929 # Number of seconds simulated

9
tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini
View file

@ -40,11 +40,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -76,11 +75,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -112,11 +110,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=10000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false

8
tests/long/00.gzip/ref/x86/linux/simple-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 12 2009 13:26:17
M5 revision 8c874c02878a 6042 default qtip tip cpuidfixstats.patch
M5 started Apr 12 2009 13:31:26
M5 executing on tater
M5 compiled Apr 21 2009 19:00:07
M5 revision e6dd09514462 6117 default qtip tip stats-update
M5 started Apr 21 2009 19:10:33
M5 executing on zizzer
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

8
tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 995738 # Simulator instruction rate (inst/s)
host_mem_usage 205000 # Number of bytes of host memory used
host_seconds 1626.30 # Real time elapsed on the host
host_tick_rate 1115968300 # Simulator tick rate (ticks/s)
host_inst_rate 1809758 # Simulator instruction rate (inst/s)
host_mem_usage 205688 # Number of bytes of host memory used
host_seconds 894.80 # Real time elapsed on the host
host_tick_rate 2028277640 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1619365954 # Number of instructions simulated
sim_seconds 1.814897 # Number of seconds simulated

46
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
View file

@ -130,11 +130,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=4
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=4
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -303,11 +302,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=1
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=4
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -437,11 +435,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=4
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=4
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -610,11 +607,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=1
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=4
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -704,14 +700,13 @@ port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio syst
[system.iocache]
type=BaseCache
addr_range=0:18446744073709551615
addr_range=0:8589934591
assoc=8
block_size=64
cpu_side_filter_ranges=549755813888:18446744073709551615
forward_snoops=false
hash_delay=1
latency=50000
max_miss_count=0
mem_side_filter_ranges=0:18446744073709551615
mshrs=20
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -739,11 +734,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=8
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=10000
max_miss_count=0
mem_side_filter_ranges=
mshrs=92
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -768,20 +762,20 @@ mem_side=system.membus.port[3]
[system.membus]
type=Bus
children=responder
children=badaddr_responder
block_size=64
bus_id=1
clock=1000
header_cycles=1
responder_set=false
width=64
default=system.membus.responder.pio
default=system.membus.badaddr_responder.pio
port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side
[system.membus.responder]
[system.membus.badaddr_responder]
type=IsaFake
pio_addr=0
pio_latency=1
pio_latency=1000
pio_size=8
platform=system.tsunami
ret_bad_addr=true
@ -824,32 +818,14 @@ port=3456
[system.toL2Bus]
type=Bus
children=responder
block_size=64
bus_id=0
clock=1000
header_cycles=1
responder_set=false
width=64
default=system.toL2Bus.responder.pio
port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side
[system.toL2Bus.responder]
type=IsaFake
pio_addr=0
pio_latency=1
pio_size=8
platform=system.tsunami
ret_bad_addr=true
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.toL2Bus.default
[system.tsunami]
type=Tsunami
children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart

8
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:30:05
M5 executing on maize
M5 compiled Apr 21 2009 17:45:48
M5 revision e6dd09514462 6117 default qtip tip stats-update
M5 started Apr 21 2009 17:52:26
M5 executing on zizzer
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux

726
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
View file

File diff suppressed because it is too large Load diff

40
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
View file

@ -130,11 +130,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=4
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=4
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -303,11 +302,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=1
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=4
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -397,14 +395,13 @@ port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio syst
[system.iocache]
type=BaseCache
addr_range=0:18446744073709551615
addr_range=0:8589934591
assoc=8
block_size=64
cpu_side_filter_ranges=549755813888:18446744073709551615
forward_snoops=false
hash_delay=1
latency=50000
max_miss_count=0
mem_side_filter_ranges=0:18446744073709551615
mshrs=20
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -432,11 +429,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=8
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=10000
max_miss_count=0
mem_side_filter_ranges=
mshrs=92
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -461,20 +457,20 @@ mem_side=system.membus.port[3]
[system.membus]
type=Bus
children=responder
children=badaddr_responder
block_size=64
bus_id=1
clock=1000
header_cycles=1
responder_set=false
width=64
default=system.membus.responder.pio
default=system.membus.badaddr_responder.pio
port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side
[system.membus.responder]
[system.membus.badaddr_responder]
type=IsaFake
pio_addr=0
pio_latency=1
pio_latency=1000
pio_size=8
platform=system.tsunami
ret_bad_addr=true
@ -517,32 +513,14 @@ port=3456
[system.toL2Bus]
type=Bus
children=responder
block_size=64
bus_id=0
clock=1000
header_cycles=1
responder_set=false
width=64
default=system.toL2Bus.responder.pio
port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.toL2Bus.responder]
type=IsaFake
pio_addr=0
pio_latency=1
pio_size=8
platform=system.tsunami
ret_bad_addr=true
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.toL2Bus.default
[system.tsunami]
type=Tsunami
children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart

10
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
View file

@ -5,12 +5,12 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:30:19
M5 executing on maize
M5 compiled Apr 21 2009 17:45:48
M5 revision e6dd09514462 6117 default qtip tip stats-update
M5 started Apr 21 2009 17:46:13
M5 executing on zizzer
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 1867363148500 because m5_exit instruction encountered
Exiting @ tick 1867362977500 because m5_exit instruction encountered

800
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
View file

@ -1,314 +1,314 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 201864 # Simulator instruction rate (inst/s)
host_mem_usage 294704 # Number of bytes of host memory used
host_seconds 263.00 # Real time elapsed on the host
host_tick_rate 7100171671 # Simulator tick rate (ticks/s)
host_inst_rate 142678 # Simulator instruction rate (inst/s)
host_mem_usage 293540 # Number of bytes of host memory used
host_seconds 372.10 # Real time elapsed on the host
host_tick_rate 5018472256 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 53090630 # Number of instructions simulated
sim_insts 53090223 # Number of instructions simulated
sim_seconds 1.867363 # Number of seconds simulated
sim_ticks 1867363148500 # Number of ticks simulated
sim_ticks 1867362977500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 6937900 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 13339861 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 41537 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 828629 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 12132448 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 14570242 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 1034900 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 8461943 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 974606 # number cycles where commit BW limit reached
system.cpu.BPredUnit.BTBHits 6932886 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 13334785 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 41560 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 829405 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 12127013 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 14563706 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 1034705 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 8461925 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 978098 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle.samples 100617513
system.cpu.commit.COM:committed_per_cycle.samples 100629475
system.cpu.commit.COM:committed_per_cycle.min_value 0
0 76371867 7590.32%
1 10755813 1068.98%
2 5991818 595.50%
3 2987930 296.96%
4 2074332 206.16%
5 671621 66.75%
6 397219 39.48%
7 392307 38.99%
8 974606 96.86%
0 76387036 7590.92%
1 10760374 1069.31%
2 5981089 594.37%
3 2990150 297.14%
4 2079430 206.64%
5 662647 65.85%
6 398739 39.62%
7 391912 38.95%
8 978098 97.20%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
system.cpu.commit.COM:count 56284983 # Number of instructions committed
system.cpu.commit.COM:loads 9308629 # Number of loads committed
system.cpu.commit.COM:membars 228003 # Number of memory barriers committed
system.cpu.commit.COM:refs 15700868 # Number of memory references committed
system.cpu.commit.COM:count 56284559 # Number of instructions committed
system.cpu.commit.COM:loads 9308572 # Number of loads committed
system.cpu.commit.COM:membars 228000 # Number of memory barriers committed
system.cpu.commit.COM:refs 15700770 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 787164 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 56284983 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 667781 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 9518126 # The number of squashed insts skipped by commit
system.cpu.committedInsts 53090630 # Number of Instructions Simulated
system.cpu.committedInsts_total 53090630 # Number of Instructions Simulated
system.cpu.cpi 2.580435 # CPI: Cycles Per Instruction
system.cpu.cpi_total 2.580435 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 214297 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_avg_miss_latency 15516.058460 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11817.323059 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_hits 192128 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_miss_latency 343975500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_rate 0.103450 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_misses 22169 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_mshr_hits 4649 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207039500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.081756 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_misses 17520 # number of LoadLockedReq MSHR misses
system.cpu.dcache.ReadReq_accesses 9342423 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 23886.371687 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22764.504418 # average ReadReq mshr miss latency
system.cpu.commit.branchMispredicts 787906 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 56284559 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 667787 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 9472622 # The number of squashed insts skipped by commit
system.cpu.committedInsts 53090223 # Number of Instructions Simulated
system.cpu.committedInsts_total 53090223 # Number of Instructions Simulated
system.cpu.cpi 2.580471 # CPI: Cycles Per Instruction
system.cpu.cpi_total 2.580471 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 214422 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_avg_miss_latency 15515.537615 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11814.147928 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_hits 192250 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_miss_latency 344010500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_rate 0.103404 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_misses 22172 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_mshr_hits 4650 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207007500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.081717 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_misses 17522 # number of LoadLockedReq MSHR misses
system.cpu.dcache.ReadReq_accesses 9342386 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 23884.018523 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22765.012818 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_hits 7809504 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 36615873000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.164082 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 1532919 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 448215 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 24692749000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.116105 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 1084704 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904972000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.StoreCondReq_accesses 219789 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_avg_miss_latency 56331.265633 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53331.265633 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_hits 189804 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_miss_latency 1689093000 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_rate 0.136426 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_misses 29985 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_mshr_miss_latency 1599138000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.136426 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_misses 29985 # number of StoreCondReq MSHR misses
system.cpu.dcache.WriteReq_accesses 6157295 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 49032.528329 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 54492.949680 # average WriteReq mshr miss latency
system.cpu.dcache.ReadReq_hits 7810012 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 36599249000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.164024 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 1532374 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 447551 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 24696009500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.116118 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 1084823 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904976000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.StoreCondReq_accesses 219797 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_avg_miss_latency 56331.488950 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53331.488950 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_hits 189796 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_miss_latency 1690001000 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_rate 0.136494 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_misses 30001 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_mshr_miss_latency 1599998000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.136494 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_misses 30001 # number of StoreCondReq MSHR misses
system.cpu.dcache.WriteReq_accesses 6157245 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 49037.572489 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 54494.404609 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_hits 3927003 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 109356855672 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.362219 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 2230292 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 1833354 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 21630322460 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.064466 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 396938 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235426497 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.avg_blocked_cycles_no_mshrs 10009.885310 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets 11500 # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 8.828407 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 138181 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 2 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 1383175962 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 23000 # number of cycles access was blocked
system.cpu.dcache.WriteReq_hits 3926713 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 109379874638 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.362261 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 2230532 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 1833591 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 21631063460 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.064467 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 396941 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235842997 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.avg_blocked_cycles_no_mshrs 10022.289139 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets 16500 # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 8.827872 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 137083 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 4 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 1373885462 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 66000 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 15499718 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 38789.408479 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 31264.685707 # average overall mshr miss latency
system.cpu.dcache.demand_hits 11736507 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 145972728672 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.242792 # miss rate for demand accesses
system.cpu.dcache.demand_misses 3763211 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 2281569 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 46323071460 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.095592 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 1481642 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_accesses 15499631 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 38794.252006 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 31264.812048 # average overall mshr miss latency
system.cpu.dcache.demand_hits 11736725 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 145979123638 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.242774 # miss rate for demand accesses
system.cpu.dcache.demand_misses 3762906 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 2281142 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 46327072960 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.095600 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 1481764 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 15499718 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 38789.408479 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 31264.685707 # average overall mshr miss latency
system.cpu.dcache.overall_accesses 15499631 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 38794.252006 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 31264.812048 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 11736507 # number of overall hits
system.cpu.dcache.overall_miss_latency 145972728672 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.242792 # miss rate for overall accesses
system.cpu.dcache.overall_misses 3763211 # number of overall misses
system.cpu.dcache.overall_mshr_hits 2281569 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 46323071460 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.095592 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 1481642 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 2140398497 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_hits 11736725 # number of overall hits
system.cpu.dcache.overall_miss_latency 145979123638 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.242774 # miss rate for overall accesses
system.cpu.dcache.overall_misses 3762906 # number of overall misses
system.cpu.dcache.overall_mshr_hits 2281142 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 46327072960 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.095600 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 1481764 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 2140818997 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 1401991 # number of replacements
system.cpu.dcache.sampled_refs 1402503 # Sample count of references to valid blocks.
system.cpu.dcache.replacements 1402110 # number of replacements
system.cpu.dcache.sampled_refs 1402622 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 511.995429 # Cycle average of tags in use
system.cpu.dcache.total_refs 12381868 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 511.995450 # Cycle average of tags in use
system.cpu.dcache.total_refs 12382168 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 21439000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 430428 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 48410304 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 42525 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 614935 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 72780900 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 37979006 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 13077120 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 1650418 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 134762 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 1151082 # Number of cycles decode is unblocking
system.cpu.dtb.data_accesses 1236420 # DTB accesses
system.cpu.dtb.data_acv 825 # DTB access violations
system.cpu.dtb.data_hits 16772347 # DTB hits
system.cpu.dtb.data_misses 44495 # DTB misses
system.cpu.dcache.writebacks 430447 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 48442278 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 42798 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 614586 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 72711050 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 37969720 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 13062350 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 1643233 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 134839 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 1155126 # Number of cycles decode is unblocking
system.cpu.dtb.data_accesses 1236133 # DTB accesses
system.cpu.dtb.data_acv 823 # DTB access violations
system.cpu.dtb.data_hits 16770289 # DTB hits
system.cpu.dtb.data_misses 44393 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 910052 # DTB read accesses
system.cpu.dtb.read_acv 586 # DTB read access violations
system.cpu.dtb.read_hits 10174508 # DTB read hits
system.cpu.dtb.read_accesses 909859 # DTB read accesses
system.cpu.dtb.read_acv 588 # DTB read access violations
system.cpu.dtb.read_hits 10173052 # DTB read hits
system.cpu.dtb.read_misses 36219 # DTB read misses
system.cpu.dtb.write_accesses 326368 # DTB write accesses
system.cpu.dtb.write_acv 239 # DTB write access violations
system.cpu.dtb.write_hits 6597839 # DTB write hits
system.cpu.dtb.write_misses 8276 # DTB write misses
system.cpu.fetch.Branches 14570242 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 9007841 # Number of cache lines fetched
system.cpu.fetch.Cycles 23500316 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 455597 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 74326781 # Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles 2461 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles 969865 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.106355 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 9007841 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 7972800 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 0.542543 # Number of inst fetches per cycle
system.cpu.dtb.write_accesses 326274 # DTB write accesses
system.cpu.dtb.write_acv 235 # DTB write access violations
system.cpu.dtb.write_hits 6597237 # DTB write hits
system.cpu.dtb.write_misses 8174 # DTB write misses
system.cpu.fetch.Branches 14563706 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 8997144 # Number of cache lines fetched
system.cpu.fetch.Cycles 23480265 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 455601 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 74265234 # Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles 2366 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles 967433 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.106306 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 8997144 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 7967591 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 0.542091 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist.samples 102267931
system.cpu.fetch.rateDist.samples 102272708
system.cpu.fetch.rateDist.min_value 0
0 87815810 8586.84%
1 1050742 102.74%
2 2021882 197.70%
3 969421 94.79%
4 3003437 293.68%
5 686434 67.12%
6 832579 81.41%
7 1218388 119.14%
8 4669238 456.57%
0 87829962 8587.82%
1 1051726 102.84%
2 2021481 197.66%
3 968950 94.74%
4 2998384 293.18%
5 688876 67.36%
6 831559 81.31%
7 1217734 119.07%
8 4664036 456.04%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
system.cpu.icache.ReadReq_accesses 9007841 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 14905.597019 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11907.422251 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 7960337 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 15613672500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.116288 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 1047504 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 51957 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 11854398500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.110520 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 995547 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs 11175.438596 # average number of cycles each access was blocked
system.cpu.icache.ReadReq_accesses 8997144 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 14906.743449 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11907.437092 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 7949609 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 15615335499 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.116430 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 1047535 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 51877 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 11855735000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.110664 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 995658 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs 11545.454545 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 7.997460 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 57 # number of cycles access was blocked
system.cpu.icache.avg_refs 7.985800 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 55 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 637000 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 635000 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 9007841 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 14905.597019 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 11907.422251 # average overall mshr miss latency
system.cpu.icache.demand_hits 7960337 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 15613672500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.116288 # miss rate for demand accesses
system.cpu.icache.demand_misses 1047504 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 51957 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 11854398500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.110520 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 995547 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_accesses 8997144 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 14906.743449 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 11907.437092 # average overall mshr miss latency
system.cpu.icache.demand_hits 7949609 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 15615335499 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.116430 # miss rate for demand accesses
system.cpu.icache.demand_misses 1047535 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 51877 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 11855735000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.110664 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 995658 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 9007841 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 14905.597019 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 11907.422251 # average overall mshr miss latency
system.cpu.icache.overall_accesses 8997144 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 14906.743449 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 11907.437092 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 7960337 # number of overall hits
system.cpu.icache.overall_miss_latency 15613672500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.116288 # miss rate for overall accesses
system.cpu.icache.overall_misses 1047504 # number of overall misses
system.cpu.icache.overall_mshr_hits 51957 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 11854398500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.110520 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 995547 # number of overall MSHR misses
system.cpu.icache.overall_hits 7949609 # number of overall hits
system.cpu.icache.overall_miss_latency 15615335499 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.116430 # miss rate for overall accesses
system.cpu.icache.overall_misses 1047535 # number of overall misses
system.cpu.icache.overall_mshr_hits 51877 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 11855735000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.110664 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 995658 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 994847 # number of replacements
system.cpu.icache.sampled_refs 995358 # Sample count of references to valid blocks.
system.cpu.icache.replacements 994957 # number of replacements
system.cpu.icache.sampled_refs 995468 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 509.772456 # Cycle average of tags in use
system.cpu.icache.total_refs 7960336 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 509.772438 # Cycle average of tags in use
system.cpu.icache.total_refs 7949608 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 25306164000 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 34729008 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 9164699 # Number of branches executed
system.cpu.iew.EXEC:nop 3680668 # number of nop insts executed
system.cpu.iew.EXEC:rate 0.420415 # Inst execution rate
system.cpu.iew.EXEC:refs 17055609 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 6621040 # Number of stores executed
system.cpu.idleCycles 34725081 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 9164165 # Number of branches executed
system.cpu.iew.EXEC:nop 3679313 # number of nop insts executed
system.cpu.iew.EXEC:rate 0.420337 # Inst execution rate
system.cpu.iew.EXEC:refs 17053432 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 6620337 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 34548488 # num instructions consuming a value
system.cpu.iew.WB:count 57002857 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.763990 # average fanout of values written-back
system.cpu.iew.WB:consumers 34505393 # num instructions consuming a value
system.cpu.iew.WB:count 56992809 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.764525 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 26394693 # num instructions producing a value
system.cpu.iew.WB:rate 0.416089 # insts written-back per cycle
system.cpu.iew.WB:sent 57104330 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 856523 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 9726576 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 11055097 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 1799800 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 1048637 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 7027136 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 65932751 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 10434569 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 539744 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 57595615 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 50922 # Number of times the IQ has become full, causing a stall
system.cpu.iew.WB:producers 26380221 # num instructions producing a value
system.cpu.iew.WB:rate 0.416013 # insts written-back per cycle
system.cpu.iew.WB:sent 57095823 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 857525 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 9717535 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 11048107 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 1799892 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 1045221 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 7018400 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 65886993 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 10433095 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 539578 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 57585192 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 49355 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 6567 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 1650418 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 550443 # Number of cycles IEW is unblocking
system.cpu.iew.iewLSQFullEvents 6548 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 1643233 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 548828 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 311143 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 426303 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 11520 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.cacheBlocked 307987 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 427807 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 11074 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 46025 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 15352 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 1746468 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 634897 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 46025 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 380989 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 475534 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 0.387532 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.387532 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 58135361 # Type of FU issued
system.cpu.iew.lsq.thread.0.memOrderViolation 45865 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 15487 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 1739535 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 626202 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 45865 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 381050 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 476475 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 0.387526 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.387526 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 58124772 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
No_OpClass 7284 0.01% # Type of FU issued
IntAlu 39619390 68.15% # Type of FU issued
IntMult 62115 0.11% # Type of FU issued
IntAlu 39611417 68.15% # Type of FU issued
IntMult 62110 0.11% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 25609 0.04% # Type of FU issued
FloatAdd 25607 0.04% # Type of FU issued
FloatCmp 0 0.00% # Type of FU issued
FloatCvt 0 0.00% # Type of FU issued
FloatMult 0 0.00% # Type of FU issued
FloatDiv 3636 0.01% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
MemRead 10789898 18.56% # Type of FU issued
MemWrite 6674141 11.48% # Type of FU issued
IprAccess 953288 1.64% # Type of FU issued
MemRead 10788116 18.56% # Type of FU issued
MemWrite 6673339 11.48% # Type of FU issued
IprAccess 953263 1.64% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
system.cpu.iq.ISSUE:fu_busy_cnt 434481 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.007474 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_busy_cnt 433051 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.007450 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
No_OpClass 0 0.00% # attempts to use FU when none available
IntAlu 52045 11.98% # attempts to use FU when none available
IntAlu 50716 11.71% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 0 0.00% # attempts to use FU when none available
@ -317,44 +317,44 @@ system.cpu.iq.ISSUE:fu_full.start_dist
FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
MemRead 278817 64.17% # attempts to use FU when none available
MemWrite 103619 23.85% # attempts to use FU when none available
MemRead 279321 64.50% # attempts to use FU when none available
MemWrite 103014 23.79% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle::samples 102267931
system.cpu.iq.ISSUE:issued_per_cycle::samples 102272708
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00%
system.cpu.iq.ISSUE:issued_per_cycle::0-1 73151138 71.53%
system.cpu.iq.ISSUE:issued_per_cycle::1-2 14628619 14.30%
system.cpu.iq.ISSUE:issued_per_cycle::2-3 6419666 6.28%
system.cpu.iq.ISSUE:issued_per_cycle::3-4 3934330 3.85%
system.cpu.iq.ISSUE:issued_per_cycle::4-5 2528894 2.47%
system.cpu.iq.ISSUE:issued_per_cycle::5-6 1032607 1.01%
system.cpu.iq.ISSUE:issued_per_cycle::6-7 444582 0.43%
system.cpu.iq.ISSUE:issued_per_cycle::7-8 106443 0.10%
system.cpu.iq.ISSUE:issued_per_cycle::8 21652 0.02%
system.cpu.iq.ISSUE:issued_per_cycle::0-1 73147659 71.52%
system.cpu.iq.ISSUE:issued_per_cycle::1-2 14648372 14.32%
system.cpu.iq.ISSUE:issued_per_cycle::2-3 6417102 6.27%
system.cpu.iq.ISSUE:issued_per_cycle::3-4 3925012 3.84%
system.cpu.iq.ISSUE:issued_per_cycle::4-5 2528533 2.47%
system.cpu.iq.ISSUE:issued_per_cycle::5-6 1035489 1.01%
system.cpu.iq.ISSUE:issued_per_cycle::6-7 441110 0.43%
system.cpu.iq.ISSUE:issued_per_cycle::7-8 106525 0.10%
system.cpu.iq.ISSUE:issued_per_cycle::8 22906 0.02%
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00%
system.cpu.iq.ISSUE:issued_per_cycle::total 102267931
system.cpu.iq.ISSUE:issued_per_cycle::total 102272708
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.568461
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.134174
system.cpu.iq.ISSUE:rate 0.424355 # Inst issue rate
system.cpu.iq.iqInstsAdded 60200389 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 58135361 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 2051694 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 8738375 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 34584 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 1383913 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 4729371 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.568331
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.133996
system.cpu.iq.ISSUE:rate 0.424275 # Inst issue rate
system.cpu.iq.iqInstsAdded 60155940 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 58124772 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 2051740 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 8691644 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 34825 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 1383953 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 4676225 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.fetch_accesses 1303895 # ITB accesses
system.cpu.itb.fetch_acv 943 # ITB acv
system.cpu.itb.fetch_hits 1264480 # ITB hits
system.cpu.itb.fetch_misses 39415 # ITB misses
system.cpu.itb.fetch_accesses 1303750 # ITB accesses
system.cpu.itb.fetch_acv 951 # ITB acv
system.cpu.itb.fetch_hits 1264322 # ITB hits
system.cpu.itb.fetch_misses 39428 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
@ -363,15 +363,15 @@ system.cpu.itb.write_accesses 0 # DT
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.kern.callpal 192656 # number of callpals executed
system.cpu.kern.callpal 192652 # number of callpals executed
system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal_swpctx 4177 2.17% 2.17% # number of callpals executed
system.cpu.kern.callpal_swpctx 4176 2.17% 2.17% # number of callpals executed
system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed
system.cpu.kern.callpal_wrent 7 0.00% 2.20% # number of callpals executed
system.cpu.kern.callpal_swpipl 175684 91.19% 93.39% # number of callpals executed
system.cpu.kern.callpal_swpipl 175681 91.19% 93.39% # number of callpals executed
system.cpu.kern.callpal_rdps 6794 3.53% 96.92% # number of callpals executed
system.cpu.kern.callpal_wrkgp 1 0.00% 96.92% # number of callpals executed
system.cpu.kern.callpal_wrusp 7 0.00% 96.92% # number of callpals executed
@ -381,41 +381,41 @@ system.cpu.kern.callpal_rti 5221 2.71% 99.64% # nu
system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed
system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.hwrei 211815 # number of hwrei instructions executed
system.cpu.kern.inst.quiesce 6383 # number of quiesce instructions executed
system.cpu.kern.ipl_count 183033 # number of times we switched to this ipl
system.cpu.kern.ipl_count_0 74957 40.95% 40.95% # number of times we switched to this ipl
system.cpu.kern.inst.hwrei 211811 # number of hwrei instructions executed
system.cpu.kern.inst.quiesce 6385 # number of quiesce instructions executed
system.cpu.kern.ipl_count 183030 # number of times we switched to this ipl
system.cpu.kern.ipl_count_0 74956 40.95% 40.95% # number of times we switched to this ipl
system.cpu.kern.ipl_count_21 237 0.13% 41.08% # number of times we switched to this ipl
system.cpu.kern.ipl_count_22 1890 1.03% 42.11% # number of times we switched to this ipl
system.cpu.kern.ipl_count_31 105949 57.89% 100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_good 149307 # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good_0 73590 49.29% 49.29% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_count_31 105947 57.89% 100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_good 149305 # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good_0 73589 49.29% 49.29% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good_21 237 0.16% 49.45% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good_22 1890 1.27% 50.71% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good_31 73590 49.29% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks 1867362274000 # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks_0 1824759658500 97.72% 97.72% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks_21 102563000 0.01% 97.72% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks_22 392423000 0.02% 97.75% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks_31 42107629500 2.25% 100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_good_31 73589 49.29% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks 1867362103000 # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks_0 1824761131000 97.72% 97.72% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks_21 102621000 0.01% 97.72% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks_22 392338000 0.02% 97.75% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks_31 42106013000 2.25% 100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_used_0 0.981763 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used_31 0.694579 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.mode_good_kernel 1911
system.cpu.kern.mode_good_user 1741
system.cpu.kern.ipl_used_31 0.694583 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.mode_good_kernel 1910
system.cpu.kern.mode_good_user 1740
system.cpu.kern.mode_good_idle 170
system.cpu.kern.mode_switch_kernel 5973 # number of protection mode switches
system.cpu.kern.mode_switch_user 1741 # number of protection mode switches
system.cpu.kern.mode_switch_kernel 5972 # number of protection mode switches
system.cpu.kern.mode_switch_user 1740 # number of protection mode switches
system.cpu.kern.mode_switch_idle 2095 # number of protection mode switches
system.cpu.kern.mode_switch_good 1.401085 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good_kernel 0.319940 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good 1.400971 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good_kernel 0.319826 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good_idle 0.081146 # fraction of useful protection mode switches
system.cpu.kern.mode_ticks_kernel 31312997500 1.68% 1.68% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks_user 3190588500 0.17% 1.85% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks_idle 1832858680000 98.15% 100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context 4178 # number of times the context was actually changed
system.cpu.kern.mode_ticks_kernel 31331138500 1.68% 1.68% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks_user 3191204500 0.17% 1.85% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks_idle 1832839752000 98.15% 100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context 4177 # number of times the context was actually changed
system.cpu.kern.syscall 326 # number of syscalls executed
system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed
system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed
@ -447,29 +447,29 @@ system.cpu.kern.syscall_98 2 0.61% 97.55% # nu
system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed
system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed
system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed
system.cpu.memDep0.conflictingLoads 3083644 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 2877472 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 11055097 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 7027136 # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles 136996939 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 14276861 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 38259280 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 1099460 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 39573188 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 2235524 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 15708 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 83522905 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 68741813 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 46071316 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 12717646 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 1650418 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 5220588 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 7812034 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 28829228 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 1704991 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 12807732 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 256915 # count of temporary serializing insts renamed
system.cpu.timesIdled 1321478 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.memDep0.conflictingLoads 3077147 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 2881540 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 11048107 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 7018400 # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles 136997789 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 14285499 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 38258957 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 1096982 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 39563718 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 2259510 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 15713 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 83436015 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 68679972 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 46025419 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 12707474 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 1643233 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 5244444 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 7766460 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 28828338 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 1705072 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 12828278 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 257070 # count of temporary serializing insts renamed
system.cpu.timesIdled 1322055 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
@ -483,55 +483,55 @@ system.disk2.dma_write_bytes 8192 # Nu
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.iocache.ReadReq_accesses 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_avg_miss_latency 115277.445087 # average ReadReq miss latency
system.iocache.ReadReq_avg_mshr_miss_latency 63277.445087 # average ReadReq mshr miss latency
system.iocache.ReadReq_miss_latency 19942998 # number of ReadReq miss cycles
system.iocache.ReadReq_avg_miss_latency 115260.104046 # average ReadReq miss latency
system.iocache.ReadReq_avg_mshr_miss_latency 63260.104046 # average ReadReq mshr miss latency
system.iocache.ReadReq_miss_latency 19939998 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_misses 173 # number of ReadReq misses
system.iocache.ReadReq_mshr_miss_latency 10946998 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency 10943998 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses
system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_avg_miss_latency 137802.098720 # average WriteReq miss latency
system.iocache.WriteReq_avg_mshr_miss_latency 85798.754910 # average WriteReq mshr miss latency
system.iocache.WriteReq_miss_latency 5725952806 # number of WriteReq miss cycles
system.iocache.WriteReq_avg_miss_latency 137794.253129 # average WriteReq miss latency
system.iocache.WriteReq_avg_mshr_miss_latency 85790.836302 # average WriteReq mshr miss latency
system.iocache.WriteReq_miss_latency 5725626806 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_misses 41552 # number of WriteReq misses
system.iocache.WriteReq_mshr_miss_latency 3565109864 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency 3564780830 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses
system.iocache.avg_blocked_cycles_no_mshrs 6162.652539 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles_no_mshrs 6161.136802 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.iocache.avg_refs 0 # Average number of references to valid blocks.
system.iocache.blocked_no_mshrs 10476 # number of cycles access was blocked
system.iocache.blocked_no_mshrs 10475 # number of cycles access was blocked
system.iocache.blocked_no_targets 0 # number of cycles access was blocked
system.iocache.blocked_cycles_no_mshrs 64559948 # number of cycles access was blocked
system.iocache.blocked_cycles_no_mshrs 64537908 # number of cycles access was blocked
system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.demand_accesses 41725 # number of demand (read+write) accesses
system.iocache.demand_avg_miss_latency 137708.707106 # average overall miss latency
system.iocache.demand_avg_mshr_miss_latency 85705.377160 # average overall mshr miss latency
system.iocache.demand_avg_miss_latency 137700.822145 # average overall miss latency
system.iocache.demand_avg_mshr_miss_latency 85697.419485 # average overall mshr miss latency
system.iocache.demand_hits 0 # number of demand (read+write) hits
system.iocache.demand_miss_latency 5745895804 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency 5745566804 # number of demand (read+write) miss cycles
system.iocache.demand_miss_rate 1 # miss rate for demand accesses
system.iocache.demand_misses 41725 # number of demand (read+write) misses
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.iocache.demand_mshr_miss_latency 3576056862 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency 3575724828 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.overall_accesses 41725 # number of overall (read+write) accesses
system.iocache.overall_avg_miss_latency 137708.707106 # average overall miss latency
system.iocache.overall_avg_mshr_miss_latency 85705.377160 # average overall mshr miss latency
system.iocache.overall_avg_miss_latency 137700.822145 # average overall miss latency
system.iocache.overall_avg_mshr_miss_latency 85697.419485 # average overall mshr miss latency
system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.iocache.overall_hits 0 # number of overall hits
system.iocache.overall_miss_latency 5745895804 # number of overall miss cycles
system.iocache.overall_miss_latency 5745566804 # number of overall miss cycles
system.iocache.overall_miss_rate 1 # miss rate for overall accesses
system.iocache.overall_misses 41725 # number of overall misses
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
system.iocache.overall_mshr_miss_latency 3576056862 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency 3575724828 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses
system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -539,88 +539,88 @@ system.iocache.overall_mshr_uncacheable_misses 0
system.iocache.replacements 41685 # number of replacements
system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.iocache.tagsinuse 1.267414 # Cycle average of tags in use
system.iocache.tagsinuse 1.267415 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.warmup_cycle 1716180054000 # Cycle when the warmup percentage was hit.
system.iocache.warmup_cycle 1716179713000 # Cycle when the warmup percentage was hit.
system.iocache.writebacks 41512 # number of writebacks
system.l2c.ReadExReq_accesses 300588 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_avg_miss_latency 52362.011561 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency 40213.127257 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_miss_latency 15739392331 # number of ReadExReq miss cycles
system.l2c.ReadExReq_accesses 300582 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_avg_miss_latency 52361.965557 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency 40206.978448 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_miss_latency 15739064331 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_misses 300588 # number of ReadExReq misses
system.l2c.ReadExReq_mshr_miss_latency 12087583496 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_misses 300582 # number of ReadExReq misses
system.l2c.ReadExReq_mshr_miss_latency 12085493996 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_misses 300588 # number of ReadExReq MSHR misses
system.l2c.ReadReq_accesses 2097395 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_avg_miss_latency 52065.516476 # average ReadReq miss latency
system.l2c.ReadReq_avg_mshr_miss_latency 40025.575526 # average ReadReq mshr miss latency
system.l2c.ReadExReq_mshr_misses 300582 # number of ReadExReq MSHR misses
system.l2c.ReadReq_accesses 2097743 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_avg_miss_latency 52046.745492 # average ReadReq miss latency
system.l2c.ReadReq_avg_mshr_miss_latency 40015.135689 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_hits 1786374 # number of ReadReq hits
system.l2c.ReadReq_miss_latency 16193469000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_rate 0.148289 # miss rate for ReadReq accesses
system.l2c.ReadReq_misses 311021 # number of ReadReq misses
system.l2c.ReadReq_hits 1786590 # number of ReadReq hits
system.l2c.ReadReq_miss_latency 16194501000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_rate 0.148328 # miss rate for ReadReq accesses
system.l2c.ReadReq_misses 311153 # number of ReadReq misses
system.l2c.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_miss_latency 12448754500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate 0.148289 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_misses 311020 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_uncacheable_latency 810514000 # number of ReadReq MSHR uncacheable cycles
system.l2c.UpgradeReq_accesses 130249 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_avg_miss_latency 52272.455021 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency 40098.173498 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_miss_latency 6808434994 # number of UpgradeReq miss cycles
system.l2c.ReadReq_mshr_miss_latency 12450789500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate 0.148327 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_misses 311152 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_uncacheable_latency 810515500 # number of ReadReq MSHR uncacheable cycles
system.l2c.UpgradeReq_accesses 130274 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_avg_miss_latency 52273.201045 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency 40097.567435 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_miss_latency 6809838993 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_misses 130249 # number of UpgradeReq misses
system.l2c.UpgradeReq_mshr_miss_latency 5222747000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_misses 130274 # number of UpgradeReq misses
system.l2c.UpgradeReq_mshr_miss_latency 5223670500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_misses 130249 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses 130274 # number of UpgradeReq MSHR misses
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_mshr_uncacheable_latency 1115855498 # number of WriteReq MSHR uncacheable cycles
system.l2c.Writeback_accesses 430428 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_hits 430428 # number of Writeback hits
system.l2c.WriteReq_mshr_uncacheable_latency 1116273498 # number of WriteReq MSHR uncacheable cycles
system.l2c.Writeback_accesses 430447 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_hits 430447 # number of Writeback hits
system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.l2c.avg_refs 4.596635 # Average number of references to valid blocks.
system.l2c.avg_refs 4.597861 # Average number of references to valid blocks.
system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_no_targets 0 # number of cycles access was blocked
system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.demand_accesses 2397983 # number of demand (read+write) accesses
system.l2c.demand_avg_miss_latency 52211.235170 # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency 40117.751887 # average overall mshr miss latency
system.l2c.demand_hits 1786374 # number of demand (read+write) hits
system.l2c.demand_miss_latency 31932861331 # number of demand (read+write) miss cycles
system.l2c.demand_miss_rate 0.255051 # miss rate for demand accesses
system.l2c.demand_misses 611609 # number of demand (read+write) misses
system.l2c.demand_accesses 2398325 # number of demand (read+write) accesses
system.l2c.demand_avg_miss_latency 52201.631966 # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency 40109.399667 # average overall mshr miss latency
system.l2c.demand_hits 1786590 # number of demand (read+write) hits
system.l2c.demand_miss_latency 31933565331 # number of demand (read+write) miss cycles
system.l2c.demand_miss_rate 0.255068 # miss rate for demand accesses
system.l2c.demand_misses 611735 # number of demand (read+write) misses
system.l2c.demand_mshr_hits 1 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency 24536337996 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_rate 0.255051 # mshr miss rate for demand accesses
system.l2c.demand_mshr_misses 611608 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_miss_latency 24536283496 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_rate 0.255067 # mshr miss rate for demand accesses
system.l2c.demand_mshr_misses 611734 # number of demand (read+write) MSHR misses
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.overall_accesses 2397983 # number of overall (read+write) accesses
system.l2c.overall_avg_miss_latency 52211.235170 # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency 40117.751887 # average overall mshr miss latency
system.l2c.overall_accesses 2398325 # number of overall (read+write) accesses
system.l2c.overall_avg_miss_latency 52201.631966 # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency 40109.399667 # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
system.l2c.overall_hits 1786374 # number of overall hits
system.l2c.overall_miss_latency 31932861331 # number of overall miss cycles
system.l2c.overall_miss_rate 0.255051 # miss rate for overall accesses
system.l2c.overall_misses 611609 # number of overall misses
system.l2c.overall_hits 1786590 # number of overall hits
system.l2c.overall_miss_latency 31933565331 # number of overall miss cycles
system.l2c.overall_miss_rate 0.255068 # miss rate for overall accesses
system.l2c.overall_misses 611735 # number of overall misses
system.l2c.overall_mshr_hits 1 # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency 24536337996 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_rate 0.255051 # mshr miss rate for overall accesses
system.l2c.overall_mshr_misses 611608 # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_latency 1926369498 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_miss_latency 24536283496 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_rate 0.255067 # mshr miss rate for overall accesses
system.l2c.overall_mshr_misses 611734 # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_latency 1926788998 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.l2c.replacements 396031 # number of replacements
system.l2c.sampled_refs 427707 # Sample count of references to valid blocks.
system.l2c.replacements 396039 # number of replacements
system.l2c.sampled_refs 427720 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.l2c.tagsinuse 30680.970322 # Cycle average of tags in use
system.l2c.total_refs 1966013 # Total number of references to valid blocks.
system.l2c.tagsinuse 30690.397149 # Cycle average of tags in use
system.l2c.total_refs 1966597 # Total number of references to valid blocks.
system.l2c.warmup_cycle 5645091000 # Cycle when the warmup percentage was hit.
system.l2c.writebacks 119091 # number of writebacks
system.l2c.writebacks 119094 # number of writebacks
system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post

8
tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:30:33
M5 executing on maize
M5 compiled Apr 21 2009 18:04:32
M5 revision e6dd09514462 6117 default qtip tip stats-update
M5 started Apr 21 2009 18:06:05
M5 executing on zizzer
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

8
tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 3425998 # Simulator instruction rate (inst/s)
host_mem_usage 331732 # Number of bytes of host memory used
host_seconds 71.17 # Real time elapsed on the host
host_tick_rate 1717182841 # Simulator tick rate (ticks/s)
host_inst_rate 2430508 # Simulator instruction rate (inst/s)
host_mem_usage 329972 # Number of bytes of host memory used
host_seconds 100.32 # Real time elapsed on the host
host_tick_rate 1218223693 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 243835278 # Number of instructions simulated
sim_seconds 0.122216 # Number of seconds simulated

9
tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
View file

@ -40,11 +40,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -76,11 +75,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -112,11 +110,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=10000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false

8
tests/long/10.mcf/ref/sparc/linux/simple-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:30:42
M5 executing on maize
M5 compiled Apr 21 2009 18:04:32
M5 revision e6dd09514462 6117 default qtip tip stats-update
M5 started Apr 21 2009 18:10:11
M5 executing on zizzer
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

8
tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1860125 # Simulator instruction rate (inst/s)
host_mem_usage 339272 # Number of bytes of host memory used
host_seconds 131.09 # Real time elapsed on the host
host_tick_rate 2795388911 # Simulator tick rate (ticks/s)
host_inst_rate 1286984 # Simulator instruction rate (inst/s)
host_mem_usage 337604 # Number of bytes of host memory used
host_seconds 189.46 # Real time elapsed on the host
host_tick_rate 1934075040 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 243835278 # Number of instructions simulated
sim_seconds 0.366435 # Number of seconds simulated

8
tests/long/10.mcf/ref/x86/linux/simple-atomic/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 12 2009 13:26:17
M5 revision 8c874c02878a 6042 default qtip tip cpuidfixstats.patch
M5 started Apr 12 2009 13:27:47
M5 executing on tater
M5 compiled Apr 21 2009 19:00:07
M5 revision e6dd09514462 6117 default qtip tip stats-update
M5 started Apr 21 2009 19:23:20
M5 executing on zizzer
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

8
tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 991817 # Simulator instruction rate (inst/s)
host_mem_usage 331908 # Number of bytes of host memory used
host_seconds 271.91 # Real time elapsed on the host
host_tick_rate 605700319 # Simulator tick rate (ticks/s)
host_inst_rate 1596079 # Simulator instruction rate (inst/s)
host_mem_usage 332596 # Number of bytes of host memory used
host_seconds 168.97 # Real time elapsed on the host
host_tick_rate 974720885 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 269686785 # Number of instructions simulated
sim_seconds 0.164697 # Number of seconds simulated

9
tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini
View file

@ -40,11 +40,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -76,11 +75,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -112,11 +110,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=10000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false

8
tests/long/10.mcf/ref/x86/linux/simple-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 12 2009 13:26:17
M5 revision 8c874c02878a 6042 default qtip tip cpuidfixstats.patch
M5 started Apr 12 2009 13:27:47
M5 executing on tater
M5 compiled Apr 21 2009 19:00:07
M5 revision e6dd09514462 6117 default qtip tip stats-update
M5 started Apr 21 2009 19:25:28
M5 executing on zizzer
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

8
tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 614932 # Simulator instruction rate (inst/s)
host_mem_usage 339532 # Number of bytes of host memory used
host_seconds 438.56 # Real time elapsed on the host
host_tick_rate 870160390 # Simulator tick rate (ticks/s)
host_inst_rate 1561663 # Simulator instruction rate (inst/s)
host_mem_usage 340216 # Number of bytes of host memory used
host_seconds 172.69 # Real time elapsed on the host
host_tick_rate 2209830759 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 269686785 # Number of instructions simulated
sim_seconds 0.381621 # Number of seconds simulated

8
tests/long/20.parser/ref/x86/linux/simple-atomic/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 12 2009 13:26:17
M5 revision 8c874c02878a 6042 default qtip tip cpuidfixstats.patch
M5 started Apr 12 2009 13:27:47
M5 executing on tater
M5 compiled Apr 21 2009 19:00:07
M5 revision e6dd09514462 6117 default qtip tip stats-update
M5 started Apr 21 2009 19:26:09
M5 executing on zizzer
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

8
tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1354692 # Simulator instruction rate (inst/s)
host_mem_usage 201092 # Number of bytes of host memory used
host_seconds 1103.93 # Real time elapsed on the host
host_tick_rate 786714284 # Simulator tick rate (ticks/s)
host_inst_rate 2677527 # Simulator instruction rate (inst/s)
host_mem_usage 201788 # Number of bytes of host memory used
host_seconds 558.53 # Real time elapsed on the host
host_tick_rate 1554928126 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1495482368 # Number of instructions simulated
sim_seconds 0.868476 # Number of seconds simulated

9
tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
View file

@ -40,11 +40,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -76,11 +75,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -112,11 +110,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=10000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false

8
tests/long/20.parser/ref/x86/linux/simple-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 12 2009 13:26:17
M5 revision 8c874c02878a 6042 default qtip tip cpuidfixstats.patch
M5 started Apr 12 2009 13:27:47
M5 executing on tater
M5 compiled Apr 21 2009 19:00:07
M5 revision e6dd09514462 6117 default qtip tip stats-update
M5 started Apr 21 2009 19:28:21
M5 executing on zizzer
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

8
tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 965325 # Simulator instruction rate (inst/s)
host_mem_usage 208960 # Number of bytes of host memory used
host_seconds 1549.20 # Real time elapsed on the host
host_tick_rate 1111767915 # Simulator tick rate (ticks/s)
host_inst_rate 1120182 # Simulator instruction rate (inst/s)
host_mem_usage 209372 # Number of bytes of host memory used
host_seconds 1335.04 # Real time elapsed on the host
host_tick_rate 1290116936 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1495482368 # Number of instructions simulated
sim_seconds 1.722353 # Number of seconds simulated

13
tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
View file

@ -104,11 +104,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -277,11 +276,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -313,11 +311,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -356,12 +353,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing
cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/eon
executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
gid=100
input=cin
max_stack_size=67108864

10
tests/long/30.eon/ref/alpha/tru64/o3-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 14 2009 23:40:03
M5 revision 4208b24ee3ad 6033 default qtip tip new-thread-status-stats-update
M5 started Apr 14 2009 23:48:49
M5 executing on phenom
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing
M5 compiled Apr 21 2009 16:38:39
M5 revision e6dd09514462 6117 default qtip tip stats-update
M5 started Apr 21 2009 17:15:52
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

8
tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 195698 # Simulator instruction rate (inst/s)
host_mem_usage 215252 # Number of bytes of host memory used
host_seconds 1919.15 # Real time elapsed on the host
host_tick_rate 70341803 # Simulator tick rate (ticks/s)
host_inst_rate 243057 # Simulator instruction rate (inst/s)
host_mem_usage 211796 # Number of bytes of host memory used
host_seconds 1545.21 # Real time elapsed on the host
host_tick_rate 87364560 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 375574819 # Number of instructions simulated
sim_seconds 0.134997 # Number of seconds simulated

8
tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:41:56
M5 executing on maize
M5 compiled Apr 21 2009 16:38:39
M5 revision e6dd09514462 6117 default qtip tip stats-update
M5 started Apr 21 2009 16:39:12
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

8
tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 5193663 # Simulator instruction rate (inst/s)
host_mem_usage 205028 # Number of bytes of host memory used
host_seconds 76.76 # Real time elapsed on the host
host_tick_rate 2596825201 # Simulator tick rate (ticks/s)
host_inst_rate 3427488 # Simulator instruction rate (inst/s)
host_mem_usage 203296 # Number of bytes of host memory used
host_seconds 116.31 # Real time elapsed on the host
host_tick_rate 1713741057 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 398664595 # Number of instructions simulated
sim_seconds 0.199332 # Number of seconds simulated

9
tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
View file

@ -40,11 +40,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -76,11 +75,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -112,11 +110,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=10000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false

8
tests/long/30.eon/ref/alpha/tru64/simple-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:44:12
M5 executing on maize
M5 compiled Apr 21 2009 16:38:39
M5 revision e6dd09514462 6117 default qtip tip stats-update
M5 started Apr 21 2009 16:39:04
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

8
tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 2545334 # Simulator instruction rate (inst/s)
host_mem_usage 212560 # Number of bytes of host memory used
host_seconds 156.63 # Real time elapsed on the host
host_tick_rate 3622337158 # Simulator tick rate (ticks/s)
host_inst_rate 1575428 # Simulator instruction rate (inst/s)
host_mem_usage 210936 # Number of bytes of host memory used
host_seconds 253.05 # Real time elapsed on the host
host_tick_rate 2242037981 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 398664609 # Number of instructions simulated
sim_seconds 0.567352 # Number of seconds simulated

13
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
View file

@ -104,11 +104,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -277,11 +276,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -313,11 +311,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -356,12 +353,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=perlbmk -I. -I lib lgred.makerand.pl
cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing
cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/perlbmk
executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
gid=100
input=cin
max_stack_size=67108864

10
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 14 2009 23:40:03
M5 revision 4208b24ee3ad 6033 default qtip tip new-thread-status-stats-update
M5 started Apr 14 2009 23:46:17
M5 executing on phenom
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing
M5 compiled Apr 21 2009 16:38:39
M5 revision e6dd09514462 6117 default qtip tip stats-update
M5 started Apr 21 2009 16:44:16
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

8
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 193760 # Simulator instruction rate (inst/s)
host_mem_usage 215160 # Number of bytes of host memory used
host_seconds 9408.76 # Real time elapsed on the host
host_tick_rate 74947150 # Simulator tick rate (ticks/s)
host_inst_rate 191030 # Simulator instruction rate (inst/s)
host_mem_usage 211708 # Number of bytes of host memory used
host_seconds 9543.22 # Real time elapsed on the host
host_tick_rate 73891181 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1823043370 # Number of instructions simulated
sim_seconds 0.705159 # Number of seconds simulated

8
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:38:04
M5 executing on maize
M5 compiled Apr 21 2009 16:38:39
M5 revision e6dd09514462 6117 default qtip tip stats-update
M5 started Apr 21 2009 16:41:45
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

8
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 5314394 # Simulator instruction rate (inst/s)
host_mem_usage 204196 # Number of bytes of host memory used
host_seconds 378.03 # Real time elapsed on the host
host_tick_rate 2657768720 # Simulator tick rate (ticks/s)
host_inst_rate 3366150 # Simulator instruction rate (inst/s)
host_mem_usage 202468 # Number of bytes of host memory used
host_seconds 596.82 # Real time elapsed on the host
host_tick_rate 1683437750 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2008987605 # Number of instructions simulated
sim_seconds 1.004711 # Number of seconds simulated

9
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
View file

@ -40,11 +40,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -76,11 +75,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -112,11 +110,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=10000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false

8
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:45:29
M5 executing on maize
M5 compiled Apr 21 2009 16:38:39
M5 revision e6dd09514462 6117 default qtip tip stats-update
M5 started Apr 21 2009 16:39:12
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

8
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 2595694 # Simulator instruction rate (inst/s)
host_mem_usage 211736 # Number of bytes of host memory used
host_seconds 773.97 # Real time elapsed on the host
host_tick_rate 3637030411 # Simulator tick rate (ticks/s)
host_inst_rate 1413347 # Simulator instruction rate (inst/s)
host_mem_usage 210092 # Number of bytes of host memory used
host_seconds 1421.44 # Real time elapsed on the host
host_tick_rate 1980352310 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2008987605 # Number of instructions simulated
sim_seconds 2.814951 # Number of seconds simulated

13
tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
View file

@ -104,11 +104,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -277,11 +276,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -313,11 +311,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -356,12 +353,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=vortex lendian.raw
cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing
cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/vortex
executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
gid=100
input=cin
max_stack_size=67108864

10
tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 14 2009 23:40:03
M5 revision 4208b24ee3ad 6033 default qtip tip new-thread-status-stats-update
M5 started Apr 14 2009 23:40:05
M5 executing on phenom
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing
M5 compiled Apr 21 2009 16:38:39
M5 revision e6dd09514462 6117 default qtip tip stats-update
M5 started Apr 21 2009 16:52:32
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

8
tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 213847 # Simulator instruction rate (inst/s)
host_mem_usage 218620 # Number of bytes of host memory used
host_seconds 372.19 # Real time elapsed on the host
host_tick_rate 72905538 # Simulator tick rate (ticks/s)
host_inst_rate 274491 # Simulator instruction rate (inst/s)
host_mem_usage 215172 # Number of bytes of host memory used
host_seconds 289.96 # Real time elapsed on the host
host_tick_rate 93580527 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 79591756 # Number of instructions simulated
sim_seconds 0.027135 # Number of seconds simulated

8
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:43:53
M5 executing on maize
M5 compiled Apr 21 2009 16:38:39
M5 revision e6dd09514462 6117 default qtip tip stats-update
M5 started Apr 21 2009 16:57:23
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

8
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 5274353 # Simulator instruction rate (inst/s)
host_mem_usage 207596 # Number of bytes of host memory used
host_seconds 16.75 # Real time elapsed on the host
host_tick_rate 2640164541 # Simulator tick rate (ticks/s)
host_inst_rate 5366735 # Simulator instruction rate (inst/s)
host_mem_usage 205860 # Number of bytes of host memory used
host_seconds 16.46 # Real time elapsed on the host
host_tick_rate 2686413423 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 88340673 # Number of instructions simulated
sim_seconds 0.044221 # Number of seconds simulated

9
tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
View file

@ -40,11 +40,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -76,11 +75,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -112,11 +110,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=10000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false

8
tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:30:03
M5 executing on maize
M5 compiled Apr 21 2009 16:38:39
M5 revision e6dd09514462 6117 default qtip tip stats-update
M5 started Apr 21 2009 16:43:17
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

8
tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 2447162 # Simulator instruction rate (inst/s)
host_mem_usage 215136 # Number of bytes of host memory used
host_seconds 36.10 # Real time elapsed on the host
host_tick_rate 3744340356 # Simulator tick rate (ticks/s)
host_inst_rate 1524580 # Simulator instruction rate (inst/s)
host_mem_usage 213492 # Number of bytes of host memory used
host_seconds 57.94 # Real time elapsed on the host
host_tick_rate 2332726052 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 88340673 # Number of instructions simulated
sim_seconds 0.135169 # Number of seconds simulated

8
tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:31:45
M5 executing on maize
M5 compiled Apr 21 2009 18:04:32
M5 revision e6dd09514462 6117 default qtip tip stats-update
M5 started Apr 21 2009 18:05:08
M5 executing on zizzer
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

8
tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 3453262 # Simulator instruction rate (inst/s)
host_mem_usage 208432 # Number of bytes of host memory used
host_seconds 39.42 # Real time elapsed on the host
host_tick_rate 1728626295 # Simulator tick rate (ticks/s)
host_inst_rate 2400032 # Simulator instruction rate (inst/s)
host_mem_usage 206680 # Number of bytes of host memory used
host_seconds 56.72 # Real time elapsed on the host
host_tick_rate 1201405231 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 136139203 # Number of instructions simulated
sim_seconds 0.068149 # Number of seconds simulated

9
tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
View file

@ -40,11 +40,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -76,11 +75,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -112,11 +110,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=10000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false

8
tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:30:34
M5 executing on maize
M5 compiled Apr 21 2009 18:04:32
M5 revision e6dd09514462 6117 default qtip tip stats-update
M5 started Apr 21 2009 18:15:57
M5 executing on zizzer
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

8
tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1887759 # Simulator instruction rate (inst/s)
host_mem_usage 215972 # Number of bytes of host memory used
host_seconds 72.12 # Real time elapsed on the host
host_tick_rate 2820090693 # Simulator tick rate (ticks/s)
host_inst_rate 1167251 # Simulator instruction rate (inst/s)
host_mem_usage 214304 # Number of bytes of host memory used
host_seconds 116.63 # Real time elapsed on the host
host_tick_rate 1743737825 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 136139203 # Number of instructions simulated
sim_seconds 0.203377 # Number of seconds simulated

13
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
View file

@ -104,11 +104,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -277,11 +276,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -313,11 +311,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -356,12 +353,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing
cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/bzip2
executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
gid=100
input=cin
max_stack_size=67108864

10
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 14 2009 23:40:03
M5 revision 4208b24ee3ad 6033 default qtip tip new-thread-status-stats-update
M5 started Apr 15 2009 00:17:29
M5 executing on phenom
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing
M5 compiled Apr 21 2009 16:38:39
M5 revision e6dd09514462 6117 default qtip tip stats-update
M5 started Apr 21 2009 16:57:40
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

8
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 188573 # Simulator instruction rate (inst/s)
host_mem_usage 207604 # Number of bytes of host memory used
host_seconds 9206.20 # Real time elapsed on the host
host_tick_rate 80631433 # Simulator tick rate (ticks/s)
host_inst_rate 165473 # Simulator instruction rate (inst/s)
host_mem_usage 204148 # Number of bytes of host memory used
host_seconds 10491.39 # Real time elapsed on the host
host_tick_rate 70754150 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1736043781 # Number of instructions simulated
sim_seconds 0.742309 # Number of seconds simulated

8
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:44:24
M5 executing on maize
M5 compiled Apr 21 2009 16:38:39
M5 revision e6dd09514462 6117 default qtip tip stats-update
M5 started Apr 21 2009 16:59:02
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

8
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 5417867 # Simulator instruction rate (inst/s)
host_mem_usage 197364 # Number of bytes of host memory used
host_seconds 335.89 # Real time elapsed on the host
host_tick_rate 2718753958 # Simulator tick rate (ticks/s)
host_inst_rate 3729984 # Simulator instruction rate (inst/s)
host_mem_usage 195632 # Number of bytes of host memory used
host_seconds 487.88 # Real time elapsed on the host
host_tick_rate 1871753572 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1819780127 # Number of instructions simulated
sim_seconds 0.913189 # Number of seconds simulated

9
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
View file

@ -40,11 +40,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -76,11 +75,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -112,11 +110,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=10000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false

8
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:43:13
M5 executing on maize
M5 compiled Apr 21 2009 16:38:39
M5 revision e6dd09514462 6117 default qtip tip stats-update
M5 started Apr 21 2009 16:41:08
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

8
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 2385042 # Simulator instruction rate (inst/s)
host_mem_usage 204904 # Number of bytes of host memory used
host_seconds 763.00 # Real time elapsed on the host
host_tick_rate 3575360927 # Simulator tick rate (ticks/s)
host_inst_rate 1697488 # Simulator instruction rate (inst/s)
host_mem_usage 203260 # Number of bytes of host memory used
host_seconds 1072.04 # Real time elapsed on the host
host_tick_rate 2544665146 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1819780127 # Number of instructions simulated
sim_seconds 2.727991 # Number of seconds simulated

8
tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 12 2009 13:26:17
M5 revision 8c874c02878a 6042 default qtip tip cpuidfixstats.patch
M5 started Apr 12 2009 13:27:47
M5 executing on tater
M5 compiled Apr 21 2009 19:00:07
M5 revision e6dd09514462 6117 default qtip tip stats-update
M5 started Apr 21 2009 19:35:29
M5 executing on zizzer
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

8
tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1691472 # Simulator instruction rate (inst/s)
host_mem_usage 197552 # Number of bytes of host memory used
host_seconds 2750.96 # Real time elapsed on the host
host_tick_rate 1028427031 # Simulator tick rate (ticks/s)
host_inst_rate 2097364 # Simulator instruction rate (inst/s)
host_mem_usage 197956 # Number of bytes of host memory used
host_seconds 2218.58 # Real time elapsed on the host
host_tick_rate 1275211959 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 4653176270 # Number of instructions simulated
sim_seconds 2.829164 # Number of seconds simulated

9
tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini
View file

@ -40,11 +40,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -76,11 +75,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -112,11 +110,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=10000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false

8
tests/long/60.bzip2/ref/x86/linux/simple-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 12 2009 13:26:17
M5 revision 8c874c02878a 6042 default qtip tip cpuidfixstats.patch
M5 started Apr 12 2009 13:27:47
M5 executing on tater
M5 compiled Apr 21 2009 19:00:07
M5 revision e6dd09514462 6117 default qtip tip stats-update
M5 started Apr 21 2009 19:50:36
M5 executing on zizzer
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

8
tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1124863 # Simulator instruction rate (inst/s)
host_mem_usage 205172 # Number of bytes of host memory used
host_seconds 4136.66 # Real time elapsed on the host
host_tick_rate 1447560054 # Simulator tick rate (ticks/s)
host_inst_rate 1080301 # Simulator instruction rate (inst/s)
host_mem_usage 205584 # Number of bytes of host memory used
host_seconds 4307.30 # Real time elapsed on the host
host_tick_rate 1390213645 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 4653176270 # Number of instructions simulated
sim_seconds 5.988064 # Number of seconds simulated

13
tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
View file

@ -104,11 +104,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -277,11 +276,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -313,11 +311,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -356,12 +353,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing
cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/twolf
executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
gid=100
input=cin
max_stack_size=67108864

10
tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 14 2009 23:40:03
M5 revision 4208b24ee3ad 6033 default qtip tip new-thread-status-stats-update
M5 started Apr 14 2009 23:40:05
M5 executing on phenom
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing
M5 compiled Apr 21 2009 16:38:39
M5 revision e6dd09514462 6117 default qtip tip stats-update
M5 started Apr 21 2009 17:02:55
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

8
tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 160619 # Simulator instruction rate (inst/s)
host_mem_usage 212880 # Number of bytes of host memory used
host_seconds 524.10 # Real time elapsed on the host
host_tick_rate 77883837 # Simulator tick rate (ticks/s)
host_inst_rate 199037 # Simulator instruction rate (inst/s)
host_mem_usage 209432 # Number of bytes of host memory used
host_seconds 422.94 # Real time elapsed on the host
host_tick_rate 96512612 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 84179709 # Number of instructions simulated
sim_seconds 0.040819 # Number of seconds simulated

8
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:36:46
M5 executing on maize
M5 compiled Apr 21 2009 16:38:39
M5 revision e6dd09514462 6117 default qtip tip stats-update
M5 started Apr 21 2009 16:51:42
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

8
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 5529646 # Simulator instruction rate (inst/s)
host_mem_usage 202292 # Number of bytes of host memory used
host_seconds 16.62 # Real time elapsed on the host
host_tick_rate 2764786682 # Simulator tick rate (ticks/s)
host_inst_rate 5612458 # Simulator instruction rate (inst/s)
host_mem_usage 200556 # Number of bytes of host memory used
host_seconds 16.38 # Real time elapsed on the host
host_tick_rate 2806199168 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 91903056 # Number of instructions simulated
sim_seconds 0.045952 # Number of seconds simulated

9
tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
View file

@ -40,11 +40,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -76,11 +75,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -112,11 +110,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=10000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false

8
tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:33:56
M5 executing on maize
M5 compiled Apr 21 2009 16:38:39
M5 revision e6dd09514462 6117 default qtip tip stats-update
M5 started Apr 21 2009 16:51:59
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

8
tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 2783619 # Simulator instruction rate (inst/s)
host_mem_usage 209832 # Number of bytes of host memory used
host_seconds 33.02 # Real time elapsed on the host
host_tick_rate 3596666384 # Simulator tick rate (ticks/s)
host_inst_rate 2784324 # Simulator instruction rate (inst/s)
host_mem_usage 208188 # Number of bytes of host memory used
host_seconds 33.01 # Real time elapsed on the host
host_tick_rate 3597581254 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 91903056 # Number of instructions simulated
sim_seconds 0.118747 # Number of seconds simulated

8
tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:32:55
M5 executing on maize
M5 compiled Apr 21 2009 18:04:32
M5 revision e6dd09514462 6117 default qtip tip stats-update
M5 started Apr 21 2009 18:14:36
M5 executing on zizzer
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

8
tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 3173092 # Simulator instruction rate (inst/s)
host_mem_usage 204068 # Number of bytes of host memory used
host_seconds 60.96 # Real time elapsed on the host
host_tick_rate 1586549351 # Simulator tick rate (ticks/s)
host_inst_rate 2403614 # Simulator instruction rate (inst/s)
host_mem_usage 202316 # Number of bytes of host memory used
host_seconds 80.48 # Real time elapsed on the host
host_tick_rate 1201810632 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 193444769 # Number of instructions simulated
sim_seconds 0.096723 # Number of seconds simulated

9
tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
View file

@ -40,11 +40,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -76,11 +75,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -112,11 +110,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=10000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false

8
tests/long/70.twolf/ref/sparc/linux/simple-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 8 2009 12:30:02
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
M5 started Apr 8 2009 12:31:47
M5 executing on maize
M5 compiled Apr 21 2009 18:04:32
M5 revision e6dd09514462 6117 default qtip tip stats-update
M5 started Apr 21 2009 18:07:46
M5 executing on zizzer
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

8
tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1944755 # Simulator instruction rate (inst/s)
host_mem_usage 211604 # Number of bytes of host memory used
host_seconds 99.47 # Real time elapsed on the host
host_tick_rate 2720193548 # Simulator tick rate (ticks/s)
host_inst_rate 1335116 # Simulator instruction rate (inst/s)
host_mem_usage 209936 # Number of bytes of host memory used
host_seconds 144.89 # Real time elapsed on the host
host_tick_rate 1867472873 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 193444769 # Number of instructions simulated
sim_seconds 0.270578 # Number of seconds simulated

10
tests/long/70.twolf/ref/x86/linux/simple-atomic/simout
View file

@ -5,13 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 12 2009 13:26:17
M5 revision 8c874c02878a 6042 default qtip tip cpuidfixstats.patch
M5 started Apr 12 2009 13:27:47
M5 executing on tater
M5 compiled Apr 21 2009 19:00:07
M5 revision e6dd09514462 6117 default qtip tip stats-update
M5 started Apr 21 2009 19:52:32
M5 executing on zizzer
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic
Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sav
Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

8
tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1002077 # Simulator instruction rate (inst/s)
host_mem_usage 204648 # Number of bytes of host memory used
host_seconds 218.14 # Real time elapsed on the host
host_tick_rate 595983507 # Simulator tick rate (ticks/s)
host_inst_rate 1749933 # Simulator instruction rate (inst/s)
host_mem_usage 205336 # Number of bytes of host memory used
host_seconds 124.92 # Real time elapsed on the host
host_tick_rate 1040768333 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 218595312 # Number of instructions simulated
sim_seconds 0.130009 # Number of seconds simulated

9
tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini
View file

@ -40,11 +40,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -76,11 +75,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
@ -112,11 +110,10 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
forward_snoops=true
hash_delay=1
latency=10000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_cache_check_push=true
prefetch_data_accesses_only=false

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