Mostly just config.ini updates, though the different response latency for bad addresses caused very minor timing changes in the O3 Linux boot tests.
50 lines
4.5 KiB
Text
50 lines
4.5 KiB
Text
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---------- Begin Simulation Statistics ----------
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host_inst_rate 5612458 # Simulator instruction rate (inst/s)
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host_mem_usage 200556 # Number of bytes of host memory used
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host_seconds 16.38 # Real time elapsed on the host
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host_tick_rate 2806199168 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 91903056 # Number of instructions simulated
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sim_seconds 0.045952 # Number of seconds simulated
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sim_ticks 45951567500 # Number of ticks simulated
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system.cpu.dtb.data_accesses 26497334 # DTB accesses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_hits 26497301 # DTB hits
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system.cpu.dtb.data_misses 33 # DTB misses
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.read_accesses 19996208 # DTB read accesses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_hits 19996198 # DTB read hits
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system.cpu.dtb.read_misses 10 # DTB read misses
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system.cpu.dtb.write_accesses 6501126 # DTB write accesses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_hits 6501103 # DTB write hits
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system.cpu.dtb.write_misses 23 # DTB write misses
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.fetch_accesses 91903136 # ITB accesses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_hits 91903089 # ITB hits
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system.cpu.itb.fetch_misses 47 # ITB misses
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.numCycles 91903136 # number of cpu cycles simulated
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system.cpu.num_insts 91903056 # Number of instructions executed
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system.cpu.num_refs 26537141 # Number of memory references
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system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
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---------- End Simulation Statistics ----------
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