7b40c36fbd
Mostly just config.ini updates, though the different response latency for bad addresses caused very minor timing changes in the O3 Linux boot tests.
656 lines
70 KiB
Text
656 lines
70 KiB
Text
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---------- Begin Simulation Statistics ----------
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host_inst_rate 142678 # Simulator instruction rate (inst/s)
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host_mem_usage 293540 # Number of bytes of host memory used
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host_seconds 372.10 # Real time elapsed on the host
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host_tick_rate 5018472256 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 53090223 # Number of instructions simulated
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sim_seconds 1.867363 # Number of seconds simulated
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sim_ticks 1867362977500 # Number of ticks simulated
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.BTBHits 6932886 # Number of BTB hits
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system.cpu.BPredUnit.BTBLookups 13334785 # Number of BTB lookups
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system.cpu.BPredUnit.RASInCorrect 41560 # Number of incorrect RAS predictions.
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system.cpu.BPredUnit.condIncorrect 829405 # Number of conditional branches incorrect
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system.cpu.BPredUnit.condPredicted 12127013 # Number of conditional branches predicted
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system.cpu.BPredUnit.lookups 14563706 # Number of BP lookups
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system.cpu.BPredUnit.usedRAS 1034705 # Number of times the RAS was used to get a target.
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system.cpu.commit.COM:branches 8461925 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 978098 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle.samples 100629475
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system.cpu.commit.COM:committed_per_cycle.min_value 0
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0 76387036 7590.92%
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1 10760374 1069.31%
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2 5981089 594.37%
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3 2990150 297.14%
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4 2079430 206.64%
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5 662647 65.85%
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6 398739 39.62%
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7 391912 38.95%
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8 978098 97.20%
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system.cpu.commit.COM:committed_per_cycle.max_value 8
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system.cpu.commit.COM:committed_per_cycle.end_dist
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system.cpu.commit.COM:count 56284559 # Number of instructions committed
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system.cpu.commit.COM:loads 9308572 # Number of loads committed
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system.cpu.commit.COM:membars 228000 # Number of memory barriers committed
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system.cpu.commit.COM:refs 15700770 # Number of memory references committed
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.branchMispredicts 787906 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 56284559 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 667787 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 9472622 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 53090223 # Number of Instructions Simulated
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system.cpu.committedInsts_total 53090223 # Number of Instructions Simulated
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system.cpu.cpi 2.580471 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 2.580471 # CPI: Total CPI of All Threads
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system.cpu.dcache.LoadLockedReq_accesses 214422 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_avg_miss_latency 15515.537615 # average LoadLockedReq miss latency
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system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11814.147928 # average LoadLockedReq mshr miss latency
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system.cpu.dcache.LoadLockedReq_hits 192250 # number of LoadLockedReq hits
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system.cpu.dcache.LoadLockedReq_miss_latency 344010500 # number of LoadLockedReq miss cycles
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system.cpu.dcache.LoadLockedReq_miss_rate 0.103404 # miss rate for LoadLockedReq accesses
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system.cpu.dcache.LoadLockedReq_misses 22172 # number of LoadLockedReq misses
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system.cpu.dcache.LoadLockedReq_mshr_hits 4650 # number of LoadLockedReq MSHR hits
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system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207007500 # number of LoadLockedReq MSHR miss cycles
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system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.081717 # mshr miss rate for LoadLockedReq accesses
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system.cpu.dcache.LoadLockedReq_mshr_misses 17522 # number of LoadLockedReq MSHR misses
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system.cpu.dcache.ReadReq_accesses 9342386 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 23884.018523 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22765.012818 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
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system.cpu.dcache.ReadReq_hits 7810012 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 36599249000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.164024 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 1532374 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 447551 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 24696009500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.116118 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 1084823 # number of ReadReq MSHR misses
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system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904976000 # number of ReadReq MSHR uncacheable cycles
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system.cpu.dcache.StoreCondReq_accesses 219797 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_avg_miss_latency 56331.488950 # average StoreCondReq miss latency
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system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53331.488950 # average StoreCondReq mshr miss latency
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system.cpu.dcache.StoreCondReq_hits 189796 # number of StoreCondReq hits
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system.cpu.dcache.StoreCondReq_miss_latency 1690001000 # number of StoreCondReq miss cycles
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system.cpu.dcache.StoreCondReq_miss_rate 0.136494 # miss rate for StoreCondReq accesses
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system.cpu.dcache.StoreCondReq_misses 30001 # number of StoreCondReq misses
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system.cpu.dcache.StoreCondReq_mshr_miss_latency 1599998000 # number of StoreCondReq MSHR miss cycles
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system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.136494 # mshr miss rate for StoreCondReq accesses
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system.cpu.dcache.StoreCondReq_mshr_misses 30001 # number of StoreCondReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 6157245 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 49037.572489 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 54494.404609 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
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system.cpu.dcache.WriteReq_hits 3926713 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 109379874638 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.362261 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 2230532 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 1833591 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 21631063460 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.064467 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 396941 # number of WriteReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235842997 # number of WriteReq MSHR uncacheable cycles
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system.cpu.dcache.avg_blocked_cycles_no_mshrs 10022.289139 # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets 16500 # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 8.827872 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 137083 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 4 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 1373885462 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 66000 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 15499631 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 38794.252006 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 31264.812048 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 11736725 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 145979123638 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.242774 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 3762906 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 2281142 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 46327072960 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.095600 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 1481764 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 15499631 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 38794.252006 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 31264.812048 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 11736725 # number of overall hits
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system.cpu.dcache.overall_miss_latency 145979123638 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.242774 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 3762906 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 2281142 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 46327072960 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.095600 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 1481764 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 2140818997 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 1402110 # number of replacements
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system.cpu.dcache.sampled_refs 1402622 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 511.995450 # Cycle average of tags in use
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system.cpu.dcache.total_refs 12382168 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 21439000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 430447 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 48442278 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:BranchMispred 42798 # Number of times decode detected a branch misprediction
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system.cpu.decode.DECODE:BranchResolved 614586 # Number of times decode resolved a branch
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system.cpu.decode.DECODE:DecodedInsts 72711050 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 37969720 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 13062350 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 1643233 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:SquashedInsts 134839 # Number of squashed instructions handled by decode
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system.cpu.decode.DECODE:UnblockCycles 1155126 # Number of cycles decode is unblocking
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system.cpu.dtb.data_accesses 1236133 # DTB accesses
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system.cpu.dtb.data_acv 823 # DTB access violations
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system.cpu.dtb.data_hits 16770289 # DTB hits
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system.cpu.dtb.data_misses 44393 # DTB misses
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.read_accesses 909859 # DTB read accesses
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system.cpu.dtb.read_acv 588 # DTB read access violations
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system.cpu.dtb.read_hits 10173052 # DTB read hits
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system.cpu.dtb.read_misses 36219 # DTB read misses
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system.cpu.dtb.write_accesses 326274 # DTB write accesses
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system.cpu.dtb.write_acv 235 # DTB write access violations
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system.cpu.dtb.write_hits 6597237 # DTB write hits
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system.cpu.dtb.write_misses 8174 # DTB write misses
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system.cpu.fetch.Branches 14563706 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 8997144 # Number of cache lines fetched
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system.cpu.fetch.Cycles 23480265 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 455601 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 74265234 # Number of instructions fetch has processed
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system.cpu.fetch.MiscStallCycles 2366 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.SquashCycles 967433 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.106306 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 8997144 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 7967591 # Number of branches that fetch has predicted taken
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system.cpu.fetch.rate 0.542091 # Number of inst fetches per cycle
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system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist.samples 102272708
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system.cpu.fetch.rateDist.min_value 0
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0 87829962 8587.82%
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1 1051726 102.84%
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2 2021481 197.66%
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3 968950 94.74%
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4 2998384 293.18%
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5 688876 67.36%
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6 831559 81.31%
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7 1217734 119.07%
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8 4664036 456.04%
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system.cpu.fetch.rateDist.max_value 8
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system.cpu.fetch.rateDist.end_dist
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system.cpu.icache.ReadReq_accesses 8997144 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 14906.743449 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 11907.437092 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 7949609 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 15615335499 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.116430 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 1047535 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_hits 51877 # number of ReadReq MSHR hits
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system.cpu.icache.ReadReq_mshr_miss_latency 11855735000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.110664 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 995658 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles_no_mshrs 11545.454545 # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 7.985800 # Average number of references to valid blocks.
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system.cpu.icache.blocked_no_mshrs 55 # number of cycles access was blocked
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system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_mshrs 635000 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 8997144 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 14906.743449 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 11907.437092 # average overall mshr miss latency
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system.cpu.icache.demand_hits 7949609 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 15615335499 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.116430 # miss rate for demand accesses
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system.cpu.icache.demand_misses 1047535 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 51877 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 11855735000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.110664 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 995658 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_accesses 8997144 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 14906.743449 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 11907.437092 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 7949609 # number of overall hits
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system.cpu.icache.overall_miss_latency 15615335499 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.116430 # miss rate for overall accesses
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system.cpu.icache.overall_misses 1047535 # number of overall misses
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system.cpu.icache.overall_mshr_hits 51877 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 11855735000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.110664 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 995658 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.replacements 994957 # number of replacements
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system.cpu.icache.sampled_refs 995468 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 509.772438 # Cycle average of tags in use
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system.cpu.icache.total_refs 7949608 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 25306164000 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idleCycles 34725081 # Total number of cycles that the CPU has spent unscheduled due to idling
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system.cpu.iew.EXEC:branches 9164165 # Number of branches executed
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system.cpu.iew.EXEC:nop 3679313 # number of nop insts executed
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system.cpu.iew.EXEC:rate 0.420337 # Inst execution rate
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system.cpu.iew.EXEC:refs 17053432 # number of memory reference insts executed
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system.cpu.iew.EXEC:stores 6620337 # Number of stores executed
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system.cpu.iew.EXEC:swp 0 # number of swp insts executed
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system.cpu.iew.WB:consumers 34505393 # num instructions consuming a value
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system.cpu.iew.WB:count 56992809 # cumulative count of insts written-back
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system.cpu.iew.WB:fanout 0.764525 # average fanout of values written-back
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system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
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system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
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system.cpu.iew.WB:producers 26380221 # num instructions producing a value
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system.cpu.iew.WB:rate 0.416013 # insts written-back per cycle
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system.cpu.iew.WB:sent 57095823 # cumulative count of insts sent to commit
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system.cpu.iew.branchMispredicts 857525 # Number of branch mispredicts detected at execute
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system.cpu.iew.iewBlockCycles 9717535 # Number of cycles IEW is blocking
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system.cpu.iew.iewDispLoadInsts 11048107 # Number of dispatched load instructions
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system.cpu.iew.iewDispNonSpecInsts 1799892 # Number of dispatched non-speculative instructions
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system.cpu.iew.iewDispSquashedInsts 1045221 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispStoreInsts 7018400 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispatchedInsts 65886993 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewExecLoadInsts 10433095 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 539578 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.iewExecutedInsts 57585192 # Number of executed instructions
|
|
system.cpu.iew.iewIQFullEvents 49355 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewLSQFullEvents 6548 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.iewSquashCycles 1643233 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewUnblockCycles 548828 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 307987 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.lsq.thread.0.forwLoads 427807 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 11074 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 45865 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 15487 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 1739535 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread.0.squashedStores 626202 # Number of stores squashed
|
|
system.cpu.iew.memOrderViolationEvents 45865 # Number of memory order violations
|
|
system.cpu.iew.predictedNotTakenIncorrect 381050 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.predictedTakenIncorrect 476475 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.ipc 0.387526 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.387526 # IPC: Total IPC of All Threads
|
|
system.cpu.iq.ISSUE:FU_type_0 58124772 # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
|
No_OpClass 7284 0.01% # Type of FU issued
|
|
IntAlu 39611417 68.15% # Type of FU issued
|
|
IntMult 62110 0.11% # Type of FU issued
|
|
IntDiv 0 0.00% # Type of FU issued
|
|
FloatAdd 25607 0.04% # Type of FU issued
|
|
FloatCmp 0 0.00% # Type of FU issued
|
|
FloatCvt 0 0.00% # Type of FU issued
|
|
FloatMult 0 0.00% # Type of FU issued
|
|
FloatDiv 3636 0.01% # Type of FU issued
|
|
FloatSqrt 0 0.00% # Type of FU issued
|
|
MemRead 10788116 18.56% # Type of FU issued
|
|
MemWrite 6673339 11.48% # Type of FU issued
|
|
IprAccess 953263 1.64% # Type of FU issued
|
|
InstPrefetch 0 0.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 433051 # FU busy when requested
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.007450 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.ISSUE:fu_full.start_dist
|
|
No_OpClass 0 0.00% # attempts to use FU when none available
|
|
IntAlu 50716 11.71% # attempts to use FU when none available
|
|
IntMult 0 0.00% # attempts to use FU when none available
|
|
IntDiv 0 0.00% # attempts to use FU when none available
|
|
FloatAdd 0 0.00% # attempts to use FU when none available
|
|
FloatCmp 0 0.00% # attempts to use FU when none available
|
|
FloatCvt 0 0.00% # attempts to use FU when none available
|
|
FloatMult 0 0.00% # attempts to use FU when none available
|
|
FloatDiv 0 0.00% # attempts to use FU when none available
|
|
FloatSqrt 0 0.00% # attempts to use FU when none available
|
|
MemRead 279321 64.50% # attempts to use FU when none available
|
|
MemWrite 103014 23.79% # attempts to use FU when none available
|
|
IprAccess 0 0.00% # attempts to use FU when none available
|
|
InstPrefetch 0 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full.end_dist
|
|
system.cpu.iq.ISSUE:issued_per_cycle::samples 102272708
|
|
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0
|
|
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00%
|
|
system.cpu.iq.ISSUE:issued_per_cycle::0-1 73147659 71.52%
|
|
system.cpu.iq.ISSUE:issued_per_cycle::1-2 14648372 14.32%
|
|
system.cpu.iq.ISSUE:issued_per_cycle::2-3 6417102 6.27%
|
|
system.cpu.iq.ISSUE:issued_per_cycle::3-4 3925012 3.84%
|
|
system.cpu.iq.ISSUE:issued_per_cycle::4-5 2528533 2.47%
|
|
system.cpu.iq.ISSUE:issued_per_cycle::5-6 1035489 1.01%
|
|
system.cpu.iq.ISSUE:issued_per_cycle::6-7 441110 0.43%
|
|
system.cpu.iq.ISSUE:issued_per_cycle::7-8 106525 0.10%
|
|
system.cpu.iq.ISSUE:issued_per_cycle::8 22906 0.02%
|
|
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00%
|
|
system.cpu.iq.ISSUE:issued_per_cycle::total 102272708
|
|
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8
|
|
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.568331
|
|
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.133996
|
|
system.cpu.iq.ISSUE:rate 0.424275 # Inst issue rate
|
|
system.cpu.iq.iqInstsAdded 60155940 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqInstsIssued 58124772 # Number of instructions issued
|
|
system.cpu.iq.iqNonSpecInstsAdded 2051740 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqSquashedInstsExamined 8691644 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedInstsIssued 34825 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 1383953 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.iqSquashedOperandsExamined 4676225 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.fetch_accesses 1303750 # ITB accesses
|
|
system.cpu.itb.fetch_acv 951 # ITB acv
|
|
system.cpu.itb.fetch_hits 1264322 # ITB hits
|
|
system.cpu.itb.fetch_misses 39428 # ITB misses
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.kern.callpal 192652 # number of callpals executed
|
|
system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal_swpctx 4176 2.17% 2.17% # number of callpals executed
|
|
system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed
|
|
system.cpu.kern.callpal_wrent 7 0.00% 2.20% # number of callpals executed
|
|
system.cpu.kern.callpal_swpipl 175681 91.19% 93.39% # number of callpals executed
|
|
system.cpu.kern.callpal_rdps 6794 3.53% 96.92% # number of callpals executed
|
|
system.cpu.kern.callpal_wrkgp 1 0.00% 96.92% # number of callpals executed
|
|
system.cpu.kern.callpal_wrusp 7 0.00% 96.92% # number of callpals executed
|
|
system.cpu.kern.callpal_rdusp 9 0.00% 96.93% # number of callpals executed
|
|
system.cpu.kern.callpal_whami 2 0.00% 96.93% # number of callpals executed
|
|
system.cpu.kern.callpal_rti 5221 2.71% 99.64% # number of callpals executed
|
|
system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed
|
|
system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu.kern.inst.hwrei 211811 # number of hwrei instructions executed
|
|
system.cpu.kern.inst.quiesce 6385 # number of quiesce instructions executed
|
|
system.cpu.kern.ipl_count 183030 # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count_0 74956 40.95% 40.95% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count_21 237 0.13% 41.08% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count_22 1890 1.03% 42.11% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count_31 105947 57.89% 100.00% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_good 149305 # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good_0 73589 49.29% 49.29% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good_21 237 0.16% 49.45% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good_22 1890 1.27% 50.71% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good_31 73589 49.29% 100.00% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_ticks 1867362103000 # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks_0 1824761131000 97.72% 97.72% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks_21 102621000 0.01% 97.72% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks_22 392338000 0.02% 97.75% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks_31 42106013000 2.25% 100.00% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_used_0 0.981763 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used_31 0.694583 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.mode_good_kernel 1910
|
|
system.cpu.kern.mode_good_user 1740
|
|
system.cpu.kern.mode_good_idle 170
|
|
system.cpu.kern.mode_switch_kernel 5972 # number of protection mode switches
|
|
system.cpu.kern.mode_switch_user 1740 # number of protection mode switches
|
|
system.cpu.kern.mode_switch_idle 2095 # number of protection mode switches
|
|
system.cpu.kern.mode_switch_good 1.400971 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good_kernel 0.319826 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good_idle 0.081146 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_ticks_kernel 31331138500 1.68% 1.68% # number of ticks spent at the given mode
|
|
system.cpu.kern.mode_ticks_user 3191204500 0.17% 1.85% # number of ticks spent at the given mode
|
|
system.cpu.kern.mode_ticks_idle 1832839752000 98.15% 100.00% # number of ticks spent at the given mode
|
|
system.cpu.kern.swap_context 4177 # number of times the context was actually changed
|
|
system.cpu.kern.syscall 326 # number of syscalls executed
|
|
system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed
|
|
system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed
|
|
system.cpu.kern.syscall_4 4 1.23% 12.88% # number of syscalls executed
|
|
system.cpu.kern.syscall_6 42 12.88% 25.77% # number of syscalls executed
|
|
system.cpu.kern.syscall_12 1 0.31% 26.07% # number of syscalls executed
|
|
system.cpu.kern.syscall_15 1 0.31% 26.38% # number of syscalls executed
|
|
system.cpu.kern.syscall_17 15 4.60% 30.98% # number of syscalls executed
|
|
system.cpu.kern.syscall_19 10 3.07% 34.05% # number of syscalls executed
|
|
system.cpu.kern.syscall_20 6 1.84% 35.89% # number of syscalls executed
|
|
system.cpu.kern.syscall_23 4 1.23% 37.12% # number of syscalls executed
|
|
system.cpu.kern.syscall_24 6 1.84% 38.96% # number of syscalls executed
|
|
system.cpu.kern.syscall_33 11 3.37% 42.33% # number of syscalls executed
|
|
system.cpu.kern.syscall_41 2 0.61% 42.94% # number of syscalls executed
|
|
system.cpu.kern.syscall_45 54 16.56% 59.51% # number of syscalls executed
|
|
system.cpu.kern.syscall_47 6 1.84% 61.35% # number of syscalls executed
|
|
system.cpu.kern.syscall_48 10 3.07% 64.42% # number of syscalls executed
|
|
system.cpu.kern.syscall_54 10 3.07% 67.48% # number of syscalls executed
|
|
system.cpu.kern.syscall_58 1 0.31% 67.79% # number of syscalls executed
|
|
system.cpu.kern.syscall_59 7 2.15% 69.94% # number of syscalls executed
|
|
system.cpu.kern.syscall_71 54 16.56% 86.50% # number of syscalls executed
|
|
system.cpu.kern.syscall_73 3 0.92% 87.42% # number of syscalls executed
|
|
system.cpu.kern.syscall_74 16 4.91% 92.33% # number of syscalls executed
|
|
system.cpu.kern.syscall_87 1 0.31% 92.64% # number of syscalls executed
|
|
system.cpu.kern.syscall_90 3 0.92% 93.56% # number of syscalls executed
|
|
system.cpu.kern.syscall_92 9 2.76% 96.32% # number of syscalls executed
|
|
system.cpu.kern.syscall_97 2 0.61% 96.93% # number of syscalls executed
|
|
system.cpu.kern.syscall_98 2 0.61% 97.55% # number of syscalls executed
|
|
system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed
|
|
system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed
|
|
system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed
|
|
system.cpu.memDep0.conflictingLoads 3077147 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 2881540 # Number of conflicting stores.
|
|
system.cpu.memDep0.insertedLoads 11048107 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 7018400 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.numCycles 136997789 # number of cpu cycles simulated
|
|
system.cpu.rename.RENAME:BlockCycles 14285499 # Number of cycles rename is blocking
|
|
system.cpu.rename.RENAME:CommittedMaps 38258957 # Number of HB maps that are committed
|
|
system.cpu.rename.RENAME:IQFullEvents 1096982 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.RENAME:IdleCycles 39563718 # Number of cycles rename is idle
|
|
system.cpu.rename.RENAME:LSQFullEvents 2259510 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RENAME:ROBFullEvents 15713 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.RENAME:RenameLookups 83436015 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.RENAME:RenamedInsts 68679972 # Number of instructions processed by rename
|
|
system.cpu.rename.RENAME:RenamedOperands 46025419 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RENAME:RunCycles 12707474 # Number of cycles rename is running
|
|
system.cpu.rename.RENAME:SquashCycles 1643233 # Number of cycles rename is squashing
|
|
system.cpu.rename.RENAME:UnblockCycles 5244444 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RENAME:UndoneMaps 7766460 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.RENAME:serializeStallCycles 28828338 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RENAME:serializingInsts 1705072 # count of serializing insts renamed
|
|
system.cpu.rename.RENAME:skidInsts 12828278 # count of insts added to the skid buffer
|
|
system.cpu.rename.RENAME:tempSerializingInsts 257070 # count of temporary serializing insts renamed
|
|
system.cpu.timesIdled 1322055 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
|
|
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
|
|
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
|
|
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
|
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
|
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
|
system.iocache.ReadReq_accesses 173 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_avg_miss_latency 115260.104046 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency 63260.104046 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_miss_latency 19939998 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_misses 173 # number of ReadReq misses
|
|
system.iocache.ReadReq_mshr_miss_latency 10943998 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses
|
|
system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses)
|
|
system.iocache.WriteReq_avg_miss_latency 137794.253129 # average WriteReq miss latency
|
|
system.iocache.WriteReq_avg_mshr_miss_latency 85790.836302 # average WriteReq mshr miss latency
|
|
system.iocache.WriteReq_miss_latency 5725626806 # number of WriteReq miss cycles
|
|
system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_misses 41552 # number of WriteReq misses
|
|
system.iocache.WriteReq_mshr_miss_latency 3564780830 # number of WriteReq MSHR miss cycles
|
|
system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses
|
|
system.iocache.avg_blocked_cycles_no_mshrs 6161.136802 # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
system.iocache.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.blocked_no_mshrs 10475 # number of cycles access was blocked
|
|
system.iocache.blocked_no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles_no_mshrs 64537908 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.demand_accesses 41725 # number of demand (read+write) accesses
|
|
system.iocache.demand_avg_miss_latency 137700.822145 # average overall miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency 85697.419485 # average overall mshr miss latency
|
|
system.iocache.demand_hits 0 # number of demand (read+write) hits
|
|
system.iocache.demand_miss_latency 5745566804 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_rate 1 # miss rate for demand accesses
|
|
system.iocache.demand_misses 41725 # number of demand (read+write) misses
|
|
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.iocache.demand_mshr_miss_latency 3575724828 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.iocache.overall_accesses 41725 # number of overall (read+write) accesses
|
|
system.iocache.overall_avg_miss_latency 137700.822145 # average overall miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency 85697.419485 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
system.iocache.overall_hits 0 # number of overall hits
|
|
system.iocache.overall_miss_latency 5745566804 # number of overall miss cycles
|
|
system.iocache.overall_miss_rate 1 # miss rate for overall accesses
|
|
system.iocache.overall_misses 41725 # number of overall misses
|
|
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.iocache.overall_mshr_miss_latency 3575724828 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.iocache.replacements 41685 # number of replacements
|
|
system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
|
|
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.iocache.tagsinuse 1.267415 # Cycle average of tags in use
|
|
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.warmup_cycle 1716179713000 # Cycle when the warmup percentage was hit.
|
|
system.iocache.writebacks 41512 # number of writebacks
|
|
system.l2c.ReadExReq_accesses 300582 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_avg_miss_latency 52361.965557 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency 40206.978448 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_miss_latency 15739064331 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_misses 300582 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_mshr_miss_latency 12085493996 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_misses 300582 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadReq_accesses 2097743 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_avg_miss_latency 52046.745492 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency 40015.135689 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_hits 1786590 # number of ReadReq hits
|
|
system.l2c.ReadReq_miss_latency 16194501000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_rate 0.148328 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_misses 311153 # number of ReadReq misses
|
|
system.l2c.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_miss_latency 12450789500 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_rate 0.148327 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_misses 311152 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_uncacheable_latency 810515500 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.UpgradeReq_accesses 130274 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_avg_miss_latency 52273.201045 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency 40097.567435 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_miss_latency 6809838993 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_misses 130274 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_mshr_miss_latency 5223670500 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_misses 130274 # number of UpgradeReq MSHR misses
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_mshr_uncacheable_latency 1116273498 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.Writeback_accesses 430447 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_hits 430447 # number of Writeback hits
|
|
system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
system.l2c.avg_refs 4.597861 # Average number of references to valid blocks.
|
|
system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.demand_accesses 2398325 # number of demand (read+write) accesses
|
|
system.l2c.demand_avg_miss_latency 52201.631966 # average overall miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency 40109.399667 # average overall mshr miss latency
|
|
system.l2c.demand_hits 1786590 # number of demand (read+write) hits
|
|
system.l2c.demand_miss_latency 31933565331 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_rate 0.255068 # miss rate for demand accesses
|
|
system.l2c.demand_misses 611735 # number of demand (read+write) misses
|
|
system.l2c.demand_mshr_hits 1 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_miss_latency 24536283496 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_rate 0.255067 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_misses 611734 # number of demand (read+write) MSHR misses
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.l2c.overall_accesses 2398325 # number of overall (read+write) accesses
|
|
system.l2c.overall_avg_miss_latency 52201.631966 # average overall miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency 40109.399667 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_hits 1786590 # number of overall hits
|
|
system.l2c.overall_miss_latency 31933565331 # number of overall miss cycles
|
|
system.l2c.overall_miss_rate 0.255068 # miss rate for overall accesses
|
|
system.l2c.overall_misses 611735 # number of overall misses
|
|
system.l2c.overall_mshr_hits 1 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_miss_latency 24536283496 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_rate 0.255067 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_misses 611734 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_uncacheable_latency 1926788998 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.l2c.replacements 396039 # number of replacements
|
|
system.l2c.sampled_refs 427720 # Sample count of references to valid blocks.
|
|
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.l2c.tagsinuse 30690.397149 # Cycle average of tags in use
|
|
system.l2c.total_refs 1966597 # Total number of references to valid blocks.
|
|
system.l2c.warmup_cycle 5645091000 # Cycle when the warmup percentage was hit.
|
|
system.l2c.writebacks 119094 # number of writebacks
|
|
system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post
|
|
system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post
|
|
system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post
|
|
system.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post
|
|
system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post
|
|
system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post
|
|
system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post
|
|
system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post
|
|
system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post
|
|
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
|
|
---------- End Simulation Statistics ----------
|