ARM: Updated regressions for changes in SE mode stack
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3 changed files with 16 additions and 17 deletions
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@ -12,7 +12,6 @@ physmem=system.physmem
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[system.cpu]
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type=AtomicSimpleCPU
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children=dtb itb tracer workload
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UnifiedTLB=true
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checker=Null
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clock=500
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cpu_id=0
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@ -58,7 +57,7 @@ egid=100
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env=
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errout=cerr
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euid=100
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executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
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executable=tests/test-progs/hello/bin/arm/linux/hello
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gid=100
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input=cin
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max_stack_size=67108864
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@ -5,12 +5,12 @@ The Regents of The University of Michigan
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All Rights Reserved
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M5 compiled Feb 27 2010 17:02:03
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M5 revision 3ba6c6c19ddd 7101 default qtip syscallfromintstats.patch tip
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M5 started Feb 27 2010 17:02:04
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M5 executing on tater
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command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic
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M5 compiled Jun 1 2010 16:08:15
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M5 revision 4b3bf0363048 7414 default qtip tip ext/linux_se_structs.patch
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M5 started Jun 1 2010 16:09:04
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M5 executing on harpertown2
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command line: ./build/ARM_SE/m5.debug -r -e tests/run.py quick/00.hello/arm/linux/simple-atomic
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Global frequency set at 1000000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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Hello world!
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Exiting @ tick 2756500 because target called exit()
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Exiting @ tick 2761000 because target called exit()
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@ -1,13 +1,13 @@
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---------- Begin Simulation Statistics ----------
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host_inst_rate 12327 # Simulator instruction rate (inst/s)
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host_mem_usage 201392 # Number of bytes of host memory used
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host_seconds 0.45 # Real time elapsed on the host
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host_tick_rate 6174277 # Simulator tick rate (ticks/s)
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host_inst_rate 92316 # Simulator instruction rate (inst/s)
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host_mem_usage 191512 # Number of bytes of host memory used
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host_seconds 0.06 # Real time elapsed on the host
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host_tick_rate 46039687 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 5501 # Number of instructions simulated
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sim_insts 5510 # Number of instructions simulated
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sim_seconds 0.000003 # Number of seconds simulated
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sim_ticks 2756500 # Number of ticks simulated
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sim_ticks 2761000 # Number of ticks simulated
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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@ -28,9 +28,9 @@ system.cpu.itb.write_accesses 0 # DT
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.numCycles 5514 # number of cpu cycles simulated
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system.cpu.num_insts 5501 # Number of instructions executed
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system.cpu.num_refs 2143 # Number of memory references
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system.cpu.numCycles 5523 # number of cpu cycles simulated
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system.cpu.num_insts 5510 # Number of instructions executed
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system.cpu.num_refs 2145 # Number of memory references
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system.cpu.workload.PROG:num_syscalls 13 # Number of system calls
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---------- End Simulation Statistics ----------
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