stats: update stats for no_value -> nan
Lots of accumulated older changes too.
This commit is contained in:
Nathan Binkert
parent
55411f7f71
commit
4a644767c5
472 changed files with 7138 additions and 8994 deletions
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@ -19,7 +19,6 @@ mem_mode=timing
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memories=system.physmem
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num_work_ids=16
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pal=/dist/m5/system/binaries/ts_osfpal
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physmem=system.physmem
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readfile=tests/halt.sh
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symbolfile=
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system_rev=1024
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@ -31,7 +30,7 @@ work_cpus_ckpt_count=0
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work_end_ckpt_count=0
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work_end_exit_count=0
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work_item_id=-1
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system_port=system.membus.port[2]
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system_port=system.membus.slave[0]
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[system.bridge]
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type=Bridge
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@ -41,8 +40,8 @@ ranges=8796093022208:18446744073709551615
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req_size=16
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resp_size=16
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write_ack=false
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master=system.iobus.port[0]
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slave=system.membus.port[0]
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master=system.iobus.slave[0]
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slave=system.membus.master[0]
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[system.cpu0]
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type=DerivO3CPU
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@ -143,7 +142,7 @@ icache_port=system.cpu0.icache.cpu_side
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[system.cpu0.dcache]
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type=BaseCache
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addr_range=0:18446744073709551615
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addr_ranges=0:18446744073709551615
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assoc=4
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block_size=64
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forward_snoops=true
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@ -164,7 +163,7 @@ trace_addr=0
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu0.dcache_port
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mem_side=system.toL2Bus.port[2]
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mem_side=system.toL2Bus.slave[1]
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[system.cpu0.dtb]
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type=AlphaTLB
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@ -435,7 +434,7 @@ opLat=3
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[system.cpu0.icache]
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type=BaseCache
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addr_range=0:18446744073709551615
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addr_ranges=0:18446744073709551615
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assoc=1
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block_size=64
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forward_snoops=true
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@ -456,7 +455,7 @@ trace_addr=0
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu0.icache_port
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mem_side=system.toL2Bus.port[1]
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mem_side=system.toL2Bus.slave[0]
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[system.cpu0.interrupts]
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type=AlphaInterrupts
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@ -567,7 +566,7 @@ icache_port=system.cpu1.icache.cpu_side
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[system.cpu1.dcache]
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type=BaseCache
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addr_range=0:18446744073709551615
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addr_ranges=0:18446744073709551615
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assoc=4
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block_size=64
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forward_snoops=true
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@ -588,7 +587,7 @@ trace_addr=0
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu1.dcache_port
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mem_side=system.toL2Bus.port[4]
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mem_side=system.toL2Bus.slave[3]
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[system.cpu1.dtb]
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type=AlphaTLB
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@ -859,7 +858,7 @@ opLat=3
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[system.cpu1.icache]
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type=BaseCache
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addr_range=0:18446744073709551615
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addr_ranges=0:18446744073709551615
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assoc=1
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block_size=64
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forward_snoops=true
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@ -880,7 +879,7 @@ trace_addr=0
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu1.icache_port
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mem_side=system.toL2Bus.port[3]
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mem_side=system.toL2Bus.slave[2]
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[system.cpu1.interrupts]
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type=AlphaInterrupts
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@ -945,11 +944,12 @@ header_cycles=1
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use_default_range=true
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width=64
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default=system.tsunami.pciconfig.pio
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port=system.bridge.master system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ide.dma system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.iocache.cpu_side
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master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
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slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
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[system.iocache]
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type=BaseCache
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addr_range=0:8589934591
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addr_ranges=0:8589934591
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assoc=8
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block_size=64
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forward_snoops=false
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@ -969,12 +969,12 @@ tgts_per_mshr=12
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trace_addr=0
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two_queue=false
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write_buffers=8
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cpu_side=system.iobus.port[32]
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mem_side=system.membus.port[3]
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cpu_side=system.iobus.master[29]
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mem_side=system.membus.slave[1]
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[system.l2c]
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type=BaseCache
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addr_range=0:18446744073709551615
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addr_ranges=0:18446744073709551615
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assoc=8
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block_size=64
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forward_snoops=true
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@ -994,8 +994,8 @@ tgts_per_mshr=16
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trace_addr=0
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two_queue=false
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write_buffers=8
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cpu_side=system.toL2Bus.port[0]
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mem_side=system.membus.port[4]
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cpu_side=system.toL2Bus.master[0]
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mem_side=system.membus.slave[2]
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[system.membus]
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type=Bus
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@ -1007,7 +1007,8 @@ header_cycles=1
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use_default_range=false
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width=64
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default=system.membus.badaddr_responder.pio
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port=system.bridge.slave system.physmem.port[0] system.system_port system.iocache.mem_side system.l2c.mem_side
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master=system.bridge.slave system.physmem.port[0]
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slave=system.system_port system.iocache.mem_side system.l2c.mem_side
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[system.membus.badaddr_responder]
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type=IsaFake
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@ -1026,14 +1027,16 @@ warn_access=
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pio=system.membus.default
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[system.physmem]
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type=PhysicalMemory
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type=SimpleMemory
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conf_table_reported=false
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file=
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in_addr_map=true
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latency=30000
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latency_var=0
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null=false
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range=0:134217727
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zero=false
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port=system.membus.port[1]
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port=system.membus.master[1]
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[system.simple_disk]
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type=SimpleDisk
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@ -1061,7 +1064,8 @@ clock=1000
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header_cycles=1
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use_default_range=false
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width=64
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port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side
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master=system.l2c.cpu_side
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slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side
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[system.tsunami]
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type=Tsunami
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@ -1078,7 +1082,7 @@ pio_latency=1000
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platform=system.tsunami
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system=system
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terminal=system.terminal
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pio=system.iobus.port[25]
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pio=system.iobus.master[24]
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[system.tsunami.cchip]
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type=TsunamiCChip
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@ -1086,7 +1090,7 @@ pio_addr=8803072344064
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pio_latency=1000
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system=system
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tsunami=system.tsunami
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pio=system.iobus.port[1]
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pio=system.iobus.master[0]
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[system.tsunami.ethernet]
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type=NSGigE
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@ -1155,9 +1159,9 @@ system=system
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tx_delay=1000000
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tx_fifo_size=524288
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tx_thread=false
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config=system.iobus.port[30]
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dma=system.iobus.port[31]
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pio=system.iobus.port[29]
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config=system.iobus.master[28]
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dma=system.iobus.slave[2]
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pio=system.iobus.master[27]
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[system.tsunami.fake_OROM]
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type=IsaFake
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@ -1173,7 +1177,7 @@ ret_data8=255
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system=system
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update_data=false
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warn_access=
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pio=system.iobus.port[9]
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pio=system.iobus.master[8]
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[system.tsunami.fake_ata0]
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type=IsaFake
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@ -1189,7 +1193,7 @@ ret_data8=255
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system=system
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update_data=false
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warn_access=
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pio=system.iobus.port[20]
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pio=system.iobus.master[19]
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[system.tsunami.fake_ata1]
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type=IsaFake
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@ -1205,7 +1209,7 @@ ret_data8=255
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system=system
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update_data=false
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warn_access=
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pio=system.iobus.port[21]
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pio=system.iobus.master[20]
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[system.tsunami.fake_pnp_addr]
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type=IsaFake
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@ -1221,7 +1225,7 @@ ret_data8=255
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system=system
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update_data=false
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warn_access=
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pio=system.iobus.port[10]
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pio=system.iobus.master[9]
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[system.tsunami.fake_pnp_read0]
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type=IsaFake
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@ -1237,7 +1241,7 @@ ret_data8=255
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system=system
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update_data=false
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warn_access=
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pio=system.iobus.port[12]
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pio=system.iobus.master[11]
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[system.tsunami.fake_pnp_read1]
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type=IsaFake
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@ -1253,7 +1257,7 @@ ret_data8=255
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system=system
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update_data=false
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warn_access=
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pio=system.iobus.port[13]
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pio=system.iobus.master[12]
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[system.tsunami.fake_pnp_read2]
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type=IsaFake
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@ -1269,7 +1273,7 @@ ret_data8=255
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system=system
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update_data=false
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warn_access=
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pio=system.iobus.port[14]
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pio=system.iobus.master[13]
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[system.tsunami.fake_pnp_read3]
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type=IsaFake
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@ -1285,7 +1289,7 @@ ret_data8=255
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system=system
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update_data=false
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warn_access=
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pio=system.iobus.port[15]
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pio=system.iobus.master[14]
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[system.tsunami.fake_pnp_read4]
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type=IsaFake
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@ -1301,7 +1305,7 @@ ret_data8=255
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system=system
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update_data=false
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warn_access=
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pio=system.iobus.port[16]
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pio=system.iobus.master[15]
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[system.tsunami.fake_pnp_read5]
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type=IsaFake
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@ -1317,7 +1321,7 @@ ret_data8=255
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system=system
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update_data=false
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warn_access=
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pio=system.iobus.port[17]
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pio=system.iobus.master[16]
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[system.tsunami.fake_pnp_read6]
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type=IsaFake
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@ -1333,7 +1337,7 @@ ret_data8=255
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system=system
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update_data=false
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warn_access=
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pio=system.iobus.port[18]
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pio=system.iobus.master[17]
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[system.tsunami.fake_pnp_read7]
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type=IsaFake
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@ -1349,7 +1353,7 @@ ret_data8=255
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system=system
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update_data=false
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warn_access=
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pio=system.iobus.port[19]
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pio=system.iobus.master[18]
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[system.tsunami.fake_pnp_write]
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type=IsaFake
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@ -1365,7 +1369,7 @@ ret_data8=255
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system=system
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update_data=false
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warn_access=
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pio=system.iobus.port[11]
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pio=system.iobus.master[10]
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[system.tsunami.fake_ppc]
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type=IsaFake
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@ -1381,7 +1385,7 @@ ret_data8=255
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system=system
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update_data=false
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warn_access=
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pio=system.iobus.port[8]
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pio=system.iobus.master[7]
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[system.tsunami.fake_sm_chip]
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type=IsaFake
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@ -1397,7 +1401,7 @@ ret_data8=255
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system=system
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update_data=false
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warn_access=
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pio=system.iobus.port[3]
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pio=system.iobus.master[2]
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[system.tsunami.fake_uart1]
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type=IsaFake
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@ -1413,7 +1417,7 @@ ret_data8=255
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system=system
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update_data=false
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warn_access=
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pio=system.iobus.port[4]
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pio=system.iobus.master[3]
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[system.tsunami.fake_uart2]
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type=IsaFake
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@ -1429,7 +1433,7 @@ ret_data8=255
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system=system
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update_data=false
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warn_access=
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pio=system.iobus.port[5]
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pio=system.iobus.master[4]
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[system.tsunami.fake_uart3]
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type=IsaFake
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@ -1445,7 +1449,7 @@ ret_data8=255
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system=system
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update_data=false
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warn_access=
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pio=system.iobus.port[6]
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pio=system.iobus.master[5]
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[system.tsunami.fake_uart4]
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type=IsaFake
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@ -1461,7 +1465,7 @@ ret_data8=255
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system=system
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update_data=false
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warn_access=
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pio=system.iobus.port[7]
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pio=system.iobus.master[6]
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[system.tsunami.fb]
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type=BadDevice
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@ -1469,7 +1473,7 @@ devicename=FrameBuffer
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pio_addr=8804615848912
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pio_latency=1000
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system=system
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pio=system.iobus.port[22]
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pio=system.iobus.master[21]
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[system.tsunami.ide]
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type=IdeController
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@ -1523,9 +1527,9 @@ pci_func=0
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pio_latency=1000
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platform=system.tsunami
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system=system
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config=system.iobus.port[27]
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dma=system.iobus.port[28]
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pio=system.iobus.port[26]
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config=system.iobus.master[26]
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dma=system.iobus.slave[1]
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pio=system.iobus.master[25]
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||||
|
||||
[system.tsunami.io]
|
||||
type=TsunamiIO
|
||||
|
|
@ -1536,7 +1540,7 @@ system=system
|
|||
time=Thu Jan 1 00:00:00 2009
|
||||
tsunami=system.tsunami
|
||||
year_is_bcd=false
|
||||
pio=system.iobus.port[23]
|
||||
pio=system.iobus.master[22]
|
||||
|
||||
[system.tsunami.pchip]
|
||||
type=TsunamiPChip
|
||||
|
|
@ -1544,7 +1548,7 @@ pio_addr=8802535473152
|
|||
pio_latency=1000
|
||||
system=system
|
||||
tsunami=system.tsunami
|
||||
pio=system.iobus.port[2]
|
||||
pio=system.iobus.master[1]
|
||||
|
||||
[system.tsunami.pciconfig]
|
||||
type=PciConfigAll
|
||||
|
|
@ -1562,5 +1566,5 @@ pio_latency=1000
|
|||
platform=system.tsunami
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
pio=system.iobus.port[24]
|
||||
pio=system.iobus.master[23]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,12 +1,13 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Feb 12 2012 17:15:14
|
||||
gem5 started Feb 12 2012 18:11:03
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
|
||||
gem5 compiled May 8 2012 15:36:31
|
||||
gem5 started May 8 2012 15:37:07
|
||||
gem5 executing on piton
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux
|
||||
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Launching CPU 1 @ 107002000
|
||||
Exiting @ tick 1899401490000 because m5_exit instruction encountered
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.899401 # Nu
|
|||
sim_ticks 1899401490000 # Number of ticks simulated
|
||||
final_tick 1899401490000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 189434 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 189434 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 6363739723 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 296196 # Number of bytes of host memory used
|
||||
host_seconds 298.47 # Real time elapsed on the host
|
||||
host_inst_rate 69911 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 69911 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2348556801 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 300512 # Number of bytes of host memory used
|
||||
host_seconds 808.75 # Real time elapsed on the host
|
||||
sim_insts 56540749 # Number of instructions simulated
|
||||
sim_ops 56540749 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 30421696 # Number of bytes read from this memory
|
||||
|
|
@ -178,8 +178,8 @@ system.l2c.blocked_cycles::no_mshrs 0 # nu
|
|||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 122679 # number of writebacks
|
||||
|
|
@ -339,7 +339,7 @@ system.iocache.blocked_cycles::no_targets 0 # n
|
|||
system.iocache.blocked::no_mshrs 10454 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs 6179.172374 # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 41520 # number of writebacks
|
||||
|
|
@ -691,30 +691,30 @@ system.tsunami.ethernet.descDMAWrites 0 # Nu
|
|||
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
||||
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
||||
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post
|
||||
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
||||
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
||||
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post
|
||||
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
||||
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
||||
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post
|
||||
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
||||
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
||||
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post
|
||||
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
||||
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
||||
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post
|
||||
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
||||
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
||||
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post
|
||||
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
||||
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
||||
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post
|
||||
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
||||
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
||||
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
||||
system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post
|
||||
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
||||
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
||||
system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post
|
||||
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
||||
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
||||
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
||||
system.cpu0.icache.replacements 923652 # number of replacements
|
||||
|
|
@ -761,7 +761,7 @@ system.cpu0.icache.blocked_cycles::no_targets 0
|
|||
system.cpu0.icache.blocked::no_mshrs 111 # number of cycles access was blocked
|
||||
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.icache.avg_blocked_cycles::no_mshrs 10234.225225 # average number of cycles each access was blocked
|
||||
system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.icache.writebacks::writebacks 196 # number of writebacks
|
||||
|
|
@ -1275,7 +1275,7 @@ system.cpu1.icache.blocked_cycles::no_targets 0
|
|||
system.cpu1.icache.blocked::no_mshrs 38 # number of cycles access was blocked
|
||||
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.icache.avg_blocked_cycles::no_mshrs 9513.157895 # average number of cycles each access was blocked
|
||||
system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.icache.writebacks::writebacks 52 # number of writebacks
|
||||
|
|
@ -1379,7 +1379,7 @@ system.cpu1.dcache.blocked_cycles::no_targets 0
|
|||
system.cpu1.dcache.blocked::no_mshrs 8713 # number of cycles access was blocked
|
||||
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 13052.272237 # average number of cycles each access was blocked
|
||||
system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.dcache.writebacks::writebacks 116478 # number of writebacks
|
||||
|
|
@ -1522,8 +1522,8 @@ system.cpu0.kern.mode_good::user 1162
|
|||
system.cpu0.kern.mode_good::idle 0
|
||||
system.cpu0.kern.mode_switch_good::kernel 0.162038 # fraction of useful protection mode switches
|
||||
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
||||
system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches
|
||||
system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches
|
||||
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
|
||||
system.cpu0.kern.mode_switch_good::total nan # fraction of useful protection mode switches
|
||||
system.cpu0.kern.mode_ticks::kernel 1897616401500 99.91% 99.91% # number of ticks spent at the given mode
|
||||
system.cpu0.kern.mode_ticks::user 1784230000 0.09% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
|
||||
|
|
|
|||
|
|
@ -19,7 +19,6 @@ mem_mode=timing
|
|||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
pal=/dist/m5/system/binaries/ts_osfpal
|
||||
physmem=system.physmem
|
||||
readfile=tests/halt.sh
|
||||
symbolfile=
|
||||
system_rev=1024
|
||||
|
|
@ -31,7 +30,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[2]
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.bridge]
|
||||
type=Bridge
|
||||
|
|
@ -41,8 +40,8 @@ ranges=8796093022208:18446744073709551615
|
|||
req_size=16
|
||||
resp_size=16
|
||||
write_ack=false
|
||||
master=system.iobus.port[0]
|
||||
slave=system.membus.port[0]
|
||||
master=system.iobus.slave[0]
|
||||
slave=system.membus.master[0]
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
|
|
@ -143,7 +142,7 @@ icache_port=system.cpu.icache.cpu_side
|
|||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
addr_range=0:18446744073709551615
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
|
|
@ -164,7 +163,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.toL2Bus.port[2]
|
||||
mem_side=system.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
|
|
@ -435,7 +434,7 @@ opLat=3
|
|||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
addr_range=0:18446744073709551615
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
|
|
@ -456,7 +455,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.toL2Bus.port[1]
|
||||
mem_side=system.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
|
@ -521,11 +520,12 @@ header_cycles=1
|
|||
use_default_range=true
|
||||
width=64
|
||||
default=system.tsunami.pciconfig.pio
|
||||
port=system.bridge.master system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ide.dma system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.iocache.cpu_side
|
||||
master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
|
||||
slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
|
||||
|
||||
[system.iocache]
|
||||
type=BaseCache
|
||||
addr_range=0:8589934591
|
||||
addr_ranges=0:8589934591
|
||||
assoc=8
|
||||
block_size=64
|
||||
forward_snoops=false
|
||||
|
|
@ -545,12 +545,12 @@ tgts_per_mshr=12
|
|||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.port[32]
|
||||
mem_side=system.membus.port[3]
|
||||
cpu_side=system.iobus.master[29]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.l2c]
|
||||
type=BaseCache
|
||||
addr_range=0:18446744073709551615
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
|
|
@ -570,8 +570,8 @@ tgts_per_mshr=16
|
|||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.toL2Bus.port[0]
|
||||
mem_side=system.membus.port[4]
|
||||
cpu_side=system.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.membus]
|
||||
type=Bus
|
||||
|
|
@ -583,7 +583,8 @@ header_cycles=1
|
|||
use_default_range=false
|
||||
width=64
|
||||
default=system.membus.badaddr_responder.pio
|
||||
port=system.bridge.slave system.physmem.port[0] system.system_port system.iocache.mem_side system.l2c.mem_side
|
||||
master=system.bridge.slave system.physmem.port[0]
|
||||
slave=system.system_port system.iocache.mem_side system.l2c.mem_side
|
||||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
|
|
@ -602,14 +603,16 @@ warn_access=
|
|||
pio=system.membus.default
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[1]
|
||||
port=system.membus.master[1]
|
||||
|
||||
[system.simple_disk]
|
||||
type=SimpleDisk
|
||||
|
|
@ -637,7 +640,8 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
master=system.l2c.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
[system.tsunami]
|
||||
type=Tsunami
|
||||
|
|
@ -654,7 +658,7 @@ pio_latency=1000
|
|||
platform=system.tsunami
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
pio=system.iobus.port[25]
|
||||
pio=system.iobus.master[24]
|
||||
|
||||
[system.tsunami.cchip]
|
||||
type=TsunamiCChip
|
||||
|
|
@ -662,7 +666,7 @@ pio_addr=8803072344064
|
|||
pio_latency=1000
|
||||
system=system
|
||||
tsunami=system.tsunami
|
||||
pio=system.iobus.port[1]
|
||||
pio=system.iobus.master[0]
|
||||
|
||||
[system.tsunami.ethernet]
|
||||
type=NSGigE
|
||||
|
|
@ -731,9 +735,9 @@ system=system
|
|||
tx_delay=1000000
|
||||
tx_fifo_size=524288
|
||||
tx_thread=false
|
||||
config=system.iobus.port[30]
|
||||
dma=system.iobus.port[31]
|
||||
pio=system.iobus.port[29]
|
||||
config=system.iobus.master[28]
|
||||
dma=system.iobus.slave[2]
|
||||
pio=system.iobus.master[27]
|
||||
|
||||
[system.tsunami.fake_OROM]
|
||||
type=IsaFake
|
||||
|
|
@ -749,7 +753,7 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.port[9]
|
||||
pio=system.iobus.master[8]
|
||||
|
||||
[system.tsunami.fake_ata0]
|
||||
type=IsaFake
|
||||
|
|
@ -765,7 +769,7 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.port[20]
|
||||
pio=system.iobus.master[19]
|
||||
|
||||
[system.tsunami.fake_ata1]
|
||||
type=IsaFake
|
||||
|
|
@ -781,7 +785,7 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.port[21]
|
||||
pio=system.iobus.master[20]
|
||||
|
||||
[system.tsunami.fake_pnp_addr]
|
||||
type=IsaFake
|
||||
|
|
@ -797,7 +801,7 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.port[10]
|
||||
pio=system.iobus.master[9]
|
||||
|
||||
[system.tsunami.fake_pnp_read0]
|
||||
type=IsaFake
|
||||
|
|
@ -813,7 +817,7 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.port[12]
|
||||
pio=system.iobus.master[11]
|
||||
|
||||
[system.tsunami.fake_pnp_read1]
|
||||
type=IsaFake
|
||||
|
|
@ -829,7 +833,7 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.port[13]
|
||||
pio=system.iobus.master[12]
|
||||
|
||||
[system.tsunami.fake_pnp_read2]
|
||||
type=IsaFake
|
||||
|
|
@ -845,7 +849,7 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.port[14]
|
||||
pio=system.iobus.master[13]
|
||||
|
||||
[system.tsunami.fake_pnp_read3]
|
||||
type=IsaFake
|
||||
|
|
@ -861,7 +865,7 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.port[15]
|
||||
pio=system.iobus.master[14]
|
||||
|
||||
[system.tsunami.fake_pnp_read4]
|
||||
type=IsaFake
|
||||
|
|
@ -877,7 +881,7 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.port[16]
|
||||
pio=system.iobus.master[15]
|
||||
|
||||
[system.tsunami.fake_pnp_read5]
|
||||
type=IsaFake
|
||||
|
|
@ -893,7 +897,7 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.port[17]
|
||||
pio=system.iobus.master[16]
|
||||
|
||||
[system.tsunami.fake_pnp_read6]
|
||||
type=IsaFake
|
||||
|
|
@ -909,7 +913,7 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.port[18]
|
||||
pio=system.iobus.master[17]
|
||||
|
||||
[system.tsunami.fake_pnp_read7]
|
||||
type=IsaFake
|
||||
|
|
@ -925,7 +929,7 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.port[19]
|
||||
pio=system.iobus.master[18]
|
||||
|
||||
[system.tsunami.fake_pnp_write]
|
||||
type=IsaFake
|
||||
|
|
@ -941,7 +945,7 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.port[11]
|
||||
pio=system.iobus.master[10]
|
||||
|
||||
[system.tsunami.fake_ppc]
|
||||
type=IsaFake
|
||||
|
|
@ -957,7 +961,7 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.port[8]
|
||||
pio=system.iobus.master[7]
|
||||
|
||||
[system.tsunami.fake_sm_chip]
|
||||
type=IsaFake
|
||||
|
|
@ -973,7 +977,7 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.port[3]
|
||||
pio=system.iobus.master[2]
|
||||
|
||||
[system.tsunami.fake_uart1]
|
||||
type=IsaFake
|
||||
|
|
@ -989,7 +993,7 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.port[4]
|
||||
pio=system.iobus.master[3]
|
||||
|
||||
[system.tsunami.fake_uart2]
|
||||
type=IsaFake
|
||||
|
|
@ -1005,7 +1009,7 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.port[5]
|
||||
pio=system.iobus.master[4]
|
||||
|
||||
[system.tsunami.fake_uart3]
|
||||
type=IsaFake
|
||||
|
|
@ -1021,7 +1025,7 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.port[6]
|
||||
pio=system.iobus.master[5]
|
||||
|
||||
[system.tsunami.fake_uart4]
|
||||
type=IsaFake
|
||||
|
|
@ -1037,7 +1041,7 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.port[7]
|
||||
pio=system.iobus.master[6]
|
||||
|
||||
[system.tsunami.fb]
|
||||
type=BadDevice
|
||||
|
|
@ -1045,7 +1049,7 @@ devicename=FrameBuffer
|
|||
pio_addr=8804615848912
|
||||
pio_latency=1000
|
||||
system=system
|
||||
pio=system.iobus.port[22]
|
||||
pio=system.iobus.master[21]
|
||||
|
||||
[system.tsunami.ide]
|
||||
type=IdeController
|
||||
|
|
@ -1099,9 +1103,9 @@ pci_func=0
|
|||
pio_latency=1000
|
||||
platform=system.tsunami
|
||||
system=system
|
||||
config=system.iobus.port[27]
|
||||
dma=system.iobus.port[28]
|
||||
pio=system.iobus.port[26]
|
||||
config=system.iobus.master[26]
|
||||
dma=system.iobus.slave[1]
|
||||
pio=system.iobus.master[25]
|
||||
|
||||
[system.tsunami.io]
|
||||
type=TsunamiIO
|
||||
|
|
@ -1112,7 +1116,7 @@ system=system
|
|||
time=Thu Jan 1 00:00:00 2009
|
||||
tsunami=system.tsunami
|
||||
year_is_bcd=false
|
||||
pio=system.iobus.port[23]
|
||||
pio=system.iobus.master[22]
|
||||
|
||||
[system.tsunami.pchip]
|
||||
type=TsunamiPChip
|
||||
|
|
@ -1120,7 +1124,7 @@ pio_addr=8802535473152
|
|||
pio_latency=1000
|
||||
system=system
|
||||
tsunami=system.tsunami
|
||||
pio=system.iobus.port[2]
|
||||
pio=system.iobus.master[1]
|
||||
|
||||
[system.tsunami.pciconfig]
|
||||
type=PciConfigAll
|
||||
|
|
@ -1138,5 +1142,5 @@ pio_latency=1000
|
|||
platform=system.tsunami
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
pio=system.iobus.port[24]
|
||||
pio=system.iobus.master[23]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,11 +1,12 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Feb 12 2012 17:15:14
|
||||
gem5 started Feb 12 2012 18:10:30
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3
|
||||
gem5 compiled May 8 2012 15:36:31
|
||||
gem5 started May 8 2012 15:37:06
|
||||
gem5 executing on piton
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux
|
||||
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 1858684403000 because m5_exit instruction encountered
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.858684 # Nu
|
|||
sim_ticks 1858684403000 # Number of ticks simulated
|
||||
final_tick 1858684403000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 192280 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 192280 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 6731751609 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 292636 # Number of bytes of host memory used
|
||||
host_seconds 276.11 # Real time elapsed on the host
|
||||
host_inst_rate 73473 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 73473 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2572309842 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 296656 # Number of bytes of host memory used
|
||||
host_seconds 722.57 # Real time elapsed on the host
|
||||
sim_insts 53089851 # Number of instructions simulated
|
||||
sim_ops 53089851 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 29847552 # Number of bytes read from this memory
|
||||
|
|
@ -117,8 +117,8 @@ system.l2c.blocked_cycles::no_mshrs 0 # nu
|
|||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 117800 # number of writebacks
|
||||
|
|
@ -233,7 +233,7 @@ system.iocache.blocked_cycles::no_targets 0 # n
|
|||
system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs 6169.250477 # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 41512 # number of writebacks
|
||||
|
|
@ -585,30 +585,30 @@ system.tsunami.ethernet.descDMAWrites 0 # Nu
|
|||
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
||||
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
||||
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post
|
||||
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
||||
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
||||
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post
|
||||
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
||||
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
||||
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post
|
||||
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
||||
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
||||
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post
|
||||
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
||||
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
||||
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post
|
||||
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
||||
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
||||
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post
|
||||
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
||||
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
||||
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
||||
system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post
|
||||
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
||||
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
||||
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
||||
system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post
|
||||
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
||||
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
||||
system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post
|
||||
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
||||
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
||||
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
||||
system.cpu.icache.replacements 1025621 # number of replacements
|
||||
|
|
@ -655,7 +655,7 @@ system.cpu.icache.blocked_cycles::no_targets 0
|
|||
system.cpu.icache.blocked::no_mshrs 150 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 11196.646667 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 238 # number of writebacks
|
||||
|
|
|
|||
|
|
@ -10,20 +10,18 @@ time_sync_spin_threshold=100000000
|
|||
type=LinuxArmSystem
|
||||
children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
|
||||
atags_addr=256
|
||||
boot_loader=/projects/pd/randd/dist/binaries/boot.arm
|
||||
boot_loader_mem=system.realview.nvmem
|
||||
boot_loader=/dist/m5/system/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
flags_addr=268435504
|
||||
gic_cpu_addr=520093952
|
||||
init_param=0
|
||||
kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
load_addr_mask=268435455
|
||||
machine_type=RealView_PBX
|
||||
mem_mode=timing
|
||||
memories=system.physmem system.realview.nvmem
|
||||
midr_regval=890224640
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=tests/halt.sh
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
@ -63,7 +61,7 @@ table_size=65536
|
|||
|
||||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img
|
||||
image_file=/dist/m5/system/disks/linux-arm-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.cpu]
|
||||
|
|
@ -662,8 +660,10 @@ warn_access=warn
|
|||
pio=system.membus.default
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
type=SimpleMemory
|
||||
conf_table_reported=true
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
|
|
@ -894,8 +894,10 @@ system=system
|
|||
pio=system.iobus.master[22]
|
||||
|
||||
[system.realview.nvmem]
|
||||
type=PhysicalMemory
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 17 2012 11:46:05
|
||||
gem5 started Mar 17 2012 18:15:21
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-checker
|
||||
gem5 compiled May 8 2012 15:17:37
|
||||
gem5 started May 8 2012 17:08:48
|
||||
gem5 executing on piton
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
info: Using bootloader at address 0x80000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 2501676293500 because m5_exit instruction encountered
|
||||
|
|
|
|||
|
|
@ -4,22 +4,13 @@ sim_seconds 2.501676 # Nu
|
|||
sim_ticks 2501676293500 # Number of ticks simulated
|
||||
final_tick 2501676293500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 79857 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 103150 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 3360326389 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 381664 # Number of bytes of host memory used
|
||||
host_seconds 744.47 # Real time elapsed on the host
|
||||
host_inst_rate 32851 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 42433 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1382341341 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 388632 # Number of bytes of host memory used
|
||||
host_seconds 1809.74 # Real time elapsed on the host
|
||||
sim_insts 59451291 # Number of instructions simulated
|
||||
sim_ops 76792341 # Number of ops (including micro ops) simulated
|
||||
system.realview.nvmem.bytes_read 64 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read 64 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory
|
||||
system.realview.nvmem.num_reads 1 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory
|
||||
system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory
|
||||
system.realview.nvmem.bw_read 26 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read 26 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total 26 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bytes_read 129652968 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 1121024 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 9585096 # Number of bytes written to this memory
|
||||
|
|
@ -30,6 +21,15 @@ system.physmem.bw_read 51826437 # To
|
|||
system.physmem.bw_inst_read 448109 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write 3831469 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total 55657906 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bytes_read 64 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read 64 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory
|
||||
system.realview.nvmem.num_reads 1 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory
|
||||
system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory
|
||||
system.realview.nvmem.bw_read 26 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read 26 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total 26 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.l2c.replacements 119784 # number of replacements
|
||||
system.l2c.tagsinuse 25999.615357 # Cycle average of tags in use
|
||||
system.l2c.total_refs 1826145 # Total number of references to valid blocks.
|
||||
|
|
@ -169,8 +169,8 @@ system.l2c.blocked_cycles::no_mshrs 0 # nu
|
|||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 102641 # number of writebacks
|
||||
|
|
@ -683,7 +683,7 @@ system.cpu.icache.blocked_cycles::no_targets 0
|
|||
system.cpu.icache.blocked::no_mshrs 416 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 7692.266827 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 59844 # number of writebacks
|
||||
|
|
@ -858,14 +858,14 @@ system.iocache.replacements 0 # nu
|
|||
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
||||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
|
||||
system.iocache.avg_refs no_value # Average number of references to valid blocks.
|
||||
system.iocache.avg_refs nan # Average number of references to valid blocks.
|
||||
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1296055922339 # number of ReadReq MSHR uncacheable cycles
|
||||
|
|
|
|||
|
|
@ -10,20 +10,18 @@ time_sync_spin_threshold=100000000
|
|||
type=LinuxArmSystem
|
||||
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
|
||||
atags_addr=256
|
||||
boot_loader=/projects/pd/randd/dist/binaries/boot.arm
|
||||
boot_loader_mem=system.realview.nvmem
|
||||
boot_loader=/dist/m5/system/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
flags_addr=268435504
|
||||
gic_cpu_addr=520093952
|
||||
init_param=0
|
||||
kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
load_addr_mask=268435455
|
||||
machine_type=RealView_PBX
|
||||
mem_mode=timing
|
||||
memories=system.physmem system.realview.nvmem
|
||||
midr_regval=890224640
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=tests/halt.sh
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
@ -63,7 +61,7 @@ table_size=65536
|
|||
|
||||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img
|
||||
image_file=/dist/m5/system/disks/linux-arm-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.cpu0]
|
||||
|
|
@ -1045,8 +1043,10 @@ warn_access=warn
|
|||
pio=system.membus.default
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
type=SimpleMemory
|
||||
conf_table_reported=true
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
|
|
@ -1277,8 +1277,10 @@ system=system
|
|||
pio=system.iobus.master[22]
|
||||
|
||||
[system.realview.nvmem]
|
||||
type=PhysicalMemory
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 17 2012 11:46:05
|
||||
gem5 started Mar 17 2012 18:22:04
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual
|
||||
gem5 compiled May 8 2012 15:17:37
|
||||
gem5 started May 8 2012 17:10:02
|
||||
gem5 executing on piton
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
info: Using bootloader at address 0x80000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 2570828403500 because m5_exit instruction encountered
|
||||
|
|
|
|||
|
|
@ -4,22 +4,13 @@ sim_seconds 2.570828 # Nu
|
|||
sim_ticks 2570828403500 # Number of ticks simulated
|
||||
final_tick 2570828403500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 96885 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 125154 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 4026902595 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 385208 # Number of bytes of host memory used
|
||||
host_seconds 638.41 # Real time elapsed on the host
|
||||
host_inst_rate 36466 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 47106 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1515652841 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 392156 # Number of bytes of host memory used
|
||||
host_seconds 1696.19 # Real time elapsed on the host
|
||||
sim_insts 61852501 # Number of instructions simulated
|
||||
sim_ops 79899751 # Number of ops (including micro ops) simulated
|
||||
system.realview.nvmem.bytes_read 384 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read 384 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory
|
||||
system.realview.nvmem.num_reads 6 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory
|
||||
system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory
|
||||
system.realview.nvmem.bw_read 149 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read 149 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total 149 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bytes_read 131418468 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 1192320 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 10172560 # Number of bytes written to this memory
|
||||
|
|
@ -30,6 +21,15 @@ system.physmem.bw_read 51119113 # To
|
|||
system.physmem.bw_inst_read 463788 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write 3956919 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total 55076032 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bytes_read 384 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read 384 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory
|
||||
system.realview.nvmem.num_reads 6 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory
|
||||
system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory
|
||||
system.realview.nvmem.bw_read 149 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read 149 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total 149 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.l2c.replacements 130877 # number of replacements
|
||||
system.l2c.tagsinuse 27573.095607 # Cycle average of tags in use
|
||||
system.l2c.total_refs 1846037 # Total number of references to valid blocks.
|
||||
|
|
@ -267,8 +267,8 @@ system.l2c.blocked_cycles::no_mshrs 0 # nu
|
|||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 111616 # number of writebacks
|
||||
|
|
@ -812,7 +812,7 @@ system.cpu0.icache.blocked_cycles::no_targets 0
|
|||
system.cpu0.icache.blocked::no_mshrs 206 # number of cycles access was blocked
|
||||
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.icache.avg_blocked_cycles::no_mshrs 8213.548544 # average number of cycles each access was blocked
|
||||
system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.icache.writebacks::writebacks 19233 # number of writebacks
|
||||
|
|
@ -1345,7 +1345,7 @@ system.cpu1.icache.blocked_cycles::no_targets 0
|
|||
system.cpu1.icache.blocked::no_mshrs 234 # number of cycles access was blocked
|
||||
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.icache.avg_blocked_cycles::no_mshrs 6555.529915 # average number of cycles each access was blocked
|
||||
system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.icache.writebacks::writebacks 32964 # number of writebacks
|
||||
|
|
@ -1523,14 +1523,14 @@ system.iocache.replacements 0 # nu
|
|||
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
||||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
|
||||
system.iocache.avg_refs no_value # Average number of references to valid blocks.
|
||||
system.iocache.avg_refs nan # Average number of references to valid blocks.
|
||||
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1308112364906 # number of ReadReq MSHR uncacheable cycles
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual FAILED!
|
||||
build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual FAILED!
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -10,20 +10,18 @@ time_sync_spin_threshold=100000000
|
|||
type=LinuxArmSystem
|
||||
children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
|
||||
atags_addr=256
|
||||
boot_loader=/projects/pd/randd/dist/binaries/boot.arm
|
||||
boot_loader_mem=system.realview.nvmem
|
||||
boot_loader=/dist/m5/system/binaries/boot.arm
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
|
||||
flags_addr=268435504
|
||||
gic_cpu_addr=520093952
|
||||
init_param=0
|
||||
kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
load_addr_mask=268435455
|
||||
machine_type=RealView_PBX
|
||||
mem_mode=timing
|
||||
memories=system.physmem system.realview.nvmem
|
||||
midr_regval=890224640
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=tests/halt.sh
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
@ -63,7 +61,7 @@ table_size=65536
|
|||
|
||||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img
|
||||
image_file=/dist/m5/system/disks/linux-arm-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.cpu]
|
||||
|
|
@ -603,8 +601,10 @@ warn_access=warn
|
|||
pio=system.membus.default
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
type=SimpleMemory
|
||||
conf_table_reported=true
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
|
|
@ -835,8 +835,10 @@ system=system
|
|||
pio=system.iobus.master[22]
|
||||
|
||||
[system.realview.nvmem]
|
||||
type=PhysicalMemory
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 17 2012 11:46:05
|
||||
gem5 started Mar 17 2012 18:11:20
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3
|
||||
gem5 compiled May 8 2012 15:17:37
|
||||
gem5 started May 8 2012 17:05:43
|
||||
gem5 executing on piton
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
|
||||
info: Using bootloader at address 0x80000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 2501676293500 because m5_exit instruction encountered
|
||||
|
|
|
|||
|
|
@ -4,22 +4,13 @@ sim_seconds 2.501676 # Nu
|
|||
sim_ticks 2501676293500 # Number of ticks simulated
|
||||
final_tick 2501676293500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 93944 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 121345 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 3953091411 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 381372 # Number of bytes of host memory used
|
||||
host_seconds 632.84 # Real time elapsed on the host
|
||||
host_inst_rate 32202 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 41595 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1355039119 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 388344 # Number of bytes of host memory used
|
||||
host_seconds 1846.20 # Real time elapsed on the host
|
||||
sim_insts 59451291 # Number of instructions simulated
|
||||
sim_ops 76792341 # Number of ops (including micro ops) simulated
|
||||
system.realview.nvmem.bytes_read 64 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read 64 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory
|
||||
system.realview.nvmem.num_reads 1 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory
|
||||
system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory
|
||||
system.realview.nvmem.bw_read 26 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read 26 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total 26 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bytes_read 129652968 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 1121024 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 9585096 # Number of bytes written to this memory
|
||||
|
|
@ -30,6 +21,15 @@ system.physmem.bw_read 51826437 # To
|
|||
system.physmem.bw_inst_read 448109 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write 3831469 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total 55657906 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bytes_read 64 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read 64 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory
|
||||
system.realview.nvmem.num_reads 1 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory
|
||||
system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory
|
||||
system.realview.nvmem.bw_read 26 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read 26 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total 26 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.l2c.replacements 119784 # number of replacements
|
||||
system.l2c.tagsinuse 25999.615357 # Cycle average of tags in use
|
||||
system.l2c.total_refs 1826145 # Total number of references to valid blocks.
|
||||
|
|
@ -169,8 +169,8 @@ system.l2c.blocked_cycles::no_mshrs 0 # nu
|
|||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 102641 # number of writebacks
|
||||
|
|
@ -638,7 +638,7 @@ system.cpu.icache.blocked_cycles::no_targets 0
|
|||
system.cpu.icache.blocked::no_mshrs 416 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 7692.266827 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 59844 # number of writebacks
|
||||
|
|
@ -813,14 +813,14 @@ system.iocache.replacements 0 # nu
|
|||
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
||||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
|
||||
system.iocache.avg_refs no_value # Average number of references to valid blocks.
|
||||
system.iocache.avg_refs nan # Average number of references to valid blocks.
|
||||
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1296055922339 # number of ReadReq MSHR uncacheable cycles
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Apr 22 2012 22:41:43
|
||||
gem5 started Apr 22 2012 23:27:12
|
||||
gem5 executing on burrito
|
||||
gem5 compiled May 8 2012 15:05:30
|
||||
gem5 started May 8 2012 16:05:33
|
||||
gem5 executing on piton
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
|
||||
warning: add_child('terminal'): child 'terminal' already has parent
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 5.169500 # Nu
|
|||
sim_ticks 5169499540500 # Number of ticks simulated
|
||||
final_tick 5169499540500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 164266 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 323704 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1990886287 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 388036 # Number of bytes of host memory used
|
||||
host_seconds 2596.58 # Real time elapsed on the host
|
||||
host_inst_rate 77808 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 153328 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 943017240 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 366644 # Number of bytes of host memory used
|
||||
host_seconds 5481.87 # Real time elapsed on the host
|
||||
sim_insts 426530860 # Number of instructions simulated
|
||||
sim_ops 840523890 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 15909184 # Number of bytes read from this memory
|
||||
|
|
@ -150,8 +150,8 @@ system.l2c.blocked_cycles::no_mshrs 0 # nu
|
|||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 141885 # number of writebacks
|
||||
|
|
@ -287,7 +287,7 @@ system.iocache.blocked_cycles::no_targets 0 # n
|
|||
system.iocache.blocked::no_mshrs 11251 # number of cycles access was blocked
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs 6119.680384 # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 46668 # number of writebacks
|
||||
|
|
@ -645,7 +645,7 @@ system.cpu.icache.blocked_cycles::no_targets 0
|
|||
system.cpu.icache.blocked::no_mshrs 292 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 9866.404110 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 1570 # number of writebacks
|
||||
|
|
@ -722,8 +722,8 @@ system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0
|
|||
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.itb_walker_cache.writebacks::writebacks 1487 # number of writebacks
|
||||
|
|
@ -790,8 +790,8 @@ system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0
|
|||
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dtb_walker_cache.writebacks::writebacks 34129 # number of writebacks
|
||||
|
|
@ -869,7 +869,7 @@ system.cpu.dcache.blocked_cycles::no_targets 0
|
|||
system.cpu.dcache.blocked::no_mshrs 3499 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 6796.936553 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 1561356 # number of writebacks
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@ e820_table=system.e820_table
|
|||
init_param=0
|
||||
intel_mp_pointer=system.intel_mp_pointer
|
||||
intel_mp_table=system.intel_mp_table
|
||||
kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
|
||||
kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
|
||||
load_addr_mask=18446744073709551615
|
||||
mem_mode=timing
|
||||
memories=system.physmem
|
||||
|
|
@ -995,7 +995,7 @@ table_size=65536
|
|||
|
||||
[system.pc.south_bridge.ide.disks0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
|
||||
image_file=/dist/m5/system/disks/linux-x86.img
|
||||
read_only=true
|
||||
|
||||
[system.pc.south_bridge.ide.disks1]
|
||||
|
|
@ -1015,7 +1015,7 @@ table_size=65536
|
|||
|
||||
[system.pc.south_bridge.ide.disks1.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
|
||||
image_file=/dist/m5/system/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.pc.south_bridge.int_lines0]
|
||||
|
|
|
|||
|
|
@ -34,27 +34,27 @@ periodic_stats_period: 1000000
|
|||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Apr/30/2012 03:41:58
|
||||
Real time: May/08/2012 16:45:52
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 635
|
||||
Elapsed_time_in_minutes: 10.5833
|
||||
Elapsed_time_in_hours: 0.176389
|
||||
Elapsed_time_in_days: 0.00734954
|
||||
Elapsed_time_in_seconds: 1474
|
||||
Elapsed_time_in_minutes: 24.5667
|
||||
Elapsed_time_in_hours: 0.409444
|
||||
Elapsed_time_in_days: 0.0170602
|
||||
|
||||
Virtual_time_in_seconds: 634.41
|
||||
Virtual_time_in_minutes: 10.5735
|
||||
Virtual_time_in_hours: 0.176225
|
||||
Virtual_time_in_days: 0.00734271
|
||||
Virtual_time_in_seconds: 1451.34
|
||||
Virtual_time_in_minutes: 24.189
|
||||
Virtual_time_in_hours: 0.40315
|
||||
Virtual_time_in_days: 0.0167979
|
||||
|
||||
Ruby_current_time: 10609379371
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 10609379371
|
||||
|
||||
mbytes_resident: 267.07
|
||||
mbytes_total: 511.406
|
||||
resident_ratio: 0.522235
|
||||
mbytes_resident: 266.27
|
||||
mbytes_total: 468.445
|
||||
resident_ratio: 0.568411
|
||||
|
||||
ruby_cycles_executed: [ 10609379372 10609379372 ]
|
||||
|
||||
|
|
@ -123,13 +123,13 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 9 count: 4764816 average: 0.0223746 |
|
|||
Resource Usage
|
||||
--------------
|
||||
page_size: 4096
|
||||
user_time: 634
|
||||
user_time: 1451
|
||||
system_time: 0
|
||||
page_reclaims: 70180
|
||||
page_faults: 196
|
||||
page_reclaims: 69308
|
||||
page_faults: 15
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
block_inputs: 14664
|
||||
block_outputs: 768
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
|
|
|||
|
|
@ -1,12 +1,13 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Apr 30 2012 03:31:05
|
||||
gem5 started Apr 30 2012 03:31:22
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86_MESI_CMP_directory/gem5.fast -d build/X86_MESI_CMP_directory/tests/fast/quick/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/X86_MESI_CMP_directory/tests/fast/quick/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory
|
||||
gem5 compiled May 8 2012 16:21:06
|
||||
gem5 started May 8 2012 16:21:17
|
||||
gem5 executing on piton
|
||||
command line: build/X86_MESI_CMP_directory/gem5.opt -d build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory
|
||||
warning: add_child('terminal'): child 'terminal' already has parent
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
|
||||
info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
|
||||
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 5304689685500 because m5_exit instruction encountered
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 5.304690 # Nu
|
|||
sim_ticks 5304689685500 # Number of ticks simulated
|
||||
final_tick 5304689685500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 216507 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 442292 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 8367043691 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 523684 # Number of bytes of host memory used
|
||||
host_seconds 634.00 # Real time elapsed on the host
|
||||
host_inst_rate 93103 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 190197 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 3598037208 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 479692 # Number of bytes of host memory used
|
||||
host_seconds 1474.33 # Real time elapsed on the host
|
||||
sim_insts 137264752 # Number of instructions simulated
|
||||
sim_ops 280412254 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 1392025556 # Number of bytes read from this memory
|
||||
|
|
|
|||
|
|
@ -19,7 +19,7 @@ init_param=0
|
|||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
memories=system.rom system.hypervisor_desc system.physmem2 system.nvram system.physmem system.partition_desc
|
||||
memories=system.hypervisor_desc system.nvram system.partition_desc system.physmem2 system.rom system.physmem
|
||||
num_work_ids=16
|
||||
nvram=system.nvram
|
||||
nvram_addr=133429198848
|
||||
|
|
@ -29,7 +29,6 @@ openboot_bin=/dist/m5/system/binaries/openboot_new.bin
|
|||
partition_desc=system.partition_desc
|
||||
partition_desc_addr=133445976064
|
||||
partition_desc_bin=/dist/m5/system/binaries/1up-md.bin
|
||||
physmem=system.physmem
|
||||
readfile=tests/halt.sh
|
||||
reset_addr=1099243192320
|
||||
reset_bin=/dist/m5/system/binaries/reset_new.bin
|
||||
|
|
@ -42,7 +41,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[9]
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.bridge]
|
||||
type=Bridge
|
||||
|
|
@ -52,8 +51,8 @@ ranges=133412421632:133412421639 134217728000:554050781183 644245094400:65283502
|
|||
req_size=16
|
||||
resp_size=16
|
||||
write_ack=false
|
||||
master=system.iobus.port[14]
|
||||
slave=system.membus.port[2]
|
||||
master=system.iobus.slave[0]
|
||||
slave=system.membus.master[2]
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
|
|
@ -66,6 +65,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
|
|
@ -84,8 +84,8 @@ system=system
|
|||
tracer=system.cpu.tracer
|
||||
width=1
|
||||
workload=
|
||||
dcache_port=system.membus.port[11]
|
||||
icache_port=system.membus.port[10]
|
||||
dcache_port=system.membus.slave[2]
|
||||
icache_port=system.membus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=SparcTLB
|
||||
|
|
@ -108,7 +108,7 @@ image=system.disk0.image
|
|||
pio_addr=134217728000
|
||||
pio_latency=2
|
||||
system=system
|
||||
pio=system.iobus.port[15]
|
||||
pio=system.iobus.master[14]
|
||||
|
||||
[system.disk0.image]
|
||||
type=CowDiskImage
|
||||
|
|
@ -124,14 +124,16 @@ image_file=/dist/m5/system/disks/disk.s10hw2
|
|||
read_only=true
|
||||
|
||||
[system.hypervisor_desc]
|
||||
type=PhysicalMemory
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=60
|
||||
latency_var=0
|
||||
null=false
|
||||
range=133446500352:133446508543
|
||||
zero=false
|
||||
port=system.membus.port[7]
|
||||
port=system.membus.master[7]
|
||||
|
||||
[system.intrctrl]
|
||||
type=IntrControl
|
||||
|
|
@ -145,7 +147,8 @@ clock=2
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.t1000.fake_clk.pio system.t1000.fake_membnks.pio system.t1000.fake_l2_1.pio system.t1000.fake_l2_2.pio system.t1000.fake_l2_3.pio system.t1000.fake_l2_4.pio system.t1000.fake_l2esr_1.pio system.t1000.fake_l2esr_2.pio system.t1000.fake_l2esr_3.pio system.t1000.fake_l2esr_4.pio system.t1000.fake_ssi.pio system.t1000.fake_jbi.pio system.t1000.puart0.pio system.t1000.hvuart.pio system.bridge.master system.disk0.pio
|
||||
master=system.t1000.fake_clk.pio system.t1000.fake_membnks.pio system.t1000.fake_l2_1.pio system.t1000.fake_l2_2.pio system.t1000.fake_l2_3.pio system.t1000.fake_l2_4.pio system.t1000.fake_l2esr_1.pio system.t1000.fake_l2esr_2.pio system.t1000.fake_l2esr_3.pio system.t1000.fake_l2esr_4.pio system.t1000.fake_ssi.pio system.t1000.fake_jbi.pio system.t1000.puart0.pio system.t1000.hvuart.pio system.disk0.pio
|
||||
slave=system.bridge.master
|
||||
|
||||
[system.membus]
|
||||
type=Bus
|
||||
|
|
@ -157,7 +160,8 @@ header_cycles=1
|
|||
use_default_range=false
|
||||
width=64
|
||||
default=system.membus.badaddr_responder.pio
|
||||
port=system.t1000.iob.pio system.t1000.htod.pio system.bridge.slave system.physmem.port[0] system.physmem2.port[0] system.rom.port[0] system.nvram.port[0] system.hypervisor_desc.port[0] system.partition_desc.port[0] system.system_port system.cpu.icache_port system.cpu.dcache_port
|
||||
master=system.t1000.iob.pio system.t1000.htod.pio system.bridge.slave system.physmem.port[0] system.physmem2.port[0] system.rom.port[0] system.nvram.port[0] system.hypervisor_desc.port[0] system.partition_desc.port[0]
|
||||
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
|
|
@ -176,54 +180,64 @@ warn_access=
|
|||
pio=system.membus.default
|
||||
|
||||
[system.nvram]
|
||||
type=PhysicalMemory
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=60
|
||||
latency_var=0
|
||||
null=false
|
||||
range=133429198848:133429207039
|
||||
zero=false
|
||||
port=system.membus.port[6]
|
||||
port=system.membus.master[6]
|
||||
|
||||
[system.partition_desc]
|
||||
type=PhysicalMemory
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=60
|
||||
latency_var=0
|
||||
null=false
|
||||
range=133445976064:133445984255
|
||||
zero=false
|
||||
port=system.membus.port[8]
|
||||
port=system.membus.master[8]
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=60
|
||||
latency_var=0
|
||||
null=false
|
||||
range=1048576:68157439
|
||||
zero=true
|
||||
port=system.membus.port[3]
|
||||
port=system.membus.master[3]
|
||||
|
||||
[system.physmem2]
|
||||
type=PhysicalMemory
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=60
|
||||
latency_var=0
|
||||
null=false
|
||||
range=2147483648:2415919103
|
||||
zero=true
|
||||
port=system.membus.port[4]
|
||||
port=system.membus.master[4]
|
||||
|
||||
[system.rom]
|
||||
type=PhysicalMemory
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=60
|
||||
latency_var=0
|
||||
null=false
|
||||
range=1099243192320:1099251580927
|
||||
zero=false
|
||||
port=system.membus.port[5]
|
||||
port=system.membus.master[5]
|
||||
|
||||
[system.t1000]
|
||||
type=T1000
|
||||
|
|
@ -245,7 +259,7 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.port[0]
|
||||
pio=system.iobus.master[0]
|
||||
|
||||
[system.t1000.fake_jbi]
|
||||
type=IsaFake
|
||||
|
|
@ -261,7 +275,7 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.port[11]
|
||||
pio=system.iobus.master[11]
|
||||
|
||||
[system.t1000.fake_l2_1]
|
||||
type=IsaFake
|
||||
|
|
@ -277,7 +291,7 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=true
|
||||
warn_access=
|
||||
pio=system.iobus.port[2]
|
||||
pio=system.iobus.master[2]
|
||||
|
||||
[system.t1000.fake_l2_2]
|
||||
type=IsaFake
|
||||
|
|
@ -293,7 +307,7 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=true
|
||||
warn_access=
|
||||
pio=system.iobus.port[3]
|
||||
pio=system.iobus.master[3]
|
||||
|
||||
[system.t1000.fake_l2_3]
|
||||
type=IsaFake
|
||||
|
|
@ -309,7 +323,7 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=true
|
||||
warn_access=
|
||||
pio=system.iobus.port[4]
|
||||
pio=system.iobus.master[4]
|
||||
|
||||
[system.t1000.fake_l2_4]
|
||||
type=IsaFake
|
||||
|
|
@ -325,7 +339,7 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=true
|
||||
warn_access=
|
||||
pio=system.iobus.port[5]
|
||||
pio=system.iobus.master[5]
|
||||
|
||||
[system.t1000.fake_l2esr_1]
|
||||
type=IsaFake
|
||||
|
|
@ -341,7 +355,7 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=true
|
||||
warn_access=
|
||||
pio=system.iobus.port[6]
|
||||
pio=system.iobus.master[6]
|
||||
|
||||
[system.t1000.fake_l2esr_2]
|
||||
type=IsaFake
|
||||
|
|
@ -357,7 +371,7 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=true
|
||||
warn_access=
|
||||
pio=system.iobus.port[7]
|
||||
pio=system.iobus.master[7]
|
||||
|
||||
[system.t1000.fake_l2esr_3]
|
||||
type=IsaFake
|
||||
|
|
@ -373,7 +387,7 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=true
|
||||
warn_access=
|
||||
pio=system.iobus.port[8]
|
||||
pio=system.iobus.master[8]
|
||||
|
||||
[system.t1000.fake_l2esr_4]
|
||||
type=IsaFake
|
||||
|
|
@ -389,7 +403,7 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=true
|
||||
warn_access=
|
||||
pio=system.iobus.port[9]
|
||||
pio=system.iobus.master[9]
|
||||
|
||||
[system.t1000.fake_membnks]
|
||||
type=IsaFake
|
||||
|
|
@ -405,7 +419,7 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.port[1]
|
||||
pio=system.iobus.master[1]
|
||||
|
||||
[system.t1000.fake_ssi]
|
||||
type=IsaFake
|
||||
|
|
@ -421,7 +435,7 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.port[10]
|
||||
pio=system.iobus.master[10]
|
||||
|
||||
[system.t1000.hterm]
|
||||
type=Terminal
|
||||
|
|
@ -436,7 +450,7 @@ pio_addr=1099255906296
|
|||
pio_latency=2
|
||||
system=system
|
||||
time=Thu Jan 1 00:00:00 2009
|
||||
pio=system.membus.port[1]
|
||||
pio=system.membus.master[1]
|
||||
|
||||
[system.t1000.hvuart]
|
||||
type=Uart8250
|
||||
|
|
@ -445,14 +459,14 @@ pio_latency=2
|
|||
platform=system.t1000
|
||||
system=system
|
||||
terminal=system.t1000.hterm
|
||||
pio=system.iobus.port[13]
|
||||
pio=system.iobus.master[13]
|
||||
|
||||
[system.t1000.iob]
|
||||
type=Iob
|
||||
pio_latency=2
|
||||
platform=system.t1000
|
||||
system=system
|
||||
pio=system.membus.port[0]
|
||||
pio=system.membus.master[0]
|
||||
|
||||
[system.t1000.pterm]
|
||||
type=Terminal
|
||||
|
|
@ -468,5 +482,5 @@ pio_latency=2
|
|||
platform=system.t1000
|
||||
system=system
|
||||
terminal=system.t1000.pterm
|
||||
pio=system.iobus.port[12]
|
||||
pio=system.iobus.master[12]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,12 +1,15 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Feb 11 2012 13:08:33
|
||||
gem5 started Feb 11 2012 14:02:46
|
||||
gem5 executing on zizzer
|
||||
command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re tests/run.py build/SPARC/tests/fast/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic
|
||||
gem5 compiled May 8 2012 15:05:42
|
||||
gem5 started May 8 2012 15:49:20
|
||||
gem5 executing on piton
|
||||
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re tests/run.py build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic
|
||||
Global frequency set at 2000000000 ticks per second
|
||||
info: No kernel set for full system simulation. Assuming you know what you're doing...
|
||||
info: No kernel set for full system simulation. Assuming you know what you're doing if not SPARC ISA
|
||||
0: system.t1000.htod: Real-time clock set to Thu Jan 1 00:00:00 2009
|
||||
|
||||
0: system.t1000.htod: Real-time clock set to 1230768000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Ignoring write to SPARC ERROR regsiter
|
||||
info: Ignoring write to SPARC ERROR regsiter
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.116889 # Nu
|
|||
sim_ticks 2233777512 # Number of ticks simulated
|
||||
final_tick 2233777512 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 2000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 4520258 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 4522035 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 4531400 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 500812 # Number of bytes of host memory used
|
||||
host_seconds 492.96 # Real time elapsed on the host
|
||||
host_inst_rate 1707325 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1707996 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1711534 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 511008 # Number of bytes of host memory used
|
||||
host_seconds 1305.13 # Real time elapsed on the host
|
||||
sim_insts 2228284650 # Number of instructions simulated
|
||||
sim_ops 2229160714 # Number of ops (including micro ops) simulated
|
||||
system.hypervisor_desc.bytes_read 16792 # Number of bytes read from this memory
|
||||
|
|
@ -19,15 +19,23 @@ system.hypervisor_desc.num_writes 0 # Nu
|
|||
system.hypervisor_desc.num_other 0 # Number of other requests responded to by this memory
|
||||
system.hypervisor_desc.bw_read 15035 # Total read bandwidth from this memory (bytes/s)
|
||||
system.hypervisor_desc.bw_total 15035 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.rom.bytes_read 1128688 # Number of bytes read from this memory
|
||||
system.rom.bytes_inst_read 432296 # Number of instructions bytes read from this memory
|
||||
system.rom.bytes_written 0 # Number of bytes written to this memory
|
||||
system.rom.num_reads 195123 # Number of read requests responded to by this memory
|
||||
system.rom.num_writes 0 # Number of write requests responded to by this memory
|
||||
system.rom.num_other 0 # Number of other requests responded to by this memory
|
||||
system.rom.bw_read 1010564 # Total read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_inst_read 387054 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_total 1010564 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.nvram.bytes_read 284 # Number of bytes read from this memory
|
||||
system.nvram.bytes_inst_read 0 # Number of instructions bytes read from this memory
|
||||
system.nvram.bytes_written 92 # Number of bytes written to this memory
|
||||
system.nvram.num_reads 284 # Number of read requests responded to by this memory
|
||||
system.nvram.num_writes 92 # Number of write requests responded to by this memory
|
||||
system.nvram.num_other 0 # Number of other requests responded to by this memory
|
||||
system.nvram.bw_read 254 # Total read bandwidth from this memory (bytes/s)
|
||||
system.nvram.bw_write 82 # Write bandwidth from this memory (bytes/s)
|
||||
system.nvram.bw_total 337 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.partition_desc.bytes_read 4846 # Number of bytes read from this memory
|
||||
system.partition_desc.bytes_inst_read 0 # Number of instructions bytes read from this memory
|
||||
system.partition_desc.bytes_written 0 # Number of bytes written to this memory
|
||||
system.partition_desc.num_reads 608 # Number of read requests responded to by this memory
|
||||
system.partition_desc.num_writes 0 # Number of write requests responded to by this memory
|
||||
system.partition_desc.num_other 0 # Number of other requests responded to by this memory
|
||||
system.partition_desc.bw_read 4339 # Total read bandwidth from this memory (bytes/s)
|
||||
system.partition_desc.bw_total 4339 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem2.bytes_read 9813991967 # Number of bytes read from this memory
|
||||
system.physmem2.bytes_inst_read 8318106840 # Number of instructions bytes read from this memory
|
||||
system.physmem2.bytes_written 897268422 # Number of bytes written to this memory
|
||||
|
|
@ -38,15 +46,15 @@ system.physmem2.bw_read 8786901931 # To
|
|||
system.physmem2.bw_inst_read 7447569684 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem2.bw_write 803364182 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem2.bw_total 9590266113 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.nvram.bytes_read 284 # Number of bytes read from this memory
|
||||
system.nvram.bytes_inst_read 0 # Number of instructions bytes read from this memory
|
||||
system.nvram.bytes_written 92 # Number of bytes written to this memory
|
||||
system.nvram.num_reads 284 # Number of read requests responded to by this memory
|
||||
system.nvram.num_writes 92 # Number of write requests responded to by this memory
|
||||
system.nvram.num_other 0 # Number of other requests responded to by this memory
|
||||
system.nvram.bw_read 254 # Total read bandwidth from this memory (bytes/s)
|
||||
system.nvram.bw_write 82 # Write bandwidth from this memory (bytes/s)
|
||||
system.nvram.bw_total 337 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.rom.bytes_read 1128688 # Number of bytes read from this memory
|
||||
system.rom.bytes_inst_read 432296 # Number of instructions bytes read from this memory
|
||||
system.rom.bytes_written 0 # Number of bytes written to this memory
|
||||
system.rom.num_reads 195123 # Number of read requests responded to by this memory
|
||||
system.rom.num_writes 0 # Number of write requests responded to by this memory
|
||||
system.rom.num_other 0 # Number of other requests responded to by this memory
|
||||
system.rom.bw_read 1010564 # Total read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_inst_read 387054 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.rom.bw_total 1010564 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bytes_read 709825348 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 612291324 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 15400223 # Number of bytes written to this memory
|
||||
|
|
@ -57,14 +65,6 @@ system.physmem.bw_read 635538091 # To
|
|||
system.physmem.bw_inst_read 548211557 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write 13788502 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total 649326593 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.partition_desc.bytes_read 4846 # Number of bytes read from this memory
|
||||
system.partition_desc.bytes_inst_read 0 # Number of instructions bytes read from this memory
|
||||
system.partition_desc.bytes_written 0 # Number of bytes written to this memory
|
||||
system.partition_desc.num_reads 608 # Number of read requests responded to by this memory
|
||||
system.partition_desc.num_writes 0 # Number of write requests responded to by this memory
|
||||
system.partition_desc.num_other 0 # Number of other requests responded to by this memory
|
||||
system.partition_desc.bw_read 4339 # Total read bandwidth from this memory (bytes/s)
|
||||
system.partition_desc.bw_total 4339 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.numCycles 2233777513 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@ load_addr_mask=1099511627775
|
|||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[0]
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=InOrderCPU
|
||||
|
|
@ -41,7 +40,6 @@ choiceCtrBits=2
|
|||
choicePredictorSize=8192
|
||||
clock=500
|
||||
cpu_id=0
|
||||
dataMemPort=dcache_port
|
||||
defer_registration=false
|
||||
div16Latency=1
|
||||
div16RepeatRate=1
|
||||
|
|
@ -56,7 +54,6 @@ do_quiesce=true
|
|||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fetchBuffSize=4
|
||||
fetchMemPort=icache_port
|
||||
functionTrace=false
|
||||
functionTraceStart=0
|
||||
function_trace=false
|
||||
|
|
@ -94,7 +91,7 @@ icache_port=system.cpu.icache.cpu_side
|
|||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
addr_range=0:18446744073709551615
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
|
|
@ -115,7 +112,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.port[1]
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
|
|
@ -123,7 +120,7 @@ size=64
|
|||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
addr_range=0:18446744073709551615
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
|
|
@ -144,7 +141,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.port[0]
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
|
@ -155,7 +152,7 @@ size=48
|
|||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_range=0:18446744073709551615
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
|
|
@ -175,8 +172,8 @@ tgts_per_mshr=5
|
|||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.port[2]
|
||||
mem_side=system.membus.port[2]
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
|
|
@ -186,7 +183,8 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -194,7 +192,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing
|
||||
cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -218,15 +216,18 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
master=system.physmem.port[0]
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[1]
|
||||
port=system.membus.master[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Feb 12 2012 17:15:14
|
||||
gem5 started Feb 12 2012 17:33:26
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing
|
||||
gem5 compiled May 8 2012 15:36:31
|
||||
gem5 started May 8 2012 15:38:38
|
||||
gem5 executing on piton
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.274300 # Nu
|
|||
sim_ticks 274300226500 # Number of ticks simulated
|
||||
final_tick 274300226500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 157937 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 157937 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 71980747 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 209892 # Number of bytes of host memory used
|
||||
host_seconds 3810.74 # Real time elapsed on the host
|
||||
host_inst_rate 71153 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 71153 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 32428333 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 214868 # Number of bytes of host memory used
|
||||
host_seconds 8458.66 # Real time elapsed on the host
|
||||
sim_insts 601856964 # Number of instructions simulated
|
||||
sim_ops 601856964 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 5894080 # Number of bytes read from this memory
|
||||
|
|
@ -57,30 +57,6 @@ system.cpu.workload.num_syscalls 17 # Nu
|
|||
system.cpu.numCycles 548600454 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 538371184 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 412150 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 59439534 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 489160920 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 89.165242 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 114514042 # Number of Load instructions committed
|
||||
system.cpu.comStores 39451321 # Number of Store instructions committed
|
||||
system.cpu.comBranches 62547159 # Number of Branches instructions committed
|
||||
system.cpu.comNops 36304520 # Number of Nop instructions committed
|
||||
system.cpu.comNonSpec 17 # Number of Non-Speculative instructions committed
|
||||
system.cpu.comInts 349039879 # Number of Integer instructions committed
|
||||
system.cpu.comFloats 24 # Number of Floating Point instructions committed
|
||||
system.cpu.committedInsts 601856964 # Number of Instructions committed (Per-Thread)
|
||||
system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 0.911513 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 0.911513 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.097077 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 1.097077 # IPC: Total IPC of All Threads
|
||||
system.cpu.branch_predictor.lookups 86318297 # Number of BP lookups
|
||||
system.cpu.branch_predictor.condPredicted 81372201 # Number of conditional branches predicted
|
||||
system.cpu.branch_predictor.condIncorrect 36359139 # Number of conditional branches incorrect
|
||||
|
|
@ -107,6 +83,30 @@ system.cpu.execution_unit.mispredictPct 58.122091 # Pe
|
|||
system.cpu.execution_unit.executions 412334574 # Number of Instructions Executed.
|
||||
system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 538371184 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 412150 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 59439534 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 489160920 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 89.165242 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 114514042 # Number of Load instructions committed
|
||||
system.cpu.comStores 39451321 # Number of Store instructions committed
|
||||
system.cpu.comBranches 62547159 # Number of Branches instructions committed
|
||||
system.cpu.comNops 36304520 # Number of Nop instructions committed
|
||||
system.cpu.comNonSpec 17 # Number of Non-Speculative instructions committed
|
||||
system.cpu.comInts 349039879 # Number of Integer instructions committed
|
||||
system.cpu.comFloats 24 # Number of Floating Point instructions committed
|
||||
system.cpu.committedInsts 601856964 # Number of Instructions committed (Per-Thread)
|
||||
system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 0.911513 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 0.911513 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.097077 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 1.097077 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 209725198 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 338875256 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 61.770867 # Percentage of cycles stage was utilized (processing insts).
|
||||
|
|
@ -165,7 +165,7 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.icache.blocked_cycles::no_targets 87500 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets 29166.666667 # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
|
|
@ -363,7 +363,7 @@ system.cpu.l2cache.blocked_cycles::no_targets 0
|
|||
system.cpu.l2cache.blocked::no_mshrs 127 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10066.929134 # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 59346 # number of writebacks
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@ load_addr_mask=1099511627775
|
|||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[0]
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
|
|
@ -127,7 +126,7 @@ icache_port=system.cpu.icache.cpu_side
|
|||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
addr_range=0:18446744073709551615
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
|
|
@ -148,7 +147,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.port[1]
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
|
|
@ -419,7 +418,7 @@ opLat=3
|
|||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
addr_range=0:18446744073709551615
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
|
|
@ -440,7 +439,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.port[0]
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
|
@ -451,7 +450,7 @@ size=48
|
|||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_range=0:18446744073709551615
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
|
|
@ -471,8 +470,8 @@ tgts_per_mshr=5
|
|||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.port[2]
|
||||
mem_side=system.membus.port[2]
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
|
|
@ -482,7 +481,8 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -490,7 +490,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing
|
||||
cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -514,15 +514,18 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
master=system.physmem.port[0]
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[1]
|
||||
port=system.membus.master[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Feb 12 2012 17:15:14
|
||||
gem5 started Feb 12 2012 17:33:40
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing
|
||||
gem5 compiled May 8 2012 15:36:31
|
||||
gem5 started May 8 2012 15:36:56
|
||||
gem5 executing on piton
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.134621 # Nu
|
|||
sim_ticks 134621123500 # Number of ticks simulated
|
||||
final_tick 134621123500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 282179 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 282179 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 67168296 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 211096 # Number of bytes of host memory used
|
||||
host_seconds 2004.24 # Real time elapsed on the host
|
||||
host_inst_rate 99995 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 99995 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 23802311 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 215740 # Number of bytes of host memory used
|
||||
host_seconds 5655.80 # Real time elapsed on the host
|
||||
sim_insts 565552443 # Number of instructions simulated
|
||||
sim_ops 565552443 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 5937600 # Number of bytes read from this memory
|
||||
|
|
@ -367,8 +367,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 445 # number of ReadReq MSHR hits
|
||||
|
|
@ -577,7 +577,7 @@ system.cpu.l2cache.blocked_cycles::no_targets 0
|
|||
system.cpu.l2cache.blocked::no_mshrs 49 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6928.571429 # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 59343 # number of writebacks
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@ load_addr_mask=1099511627775
|
|||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[0]
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
|
|
@ -39,6 +38,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
|
|
@ -57,8 +57,8 @@ system=system
|
|||
tracer=system.cpu.tracer
|
||||
width=1
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.membus.port[3]
|
||||
icache_port=system.membus.port[2]
|
||||
dcache_port=system.membus.slave[2]
|
||||
icache_port=system.membus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
|
|
@ -77,7 +77,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-atomic
|
||||
cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -101,15 +101,18 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
|
||||
master=system.physmem.port[0]
|
||||
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[1]
|
||||
port=system.membus.master[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Feb 11 2012 13:05:17
|
||||
gem5 started Feb 11 2012 13:10:30
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-atomic
|
||||
gem5 compiled May 8 2012 15:36:31
|
||||
gem5 started May 8 2012 15:37:40
|
||||
gem5 executing on piton
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.300931 # Nu
|
|||
sim_ticks 300930958000 # Number of ticks simulated
|
||||
final_tick 300930958000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 5630967 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 5630966 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2815505896 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 200704 # Number of bytes of host memory used
|
||||
host_seconds 106.88 # Real time elapsed on the host
|
||||
host_inst_rate 2479447 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2479447 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1239733454 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 205680 # Number of bytes of host memory used
|
||||
host_seconds 242.74 # Real time elapsed on the host
|
||||
sim_insts 601856964 # Number of instructions simulated
|
||||
sim_ops 601856964 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 2782990928 # Number of bytes read from this memory
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@ load_addr_mask=1099511627775
|
|||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[0]
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
|
|
@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side
|
|||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
addr_range=0:18446744073709551615
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
|
|
@ -80,7 +79,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.port[1]
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
|
|
@ -88,7 +87,7 @@ size=64
|
|||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
addr_range=0:18446744073709551615
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
|
|
@ -109,7 +108,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.port[0]
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
|
@ -120,7 +119,7 @@ size=48
|
|||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_range=0:18446744073709551615
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
|
|
@ -140,8 +139,8 @@ tgts_per_mshr=5
|
|||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.port[2]
|
||||
mem_side=system.membus.port[2]
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
|
|
@ -151,7 +150,8 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -159,7 +159,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing
|
||||
cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -183,15 +183,18 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
master=system.physmem.port[0]
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[1]
|
||||
port=system.membus.master[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Feb 11 2012 13:05:17
|
||||
gem5 started Feb 11 2012 13:10:31
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing
|
||||
gem5 compiled May 8 2012 15:36:31
|
||||
gem5 started May 8 2012 15:37:07
|
||||
gem5 executing on piton
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.765623 # Nu
|
|||
sim_ticks 765623032000 # Number of ticks simulated
|
||||
final_tick 765623032000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2698243 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2698243 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 3432438217 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 209572 # Number of bytes of host memory used
|
||||
host_seconds 223.06 # Real time elapsed on the host
|
||||
host_inst_rate 835603 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 835603 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1062971026 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 214568 # Number of bytes of host memory used
|
||||
host_seconds 720.27 # Real time elapsed on the host
|
||||
sim_insts 601856964 # Number of instructions simulated
|
||||
sim_ops 601856964 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 5889984 # Number of bytes read from this memory
|
||||
|
|
@ -119,8 +119,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 795 # number of ReadReq MSHR misses
|
||||
|
|
@ -195,8 +195,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 408190 # number of writebacks
|
||||
|
|
@ -302,8 +302,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 59341 # number of writebacks
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@ load_addr_mask=1099511627775
|
|||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
@ -509,12 +508,12 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing
|
||||
cwd=build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/gzip
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -537,8 +536,10 @@ master=system.physmem.port[0]
|
|||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 17 2012 11:46:05
|
||||
gem5 started Mar 17 2012 16:38:16
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing
|
||||
gem5 compiled May 8 2012 15:17:37
|
||||
gem5 started May 8 2012 16:20:58
|
||||
gem5 executing on piton
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.164248 # Nu
|
|||
sim_ticks 164248292500 # Number of ticks simulated
|
||||
final_tick 164248292500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 250614 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 264817 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 72208895 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 224524 # Number of bytes of host memory used
|
||||
host_seconds 2274.63 # Real time elapsed on the host
|
||||
host_inst_rate 95192 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 100587 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 27427613 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 231504 # Number of bytes of host memory used
|
||||
host_seconds 5988.43 # Real time elapsed on the host
|
||||
sim_insts 570052728 # Number of instructions simulated
|
||||
sim_ops 602360935 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 5850432 # Number of bytes read from this memory
|
||||
|
|
@ -377,8 +377,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 310 # number of ReadReq MSHR hits
|
||||
|
|
@ -474,7 +474,7 @@ system.cpu.dcache.blocked_cycles::no_targets 0
|
|||
system.cpu.dcache.blocked::no_mshrs 2180 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 4389.455963 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 394908 # number of writebacks
|
||||
|
|
@ -601,7 +601,7 @@ system.cpu.l2cache.blocked_cycles::no_targets 0
|
|||
system.cpu.l2cache.blocked::no_mshrs 332 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6039.156627 # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 58158 # number of writebacks
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@ load_addr_mask=1099511627775
|
|||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
@ -39,6 +38,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
|
|
@ -95,12 +95,12 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-atomic
|
||||
cwd=build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/gzip
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -123,8 +123,10 @@ master=system.physmem.port[0]
|
|||
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 17 2012 11:46:05
|
||||
gem5 started Mar 17 2012 16:54:39
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-atomic
|
||||
gem5 compiled May 8 2012 15:17:37
|
||||
gem5 started May 8 2012 16:21:51
|
||||
gem5 executing on piton
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.301191 # Nu
|
|||
sim_ticks 301191370000 # Number of ticks simulated
|
||||
final_tick 301191370000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2848986 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3010454 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1505284316 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 213580 # Number of bytes of host memory used
|
||||
host_seconds 200.09 # Real time elapsed on the host
|
||||
host_inst_rate 1201570 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1269670 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 634859326 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 220780 # Number of bytes of host memory used
|
||||
host_seconds 474.42 # Real time elapsed on the host
|
||||
sim_insts 570051644 # Number of instructions simulated
|
||||
sim_ops 602359851 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 2680160157 # Number of bytes read from this memory
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@ load_addr_mask=1099511627775
|
|||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
@ -178,12 +177,12 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing
|
||||
cwd=build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/gzip
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -206,8 +205,10 @@ master=system.physmem.port[0]
|
|||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 17 2012 11:46:05
|
||||
gem5 started Mar 17 2012 16:58:09
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing
|
||||
gem5 compiled May 8 2012 15:17:37
|
||||
gem5 started May 8 2012 16:22:17
|
||||
gem5 executing on piton
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.796763 # Nu
|
|||
sim_ticks 796762926000 # Number of ticks simulated
|
||||
final_tick 796762926000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2008356 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2120897 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2814551305 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 222752 # Number of bytes of host memory used
|
||||
host_seconds 283.09 # Real time elapsed on the host
|
||||
host_inst_rate 606714 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 640712 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 850261270 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 229976 # Number of bytes of host memory used
|
||||
host_seconds 937.08 # Real time elapsed on the host
|
||||
sim_insts 568539343 # Number of instructions simulated
|
||||
sim_ops 600398281 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 5759488 # Number of bytes read from this memory
|
||||
|
|
@ -129,8 +129,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 643 # number of ReadReq MSHR misses
|
||||
|
|
@ -213,8 +213,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 392392 # number of writebacks
|
||||
|
|
@ -323,8 +323,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 57886 # number of writebacks
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@ load_addr_mask=1099511627775
|
|||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[0]
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
|
|
@ -127,7 +126,7 @@ icache_port=system.cpu.icache.cpu_side
|
|||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
addr_range=0:18446744073709551615
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
|
|
@ -148,7 +147,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.port[1]
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=SparcTLB
|
||||
|
|
@ -419,7 +418,7 @@ opLat=3
|
|||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
addr_range=0:18446744073709551615
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
|
|
@ -440,7 +439,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.port[0]
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=SparcInterrupts
|
||||
|
|
@ -451,7 +450,7 @@ size=64
|
|||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_range=0:18446744073709551615
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
|
|
@ -471,8 +470,8 @@ tgts_per_mshr=5
|
|||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.port[2]
|
||||
mem_side=system.membus.port[2]
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
|
|
@ -482,7 +481,8 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -490,7 +490,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing
|
||||
cwd=build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -514,15 +514,18 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
master=system.physmem.port[0]
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[1]
|
||||
port=system.membus.master[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Feb 12 2012 17:18:12
|
||||
gem5 started Feb 12 2012 18:18:25
|
||||
gem5 executing on zizzer
|
||||
command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing
|
||||
gem5 compiled May 8 2012 15:05:42
|
||||
gem5 started May 8 2012 15:43:17
|
||||
gem5 executing on piton
|
||||
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.388554 # Nu
|
|||
sim_ticks 388554296500 # Number of ticks simulated
|
||||
final_tick 388554296500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 229375 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 230098 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 63606554 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 214136 # Number of bytes of host memory used
|
||||
host_seconds 6108.71 # Real time elapsed on the host
|
||||
host_inst_rate 119684 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 120061 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 33188741 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 223864 # Number of bytes of host memory used
|
||||
host_seconds 11707.41 # Real time elapsed on the host
|
||||
sim_insts 1401188958 # Number of instructions simulated
|
||||
sim_ops 1405604152 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 5987456 # Number of bytes read from this memory
|
||||
|
|
@ -333,8 +333,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 624 # number of ReadReq MSHR hits
|
||||
|
|
@ -426,7 +426,7 @@ system.cpu.dcache.blocked_cycles::no_targets 0
|
|||
system.cpu.dcache.blocked::no_mshrs 7 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2214.285714 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 413195 # number of writebacks
|
||||
|
|
@ -549,8 +549,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 59190 # number of writebacks
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@ load_addr_mask=1099511627775
|
|||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[0]
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
|
|
@ -39,6 +38,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
|
|
@ -57,8 +57,8 @@ system=system
|
|||
tracer=system.cpu.tracer
|
||||
width=1
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.membus.port[3]
|
||||
icache_port=system.membus.port[2]
|
||||
dcache_port=system.membus.slave[2]
|
||||
icache_port=system.membus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=SparcTLB
|
||||
|
|
@ -77,7 +77,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-atomic
|
||||
cwd=build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -101,15 +101,18 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
|
||||
master=system.physmem.port[0]
|
||||
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[1]
|
||||
port=system.membus.master[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Feb 11 2012 13:08:33
|
||||
gem5 started Feb 11 2012 13:56:17
|
||||
gem5 executing on zizzer
|
||||
command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-atomic
|
||||
gem5 compiled May 8 2012 15:05:42
|
||||
gem5 started May 8 2012 15:43:18
|
||||
gem5 executing on piton
|
||||
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.744764 # Nu
|
|||
sim_ticks 744764119000 # Number of ticks simulated
|
||||
final_tick 744764119000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 4631105 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 4644873 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2322443893 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 203508 # Number of bytes of host memory used
|
||||
host_seconds 320.68 # Real time elapsed on the host
|
||||
host_inst_rate 1723625 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1728749 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 864377228 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 213676 # Number of bytes of host memory used
|
||||
host_seconds 861.62 # Real time elapsed on the host
|
||||
sim_insts 1485108101 # Number of instructions simulated
|
||||
sim_ops 1489523295 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 7326269637 # Number of bytes read from this memory
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@ load_addr_mask=1099511627775
|
|||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[0]
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
|
|
@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side
|
|||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
addr_range=0:18446744073709551615
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
|
|
@ -80,7 +79,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.port[1]
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=SparcTLB
|
||||
|
|
@ -88,7 +87,7 @@ size=64
|
|||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
addr_range=0:18446744073709551615
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
|
|
@ -109,7 +108,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.port[0]
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=SparcInterrupts
|
||||
|
|
@ -120,7 +119,7 @@ size=64
|
|||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_range=0:18446744073709551615
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
|
|
@ -140,8 +139,8 @@ tgts_per_mshr=5
|
|||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.port[2]
|
||||
mem_side=system.membus.port[2]
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
|
|
@ -151,7 +150,8 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -159,7 +159,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing
|
||||
cwd=build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -183,15 +183,18 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
master=system.physmem.port[0]
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[1]
|
||||
port=system.membus.master[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Feb 11 2012 13:08:33
|
||||
gem5 started Feb 11 2012 13:56:19
|
||||
gem5 executing on zizzer
|
||||
command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing
|
||||
gem5 compiled May 8 2012 15:05:42
|
||||
gem5 started May 8 2012 15:43:22
|
||||
gem5 executing on piton
|
||||
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.064259 # Nu
|
|||
sim_ticks 2064258667000 # Number of ticks simulated
|
||||
final_tick 2064258667000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2132645 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2138986 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2964317062 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 212372 # Number of bytes of host memory used
|
||||
host_seconds 696.37 # Real time elapsed on the host
|
||||
host_inst_rate 667477 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 669461 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 927773801 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 222564 # Number of bytes of host memory used
|
||||
host_seconds 2224.96 # Real time elapsed on the host
|
||||
sim_insts 1485108101 # Number of instructions simulated
|
||||
sim_ops 1489523295 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 5909952 # Number of bytes read from this memory
|
||||
|
|
@ -87,8 +87,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1107 # number of ReadReq MSHR misses
|
||||
|
|
@ -173,8 +173,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 407009 # number of writebacks
|
||||
|
|
@ -289,8 +289,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 59035 # number of writebacks
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@ load_addr_mask=1099511627775
|
|||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[0]
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
|
|
@ -127,7 +126,7 @@ icache_port=system.cpu.icache.cpu_side
|
|||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
addr_range=0:18446744073709551615
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
|
|
@ -148,7 +147,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.port[1]
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
|
|
@ -159,7 +158,7 @@ walker=system.cpu.dtb.walker
|
|||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.port[3]
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
|
|
@ -426,7 +425,7 @@ opLat=3
|
|||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
addr_range=0:18446744073709551615
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
|
|
@ -447,7 +446,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.port[0]
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
|
|
@ -455,8 +454,9 @@ int_latency=1000
|
|||
pio_addr=2305843009213693952
|
||||
pio_latency=1000
|
||||
system=system
|
||||
int_port=system.membus.port[4]
|
||||
pio=system.membus.port[3]
|
||||
int_master=system.membus.slave[2]
|
||||
int_slave=system.membus.master[2]
|
||||
pio=system.membus.master[1]
|
||||
|
||||
[system.cpu.itb]
|
||||
type=X86TLB
|
||||
|
|
@ -467,11 +467,11 @@ walker=system.cpu.itb.walker
|
|||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.port[2]
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_range=0:18446744073709551615
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
|
|
@ -491,8 +491,8 @@ tgts_per_mshr=5
|
|||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.port[4]
|
||||
mem_side=system.membus.port[2]
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
|
|
@ -502,7 +502,8 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -510,7 +511,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing
|
||||
cwd=build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -534,15 +535,18 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
|
||||
master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
|
||||
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[1]
|
||||
port=system.membus.master[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Feb 12 2012 17:18:12
|
||||
gem5 started Feb 12 2012 18:30:36
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing
|
||||
gem5 compiled May 8 2012 15:05:30
|
||||
gem5 started May 8 2012 15:50:46
|
||||
gem5 executing on piton
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.637054 # Nu
|
|||
sim_ticks 637054100000 # Number of ticks simulated
|
||||
final_tick 637054100000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 99624 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 183562 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 72118142 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 221144 # Number of bytes of host memory used
|
||||
host_seconds 8833.48 # Real time elapsed on the host
|
||||
host_inst_rate 56200 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 103552 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 40683578 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 226404 # Number of bytes of host memory used
|
||||
host_seconds 15658.75 # Real time elapsed on the host
|
||||
sim_insts 880025312 # Number of instructions simulated
|
||||
sim_ops 1621493982 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 5835840 # Number of bytes read from this memory
|
||||
|
|
@ -330,8 +330,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 428 # number of ReadReq MSHR hits
|
||||
|
|
@ -412,8 +412,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 400737 # number of writebacks
|
||||
|
|
@ -534,8 +534,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 58331 # number of writebacks
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@ load_addr_mask=1099511627775
|
|||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[0]
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
|
|
@ -39,6 +38,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
|
|
@ -57,8 +57,8 @@ system=system
|
|||
tracer=system.cpu.tracer
|
||||
width=1
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.membus.port[3]
|
||||
icache_port=system.membus.port[2]
|
||||
dcache_port=system.membus.slave[2]
|
||||
icache_port=system.membus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
|
|
@ -69,7 +69,7 @@ walker=system.cpu.dtb.walker
|
|||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
system=system
|
||||
port=system.membus.port[5]
|
||||
port=system.membus.slave[4]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
|
|
@ -77,8 +77,9 @@ int_latency=1000
|
|||
pio_addr=2305843009213693952
|
||||
pio_latency=1000
|
||||
system=system
|
||||
int_port=system.membus.port[7]
|
||||
pio=system.membus.port[6]
|
||||
int_master=system.membus.slave[5]
|
||||
int_slave=system.membus.master[2]
|
||||
pio=system.membus.master[1]
|
||||
|
||||
[system.cpu.itb]
|
||||
type=X86TLB
|
||||
|
|
@ -89,7 +90,7 @@ walker=system.cpu.itb.walker
|
|||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
system=system
|
||||
port=system.membus.port[4]
|
||||
port=system.membus.slave[3]
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -97,7 +98,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-atomic
|
||||
cwd=build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -121,15 +122,18 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port
|
||||
master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
|
||||
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[1]
|
||||
port=system.membus.master[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Feb 11 2012 13:08:53
|
||||
gem5 started Feb 11 2012 14:08:56
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-atomic
|
||||
gem5 compiled May 8 2012 15:05:30
|
||||
gem5 started May 8 2012 15:50:47
|
||||
gem5 executing on piton
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.963993 # Nu
|
|||
sim_ticks 963992704000 # Number of ticks simulated
|
||||
final_tick 963992704000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1632386 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3007760 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1788140018 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 210284 # Number of bytes of host memory used
|
||||
host_seconds 539.10 # Real time elapsed on the host
|
||||
host_inst_rate 616329 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1135620 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 675136354 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 215452 # Number of bytes of host memory used
|
||||
host_seconds 1427.85 # Real time elapsed on the host
|
||||
sim_insts 880025313 # Number of instructions simulated
|
||||
sim_ops 1621493983 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 11334586825 # Number of bytes read from this memory
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@ load_addr_mask=1099511627775
|
|||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[0]
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
|
|
@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side
|
|||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
addr_range=0:18446744073709551615
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
|
|
@ -80,7 +79,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.port[1]
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
|
|
@ -91,11 +90,11 @@ walker=system.cpu.dtb.walker
|
|||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.port[3]
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
addr_range=0:18446744073709551615
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
|
|
@ -116,7 +115,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.port[0]
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
|
|
@ -124,8 +123,9 @@ int_latency=1000
|
|||
pio_addr=2305843009213693952
|
||||
pio_latency=1000
|
||||
system=system
|
||||
int_port=system.membus.port[4]
|
||||
pio=system.membus.port[3]
|
||||
int_master=system.membus.slave[2]
|
||||
int_slave=system.membus.master[2]
|
||||
pio=system.membus.master[1]
|
||||
|
||||
[system.cpu.itb]
|
||||
type=X86TLB
|
||||
|
|
@ -136,11 +136,11 @@ walker=system.cpu.itb.walker
|
|||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.port[2]
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_range=0:18446744073709551615
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
|
|
@ -160,8 +160,8 @@ tgts_per_mshr=5
|
|||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.port[4]
|
||||
mem_side=system.membus.port[2]
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
|
|
@ -171,7 +171,8 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -179,7 +180,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing
|
||||
cwd=build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -203,15 +204,18 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
|
||||
master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
|
||||
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[1]
|
||||
port=system.membus.master[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Feb 11 2012 13:08:53
|
||||
gem5 started Feb 11 2012 14:11:10
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing
|
||||
gem5 compiled May 8 2012 15:05:30
|
||||
gem5 started May 8 2012 15:52:52
|
||||
gem5 executing on piton
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.803259 # Nu
|
|||
sim_ticks 1803258587000 # Number of ticks simulated
|
||||
final_tick 1803258587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 972144 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1791227 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1992018099 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 219200 # Number of bytes of host memory used
|
||||
host_seconds 905.24 # Real time elapsed on the host
|
||||
host_inst_rate 328587 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 605440 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 673307954 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 224396 # Number of bytes of host memory used
|
||||
host_seconds 2678.21 # Real time elapsed on the host
|
||||
sim_insts 880025313 # Number of instructions simulated
|
||||
sim_ops 1621493983 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 5725952 # Number of bytes read from this memory
|
||||
|
|
@ -87,8 +87,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 722 # number of ReadReq MSHR misses
|
||||
|
|
@ -163,8 +163,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 396372 # number of writebacks
|
||||
|
|
@ -270,8 +270,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 58007 # number of writebacks
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@ load_addr_mask=1099511627775
|
|||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
@ -509,14 +508,14 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=mcf mcf.in
|
||||
cwd=build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing
|
||||
cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/mcf
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
|
||||
gid=100
|
||||
input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
|
||||
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -537,8 +536,10 @@ master=system.physmem.port[0]
|
|||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 17 2012 11:46:05
|
||||
gem5 started Mar 17 2012 17:02:50
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing
|
||||
gem5 compiled May 8 2012 15:17:37
|
||||
gem5 started May 8 2012 16:22:28
|
||||
gem5 executing on piton
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.025989 # Nu
|
|||
sim_ticks 25988864000 # Number of ticks simulated
|
||||
final_tick 25988864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 238212 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 239922 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 68332245 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 357212 # Number of bytes of host memory used
|
||||
host_seconds 380.33 # Real time elapsed on the host
|
||||
host_inst_rate 71403 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 71915 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 20482160 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 364344 # Number of bytes of host memory used
|
||||
host_seconds 1268.85 # Real time elapsed on the host
|
||||
sim_insts 90599356 # Number of instructions simulated
|
||||
sim_ops 91249910 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 999040 # Number of bytes read from this memory
|
||||
|
|
@ -378,8 +378,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 223 # number of ReadReq MSHR hits
|
||||
|
|
@ -475,7 +475,7 @@ system.cpu.dcache.blocked_cycles::no_targets 0
|
|||
system.cpu.dcache.blocked::no_mshrs 8078 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2860.120698 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 942908 # number of writebacks
|
||||
|
|
@ -594,8 +594,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 32 # number of writebacks
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@ load_addr_mask=1099511627775
|
|||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
@ -39,6 +38,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
|
|
@ -95,14 +95,14 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=mcf mcf.in
|
||||
cwd=build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-atomic
|
||||
cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/mcf
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
|
||||
gid=100
|
||||
input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
|
||||
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -123,8 +123,10 @@ master=system.physmem.port[0]
|
|||
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 17 2012 11:46:05
|
||||
gem5 started Mar 17 2012 17:03:02
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-atomic
|
||||
gem5 compiled May 8 2012 15:17:37
|
||||
gem5 started May 8 2012 16:24:24
|
||||
gem5 executing on piton
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.054241 # Nu
|
|||
sim_ticks 54240666000 # Number of ticks simulated
|
||||
final_tick 54240666000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2795699 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2815772 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1673691127 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 346432 # Number of bytes of host memory used
|
||||
host_seconds 32.41 # Real time elapsed on the host
|
||||
host_inst_rate 1203852 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1212496 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 720706000 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 353596 # Number of bytes of host memory used
|
||||
host_seconds 75.26 # Real time elapsed on the host
|
||||
sim_insts 90602415 # Number of instructions simulated
|
||||
sim_ops 91252969 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 521339715 # Number of bytes read from this memory
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@ load_addr_mask=1099511627775
|
|||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
@ -178,14 +177,14 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=mcf mcf.in
|
||||
cwd=build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing
|
||||
cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/mcf
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
|
||||
gid=100
|
||||
input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
|
||||
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -206,8 +205,10 @@ master=system.physmem.port[0]
|
|||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 17 2012 11:46:05
|
||||
gem5 started Mar 17 2012 17:03:45
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing
|
||||
gem5 compiled May 8 2012 15:17:37
|
||||
gem5 started May 8 2012 16:24:48
|
||||
gem5 executing on piton
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.148086 # Nu
|
|||
sim_ticks 148086239000 # Number of ticks simulated
|
||||
final_tick 148086239000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1876733 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1890189 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 3068313156 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 355600 # Number of bytes of host memory used
|
||||
host_seconds 48.26 # Real time elapsed on the host
|
||||
host_inst_rate 549790 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 553732 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 898863423 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 362780 # Number of bytes of host memory used
|
||||
host_seconds 164.75 # Real time elapsed on the host
|
||||
sim_insts 90576869 # Number of instructions simulated
|
||||
sim_ops 91226321 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 986112 # Number of bytes read from this memory
|
||||
|
|
@ -129,8 +129,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 599 # number of ReadReq MSHR misses
|
||||
|
|
@ -213,8 +213,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 942309 # number of writebacks
|
||||
|
|
@ -323,8 +323,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 32 # number of writebacks
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@ load_addr_mask=1099511627775
|
|||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[0]
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
|
|
@ -39,6 +38,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
|
|
@ -57,8 +57,8 @@ system=system
|
|||
tracer=system.cpu.tracer
|
||||
width=1
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.membus.port[3]
|
||||
icache_port=system.membus.port[2]
|
||||
dcache_port=system.membus.slave[2]
|
||||
icache_port=system.membus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=SparcTLB
|
||||
|
|
@ -77,7 +77,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=mcf mcf.in
|
||||
cwd=build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-atomic
|
||||
cwd=build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -101,15 +101,18 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
|
||||
master=system.physmem.port[0]
|
||||
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:268435455
|
||||
zero=false
|
||||
port=system.membus.port[1]
|
||||
port=system.membus.master[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Feb 11 2012 13:08:33
|
||||
gem5 started Feb 11 2012 13:56:49
|
||||
gem5 executing on zizzer
|
||||
command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-atomic
|
||||
gem5 compiled May 8 2012 15:05:42
|
||||
gem5 started May 8 2012 15:43:24
|
||||
gem5 executing on piton
|
||||
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.122216 # Nu
|
|||
sim_ticks 122215830000 # Number of ticks simulated
|
||||
final_tick 122215830000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 4048457 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 4048623 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2029262264 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 335836 # Number of bytes of host memory used
|
||||
host_seconds 60.23 # Real time elapsed on the host
|
||||
host_inst_rate 1503519 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1503581 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 753629165 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 346024 # Number of bytes of host memory used
|
||||
host_seconds 162.17 # Real time elapsed on the host
|
||||
sim_insts 243825163 # Number of instructions simulated
|
||||
sim_ops 243835278 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 1306360053 # Number of bytes read from this memory
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@ load_addr_mask=1099511627775
|
|||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[0]
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
|
|
@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side
|
|||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
addr_range=0:18446744073709551615
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
|
|
@ -80,7 +79,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.port[1]
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=SparcTLB
|
||||
|
|
@ -88,7 +87,7 @@ size=64
|
|||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
addr_range=0:18446744073709551615
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
|
|
@ -109,7 +108,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.port[0]
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=SparcInterrupts
|
||||
|
|
@ -120,7 +119,7 @@ size=64
|
|||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_range=0:18446744073709551615
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
|
|
@ -140,8 +139,8 @@ tgts_per_mshr=5
|
|||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.port[2]
|
||||
mem_side=system.membus.port[2]
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
|
|
@ -151,7 +150,8 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -159,7 +159,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=mcf mcf.in
|
||||
cwd=build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing
|
||||
cwd=build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -183,15 +183,18 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
master=system.physmem.port[0]
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:268435455
|
||||
zero=false
|
||||
port=system.membus.port[1]
|
||||
port=system.membus.master[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Feb 11 2012 13:08:33
|
||||
gem5 started Feb 11 2012 13:58:00
|
||||
gem5 executing on zizzer
|
||||
command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing
|
||||
gem5 compiled May 8 2012 15:05:42
|
||||
gem5 started May 8 2012 15:44:07
|
||||
gem5 executing on piton
|
||||
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.362431 # Nu
|
|||
sim_ticks 362430887000 # Number of ticks simulated
|
||||
final_tick 362430887000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1947938 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1948018 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2895487158 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 344700 # Number of bytes of host memory used
|
||||
host_seconds 125.17 # Real time elapsed on the host
|
||||
host_inst_rate 628265 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 628291 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 933876298 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 354916 # Number of bytes of host memory used
|
||||
host_seconds 388.09 # Real time elapsed on the host
|
||||
sim_insts 243825163 # Number of instructions simulated
|
||||
sim_ops 243835278 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 1001472 # Number of bytes read from this memory
|
||||
|
|
@ -87,8 +87,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 882 # number of ReadReq MSHR misses
|
||||
|
|
@ -173,8 +173,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 935237 # number of writebacks
|
||||
|
|
@ -289,8 +289,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 40 # number of writebacks
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@ load_addr_mask=1099511627775
|
|||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[0]
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
|
|
@ -127,7 +126,7 @@ icache_port=system.cpu.icache.cpu_side
|
|||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
addr_range=0:18446744073709551615
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
|
|
@ -148,7 +147,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.port[1]
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
|
|
@ -159,7 +158,7 @@ walker=system.cpu.dtb.walker
|
|||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.port[3]
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
|
|
@ -426,7 +425,7 @@ opLat=3
|
|||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
addr_range=0:18446744073709551615
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
|
|
@ -447,7 +446,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.port[0]
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
|
|
@ -455,8 +454,9 @@ int_latency=1000
|
|||
pio_addr=2305843009213693952
|
||||
pio_latency=1000
|
||||
system=system
|
||||
int_port=system.membus.port[4]
|
||||
pio=system.membus.port[3]
|
||||
int_master=system.membus.slave[2]
|
||||
int_slave=system.membus.master[2]
|
||||
pio=system.membus.master[1]
|
||||
|
||||
[system.cpu.itb]
|
||||
type=X86TLB
|
||||
|
|
@ -467,11 +467,11 @@ walker=system.cpu.itb.walker
|
|||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.port[2]
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_range=0:18446744073709551615
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
|
|
@ -491,8 +491,8 @@ tgts_per_mshr=5
|
|||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.port[4]
|
||||
mem_side=system.membus.port[2]
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
|
|
@ -502,7 +502,8 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -510,7 +511,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=mcf mcf.in
|
||||
cwd=build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing
|
||||
cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -534,15 +535,18 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
|
||||
master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
|
||||
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:268435455
|
||||
zero=false
|
||||
port=system.membus.port[1]
|
||||
port=system.membus.master[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Feb 12 2012 17:18:12
|
||||
gem5 started Feb 12 2012 18:37:07
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing
|
||||
gem5 compiled May 8 2012 15:05:30
|
||||
gem5 started May 8 2012 15:53:18
|
||||
gem5 executing on piton
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.067367 # Nu
|
|||
sim_ticks 67367177000 # Number of ticks simulated
|
||||
final_tick 67367177000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 124120 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 218555 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 52925417 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 355732 # Number of bytes of host memory used
|
||||
host_seconds 1272.87 # Real time elapsed on the host
|
||||
host_inst_rate 46452 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 81794 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 19807267 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 361860 # Number of bytes of host memory used
|
||||
host_seconds 3401.13 # Real time elapsed on the host
|
||||
sim_insts 157988582 # Number of instructions simulated
|
||||
sim_ops 278192519 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 3905024 # Number of bytes read from this memory
|
||||
|
|
@ -331,8 +331,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 315 # number of ReadReq MSHR hits
|
||||
|
|
@ -413,8 +413,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 1879081 # number of writebacks
|
||||
|
|
@ -536,8 +536,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 13993 # number of writebacks
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@ load_addr_mask=1099511627775
|
|||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[0]
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
|
|
@ -39,6 +38,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
|
|
@ -57,8 +57,8 @@ system=system
|
|||
tracer=system.cpu.tracer
|
||||
width=1
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.membus.port[3]
|
||||
icache_port=system.membus.port[2]
|
||||
dcache_port=system.membus.slave[2]
|
||||
icache_port=system.membus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
|
|
@ -69,7 +69,7 @@ walker=system.cpu.dtb.walker
|
|||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
system=system
|
||||
port=system.membus.port[5]
|
||||
port=system.membus.slave[4]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
|
|
@ -77,8 +77,9 @@ int_latency=1000
|
|||
pio_addr=2305843009213693952
|
||||
pio_latency=1000
|
||||
system=system
|
||||
int_port=system.membus.port[7]
|
||||
pio=system.membus.port[6]
|
||||
int_master=system.membus.slave[5]
|
||||
int_slave=system.membus.master[2]
|
||||
pio=system.membus.master[1]
|
||||
|
||||
[system.cpu.itb]
|
||||
type=X86TLB
|
||||
|
|
@ -89,7 +90,7 @@ walker=system.cpu.itb.walker
|
|||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
system=system
|
||||
port=system.membus.port[4]
|
||||
port=system.membus.slave[3]
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -97,7 +98,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=mcf mcf.in
|
||||
cwd=build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-atomic
|
||||
cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -121,15 +122,18 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port
|
||||
master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
|
||||
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:268435455
|
||||
zero=false
|
||||
port=system.membus.port[1]
|
||||
port=system.membus.master[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Feb 11 2012 13:08:53
|
||||
gem5 started Feb 11 2012 14:18:06
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-atomic
|
||||
gem5 compiled May 8 2012 15:05:30
|
||||
gem5 started May 8 2012 15:53:55
|
||||
gem5 executing on piton
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.168950 # Nu
|
|||
sim_ticks 168950072000 # Number of ticks simulated
|
||||
final_tick 168950072000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1605694 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2827368 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1717098424 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 344660 # Number of bytes of host memory used
|
||||
host_seconds 98.39 # Real time elapsed on the host
|
||||
host_inst_rate 603392 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1062476 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 645256130 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 350676 # Number of bytes of host memory used
|
||||
host_seconds 261.83 # Real time elapsed on the host
|
||||
sim_insts 157988583 # Number of instructions simulated
|
||||
sim_ops 278192520 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 2458815679 # Number of bytes read from this memory
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@ load_addr_mask=1099511627775
|
|||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[0]
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
|
|
@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side
|
|||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
addr_range=0:18446744073709551615
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
|
|
@ -80,7 +79,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.port[1]
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
|
|
@ -91,11 +90,11 @@ walker=system.cpu.dtb.walker
|
|||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.port[3]
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
addr_range=0:18446744073709551615
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
|
|
@ -116,7 +115,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.port[0]
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
|
|
@ -124,8 +123,9 @@ int_latency=1000
|
|||
pio_addr=2305843009213693952
|
||||
pio_latency=1000
|
||||
system=system
|
||||
int_port=system.membus.port[4]
|
||||
pio=system.membus.port[3]
|
||||
int_master=system.membus.slave[2]
|
||||
int_slave=system.membus.master[2]
|
||||
pio=system.membus.master[1]
|
||||
|
||||
[system.cpu.itb]
|
||||
type=X86TLB
|
||||
|
|
@ -136,11 +136,11 @@ walker=system.cpu.itb.walker
|
|||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.port[2]
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_range=0:18446744073709551615
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
|
|
@ -160,8 +160,8 @@ tgts_per_mshr=5
|
|||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.port[4]
|
||||
mem_side=system.membus.port[2]
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
|
|
@ -171,7 +171,8 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -179,7 +180,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=mcf mcf.in
|
||||
cwd=build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing
|
||||
cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -203,15 +204,18 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
|
||||
master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
|
||||
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:268435455
|
||||
zero=false
|
||||
port=system.membus.port[1]
|
||||
port=system.membus.master[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Feb 11 2012 13:08:53
|
||||
gem5 started Feb 11 2012 14:19:55
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing
|
||||
gem5 compiled May 8 2012 15:05:30
|
||||
gem5 started May 8 2012 15:54:19
|
||||
gem5 executing on piton
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.370011 # Nu
|
|||
sim_ticks 370010840000 # Number of ticks simulated
|
||||
final_tick 370010840000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 912216 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1606265 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2136418129 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 353708 # Number of bytes of host memory used
|
||||
host_seconds 173.19 # Real time elapsed on the host
|
||||
host_inst_rate 306323 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 539385 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 717411215 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 359620 # Number of bytes of host memory used
|
||||
host_seconds 515.76 # Real time elapsed on the host
|
||||
sim_insts 157988583 # Number of instructions simulated
|
||||
sim_ops 278192520 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 4900800 # Number of bytes read from this memory
|
||||
|
|
@ -87,8 +87,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses
|
||||
|
|
@ -163,8 +163,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 1437080 # number of writebacks
|
||||
|
|
@ -270,8 +270,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 29460 # number of writebacks
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@ load_addr_mask=1099511627775
|
|||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
@ -509,14 +508,14 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=parser 2.1.dict -batch
|
||||
cwd=build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing
|
||||
cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/parser
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/parser
|
||||
gid=100
|
||||
input=/projects/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in
|
||||
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -537,8 +536,10 @@ master=system.physmem.port[0]
|
|||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 17 2012 11:46:05
|
||||
gem5 started Mar 17 2012 17:04:44
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing
|
||||
gem5 compiled May 8 2012 15:17:37
|
||||
gem5 started May 8 2012 16:25:50
|
||||
gem5 executing on piton
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
@ -67,4 +67,4 @@ info: Increasing stack size by one page.
|
|||
about 2 million people attended
|
||||
the five best costumes got prizes
|
||||
No errors!
|
||||
Exiting @ tick 233057542500 because target called exit()
|
||||
Exiting @ tick 233090215000 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -16,7 +16,6 @@ load_addr_mask=1099511627775
|
|||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
@ -39,6 +38,7 @@ do_checkpoint_insts=true
|
|||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
|
|
@ -95,14 +95,14 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=parser 2.1.dict -batch
|
||||
cwd=build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-atomic
|
||||
cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/parser
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/parser
|
||||
gid=100
|
||||
input=/projects/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in
|
||||
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -123,8 +123,10 @@ master=system.physmem.port[0]
|
|||
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 17 2012 11:46:05
|
||||
gem5 started Mar 17 2012 17:09:21
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-atomic
|
||||
gem5 compiled May 8 2012 15:17:37
|
||||
gem5 started May 8 2012 16:27:44
|
||||
gem5 executing on piton
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.290499 # Nu
|
|||
sim_ticks 290498972000 # Number of ticks simulated
|
||||
final_tick 290498972000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2826052 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3185244 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1620598119 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 217292 # Number of bytes of host memory used
|
||||
host_seconds 179.25 # Real time elapsed on the host
|
||||
host_inst_rate 1142576 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1287798 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 655209825 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 224168 # Number of bytes of host memory used
|
||||
host_seconds 443.37 # Real time elapsed on the host
|
||||
sim_insts 506581615 # Number of instructions simulated
|
||||
sim_ops 570968176 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 2489298238 # Number of bytes read from this memory
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@ load_addr_mask=1099511627775
|
|||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
@ -178,14 +177,14 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=parser 2.1.dict -batch
|
||||
cwd=build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing
|
||||
cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/parser
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/parser
|
||||
gid=100
|
||||
input=/projects/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in
|
||||
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -206,8 +205,10 @@ master=system.physmem.port[0]
|
|||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 17 2012 11:46:05
|
||||
gem5 started Mar 17 2012 17:11:24
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing
|
||||
gem5 compiled May 8 2012 15:17:37
|
||||
gem5 started May 8 2012 16:29:57
|
||||
gem5 executing on piton
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.722234 # Nu
|
|||
sim_ticks 722234364000 # Number of ticks simulated
|
||||
final_tick 722234364000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1807546 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2036799 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2585159889 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 226208 # Number of bytes of host memory used
|
||||
host_seconds 279.38 # Real time elapsed on the host
|
||||
host_inst_rate 593765 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 669073 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 849204818 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 233356 # Number of bytes of host memory used
|
||||
host_seconds 850.48 # Real time elapsed on the host
|
||||
sim_insts 504986861 # Number of instructions simulated
|
||||
sim_ops 569034848 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read 14797056 # Number of bytes read from this memory
|
||||
|
|
@ -129,8 +129,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11521 # number of ReadReq MSHR misses
|
||||
|
|
@ -213,8 +213,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 1025440 # number of writebacks
|
||||
|
|
@ -323,8 +323,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 172302 # number of writebacks
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@ load_addr_mask=1099511627775
|
|||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[0]
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
|
|
@ -127,7 +126,7 @@ icache_port=system.cpu.icache.cpu_side
|
|||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
addr_range=0:18446744073709551615
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
|
|
@ -148,7 +147,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.port[1]
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
|
|
@ -159,7 +158,7 @@ walker=system.cpu.dtb.walker
|
|||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.port[3]
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
|
|
@ -426,7 +425,7 @@ opLat=3
|
|||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
addr_range=0:18446744073709551615
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
|
|
@ -447,7 +446,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.port[0]
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
|
|
@ -455,8 +454,9 @@ int_latency=1000
|
|||
pio_addr=2305843009213693952
|
||||
pio_latency=1000
|
||||
system=system
|
||||
int_port=system.membus.port[4]
|
||||
pio=system.membus.port[3]
|
||||
int_master=system.membus.slave[2]
|
||||
int_slave=system.membus.master[2]
|
||||
pio=system.membus.master[1]
|
||||
|
||||
[system.cpu.itb]
|
||||
type=X86TLB
|
||||
|
|
@ -467,11 +467,11 @@ walker=system.cpu.itb.walker
|
|||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.port[2]
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
addr_range=0:18446744073709551615
|
||||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
block_size=64
|
||||
forward_snoops=true
|
||||
|
|
@ -491,8 +491,8 @@ tgts_per_mshr=5
|
|||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.port[4]
|
||||
mem_side=system.membus.port[2]
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
|
|
@ -502,7 +502,8 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -510,7 +511,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=parser 2.1.dict -batch
|
||||
cwd=build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing
|
||||
cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -534,15 +535,18 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
|
||||
master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
|
||||
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
type=SimpleMemory
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[1]
|
||||
port=system.membus.master[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Feb 12 2012 17:18:12
|
||||
gem5 started Feb 12 2012 18:44:57
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing
|
||||
gem5 compiled May 8 2012 15:05:30
|
||||
gem5 started May 8 2012 15:55:07
|
||||
gem5 executing on piton
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
|
|||
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Reference in a new issue