Update stats after elimination of Unallocated state.
Somehow ending threads with halt() instead of deallocate() reduces the squash count on o3 by 1 (and a few other similarly trivial changes).
This commit is contained in:
Steve Reinhardt
parent
8882dc1283
commit
48d4ca522a
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@ -356,12 +356,12 @@ type=ExeTracer
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[system.cpu.workload]
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type=LiveProcess
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cmd=gzip input.log 1
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cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing
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cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing
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egid=100
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env=
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errout=cerr
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euid=100
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executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
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executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/gzip
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gid=100
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input=cin
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max_stack_size=67108864
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||||
|
|
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|||
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|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Apr 8 2009 12:30:02
|
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M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
|
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M5 started Apr 8 2009 12:37:48
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M5 executing on maize
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command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing
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M5 compiled Apr 14 2009 23:40:03
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||||
M5 revision 4208b24ee3ad 6033 default qtip tip new-thread-status-stats-update
|
||||
M5 started Apr 14 2009 23:40:05
|
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M5 executing on phenom
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing
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Global frequency set at 1000000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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info: Increasing stack size by one page.
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@ -1,9 +1,9 @@
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---------- Begin Simulation Statistics ----------
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host_inst_rate 312901 # Simulator instruction rate (inst/s)
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host_mem_usage 206004 # Number of bytes of host memory used
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host_seconds 1807.45 # Real time elapsed on the host
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host_tick_rate 92438667 # Simulator tick rate (ticks/s)
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host_inst_rate 252050 # Simulator instruction rate (inst/s)
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host_mem_usage 207828 # Number of bytes of host memory used
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host_seconds 2243.81 # Real time elapsed on the host
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host_tick_rate 74461791 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 565552443 # Number of instructions simulated
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sim_seconds 0.167078 # Number of seconds simulated
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@ -20,9 +20,9 @@ system.cpu.commit.COM:branches 62547159 # Nu
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system.cpu.commit.COM:bw_lim_events 17700250 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle.samples 322711249
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system.cpu.commit.COM:committed_per_cycle.samples 322711250
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system.cpu.commit.COM:committed_per_cycle.min_value 0
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0 108088757 3349.40%
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0 108088758 3349.40%
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1 100475751 3113.49%
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2 37367184 1157.91%
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3 9733028 301.60%
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@ -144,7 +144,7 @@ system.cpu.fetch.CacheLines 66014406 # Nu
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system.cpu.fetch.Cycles 197129335 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 1352914 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 698864013 # Number of instructions fetch has processed
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system.cpu.fetch.SquashCycles 4233116 # Number of cycles fetch has spent squashing
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system.cpu.fetch.SquashCycles 4233115 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.227555 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 66014406 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 67411078 # Number of branches that fetch has predicted taken
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|
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@ -356,12 +356,12 @@ type=ExeTracer
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[system.cpu.workload]
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type=LiveProcess
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cmd=gzip input.log 1
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cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
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cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing
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egid=100
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env=
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errout=cerr
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euid=100
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executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip
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executable=/home/stever/m5/dist/cpu2000/binaries/sparc/linux/gzip
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gid=100
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input=cin
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max_stack_size=67108864
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||||
|
|
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|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
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All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Apr 8 2009 12:30:02
|
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M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
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M5 started Apr 8 2009 12:30:04
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M5 executing on maize
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command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
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M5 compiled Apr 14 2009 21:09:22
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M5 revision 4208b24ee3ad 6033 default qtip tip new-thread-status-stats-update
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M5 started Apr 14 2009 23:40:01
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M5 executing on phenom
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command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing
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Global frequency set at 1000000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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spec_init
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@ -1,9 +1,9 @@
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---------- Begin Simulation Statistics ----------
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host_inst_rate 150366 # Simulator instruction rate (inst/s)
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host_mem_usage 208016 # Number of bytes of host memory used
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host_seconds 9347.96 # Real time elapsed on the host
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host_tick_rate 117957212 # Simulator tick rate (ticks/s)
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host_inst_rate 120324 # Simulator instruction rate (inst/s)
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host_mem_usage 213384 # Number of bytes of host memory used
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host_seconds 11681.98 # Real time elapsed on the host
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host_tick_rate 94389741 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 1405618365 # Number of instructions simulated
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sim_seconds 1.102659 # Number of seconds simulated
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@ -133,7 +133,7 @@ system.cpu.fetch.CacheLines 354588619 # Nu
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system.cpu.fetch.Cycles 1199300749 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 10659931 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 3732201000 # Number of instructions fetch has processed
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system.cpu.fetch.SquashCycles 88873600 # Number of cycles fetch has spent squashing
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system.cpu.fetch.SquashCycles 88873599 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.115384 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 354588619 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 182414509 # Number of branches that fetch has predicted taken
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@ -356,12 +356,12 @@ type=ExeTracer
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[system.cpu.workload]
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type=LiveProcess
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cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
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cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing
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cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing
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egid=100
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env=
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errout=cerr
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euid=100
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executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
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executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/eon
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gid=100
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input=cin
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max_stack_size=67108864
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|
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|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Apr 8 2009 12:30:02
|
||||
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
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M5 started Apr 8 2009 12:46:50
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M5 executing on maize
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command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing
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M5 compiled Apr 14 2009 23:40:03
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M5 revision 4208b24ee3ad 6033 default qtip tip new-thread-status-stats-update
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M5 started Apr 14 2009 23:48:49
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M5 executing on phenom
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command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing
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Global frequency set at 1000000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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info: Increasing stack size by one page.
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@ -1,9 +1,9 @@
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---------- Begin Simulation Statistics ----------
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host_inst_rate 244825 # Simulator instruction rate (inst/s)
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host_mem_usage 213432 # Number of bytes of host memory used
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host_seconds 1534.05 # Real time elapsed on the host
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host_tick_rate 88000012 # Simulator tick rate (ticks/s)
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host_inst_rate 195698 # Simulator instruction rate (inst/s)
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host_mem_usage 215252 # Number of bytes of host memory used
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host_seconds 1919.15 # Real time elapsed on the host
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host_tick_rate 70341803 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 375574819 # Number of instructions simulated
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sim_seconds 0.134997 # Number of seconds simulated
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@ -20,9 +20,9 @@ system.cpu.commit.COM:branches 44587532 # Nu
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system.cpu.commit.COM:bw_lim_events 13163574 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle.samples 254545672
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system.cpu.commit.COM:committed_per_cycle.samples 254545673
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system.cpu.commit.COM:committed_per_cycle.min_value 0
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0 123085209 4835.49%
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0 123085210 4835.49%
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1 50466868 1982.63%
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2 18758377 736.94%
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3 19955031 783.95%
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@ -144,7 +144,7 @@ system.cpu.fetch.CacheLines 63866189 # Nu
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system.cpu.fetch.Cycles 169616790 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 1519057 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 544903543 # Number of instructions fetch has processed
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system.cpu.fetch.SquashCycles 6123543 # Number of cycles fetch has spent squashing
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system.cpu.fetch.SquashCycles 6123542 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.230412 # Number of branch fetches per cycle
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||||
system.cpu.fetch.icacheStallCycles 63866189 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 50640538 # Number of branches that fetch has predicted taken
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@ -356,12 +356,12 @@ type=ExeTracer
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[system.cpu.workload]
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type=LiveProcess
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cmd=perlbmk -I. -I lib lgred.makerand.pl
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cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing
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cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing
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egid=100
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env=
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errout=cerr
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euid=100
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executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
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executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/perlbmk
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gid=100
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input=cin
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max_stack_size=67108864
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|
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|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Apr 8 2009 12:30:02
|
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M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
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M5 started Apr 8 2009 12:41:37
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M5 executing on maize
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command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing
|
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M5 compiled Apr 14 2009 23:40:03
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M5 revision 4208b24ee3ad 6033 default qtip tip new-thread-status-stats-update
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M5 started Apr 14 2009 23:46:17
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M5 executing on phenom
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command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing
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Global frequency set at 1000000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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info: Increasing stack size by one page.
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@ -1,9 +1,9 @@
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---------- Begin Simulation Statistics ----------
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host_inst_rate 236247 # Simulator instruction rate (inst/s)
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host_mem_usage 213344 # Number of bytes of host memory used
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host_seconds 7716.70 # Real time elapsed on the host
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host_tick_rate 91380999 # Simulator tick rate (ticks/s)
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host_inst_rate 193760 # Simulator instruction rate (inst/s)
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host_mem_usage 215160 # Number of bytes of host memory used
|
||||
host_seconds 9408.76 # Real time elapsed on the host
|
||||
host_tick_rate 74947150 # Simulator tick rate (ticks/s)
|
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 1823043370 # Number of instructions simulated
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sim_seconds 0.705159 # Number of seconds simulated
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@ -20,9 +20,9 @@ system.cpu.commit.COM:branches 266706457 # Nu
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system.cpu.commit.COM:bw_lim_events 68860244 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 1310002800
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 1310002801
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system.cpu.commit.COM:committed_per_cycle.min_value 0
|
||||
0 603585596 4607.51%
|
||||
0 603585597 4607.51%
|
||||
1 273587005 2088.45%
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||||
2 174037133 1328.52%
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3 65399708 499.23%
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|
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@ -144,7 +144,7 @@ system.cpu.fetch.CacheLines 348447899 # Nu
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|||
system.cpu.fetch.Cycles 928021937 # Number of cycles fetch has run and was not squashing or blocked
|
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system.cpu.fetch.IcacheSquashes 4387629 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 3030218619 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 29544622 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.SquashCycles 29544621 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.247763 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 348447899 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 290350352 # Number of branches that fetch has predicted taken
|
||||
|
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|
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@ -356,12 +356,12 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=vortex lendian.raw
|
||||
cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing
|
||||
cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
|
||||
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/vortex
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Apr 8 2009 12:30:02
|
||||
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
|
||||
M5 started Apr 8 2009 12:36:30
|
||||
M5 executing on maize
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing
|
||||
M5 compiled Apr 14 2009 23:40:03
|
||||
M5 revision 4208b24ee3ad 6033 default qtip tip new-thread-status-stats-update
|
||||
M5 started Apr 14 2009 23:40:05
|
||||
M5 executing on phenom
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
|
|
|||
|
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@ -1,9 +1,9 @@
|
|||
|
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---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 259851 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 216888 # Number of bytes of host memory used
|
||||
host_seconds 306.30 # Real time elapsed on the host
|
||||
host_tick_rate 88589448 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 213847 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 218620 # Number of bytes of host memory used
|
||||
host_seconds 372.19 # Real time elapsed on the host
|
||||
host_tick_rate 72905538 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 79591756 # Number of instructions simulated
|
||||
sim_seconds 0.027135 # Number of seconds simulated
|
||||
|
|
@ -20,9 +20,9 @@ system.cpu.commit.COM:branches 13754477 # Nu
|
|||
system.cpu.commit.COM:bw_lim_events 3320894 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 51751168
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 51751169
|
||||
system.cpu.commit.COM:committed_per_cycle.min_value 0
|
||||
0 22506445 4348.97%
|
||||
0 22506446 4348.97%
|
||||
1 11357579 2194.65%
|
||||
2 5114502 988.29%
|
||||
3 3560855 688.07%
|
||||
|
|
@ -144,7 +144,7 @@ system.cpu.fetch.CacheLines 13386072 # Nu
|
|||
system.cpu.fetch.Cycles 33247230 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 153162 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 103308065 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 567638 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.SquashCycles 567637 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.299421 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 13386072 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 9981179 # Number of branches that fetch has predicted taken
|
||||
|
|
|
|||
|
|
@ -356,12 +356,12 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=bzip2 input.source 1
|
||||
cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing
|
||||
cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
|
||||
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/bzip2
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Apr 8 2009 12:30:02
|
||||
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
|
||||
M5 started Apr 8 2009 12:33:27
|
||||
M5 executing on maize
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing
|
||||
M5 compiled Apr 14 2009 23:40:03
|
||||
M5 revision 4208b24ee3ad 6033 default qtip tip new-thread-status-stats-update
|
||||
M5 started Apr 15 2009 00:17:29
|
||||
M5 executing on phenom
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 226919 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 205788 # Number of bytes of host memory used
|
||||
host_seconds 7650.48 # Real time elapsed on the host
|
||||
host_tick_rate 97027777 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 188573 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 207604 # Number of bytes of host memory used
|
||||
host_seconds 9206.20 # Real time elapsed on the host
|
||||
host_tick_rate 80631433 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 1736043781 # Number of instructions simulated
|
||||
sim_seconds 0.742309 # Number of seconds simulated
|
||||
|
|
@ -20,9 +20,9 @@ system.cpu.commit.COM:branches 214632552 # Nu
|
|||
system.cpu.commit.COM:bw_lim_events 62782585 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 1379215338
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 1379215339
|
||||
system.cpu.commit.COM:committed_per_cycle.min_value 0
|
||||
0 736540830 5340.29%
|
||||
0 736540831 5340.29%
|
||||
1 260049504 1885.49%
|
||||
2 126970462 920.60%
|
||||
3 77723426 563.53%
|
||||
|
|
@ -152,7 +152,7 @@ system.cpu.fetch.CacheLines 355180518 # Nu
|
|||
system.cpu.fetch.Cycles 920206770 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 7941781 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 2863046502 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 28103166 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.SquashCycles 28103165 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.232721 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 355180518 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 336596037 # Number of branches that fetch has predicted taken
|
||||
|
|
|
|||
|
|
@ -356,12 +356,12 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=twolf smred
|
||||
cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing
|
||||
cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
|
||||
executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/twolf
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Apr 8 2009 12:30:02
|
||||
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
|
||||
M5 started Apr 8 2009 12:37:03
|
||||
M5 executing on maize
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing
|
||||
M5 compiled Apr 14 2009 23:40:03
|
||||
M5 revision 4208b24ee3ad 6033 default qtip tip new-thread-status-stats-update
|
||||
M5 started Apr 14 2009 23:40:05
|
||||
M5 executing on phenom
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 205890 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 211060 # Number of bytes of host memory used
|
||||
host_seconds 408.86 # Real time elapsed on the host
|
||||
host_tick_rate 99836021 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 160619 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 212880 # Number of bytes of host memory used
|
||||
host_seconds 524.10 # Real time elapsed on the host
|
||||
host_tick_rate 77883837 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 84179709 # Number of instructions simulated
|
||||
sim_seconds 0.040819 # Number of seconds simulated
|
||||
|
|
@ -20,9 +20,9 @@ system.cpu.commit.COM:branches 10240685 # Nu
|
|||
system.cpu.commit.COM:bw_lim_events 2855802 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 73457196
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 73457197
|
||||
system.cpu.commit.COM:committed_per_cycle.min_value 0
|
||||
0 36278941 4938.79%
|
||||
0 36278942 4938.79%
|
||||
1 18156304 2471.68%
|
||||
2 7455517 1014.95%
|
||||
3 3880419 528.26%
|
||||
|
|
@ -144,7 +144,7 @@ system.cpu.fetch.CacheLines 19230003 # Nu
|
|||
system.cpu.fetch.Cycles 50198038 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 519723 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 167554902 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 2079597 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.SquashCycles 2079596 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.238476 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 19230003 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 14728574 # Number of branches that fetch has predicted taken
|
||||
|
|
|
|||
|
|
@ -361,7 +361,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Apr 8 2009 12:30:02
|
||||
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
|
||||
M5 started Apr 8 2009 12:44:12
|
||||
M5 executing on maize
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing
|
||||
M5 compiled Apr 14 2009 16:03:56
|
||||
M5 revision 5716400b2110+ 6033+ default qtip tip new-thread-status-stats-update
|
||||
M5 started Apr 14 2009 16:03:59
|
||||
M5 executing on phenom
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 62049 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 202540 # Number of bytes of host memory used
|
||||
host_seconds 0.10 # Real time elapsed on the host
|
||||
host_tick_rate 120907399 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 100618 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 204352 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
host_tick_rate 195881226 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 6386 # Number of instructions simulated
|
||||
sim_seconds 0.000012 # Number of seconds simulated
|
||||
|
|
@ -19,10 +19,10 @@ system.cpu.BPredUnit.usedRAS 304 # Nu
|
|||
system.cpu.commit.COM:branches 1051 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 115 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 12416 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 12417 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0-1 9513 76.62% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0-1 9514 76.62% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1-2 1627 13.10% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2-3 488 3.93% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3-4 267 2.15% # Number of insts commited each cycle
|
||||
|
|
@ -32,10 +32,10 @@ system.cpu.commit.COM:committed_per_cycle::6-7 96 0.77%
|
|||
system.cpu.commit.COM:committed_per_cycle::7-8 53 0.43% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 115 0.93% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 12416 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 12417 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 0.515706 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.304935 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 0.515664 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.304890 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 6403 # Number of instructions committed
|
||||
system.cpu.commit.COM:loads 1185 # Number of loads committed
|
||||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
|
|
@ -144,7 +144,7 @@ system.cpu.fetch.CacheLines 1802 # Nu
|
|||
system.cpu.fetch.Cycles 4308 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 270 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 13251 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 502 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.SquashCycles 501 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.090701 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 1802 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 1110 # Number of branches that fetch has predicted taken
|
||||
|
|
|
|||
|
|
@ -361,7 +361,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
|
||||
executable=tests/test-progs/hello/bin/alpha/tru64/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Apr 8 2009 12:30:02
|
||||
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
|
||||
M5 started Apr 8 2009 12:44:10
|
||||
M5 executing on maize
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing
|
||||
M5 compiled Apr 14 2009 16:03:56
|
||||
M5 revision 5716400b2110+ 6033+ default qtip tip new-thread-status-stats-update
|
||||
M5 started Apr 14 2009 16:03:59
|
||||
M5 executing on phenom
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 53715 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 201548 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
host_tick_rate 160751052 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 72174 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 203356 # Number of bytes of host memory used
|
||||
host_seconds 0.03 # Real time elapsed on the host
|
||||
host_tick_rate 215783466 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 2387 # Number of instructions simulated
|
||||
sim_seconds 0.000007 # Number of seconds simulated
|
||||
|
|
@ -19,10 +19,10 @@ system.cpu.BPredUnit.usedRAS 165 # Nu
|
|||
system.cpu.commit.COM:branches 396 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 38 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 6196
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 6197
|
||||
system.cpu.commit.COM:committed_per_cycle::min_value 0
|
||||
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00%
|
||||
system.cpu.commit.COM:committed_per_cycle::0-1 5239 84.55%
|
||||
system.cpu.commit.COM:committed_per_cycle::0-1 5240 84.56%
|
||||
system.cpu.commit.COM:committed_per_cycle::1-2 263 4.24%
|
||||
system.cpu.commit.COM:committed_per_cycle::2-3 334 5.39%
|
||||
system.cpu.commit.COM:committed_per_cycle::3-4 134 2.16%
|
||||
|
|
@ -32,10 +32,10 @@ system.cpu.commit.COM:committed_per_cycle::6-7 32 0.52%
|
|||
system.cpu.commit.COM:committed_per_cycle::7-8 20 0.32%
|
||||
system.cpu.commit.COM:committed_per_cycle::8 38 0.61%
|
||||
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00%
|
||||
system.cpu.commit.COM:committed_per_cycle::total 6196
|
||||
system.cpu.commit.COM:committed_per_cycle::total 6197
|
||||
system.cpu.commit.COM:committed_per_cycle::max_value 8
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 0.415752
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.208059
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 0.415685
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.207973
|
||||
system.cpu.commit.COM:count 2576 # Number of instructions committed
|
||||
system.cpu.commit.COM:loads 415 # Number of loads committed
|
||||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
|
|
@ -144,7 +144,7 @@ system.cpu.fetch.CacheLines 747 # Nu
|
|||
system.cpu.fetch.Cycles 1709 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 115 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 5393 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 240 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.SquashCycles 239 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.059790 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 747 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 363 # Number of branches that fetch has predicted taken
|
||||
|
|
|
|||
|
|
@ -361,7 +361,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -380,7 +380,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Apr 8 2009 12:30:02
|
||||
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
|
||||
M5 started Apr 8 2009 12:44:23
|
||||
M5 executing on maize
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing
|
||||
M5 compiled Apr 14 2009 16:03:56
|
||||
M5 revision 5716400b2110+ 6033+ default qtip tip new-thread-status-stats-update
|
||||
M5 started Apr 14 2009 16:03:57
|
||||
M5 executing on phenom
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 98882 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 203072 # Number of bytes of host memory used
|
||||
host_seconds 0.13 # Real time elapsed on the host
|
||||
host_tick_rate 110106309 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 12362 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 204880 # Number of bytes of host memory used
|
||||
host_seconds 1.03 # Real time elapsed on the host
|
||||
host_tick_rate 13784522 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 12773 # Number of instructions simulated
|
||||
sim_seconds 0.000014 # Number of seconds simulated
|
||||
|
|
@ -23,10 +23,10 @@ system.cpu.commit.COM:bw_lim_events 122 # nu
|
|||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:bw_limited_0 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:bw_limited_1 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 22837 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 22838 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0-1 16880 73.92% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0-1 16881 73.92% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1-2 3016 13.21% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2-3 1386 6.07% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3-4 576 2.52% # Number of insts commited each cycle
|
||||
|
|
@ -36,10 +36,10 @@ system.cpu.commit.COM:committed_per_cycle::6-7 170 0.74%
|
|||
system.cpu.commit.COM:committed_per_cycle::7-8 93 0.41% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 122 0.53% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 22837 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 22838 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 0.560800 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.272250 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 0.560776 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.272228 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 12807 # Number of instructions committed
|
||||
system.cpu.commit.COM:count_0 6403 # Number of instructions committed
|
||||
system.cpu.commit.COM:count_1 6404 # Number of instructions committed
|
||||
|
|
@ -202,7 +202,7 @@ system.cpu.dcache.warmup_cycle 0 # Cy
|
|||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.dcache.writebacks_0 0 # number of writebacks
|
||||
system.cpu.dcache.writebacks_1 0 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 5062 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BlockedCycles 5063 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 441 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 602 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 27492 # Number of instructions handled by decode
|
||||
|
|
@ -232,7 +232,7 @@ system.cpu.fetch.CacheLines 4113 # Nu
|
|||
system.cpu.fetch.Cycles 9444 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 613 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 30949 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 1714 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.SquashCycles 1712 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.194639 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 4113 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 1597 # Number of branches that fetch has predicted taken
|
||||
|
|
@ -737,7 +737,7 @@ system.cpu.rename.RENAME:RunCycles 4546 # Nu
|
|||
system.cpu.rename.RENAME:SquashCycles 2128 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 1422 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 10372 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 849 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializeStallCycles 850 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 3399 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 36 # count of temporary serializing insts renamed
|
||||
|
|
|
|||
|
|
@ -361,7 +361,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest
|
||||
executable=tests/test-progs/insttest/bin/sparc/linux/insttest
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Apr 8 2009 12:30:02
|
||||
M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
|
||||
M5 started Apr 8 2009 12:32:54
|
||||
M5 executing on maize
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing
|
||||
M5 compiled Apr 14 2009 16:03:50
|
||||
M5 revision 5716400b2110+ 6033+ default qtip tip new-thread-status-stats-update
|
||||
M5 started Apr 14 2009 16:03:52
|
||||
M5 executing on phenom
|
||||
command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Begining test of difficult SPARC instructions...
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 71088 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 203480 # Number of bytes of host memory used
|
||||
host_seconds 0.20 # Real time elapsed on the host
|
||||
host_tick_rate 136384184 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 9495 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 208836 # Number of bytes of host memory used
|
||||
host_seconds 1.52 # Real time elapsed on the host
|
||||
host_tick_rate 18237542 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 14449 # Number of instructions simulated
|
||||
sim_seconds 0.000028 # Number of seconds simulated
|
||||
|
|
@ -127,7 +127,7 @@ system.cpu.fetch.CacheLines 7356 # Nu
|
|||
system.cpu.fetch.Cycles 24020 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 845 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 58247 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 3019 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.SquashCycles 3018 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.205588 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 7356 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 4398 # Number of branches that fetch has predicted taken
|
||||
|
|
|
|||
Loading…
Reference in a new issue