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tests: update stats for name changes

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This commit is contained in:
Nathan Binkert 2011-04-19 18:45:23 -07:00
parent 63371c8664
commit 8c1563096c
420 changed files with 9084 additions and 8183 deletions
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3
tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
View file

@ -86,6 +86,7 @@ assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
@ -121,6 +122,7 @@ assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
@ -156,6 +158,7 @@ assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=10000
max_miss_count=0
mshrs=10

7
tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout
View file

@ -5,10 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 23 2011 05:47:47
M5 revision Unknown
M5 started Feb 23 2011 05:49:05
M5 executing on m55-001.pool
M5 compiled Apr 19 2011 11:52:53
M5 started Apr 19 2011 11:58:24
M5 executing on maize
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

94
tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
View file

@ -1,37 +1,25 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 145740 # Simulator instruction rate (inst/s)
host_mem_usage 390376 # Number of bytes of host memory used
host_seconds 4129.65 # Real time elapsed on the host
host_tick_rate 63356930 # Simulator tick rate (ticks/s)
host_inst_rate 209357 # Simulator instruction rate (inst/s)
host_mem_usage 403360 # Number of bytes of host memory used
host_seconds 2874.78 # Real time elapsed on the host
host_tick_rate 91012809 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 601856964 # Number of instructions simulated
sim_seconds 0.261642 # Number of seconds simulated
sim_ticks 261641972500 # Number of ticks simulated
system.cpu.AGEN-Unit.agens 155868116 # Number of Address Generations
system.cpu.Branch-Predictor.BTBHitPct 90.344266 # BTB Hit Percentage
system.cpu.Branch-Predictor.BTBHits 29143677 # Number of BTB hits
system.cpu.Branch-Predictor.BTBLookups 32258469 # Number of BTB lookups
system.cpu.Branch-Predictor.RASInCorrect 6 # Number of incorrect RAS predictions.
system.cpu.Branch-Predictor.condIncorrect 22153653 # Number of conditional branches incorrect
system.cpu.Branch-Predictor.condPredicted 59309256 # Number of conditional branches predicted
system.cpu.Branch-Predictor.lookups 64114012 # Number of BP lookups
system.cpu.Branch-Predictor.predictedNotTaken 31921338 # Number of Branches Predicted As Not Taken (False).
system.cpu.Branch-Predictor.predictedTaken 32192674 # Number of Branches Predicted As Taken (True).
system.cpu.Branch-Predictor.usedRAS 1197609 # Number of times the RAS was used to get a target.
system.cpu.Execution-Unit.executions 419011350 # Number of Instructions Executed.
system.cpu.Execution-Unit.mispredictPct 35.419120 # Percentage of Incorrect Branches Predicts
system.cpu.Execution-Unit.mispredicted 22153653 # Number of Branches Incorrectly Predicted
system.cpu.Execution-Unit.predicted 40393506 # Number of Branches Incorrectly Predicted
system.cpu.Execution-Unit.predictedNotTakenIncorrect 19275234 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.Execution-Unit.predictedTakenIncorrect 2878419 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.Mult-Div-Unit.divides 0 # Number of Divide Operations Executed
system.cpu.Mult-Div-Unit.multiplies 6482 # Number of Multipy Operations Executed
system.cpu.RegFile-Manager.regFileAccesses 1022190210 # Number of Total Accesses (Read+Write) to the Register File
system.cpu.RegFile-Manager.regFileReads 558335321 # Number of Reads from Register File
system.cpu.RegFile-Manager.regFileWrites 463854889 # Number of Writes to Register File
system.cpu.RegFile-Manager.regForwards 256259728 # Number of Registers Read Through Forwarding Logic
system.cpu.activity 88.058146 # Percentage of cycles cpu is active
system.cpu.agen_unit.agens 155868116 # Number of Address Generations
system.cpu.branch_predictor.BTBHitPct 90.344266 # BTB Hit Percentage
system.cpu.branch_predictor.BTBHits 29143677 # Number of BTB hits
system.cpu.branch_predictor.BTBLookups 32258469 # Number of BTB lookups
system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.condIncorrect 22153653 # Number of conditional branches incorrect
system.cpu.branch_predictor.condPredicted 59309256 # Number of conditional branches predicted
system.cpu.branch_predictor.lookups 64114012 # Number of BP lookups
system.cpu.branch_predictor.predictedNotTaken 31921338 # Number of Branches Predicted As Not Taken (False).
system.cpu.branch_predictor.predictedTaken 32192674 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target.
system.cpu.comBranches 62547159 # Number of Branches instructions committed
system.cpu.comFloats 24 # Number of Floating Point instructions committed
system.cpu.comInts 349039879 # Number of Integer instructions committed
@ -88,8 +76,8 @@ system.cpu.dcache.demand_mshr_misses 455395 # nu
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.998946 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4091.682212 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.998946 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 21854.685324 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 19449.234181 # average overall mshr miss latency
@ -127,6 +115,12 @@ system.cpu.dtb.write_accesses 39453623 # DT
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 39451321 # DTB write hits
system.cpu.dtb.write_misses 2302 # DTB write misses
system.cpu.execution_unit.executions 419011350 # Number of Instructions Executed.
system.cpu.execution_unit.mispredictPct 35.419120 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.mispredicted 22153653 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 40393506 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predictedNotTakenIncorrect 19275234 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.predictedTakenIncorrect 2878419 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.icache.ReadReq_accesses 25645163 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 55761.178862 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53508.177570 # average ReadReq mshr miss latency
@ -160,8 +154,8 @@ system.cpu.icache.demand_mshr_misses 856 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.355592 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 728.253324 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.355592 # Average percentage of cache occupancy
system.cpu.icache.overall_accesses 25645163 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 55761.178862 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53508.177570 # average overall mshr miss latency
@ -246,10 +240,10 @@ system.cpu.l2cache.demand_mshr_misses 92098 # nu
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.050363 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.487947 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 1650.286010 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 15989.036396 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.050363 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.487947 # Average percentage of cache occupancy
system.cpu.l2cache.overall_accesses 456251 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52157.973029 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40004.212904 # average overall mshr miss latency
@ -271,31 +265,37 @@ system.cpu.l2cache.tagsinuse 17639.322406 # Cy
system.cpu.l2cache.total_refs 445702 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 59346 # number of writebacks
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed
system.cpu.numCycles 523283946 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.regfile_manager.regFileAccesses 1022190210 # Number of Total Accesses (Read+Write) to the Register File
system.cpu.regfile_manager.regFileReads 558335321 # Number of Reads from Register File
system.cpu.regfile_manager.regFileWrites 463854889 # Number of Writes to Register File
system.cpu.regfile_manager.regForwards 256259728 # Number of Registers Read Through Forwarding Logic
system.cpu.runCycles 460794140 # Number of cycles cpu stages are processed.
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
system.cpu.stage-0.idleCycles 186436323 # Number of cycles 0 instructions are processed.
system.cpu.stage-0.runCycles 336847623 # Number of cycles 1+ instructions are processed.
system.cpu.stage-0.utilization 64.371863 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage-1.idleCycles 209154116 # Number of cycles 0 instructions are processed.
system.cpu.stage-1.runCycles 314129830 # Number of cycles 1+ instructions are processed.
system.cpu.stage-1.utilization 60.030473 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage-2.idleCycles 197582511 # Number of cycles 0 instructions are processed.
system.cpu.stage-2.runCycles 325701435 # Number of cycles 1+ instructions are processed.
system.cpu.stage-2.utilization 62.241817 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage-3.idleCycles 410314498 # Number of cycles 0 instructions are processed.
system.cpu.stage-3.runCycles 112969448 # Number of cycles 1+ instructions are processed.
system.cpu.stage-3.utilization 21.588556 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage-4.idleCycles 180086100 # Number of cycles 0 instructions are processed.
system.cpu.stage-4.runCycles 343197846 # Number of cycles 1+ instructions are processed.
system.cpu.stage-4.utilization 65.585396 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage0.idleCycles 186436323 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 336847623 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 64.371863 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 209154116 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 314129830 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 60.030473 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 197582511 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 325701435 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 62.241817 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 410314498 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 112969448 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 21.588556 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 180086100 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 343197846 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 65.585396 # Percentage of cycles stage was utilized (processing insts).
system.cpu.threadCycles 508404874 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.timesIdled 455729 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
system.cpu.workload.num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ----------

2
tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
View file

@ -25,6 +25,8 @@ BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
RASSize=16
SQEntries=32
SSITSize=1024

6
tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
View file

@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Mar 17 2011 21:44:37
M5 started Mar 17 2011 22:44:08
M5 executing on zizzer
M5 compiled Apr 19 2011 11:52:53
M5 started Apr 19 2011 12:05:54
M5 executing on maize
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

336
tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 243015 # Simulator instruction rate (inst/s)
host_mem_usage 208616 # Number of bytes of host memory used
host_seconds 2327.23 # Real time elapsed on the host
host_tick_rate 69757618 # Simulator tick rate (ticks/s)
host_inst_rate 385051 # Simulator instruction rate (inst/s)
host_mem_usage 204468 # Number of bytes of host memory used
host_seconds 1468.77 # Real time elapsed on the host
host_tick_rate 110529153 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 565552443 # Number of instructions simulated
sim_seconds 0.162342 # Number of seconds simulated
@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 4119052 # Nu
system.cpu.BPredUnit.condPredicted 70244988 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 76158972 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 1672188 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 62547159 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 20370282 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 315015358 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.910564 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 2.344745 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 102187516 32.44% 32.44% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 100337503 31.85% 64.29% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 36333939 11.53% 75.82% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 9834278 3.12% 78.95% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 9585018 3.04% 81.99% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 21675104 6.88% 88.87% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 13171126 4.18% 93.05% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 1520592 0.48% 93.53% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 20370282 6.47% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 315015358 # Number of insts commited each cycle
system.cpu.commit.COM:count 601856963 # Number of instructions committed
system.cpu.commit.COM:fp_insts 1520 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 1197610 # Number of function calls committed.
system.cpu.commit.COM:int_insts 563954763 # Number of committed integer instructions.
system.cpu.commit.COM:loads 114514042 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 153965363 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 4118243 # The number of times a branch was mispredicted
system.cpu.commit.branches 62547159 # Number of branches committed
system.cpu.commit.bw_lim_events 20370282 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 59876142 # The number of squashed insts skipped by commit
system.cpu.commit.committed_per_cycle::samples 315015358 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.910564 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.344745 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 102187516 32.44% 32.44% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 100337503 31.85% 64.29% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 36333939 11.53% 75.82% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 9834278 3.12% 78.95% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 9585018 3.04% 81.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 21675104 6.88% 88.87% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 13171126 4.18% 93.05% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 1520592 0.48% 93.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 20370282 6.47% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 315015358 # Number of insts commited each cycle
system.cpu.commit.count 601856963 # Number of instructions committed
system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions.
system.cpu.commit.function_calls 1197610 # Number of function calls committed.
system.cpu.commit.int_insts 563954763 # Number of committed integer instructions.
system.cpu.commit.loads 114514042 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.refs 153965363 # Number of memory references committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.committedInsts 565552443 # Number of Instructions Simulated
system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated
system.cpu.cpi 0.574101 # CPI: Cycles Per Instruction
@ -98,8 +98,8 @@ system.cpu.dcache.demand_mshr_misses 475134 # nu
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.999549 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4094.151824 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.999549 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses 151655852 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 14624.181040 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 9493.104038 # average overall mshr miss latency
@ -121,15 +121,15 @@ system.cpu.dcache.tagsinuse 4094.151824 # Cy
system.cpu.dcache.total_refs 149582206 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 126677000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 423176 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 44833716 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 844 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 4163323 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 687863087 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 142213399 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 122593858 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 9601978 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 3402 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 5374385 # Number of cycles decode is unblocking
system.cpu.decode.BlockedCycles 44833716 # Number of cycles decode is blocked
system.cpu.decode.BranchMispred 844 # Number of times decode detected a branch misprediction
system.cpu.decode.BranchResolved 4163323 # Number of times decode resolved a branch
system.cpu.decode.DecodedInsts 687863087 # Number of instructions handled by decode
system.cpu.decode.IdleCycles 142213399 # Number of cycles decode is idle
system.cpu.decode.RunCycles 122593858 # Number of cycles decode is running
system.cpu.decode.SquashCycles 9601978 # Number of cycles decode is squashing
system.cpu.decode.SquashedInsts 3402 # Number of squashed instructions handled by decode
system.cpu.decode.UnblockCycles 5374385 # Number of cycles decode is unblocking
system.cpu.dtb.data_accesses 163150258 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 163097305 # DTB hits
@ -209,8 +209,8 @@ system.cpu.icache.demand_mshr_misses 909 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.378270 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 774.695980 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.378270 # Average percentage of cache occupancy
system.cpu.icache.overall_accesses 65447834 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 36501.303215 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35511.551155 # average overall mshr miss latency
@ -233,21 +233,13 @@ system.cpu.icache.total_refs 65446683 # To
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 67100 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 67449018 # Number of branches executed
system.cpu.iew.EXEC:nop 43212719 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.845435 # Inst execution rate
system.cpu.iew.EXEC:refs 163178153 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 40932468 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 486897348 # num instructions consuming a value
system.cpu.iew.WB:count 595948678 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.812979 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 395837342 # num instructions producing a value
system.cpu.iew.WB:rate 1.835470 # insts written-back per cycle
system.cpu.iew.WB:sent 597097102 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 4605504 # Number of branch mispredicts detected at execute
system.cpu.iew.exec_branches 67449018 # Number of branches executed
system.cpu.iew.exec_nop 43212719 # number of nop insts executed
system.cpu.iew.exec_rate 1.845435 # Inst execution rate
system.cpu.iew.exec_refs 163178153 # number of memory reference insts executed
system.cpu.iew.exec_stores 40932468 # Number of stores executed
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.iewBlockCycles 1354512 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 125962189 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions
@ -275,103 +267,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 3134413 #
system.cpu.iew.memOrderViolationEvents 24101 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 952315 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 3653189 # Number of branches that were predicted taken incorrectly
system.cpu.iew.wb_consumers 486897348 # num instructions consuming a value
system.cpu.iew.wb_count 595948678 # cumulative count of insts written-back
system.cpu.iew.wb_fanout 0.812979 # average fanout of values written-back
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_producers 395837342 # num instructions producing a value
system.cpu.iew.wb_rate 1.835470 # insts written-back per cycle
system.cpu.iew.wb_sent 597097102 # cumulative count of insts sent to commit
system.cpu.int_regfile_reads 844972523 # number of integer regfile reads
system.cpu.int_regfile_writes 489243634 # number of integer regfile writes
system.cpu.ipc 1.741853 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.741853 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 439577743 72.58% 72.58% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 6656 0.00% 72.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 30 0.00% 72.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 5 0.00% 72.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 5 0.00% 72.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 4 0.00% 72.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 124281005 20.52% 93.11% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 41743673 6.89% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 605609121 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 5929666 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.009791 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 5228922 88.18% 88.18% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 48 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 403247 6.80% 94.98% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 297449 5.02% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 324617336 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.865609 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.727719 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 90473429 27.87% 27.87% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 62743019 19.33% 47.20% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 78570143 24.20% 71.40% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 32526937 10.02% 81.42% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 31455135 9.69% 91.11% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 13029774 4.01% 95.13% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 14124566 4.35% 99.48% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 1126465 0.35% 99.83% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 567868 0.17% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 324617336 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.865224 # Inst issue rate
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 439577743 72.58% 72.58% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 6656 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 30 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 5 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 4 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 124281005 20.52% 93.11% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 41743673 6.89% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 605609121 # Type of FU issued
system.cpu.iq.fp_alu_accesses 1669 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 3317 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 1594 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 1802 # Number of floating instruction queue writes
system.cpu.iq.fu_busy_cnt 5929666 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.009791 # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 5228922 88.18% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 48 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 403247 6.80% 94.98% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 297449 5.02% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.int_alu_accesses 611537118 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 1541773318 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 595947084 # Number of integer instruction queue wakeup accesses
@ -383,6 +365,24 @@ system.cpu.iq.iqSquashedInstsExamined 51673321 # Nu
system.cpu.iq.iqSquashedInstsIssued 11391 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 26894119 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.issued_per_cycle::samples 324617336 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.865609 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.727719 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 90473429 27.87% 27.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 62743019 19.33% 47.20% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 78570143 24.20% 71.40% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 32526937 10.02% 81.42% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 31455135 9.69% 91.11% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 13029774 4.01% 95.13% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 14124566 4.35% 99.48% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 1126465 0.35% 99.83% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 567868 0.17% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 324617336 # Number of insts issued each cycle
system.cpu.iq.rate 1.865224 # Inst issue rate
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
@ -443,10 +443,10 @@ system.cpu.l2cache.demand_mshr_misses 92757 # nu
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.052925 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.487884 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 1734.245593 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 15986.969370 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.052925 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.487884 # Average percentage of cache occupancy
system.cpu.l2cache.overall_accesses 476043 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34447.863773 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31236.300225 # average overall mshr miss latency
@ -477,28 +477,28 @@ system.cpu.misc_regfile_writes 1 # nu
system.cpu.numCycles 324684436 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 12564419 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 31522766 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 149604933 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 659383 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 101 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 894089158 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 678776451 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 517767610 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 115293181 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 9601978 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 37552130 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 53912721 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 1965 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 894087193 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 695 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 31 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 73444449 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 30 # count of temporary serializing insts renamed
system.cpu.rename.BlockCycles 12564419 # Number of cycles rename is blocking
system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed
system.cpu.rename.IQFullEvents 31522766 # Number of times rename has blocked due to IQ full
system.cpu.rename.IdleCycles 149604933 # Number of cycles rename is idle
system.cpu.rename.LSQFullEvents 659383 # Number of times rename has blocked due to LSQ full
system.cpu.rename.ROBFullEvents 101 # Number of times rename has blocked due to ROB full
system.cpu.rename.RenameLookups 894089158 # Number of register rename lookups that rename has made
system.cpu.rename.RenamedInsts 678776451 # Number of instructions processed by rename
system.cpu.rename.RenamedOperands 517767610 # Number of destination operands rename has renamed
system.cpu.rename.RunCycles 115293181 # Number of cycles rename is running
system.cpu.rename.SquashCycles 9601978 # Number of cycles rename is squashing
system.cpu.rename.UnblockCycles 37552130 # Number of cycles rename is unblocking
system.cpu.rename.UndoneMaps 53912721 # Number of HB maps that are undone due to squashing
system.cpu.rename.fp_rename_lookups 1965 # Number of floating rename lookups
system.cpu.rename.int_rename_lookups 894087193 # Number of integer rename lookups
system.cpu.rename.serializeStallCycles 695 # count of cycles rename stalled for serializing inst
system.cpu.rename.serializingInsts 31 # count of serializing insts renamed
system.cpu.rename.skidInsts 73444449 # count of insts added to the skid buffer
system.cpu.rename.tempSerializingInsts 30 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 956313792 # The number of ROB reads
system.cpu.rob.rob_writes 1333072216 # The number of ROB writes
system.cpu.timesIdled 2037 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
system.cpu.workload.num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ----------

7
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout
View file

@ -5,10 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 7 2011 01:47:18
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Feb 7 2011 01:47:37
M5 executing on burrito
M5 compiled Apr 19 2011 11:52:53
M5 started Apr 19 2011 11:58:35
M5 executing on maize
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

10
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1697811 # Simulator instruction rate (inst/s)
host_mem_usage 218112 # Number of bytes of host memory used
host_seconds 354.49 # Real time elapsed on the host
host_tick_rate 848911876 # Simulator tick rate (ticks/s)
host_inst_rate 6401056 # Simulator instruction rate (inst/s)
host_mem_usage 195828 # Number of bytes of host memory used
host_seconds 94.02 # Real time elapsed on the host
host_tick_rate 3200547989 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 601856964 # Number of instructions simulated
sim_seconds 0.300931 # Number of seconds simulated
@ -61,6 +61,6 @@ system.cpu.num_int_register_writes 463854847 # nu
system.cpu.num_load_insts 114516673 # Number of load instructions
system.cpu.num_mem_refs 153970296 # number of memory refs
system.cpu.num_store_insts 39453623 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
system.cpu.workload.num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ----------

3
tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
View file

@ -51,6 +51,7 @@ assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
@ -86,6 +87,7 @@ assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
@ -121,6 +123,7 @@ assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=10000
max_miss_count=0
mshrs=10

7
tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout
View file

@ -5,10 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 7 2011 01:47:18
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Feb 7 2011 01:47:36
M5 executing on burrito
M5 compiled Apr 19 2011 11:52:53
M5 started Apr 19 2011 11:58:24
M5 executing on maize
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

18
tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 591495 # Simulator instruction rate (inst/s)
host_mem_usage 225828 # Number of bytes of host memory used
host_seconds 1017.52 # Real time elapsed on the host
host_tick_rate 752441266 # Simulator tick rate (ticks/s)
host_inst_rate 2829112 # Simulator instruction rate (inst/s)
host_mem_usage 203572 # Number of bytes of host memory used
host_seconds 212.74 # Real time elapsed on the host
host_tick_rate 3598913072 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 601856964 # Number of instructions simulated
sim_seconds 0.765623 # Number of seconds simulated
@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses 455395 # nu
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.999553 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4094.170317 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.999553 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 22414.479737 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 19414.479737 # average overall mshr miss latency
@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses 795 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.328778 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 673.337154 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.328778 # Average percentage of cache occupancy
system.cpu.icache.overall_accesses 601861898 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
@ -205,10 +205,10 @@ system.cpu.l2cache.demand_mshr_misses 92031 # nu
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.052565 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.491366 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 1722.436058 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 16101.078831 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.052565 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.491366 # Average percentage of cache occupancy
system.cpu.l2cache.overall_accesses 456190 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
@ -250,6 +250,6 @@ system.cpu.num_int_register_writes 463854847 # nu
system.cpu.num_load_insts 114516673 # Number of load instructions
system.cpu.num_mem_refs 153970296 # number of memory refs
system.cpu.num_store_insts 39453623 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
system.cpu.workload.num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ----------

2
tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini
View file

@ -498,7 +498,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/arm/scratch/alisai01/dist/cpu2000/binaries/arm/linux/gzip
executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
gid=100
input=cin
max_stack_size=67108864

8
tests/long/00.gzip/ref/arm/linux/o3-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Mar 30 2011 17:47:57
M5 started Mar 30 2011 17:54:33
M5 executing on u200439-lin.austin.arm.com
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing
M5 compiled Apr 19 2011 12:47:10
M5 started Apr 19 2011 12:47:12
M5 executing on maize
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init

334
tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 238408 # Simulator instruction rate (inst/s)
host_mem_usage 258640 # Number of bytes of host memory used
host_seconds 2526.59 # Real time elapsed on the host
host_tick_rate 77778012 # Simulator tick rate (ticks/s)
host_inst_rate 283332 # Simulator instruction rate (inst/s)
host_mem_usage 214996 # Number of bytes of host memory used
host_seconds 2125.99 # Real time elapsed on the host
host_tick_rate 92433779 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 602359865 # Number of instructions simulated
sim_seconds 0.196513 # Number of seconds simulated
@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 3832102 # Nu
system.cpu.BPredUnit.condPredicted 81880205 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 88398894 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 1393010 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 70828614 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 7897771 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 379244728 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.588315 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.904338 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 123478650 32.56% 32.56% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 123013107 32.44% 65.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 59170888 15.60% 80.60% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 18488020 4.87% 85.47% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 17225820 4.54% 90.01% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 14373715 3.79% 93.80% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 7590349 2.00% 95.81% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 8006408 2.11% 97.92% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 7897771 2.08% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 379244728 # Number of insts commited each cycle
system.cpu.commit.COM:count 602359916 # Number of instructions committed
system.cpu.commit.COM:fp_insts 16 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 997573 # Number of function calls committed.
system.cpu.commit.COM:int_insts 533522691 # Number of committed integer instructions.
system.cpu.commit.COM:loads 148952607 # Number of loads committed
system.cpu.commit.COM:membars 1328 # Number of memory barriers committed
system.cpu.commit.COM:refs 219173633 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 3891220 # The number of times a branch was mispredicted
system.cpu.commit.branches 70828614 # Number of branches committed
system.cpu.commit.bw_lim_events 7897771 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.commitCommittedInsts 602359916 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 6310 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 86859726 # The number of squashed insts skipped by commit
system.cpu.commit.committed_per_cycle::samples 379244728 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.588315 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.904338 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 123478650 32.56% 32.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 123013107 32.44% 65.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 59170888 15.60% 80.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 18488020 4.87% 85.47% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 17225820 4.54% 90.01% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 14373715 3.79% 93.80% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 7590349 2.00% 95.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 8006408 2.11% 97.92% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 7897771 2.08% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 379244728 # Number of insts commited each cycle
system.cpu.commit.count 602359916 # Number of instructions committed
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
system.cpu.commit.function_calls 997573 # Number of function calls committed.
system.cpu.commit.int_insts 533522691 # Number of committed integer instructions.
system.cpu.commit.loads 148952607 # Number of loads committed
system.cpu.commit.membars 1328 # Number of memory barriers committed
system.cpu.commit.refs 219173633 # Number of memory references committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.committedInsts 602359865 # Number of Instructions Simulated
system.cpu.committedInsts_total 602359865 # Number of Instructions Simulated
system.cpu.cpi 0.652478 # CPI: Cycles Per Instruction
@ -105,8 +105,8 @@ system.cpu.dcache.demand_mshr_misses 443820 # nu
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.999719 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4094.849519 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.999719 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses 208812765 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 17229.974009 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 9270.687452 # average overall mshr miss latency
@ -128,15 +128,15 @@ system.cpu.dcache.tagsinuse 4094.849519 # Cy
system.cpu.dcache.total_refs 207082021 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 89315000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 394264 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 64227537 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 1274 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 5983982 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 722350979 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 163737957 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 138388023 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 12871984 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 4747 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 12891210 # Number of cycles decode is unblocking
system.cpu.decode.BlockedCycles 64227537 # Number of cycles decode is blocked
system.cpu.decode.BranchMispred 1274 # Number of times decode detected a branch misprediction
system.cpu.decode.BranchResolved 5983982 # Number of times decode resolved a branch
system.cpu.decode.DecodedInsts 722350979 # Number of instructions handled by decode
system.cpu.decode.IdleCycles 163737957 # Number of cycles decode is idle
system.cpu.decode.RunCycles 138388023 # Number of cycles decode is running
system.cpu.decode.SquashCycles 12871984 # Number of cycles decode is squashing
system.cpu.decode.SquashedInsts 4747 # Number of squashed instructions handled by decode
system.cpu.decode.UnblockCycles 12891210 # Number of cycles decode is unblocking
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
@ -220,8 +220,8 @@ system.cpu.icache.demand_mshr_misses 722 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.307172 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 629.087764 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.307172 # Average percentage of cache occupancy
system.cpu.icache.overall_accesses 71395519 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 35429.359823 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 34341.412742 # average overall mshr miss latency
@ -244,21 +244,13 @@ system.cpu.icache.total_refs 71394613 # To
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 909571 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 73704412 # Number of branches executed
system.cpu.iew.EXEC:nop 61098 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.622472 # Inst execution rate
system.cpu.iew.EXEC:refs 239165331 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 73423365 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 736448308 # num instructions consuming a value
system.cpu.iew.WB:count 631945179 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.594878 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 438096934 # num instructions producing a value
system.cpu.iew.WB:rate 1.607895 # insts written-back per cycle
system.cpu.iew.WB:sent 632881856 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 4305441 # Number of branch mispredicts detected at execute
system.cpu.iew.exec_branches 73704412 # Number of branches executed
system.cpu.iew.exec_nop 61098 # number of nop insts executed
system.cpu.iew.exec_rate 1.622472 # Inst execution rate
system.cpu.iew.exec_refs 239165331 # number of memory reference insts executed
system.cpu.iew.exec_stores 73423365 # Number of stores executed
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.iewBlockCycles 811047 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 176106355 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 5819 # Number of dispatched non-speculative instructions
@ -286,103 +278,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 11966835 #
system.cpu.iew.memOrderViolationEvents 611520 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 628522 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 3676919 # Number of branches that were predicted taken incorrectly
system.cpu.iew.wb_consumers 736448308 # num instructions consuming a value
system.cpu.iew.wb_count 631945179 # cumulative count of insts written-back
system.cpu.iew.wb_fanout 0.594878 # average fanout of values written-back
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_producers 438096934 # num instructions producing a value
system.cpu.iew.wb_rate 1.607895 # insts written-back per cycle
system.cpu.iew.wb_sent 632881856 # cumulative count of insts sent to commit
system.cpu.int_regfile_reads 1724767298 # number of integer regfile reads
system.cpu.int_regfile_writes 495432851 # number of integer regfile writes
system.cpu.ipc 1.532620 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.532620 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 400863775 62.26% 62.26% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 6585 0.00% 62.27% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 3 0.00% 62.27% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 168265891 26.14% 88.40% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 74671891 11.60% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 643808145 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 3945011 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.006128 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 107679 2.73% 2.73% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 3407280 86.37% 89.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 430052 10.90% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 392116711 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.641879 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.551770 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 108904518 27.77% 27.77% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 107421508 27.40% 55.17% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 76290088 19.46% 74.62% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 48454562 12.36% 86.98% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 26882762 6.86% 93.84% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 16851716 4.30% 98.14% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 5414053 1.38% 99.52% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 1011203 0.26% 99.77% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 886301 0.23% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 392116711 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.638079 # Inst issue rate
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 400863775 62.26% 62.26% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 6585 0.00% 62.27% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.27% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 168265891 26.14% 88.40% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 74671891 11.60% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 643808145 # Type of FU issued
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
system.cpu.iq.fu_busy_cnt 3945011 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.006128 # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 107679 2.73% 2.73% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.73% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 3407280 86.37% 89.10% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 430052 10.90% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.int_alu_accesses 647753136 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 1684034505 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 631945163 # Number of integer instruction queue wakeup accesses
@ -394,6 +376,24 @@ system.cpu.iq.iqSquashedInstsExamined 86496318 # Nu
system.cpu.iq.iqSquashedInstsIssued 356529 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 850 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 162226931 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.issued_per_cycle::samples 392116711 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.641879 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.551770 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 108904518 27.77% 27.77% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 107421508 27.40% 55.17% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 76290088 19.46% 74.62% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 48454562 12.36% 86.98% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 26882762 6.86% 93.84% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 16851716 4.30% 98.14% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 5414053 1.38% 99.52% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 1011203 0.26% 99.77% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 886301 0.23% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 392116711 # Number of insts issued each cycle
system.cpu.iq.rate 1.638079 # Inst issue rate
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
@ -468,10 +468,10 @@ system.cpu.l2cache.demand_mshr_misses 91150 # nu
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.057260 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.487109 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 1876.282231 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 15961.603623 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.057260 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.487109 # Average percentage of cache occupancy
system.cpu.l2cache.overall_accesses 444538 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34340.043442 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31188.047175 # average overall mshr miss latency
@ -502,27 +502,27 @@ system.cpu.misc_regfile_writes 2682 # nu
system.cpu.numCycles 393026282 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 9628088 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 471021820 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 50048668 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 176696020 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 1915065 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 2034394520 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 711291370 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 553214444 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 138291459 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 12871984 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 54521168 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 82192621 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 96 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 2034394424 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 107992 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 6480 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 91409775 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 6477 # count of temporary serializing insts renamed
system.cpu.rename.BlockCycles 9628088 # Number of cycles rename is blocking
system.cpu.rename.CommittedMaps 471021820 # Number of HB maps that are committed
system.cpu.rename.IQFullEvents 50048668 # Number of times rename has blocked due to IQ full
system.cpu.rename.IdleCycles 176696020 # Number of cycles rename is idle
system.cpu.rename.LSQFullEvents 1915065 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenameLookups 2034394520 # Number of register rename lookups that rename has made
system.cpu.rename.RenamedInsts 711291370 # Number of instructions processed by rename
system.cpu.rename.RenamedOperands 553214444 # Number of destination operands rename has renamed
system.cpu.rename.RunCycles 138291459 # Number of cycles rename is running
system.cpu.rename.SquashCycles 12871984 # Number of cycles rename is squashing
system.cpu.rename.UnblockCycles 54521168 # Number of cycles rename is unblocking
system.cpu.rename.UndoneMaps 82192621 # Number of HB maps that are undone due to squashing
system.cpu.rename.fp_rename_lookups 96 # Number of floating rename lookups
system.cpu.rename.int_rename_lookups 2034394424 # Number of integer rename lookups
system.cpu.rename.serializeStallCycles 107992 # count of cycles rename stalled for serializing inst
system.cpu.rename.serializingInsts 6480 # count of serializing insts renamed
system.cpu.rename.skidInsts 91409775 # count of insts added to the skid buffer
system.cpu.rename.tempSerializingInsts 6477 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 1060565987 # The number of ROB reads
system.cpu.rob.rob_writes 1391311417 # The number of ROB writes
system.cpu.timesIdled 36947 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 48 # Number of system calls
system.cpu.workload.num_syscalls 48 # Number of system calls
---------- End Simulation Statistics ----------

4
tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini
View file

@ -61,12 +61,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic
cwd=build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic
egid=100
env=
errout=cerr
euid=100
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/gzip
executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
gid=100
input=cin
max_stack_size=67108864

8
tests/long/00.gzip/ref/arm/linux/simple-atomic/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Mar 30 2011 17:47:57
M5 started Mar 30 2011 17:54:33
M5 executing on u200439-lin.austin.arm.com
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic
M5 compiled Apr 19 2011 12:47:10
M5 started Apr 19 2011 12:47:58
M5 executing on maize
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init

10
tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1048186 # Simulator instruction rate (inst/s)
host_mem_usage 246964 # Number of bytes of host memory used
host_seconds 574.67 # Real time elapsed on the host
host_tick_rate 524112689 # Simulator tick rate (ticks/s)
host_inst_rate 4079554 # Simulator instruction rate (inst/s)
host_mem_usage 206080 # Number of bytes of host memory used
host_seconds 147.65 # Real time elapsed on the host
host_tick_rate 2039852029 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 602359851 # Number of instructions simulated
sim_seconds 0.301191 # Number of seconds simulated
@ -71,6 +71,6 @@ system.cpu.num_int_register_writes 458076290 # nu
system.cpu.num_load_insts 148952594 # Number of load instructions
system.cpu.num_mem_refs 219173607 # number of memory refs
system.cpu.num_store_insts 70221013 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 48 # Number of system calls
system.cpu.workload.num_syscalls 48 # Number of system calls
---------- End Simulation Statistics ----------

4
tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini
View file

@ -164,12 +164,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing
cwd=build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing
egid=100
env=
errout=cerr
euid=100
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/gzip
executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
gid=100
input=cin
max_stack_size=67108864

8
tests/long/00.gzip/ref/arm/linux/simple-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Mar 30 2011 17:47:57
M5 started Mar 30 2011 17:54:33
M5 executing on u200439-lin.austin.arm.com
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing
M5 compiled Apr 19 2011 12:47:10
M5 started Apr 19 2011 12:48:29
M5 executing on maize
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init

18
tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 590565 # Simulator instruction rate (inst/s)
host_mem_usage 254684 # Number of bytes of host memory used
host_seconds 1016.65 # Real time elapsed on the host
host_tick_rate 783712761 # Simulator tick rate (ticks/s)
host_inst_rate 2132031 # Simulator instruction rate (inst/s)
host_mem_usage 213820 # Number of bytes of host memory used
host_seconds 281.61 # Real time elapsed on the host
host_tick_rate 2829324901 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 600398281 # Number of instructions simulated
sim_seconds 0.796763 # Number of seconds simulated
@ -54,8 +54,8 @@ system.cpu.dcache.demand_mshr_misses 437564 # nu
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.999566 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4094.222434 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.999566 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses 217209383 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 22578.841038 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 19578.841038 # average overall mshr miss latency
@ -130,8 +130,8 @@ system.cpu.icache.demand_mshr_misses 643 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.282094 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 577.728532 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.282094 # Average percentage of cache occupancy
system.cpu.icache.overall_accesses 570074535 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 54236.391913 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 51236.391913 # average overall mshr miss latency
@ -219,10 +219,10 @@ system.cpu.l2cache.demand_mshr_misses 89992 # nu
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.053777 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.492610 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 1762.179345 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 16141.835335 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.053777 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.492610 # Average percentage of cache occupancy
system.cpu.l2cache.overall_accesses 438207 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
@ -264,6 +264,6 @@ system.cpu.num_int_register_writes 458076290 # nu
system.cpu.num_load_insts 148952594 # Number of load instructions
system.cpu.num_mem_refs 219173607 # number of memory refs
system.cpu.num_store_insts 70221013 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 48 # Number of system calls
system.cpu.workload.num_syscalls 48 # Number of system calls
---------- End Simulation Statistics ----------

2
tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
View file

@ -25,6 +25,8 @@ BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
RASSize=16
SQEntries=32
SSITSize=1024

6
tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
View file

@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Mar 17 2011 23:04:27
M5 started Mar 17 2011 23:11:57
M5 executing on zizzer
M5 compiled Apr 19 2011 12:19:46
M5 started Apr 19 2011 12:20:08
M5 executing on maize
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

330
tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 165963 # Simulator instruction rate (inst/s)
host_mem_usage 210376 # Number of bytes of host memory used
host_seconds 8469.40 # Real time elapsed on the host
host_tick_rate 68767363 # Simulator tick rate (ticks/s)
host_inst_rate 280029 # Simulator instruction rate (inst/s)
host_mem_usage 206320 # Number of bytes of host memory used
host_seconds 5019.49 # Real time elapsed on the host
host_tick_rate 116031336 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1405604152 # Number of instructions simulated
sim_seconds 0.582418 # Number of seconds simulated
@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 5339067 # Nu
system.cpu.BPredUnit.condPredicted 103713551 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 103713551 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 86248929 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 26710610 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 1136580592 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.310530 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.747403 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 402922453 35.45% 35.45% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 477569543 42.02% 77.47% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 55697713 4.90% 82.37% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 97088718 8.54% 90.91% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 32658945 2.87% 93.78% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 8438570 0.74% 94.53% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 25679618 2.26% 96.79% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 9814422 0.86% 97.65% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 26710610 2.35% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 1136580592 # Number of insts commited each cycle
system.cpu.commit.COM:count 1489523295 # Number of instructions committed
system.cpu.commit.COM:fp_insts 8452036 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
system.cpu.commit.COM:int_insts 1319476388 # Number of committed integer instructions.
system.cpu.commit.COM:loads 402512844 # Number of loads committed
system.cpu.commit.COM:membars 51356 # Number of memory barriers committed
system.cpu.commit.COM:refs 569360986 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 5339067 # The number of times a branch was mispredicted
system.cpu.commit.branches 86248929 # Number of branches committed
system.cpu.commit.bw_lim_events 26710610 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.commitCommittedInsts 1489523295 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 199490556 # The number of squashed insts skipped by commit
system.cpu.commit.committed_per_cycle::samples 1136580592 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.310530 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.747403 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 402922453 35.45% 35.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 477569543 42.02% 77.47% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 55697713 4.90% 82.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 97088718 8.54% 90.91% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 32658945 2.87% 93.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 8438570 0.74% 94.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 25679618 2.26% 96.79% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 9814422 0.86% 97.65% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 26710610 2.35% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1136580592 # Number of insts commited each cycle
system.cpu.commit.count 1489523295 # Number of instructions committed
system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
system.cpu.commit.int_insts 1319476388 # Number of committed integer instructions.
system.cpu.commit.loads 402512844 # Number of loads committed
system.cpu.commit.membars 51356 # Number of memory barriers committed
system.cpu.commit.refs 569360986 # Number of memory references committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.committedInsts 1405604152 # Number of Instructions Simulated
system.cpu.committedInsts_total 1405604152 # Number of Instructions Simulated
system.cpu.cpi 0.828709 # CPI: Cycles Per Instruction
@ -106,8 +106,8 @@ system.cpu.dcache.demand_mshr_misses 481375 # nu
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.999855 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4095.405595 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.999855 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses 458308294 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 15159.332747 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 10578.009334 # average overall mshr miss latency
@ -129,12 +129,12 @@ system.cpu.dcache.tagsinuse 4095.405595 # Cy
system.cpu.dcache.total_refs 455672050 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 132278000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 428224 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 373408138 # Number of cycles decode is blocked
system.cpu.decode.DECODE:DecodedInsts 1727466392 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 394807577 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 348667632 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 27885594 # Number of cycles decode is squashing
system.cpu.decode.DECODE:UnblockCycles 19696634 # Number of cycles decode is unblocking
system.cpu.decode.BlockedCycles 373408138 # Number of cycles decode is blocked
system.cpu.decode.DecodedInsts 1727466392 # Number of instructions handled by decode
system.cpu.decode.IdleCycles 394807577 # Number of cycles decode is idle
system.cpu.decode.RunCycles 348667632 # Number of cycles decode is running
system.cpu.decode.SquashCycles 27885594 # Number of cycles decode is squashing
system.cpu.decode.UnblockCycles 19696634 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 103713551 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 170870865 # Number of cache lines fetched
system.cpu.fetch.Cycles 370648133 # Number of cycles fetch has run and was not squashing or blocked
@ -198,8 +198,8 @@ system.cpu.icache.demand_mshr_misses 1297 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.511535 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1047.623620 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.511535 # Average percentage of cache occupancy
system.cpu.icache.overall_accesses 170870865 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 35272.495756 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35056.283732 # average overall mshr miss latency
@ -222,21 +222,13 @@ system.cpu.icache.total_refs 170869098 # To
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 370544 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 89603944 # Number of branches executed
system.cpu.iew.EXEC:nop 100373819 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.267070 # Inst execution rate
system.cpu.iew.EXEC:refs 591399205 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 170154785 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 1209973999 # num instructions consuming a value
system.cpu.iew.WB:count 1473173854 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.961076 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 1162877329 # num instructions producing a value
system.cpu.iew.WB:rate 1.264705 # insts written-back per cycle
system.cpu.iew.WB:sent 1474297623 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 5675287 # Number of branch mispredicts detected at execute
system.cpu.iew.exec_branches 89603944 # Number of branches executed
system.cpu.iew.exec_nop 100373819 # number of nop insts executed
system.cpu.iew.exec_rate 1.267070 # Inst execution rate
system.cpu.iew.exec_refs 591399205 # number of memory reference insts executed
system.cpu.iew.exec_stores 170154785 # Number of stores executed
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.iewBlockCycles 2507924 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 461157302 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 2999936 # Number of dispatched non-speculative instructions
@ -264,103 +256,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 20174020 #
system.cpu.iew.memOrderViolationEvents 460365 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 670427 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 5004860 # Number of branches that were predicted taken incorrectly
system.cpu.iew.wb_consumers 1209973999 # num instructions consuming a value
system.cpu.iew.wb_count 1473173854 # cumulative count of insts written-back
system.cpu.iew.wb_fanout 0.961076 # average fanout of values written-back
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_producers 1162877329 # num instructions producing a value
system.cpu.iew.wb_rate 1.264705 # insts written-back per cycle
system.cpu.iew.wb_sent 1474297623 # cumulative count of insts sent to commit
system.cpu.int_regfile_reads 1997794756 # number of integer regfile reads
system.cpu.int_regfile_writes 1296594839 # number of integer regfile writes
system.cpu.ipc 1.206697 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.206697 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 883945189 59.64% 59.64% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 59.64% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 59.64% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2631981 0.18% 59.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 424001958 28.61% 88.42% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 171668003 11.58% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 1482247131 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 3391020 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.002288 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 214212 6.32% 6.32% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 6.32% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 6.32% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 187778 5.54% 11.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 2748667 81.06% 92.91% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 240363 7.09% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 1164465575 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.272899 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.148641 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 309298241 26.56% 26.56% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 465738905 40.00% 66.56% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 229121985 19.68% 86.23% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 104115000 8.94% 95.17% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 41467759 3.56% 98.74% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 8912842 0.77% 99.50% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 5349281 0.46% 99.96% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 304172 0.03% 99.99% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 157390 0.01% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 1164465575 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.272494 # Inst issue rate
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 883945189 59.64% 59.64% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.64% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.64% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2631981 0.18% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.81% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 424001958 28.61% 88.42% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 171668003 11.58% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 1482247131 # Type of FU issued
system.cpu.iq.fp_alu_accesses 9142959 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 17762219 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 8523024 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 9165283 # Number of floating instruction queue writes
system.cpu.iq.fu_busy_cnt 3391020 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.002288 # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 214212 6.32% 6.32% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 6.32% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 6.32% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 187778 5.54% 11.85% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.85% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 2748667 81.06% 92.91% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 240363 7.09% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.int_alu_accesses 1476495192 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 4114870575 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 1464650830 # Number of integer instruction queue wakeup accesses
@ -372,6 +354,24 @@ system.cpu.iq.iqSquashedInstsExamined 182705519 # Nu
system.cpu.iq.iqSquashedInstsIssued 281937 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 855886 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 240684944 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.issued_per_cycle::samples 1164465575 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.272899 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.148641 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 309298241 26.56% 26.56% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 465738905 40.00% 66.56% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 229121985 19.68% 86.23% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 104115000 8.94% 95.17% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 41467759 3.56% 98.74% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 8912842 0.77% 99.50% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 5349281 0.46% 99.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 304172 0.03% 99.99% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 157390 0.01% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 1164465575 # Number of insts issued each cycle
system.cpu.iq.rate 1.272494 # Inst issue rate
system.cpu.l2cache.ReadExReq_accesses 268051 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34407.834444 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31320.706026 # average ReadExReq mshr miss latency
@ -416,10 +416,10 @@ system.cpu.l2cache.demand_mshr_misses 94147 # nu
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.059800 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.479227 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 1959.521413 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 15703.307498 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.059800 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.479227 # Average percentage of cache occupancy
system.cpu.l2cache.overall_accesses 482679 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34275.266339 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31207.701786 # average overall mshr miss latency
@ -450,28 +450,28 @@ system.cpu.misc_regfile_writes 2258933 # nu
system.cpu.numCycles 1164836119 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 115497905 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 1244770452 # Number of HB maps that are committed
system.cpu.rename.RENAME:FullRegisterEvents 28107626 # Number of times there has been no free registers
system.cpu.rename.RENAME:IQFullEvents 128337052 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 433132347 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 40459205 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 2887426636 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 1709740875 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 1426816340 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 325737783 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 27885594 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 209164686 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 182045888 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 33660518 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 2853766118 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 53047260 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 3085415 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 378977297 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 3085429 # count of temporary serializing insts renamed
system.cpu.rename.BlockCycles 115497905 # Number of cycles rename is blocking
system.cpu.rename.CommittedMaps 1244770452 # Number of HB maps that are committed
system.cpu.rename.FullRegisterEvents 28107626 # Number of times there has been no free registers
system.cpu.rename.IQFullEvents 128337052 # Number of times rename has blocked due to IQ full
system.cpu.rename.IdleCycles 433132347 # Number of cycles rename is idle
system.cpu.rename.LSQFullEvents 40459205 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenameLookups 2887426636 # Number of register rename lookups that rename has made
system.cpu.rename.RenamedInsts 1709740875 # Number of instructions processed by rename
system.cpu.rename.RenamedOperands 1426816340 # Number of destination operands rename has renamed
system.cpu.rename.RunCycles 325737783 # Number of cycles rename is running
system.cpu.rename.SquashCycles 27885594 # Number of cycles rename is squashing
system.cpu.rename.UnblockCycles 209164686 # Number of cycles rename is unblocking
system.cpu.rename.UndoneMaps 182045888 # Number of HB maps that are undone due to squashing
system.cpu.rename.fp_rename_lookups 33660518 # Number of floating rename lookups
system.cpu.rename.int_rename_lookups 2853766118 # Number of integer rename lookups
system.cpu.rename.serializeStallCycles 53047260 # count of cycles rename stalled for serializing inst
system.cpu.rename.serializingInsts 3085415 # count of serializing insts renamed
system.cpu.rename.skidInsts 378977297 # count of insts added to the skid buffer
system.cpu.rename.tempSerializingInsts 3085429 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 2798818963 # The number of ROB reads
system.cpu.rob.rob_writes 3405946340 # The number of ROB writes
system.cpu.timesIdled 11499 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 49 # Number of system calls
system.cpu.workload.num_syscalls 49 # Number of system calls
---------- End Simulation Statistics ----------

7
tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout
View file

@ -5,10 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 7 2011 02:13:30
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Feb 7 2011 02:14:57
M5 executing on burrito
M5 compiled Apr 19 2011 12:19:46
M5 started Apr 19 2011 12:21:44
M5 executing on maize
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

10
tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1524596 # Simulator instruction rate (inst/s)
host_mem_usage 219684 # Number of bytes of host memory used
host_seconds 977.00 # Real time elapsed on the host
host_tick_rate 762300416 # Simulator tick rate (ticks/s)
host_inst_rate 4954155 # Simulator instruction rate (inst/s)
host_mem_usage 197572 # Number of bytes of host memory used
host_seconds 300.66 # Real time elapsed on the host
host_tick_rate 2477084432 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1489523295 # Number of instructions simulated
sim_seconds 0.744764 # Number of seconds simulated
@ -29,6 +29,6 @@ system.cpu.num_int_register_writes 1234411208 # nu
system.cpu.num_load_insts 402515346 # Number of load instructions
system.cpu.num_mem_refs 569365767 # number of memory refs
system.cpu.num_store_insts 166850421 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 49 # Number of system calls
system.cpu.workload.num_syscalls 49 # Number of system calls
---------- End Simulation Statistics ----------

3
tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
View file

@ -51,6 +51,7 @@ assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
@ -86,6 +87,7 @@ assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
@ -121,6 +123,7 @@ assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=10000
max_miss_count=0
mshrs=10

7
tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
View file

@ -5,10 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 7 2011 02:13:30
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Feb 7 2011 02:13:36
M5 executing on burrito
M5 compiled Apr 19 2011 12:19:46
M5 started Apr 19 2011 12:20:53
M5 executing on maize
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

18
tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 594721 # Simulator instruction rate (inst/s)
host_mem_usage 227400 # Number of bytes of host memory used
host_seconds 2504.58 # Real time elapsed on the host
host_tick_rate 824195004 # Simulator tick rate (ticks/s)
host_inst_rate 2608442 # Simulator instruction rate (inst/s)
host_mem_usage 205324 # Number of bytes of host memory used
host_seconds 571.04 # Real time elapsed on the host
host_tick_rate 3614912787 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1489523295 # Number of instructions simulated
sim_seconds 2.064259 # Number of seconds simulated
@ -60,8 +60,8 @@ system.cpu.dcache.demand_mshr_misses 453214 # nu
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.999811 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4095.226955 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.999811 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses 569359660 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 22454.694692 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 19454.694692 # average overall mshr miss latency
@ -115,8 +115,8 @@ system.cpu.icache.demand_mshr_misses 1107 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.442603 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 906.450625 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.442603 # Average percentage of cache occupancy
system.cpu.icache.overall_accesses 1485113012 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 55848.238482 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency
@ -183,10 +183,10 @@ system.cpu.l2cache.demand_mshr_misses 92343 # nu
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.057187 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.483685 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 1873.919591 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 15849.385934 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.057187 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.483685 # Average percentage of cache occupancy
system.cpu.l2cache.overall_accesses 454328 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
@ -228,6 +228,6 @@ system.cpu.num_int_register_writes 1234411207 # nu
system.cpu.num_load_insts 402515346 # Number of load instructions
system.cpu.num_mem_refs 569365767 # number of memory refs
system.cpu.num_store_insts 166850421 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 49 # Number of system calls
system.cpu.workload.num_syscalls 49 # Number of system calls
---------- End Simulation Statistics ----------

2
tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini
View file

@ -25,6 +25,8 @@ BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
RASSize=16
SQEntries=32
SSITSize=1024

6
tests/long/00.gzip/ref/x86/linux/o3-timing/simout
View file

@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Mar 18 2011 20:12:06
M5 started Mar 18 2011 20:12:27
M5 executing on zizzer
M5 compiled Apr 19 2011 12:22:33
M5 started Apr 19 2011 12:31:00
M5 executing on maize
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

330
tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 151077 # Simulator instruction rate (inst/s)
host_mem_usage 216016 # Number of bytes of host memory used
host_seconds 10732.89 # Real time elapsed on the host
host_tick_rate 69979188 # Simulator tick rate (ticks/s)
host_inst_rate 229365 # Simulator instruction rate (inst/s)
host_mem_usage 211952 # Number of bytes of host memory used
host_seconds 7069.49 # Real time elapsed on the host
host_tick_rate 106242349 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1621493982 # Number of instructions simulated
sim_seconds 0.751079 # Number of seconds simulated
@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 8971423 # Nu
system.cpu.BPredUnit.condPredicted 179993455 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 179993455 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 107161579 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 11445860 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 1402522347 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.156127 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.381739 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 522037324 37.22% 37.22% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 531767209 37.92% 75.14% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 125147036 8.92% 84.06% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 139348503 9.94% 93.99% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 42559094 3.03% 97.03% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 23457685 1.67% 98.70% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 5021941 0.36% 99.06% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 1737695 0.12% 99.18% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 11445860 0.82% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 1402522347 # Number of insts commited each cycle
system.cpu.commit.COM:count 1621493982 # Number of instructions committed
system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
system.cpu.commit.COM:int_insts 1621354492 # Number of committed integer instructions.
system.cpu.commit.COM:loads 419042125 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 607228182 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 8971450 # The number of times a branch was mispredicted
system.cpu.commit.branches 107161579 # Number of branches committed
system.cpu.commit.bw_lim_events 11445860 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.commitCommittedInsts 1621493982 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 721713449 # The number of squashed insts skipped by commit
system.cpu.commit.committed_per_cycle::samples 1402522347 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.156127 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.381739 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 522037324 37.22% 37.22% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 531767209 37.92% 75.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 125147036 8.92% 84.06% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 139348503 9.94% 93.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 42559094 3.03% 97.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 23457685 1.67% 98.70% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 5021941 0.36% 99.06% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 1737695 0.12% 99.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 11445860 0.82% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1402522347 # Number of insts commited each cycle
system.cpu.commit.count 1621493982 # Number of instructions committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
system.cpu.commit.int_insts 1621354492 # Number of committed integer instructions.
system.cpu.commit.loads 419042125 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.refs 607228182 # Number of memory references committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.committedInsts 1621493982 # Number of Instructions Simulated
system.cpu.committedInsts_total 1621493982 # Number of Instructions Simulated
system.cpu.cpi 0.926404 # CPI: Cycles Per Instruction
@ -96,8 +96,8 @@ system.cpu.dcache.demand_mshr_misses 465016 # nu
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.999792 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4095.146726 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.999792 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses 513587988 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 18150.803874 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 8690.812783 # average overall mshr miss latency
@ -119,12 +119,12 @@ system.cpu.dcache.tagsinuse 4095.146726 # Cy
system.cpu.dcache.total_refs 512136646 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 317706000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 411408 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 587921420 # Number of cycles decode is blocked
system.cpu.decode.DECODE:DecodedInsts 2472731706 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 429893143 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 331529130 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 99378480 # Number of cycles decode is squashing
system.cpu.decode.DECODE:UnblockCycles 53178654 # Number of cycles decode is unblocking
system.cpu.decode.BlockedCycles 587921420 # Number of cycles decode is blocked
system.cpu.decode.DecodedInsts 2472731706 # Number of instructions handled by decode
system.cpu.decode.IdleCycles 429893143 # Number of cycles decode is idle
system.cpu.decode.RunCycles 331529130 # Number of cycles decode is running
system.cpu.decode.SquashCycles 99378480 # Number of cycles decode is squashing
system.cpu.decode.UnblockCycles 53178654 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 179993455 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 170058043 # Number of cache lines fetched
system.cpu.fetch.Cycles 400227143 # Number of cycles fetch has run and was not squashing or blocked
@ -187,8 +187,8 @@ system.cpu.icache.demand_mshr_misses 869 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.387535 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 793.670730 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.387535 # Average percentage of cache occupancy
system.cpu.icache.overall_accesses 170058043 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 35240.756303 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35321.058688 # average overall mshr miss latency
@ -211,21 +211,13 @@ system.cpu.icache.total_refs 170056853 # To
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 257635 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 111429178 # Number of branches executed
system.cpu.iew.EXEC:nop 0 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.227514 # Inst execution rate
system.cpu.iew.EXEC:refs 636597814 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 191695864 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 2082700302 # num instructions consuming a value
system.cpu.iew.WB:count 1838995466 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.683970 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 1424504384 # num instructions producing a value
system.cpu.iew.WB:rate 1.224235 # insts written-back per cycle
system.cpu.iew.WB:sent 1842743630 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 9107858 # Number of branch mispredicts detected at execute
system.cpu.iew.exec_branches 111429178 # Number of branches executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_rate 1.227514 # Inst execution rate
system.cpu.iew.exec_refs 636597814 # number of memory reference insts executed
system.cpu.iew.exec_stores 191695864 # Number of stores executed
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.iewBlockCycles 1395305 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 615851374 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 81 # Number of dispatched non-speculative instructions
@ -253,103 +245,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 62612798 #
system.cpu.iew.memOrderViolationEvents 6399400 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 4677718 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 4430140 # Number of branches that were predicted taken incorrectly
system.cpu.iew.wb_consumers 2082700302 # num instructions consuming a value
system.cpu.iew.wb_count 1838995466 # cumulative count of insts written-back
system.cpu.iew.wb_fanout 0.683970 # average fanout of values written-back
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_producers 1424504384 # num instructions producing a value
system.cpu.iew.wb_rate 1.224235 # insts written-back per cycle
system.cpu.iew.wb_sent 1842743630 # cumulative count of insts sent to commit
system.cpu.int_regfile_reads 3236941415 # number of integer regfile reads
system.cpu.int_regfile_writes 1831971139 # number of integer regfile writes
system.cpu.ipc 1.079443 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.079443 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 28079218 1.51% 1.51% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1185434411 63.84% 65.35% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 451340139 24.30% 89.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 192134588 10.35% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 1856988356 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 4273878 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.002302 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 161807 3.79% 3.79% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 3493887 81.75% 85.54% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 618184 14.46% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 1501900827 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.236425 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.221094 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 463034659 30.83% 30.83% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 580779168 38.67% 69.50% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 218589752 14.55% 84.05% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 151066938 10.06% 94.11% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 63504112 4.23% 98.34% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 18859628 1.26% 99.60% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 5092601 0.34% 99.94% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 833076 0.06% 99.99% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 140893 0.01% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 1501900827 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.236213 # Inst issue rate
system.cpu.iq.FU_type_0::No_OpClass 28079218 1.51% 1.51% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1185434411 63.84% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 451340139 24.30% 89.65% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 192134588 10.35% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 1856988356 # Type of FU issued
system.cpu.iq.fp_alu_accesses 19 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 35 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 12 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 32 # Number of floating instruction queue writes
system.cpu.iq.fu_busy_cnt 4273878 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.002302 # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 161807 3.79% 3.79% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.79% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 3493887 81.75% 85.54% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 618184 14.46% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.int_alu_accesses 1833182997 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 5220358647 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 1838995454 # Number of integer instruction queue wakeup accesses
@ -361,6 +343,24 @@ system.cpu.iq.iqSquashedInstsExamined 721564206 # Nu
system.cpu.iq.iqSquashedInstsIssued 207265 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 31 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 1518322063 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.issued_per_cycle::samples 1501900827 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.236425 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.221094 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 463034659 30.83% 30.83% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 580779168 38.67% 69.50% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 218589752 14.55% 84.05% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 151066938 10.06% 94.11% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 63504112 4.23% 98.34% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 18859628 1.26% 99.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 5092601 0.34% 99.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 833076 0.06% 99.99% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 140893 0.01% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 1501900827 # Number of insts issued each cycle
system.cpu.iq.rate 1.236213 # Inst issue rate
system.cpu.l2cache.ReadExReq_accesses 250113 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34407.651379 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31155.730459 # average ReadExReq mshr miss latency
@ -405,10 +405,10 @@ system.cpu.l2cache.demand_mshr_misses 91933 # nu
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.058491 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.491164 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 1916.626475 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 16094.448281 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.058491 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.491164 # Average percentage of cache occupancy
system.cpu.l2cache.overall_accesses 465885 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34310.106273 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31101.889419 # average overall mshr miss latency
@ -438,28 +438,28 @@ system.cpu.misc_regfile_reads 931071836 # nu
system.cpu.numCycles 1502158462 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 169288978 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 1617994650 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 298516669 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 493321936 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 107168100 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 70 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 5808956116 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 2397077126 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 2395694665 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 310095488 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 99378480 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 429812969 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 777700015 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 64 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 5808956052 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 2976 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 89 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 706930007 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 89 # count of temporary serializing insts renamed
system.cpu.rename.BlockCycles 169288978 # Number of cycles rename is blocking
system.cpu.rename.CommittedMaps 1617994650 # Number of HB maps that are committed
system.cpu.rename.IQFullEvents 298516669 # Number of times rename has blocked due to IQ full
system.cpu.rename.IdleCycles 493321936 # Number of cycles rename is idle
system.cpu.rename.LSQFullEvents 107168100 # Number of times rename has blocked due to LSQ full
system.cpu.rename.ROBFullEvents 70 # Number of times rename has blocked due to ROB full
system.cpu.rename.RenameLookups 5808956116 # Number of register rename lookups that rename has made
system.cpu.rename.RenamedInsts 2397077126 # Number of instructions processed by rename
system.cpu.rename.RenamedOperands 2395694665 # Number of destination operands rename has renamed
system.cpu.rename.RunCycles 310095488 # Number of cycles rename is running
system.cpu.rename.SquashCycles 99378480 # Number of cycles rename is squashing
system.cpu.rename.UnblockCycles 429812969 # Number of cycles rename is unblocking
system.cpu.rename.UndoneMaps 777700015 # Number of HB maps that are undone due to squashing
system.cpu.rename.fp_rename_lookups 64 # Number of floating rename lookups
system.cpu.rename.int_rename_lookups 5808956052 # Number of integer rename lookups
system.cpu.rename.serializeStallCycles 2976 # count of cycles rename stalled for serializing inst
system.cpu.rename.serializingInsts 89 # count of serializing insts renamed
system.cpu.rename.skidInsts 706930007 # count of insts added to the skid buffer
system.cpu.rename.tempSerializingInsts 89 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 3734283918 # The number of ROB reads
system.cpu.rob.rob_writes 4785794667 # The number of ROB writes
system.cpu.timesIdled 45615 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 48 # Number of system calls
system.cpu.workload.num_syscalls 48 # Number of system calls
---------- End Simulation Statistics ----------

7
tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
View file

@ -5,10 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 8 2011 00:58:32
M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip
M5 started Feb 8 2011 00:58:34
M5 executing on burrito
M5 compiled Apr 19 2011 12:22:33
M5 started Apr 19 2011 12:22:36
M5 executing on maize
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

10
tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 2470310 # Simulator instruction rate (inst/s)
host_mem_usage 224012 # Number of bytes of host memory used
host_seconds 656.39 # Real time elapsed on the host
host_tick_rate 1468620897 # Simulator tick rate (ticks/s)
host_inst_rate 3280168 # Simulator instruction rate (inst/s)
host_mem_usage 202508 # Number of bytes of host memory used
host_seconds 494.33 # Real time elapsed on the host
host_tick_rate 1950088412 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1621493983 # Number of instructions simulated
sim_seconds 0.963993 # Number of seconds simulated
@ -29,6 +29,6 @@ system.cpu.num_int_register_writes 1617994650 # nu
system.cpu.num_load_insts 419042125 # Number of load instructions
system.cpu.num_mem_refs 607228182 # number of memory refs
system.cpu.num_store_insts 188186057 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 48 # Number of system calls
system.cpu.workload.num_syscalls 48 # Number of system calls
---------- End Simulation Statistics ----------

3
tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini
View file

@ -51,6 +51,7 @@ assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
@ -86,6 +87,7 @@ assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
@ -121,6 +123,7 @@ assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=10000
max_miss_count=0
mshrs=10

7
tests/long/00.gzip/ref/x86/linux/simple-timing/simout
View file

@ -5,10 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 8 2011 00:58:32
M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip
M5 started Feb 8 2011 00:58:34
M5 executing on burrito
M5 compiled Apr 19 2011 12:22:33
M5 started Apr 19 2011 12:23:09
M5 executing on maize
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

18
tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1667736 # Simulator instruction rate (inst/s)
host_mem_usage 231728 # Number of bytes of host memory used
host_seconds 972.27 # Real time elapsed on the host
host_tick_rate 1854683738 # Simulator tick rate (ticks/s)
host_inst_rate 2023797 # Simulator instruction rate (inst/s)
host_mem_usage 210248 # Number of bytes of host memory used
host_seconds 801.21 # Real time elapsed on the host
host_tick_rate 2250658484 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1621493983 # Number of instructions simulated
sim_seconds 1.803259 # Number of seconds simulated
@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses 442048 # nu
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.999731 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4094.896939 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.999731 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses 607228182 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 22431.962140 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 19431.962140 # average overall mshr miss latency
@ -105,8 +105,8 @@ system.cpu.icache.demand_mshr_misses 722 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.322357 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 660.186297 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.322357 # Average percentage of cache occupancy
system.cpu.icache.overall_accesses 1186516740 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
@ -173,10 +173,10 @@ system.cpu.l2cache.demand_mshr_misses 89468 # nu
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.057043 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.494010 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 1869.199731 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 16187.723361 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.057043 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.494010 # Average percentage of cache occupancy
system.cpu.l2cache.overall_accesses 442770 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
@ -218,6 +218,6 @@ system.cpu.num_int_register_writes 1617994650 # nu
system.cpu.num_load_insts 419042125 # Number of load instructions
system.cpu.num_mem_refs 607228182 # number of memory refs
system.cpu.num_store_insts 188186057 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 48 # Number of system calls
system.cpu.workload.num_syscalls 48 # Number of system calls
---------- End Simulation Statistics ----------

4
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
View file

@ -50,6 +50,8 @@ BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
RASSize=16
SQEntries=32
SSITSize=1024
@ -483,6 +485,8 @@ BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
RASSize=16
SQEntries=32
SSITSize=1024

6
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
View file

@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Mar 17 2011 22:48:41
M5 started Mar 17 2011 22:50:14
M5 executing on zizzer
M5 compiled Apr 19 2011 12:17:36
M5 started Apr 19 2011 12:17:43
M5 executing on maize
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux

662
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 127019 # Simulator instruction rate (inst/s)
host_mem_usage 296760 # Number of bytes of host memory used
host_seconds 449.39 # Real time elapsed on the host
host_tick_rate 4231820542 # Simulator tick rate (ticks/s)
host_inst_rate 245660 # Simulator instruction rate (inst/s)
host_mem_usage 294304 # Number of bytes of host memory used
host_seconds 232.36 # Real time elapsed on the host
host_tick_rate 8184534150 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 57080594 # Number of instructions simulated
sim_seconds 1.901725 # Number of seconds simulated
@ -16,38 +16,38 @@ system.cpu0.BPredUnit.condIncorrect 455851 # Nu
system.cpu0.BPredUnit.condPredicted 9912652 # Number of conditional branches predicted
system.cpu0.BPredUnit.lookups 11764241 # Number of BP lookups
system.cpu0.BPredUnit.usedRAS 785162 # Number of times the RAS was used to get a target.
system.cpu0.commit.COM:branches 7026012 # Number of branches committed
system.cpu0.commit.COM:bw_lim_events 938799 # number cycles where commit BW limit reached
system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu0.commit.COM:committed_per_cycle::samples 72953049 # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::mean 0.644604 # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::stdev 1.459058 # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::0 53597246 73.47% 73.47% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::1 8417746 11.54% 85.01% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::2 4840163 6.63% 91.64% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::3 2111570 2.89% 94.54% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::4 1587453 2.18% 96.71% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::5 575078 0.79% 97.50% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::6 337488 0.46% 97.96% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::7 547506 0.75% 98.71% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::8 938799 1.29% 100.00% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::total 72953049 # Number of insts commited each cycle
system.cpu0.commit.COM:count 47025846 # Number of instructions committed
system.cpu0.commit.COM:fp_insts 287589 # Number of committed floating point instructions.
system.cpu0.commit.COM:function_calls 606692 # Number of function calls committed.
system.cpu0.commit.COM:int_insts 43528406 # Number of committed integer instructions.
system.cpu0.commit.COM:loads 7569996 # Number of loads committed
system.cpu0.commit.COM:membars 198353 # Number of memory barriers committed
system.cpu0.commit.COM:refs 12959088 # Number of memory references committed
system.cpu0.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu0.commit.branchMispredicts 606344 # The number of times a branch was mispredicted
system.cpu0.commit.branches 7026012 # Number of branches committed
system.cpu0.commit.bw_lim_events 938799 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu0.commit.commitCommittedInsts 47025846 # The number of committed instructions
system.cpu0.commit.commitNonSpecStalls 585526 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.commitSquashedInsts 5969393 # The number of squashed insts skipped by commit
system.cpu0.commit.committed_per_cycle::samples 72953049 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.644604 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.459058 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0 53597246 73.47% 73.47% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 8417746 11.54% 85.01% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 4840163 6.63% 91.64% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 2111570 2.89% 94.54% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 1587453 2.18% 96.71% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 575078 0.79% 97.50% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 337488 0.46% 97.96% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 547506 0.75% 98.71% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 938799 1.29% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total 72953049 # Number of insts commited each cycle
system.cpu0.commit.count 47025846 # Number of instructions committed
system.cpu0.commit.fp_insts 287589 # Number of committed floating point instructions.
system.cpu0.commit.function_calls 606692 # Number of function calls committed.
system.cpu0.commit.int_insts 43528406 # Number of committed integer instructions.
system.cpu0.commit.loads 7569996 # Number of loads committed
system.cpu0.commit.membars 198353 # Number of memory barriers committed
system.cpu0.commit.refs 12959088 # Number of memory references committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu0.committedInsts 44336308 # Number of Instructions Simulated
system.cpu0.committedInsts_total 44336308 # Number of Instructions Simulated
system.cpu0.cpi 2.365714 # CPI: Cycles Per Instruction
@ -161,10 +161,10 @@ system.cpu0.dcache.demand_mshr_misses 1044131 # nu
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.occ_%::0 0.956764 # Average percentage of cache occupancy
system.cpu0.dcache.occ_%::1 -0.001953 # Average percentage of cache occupancy
system.cpu0.dcache.occ_blocks::0 489.863061 # Average occupied blocks per context
system.cpu0.dcache.occ_blocks::1 -1.000000 # Average occupied blocks per context
system.cpu0.dcache.occ_percent::0 0.956764 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::1 -0.001953 # Average percentage of cache occupancy
system.cpu0.dcache.overall_accesses::0 12748257 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 12748257 # number of overall (read+write) accesses
@ -198,15 +198,15 @@ system.cpu0.dcache.tagsinuse 488.863062 # Cy
system.cpu0.dcache.total_refs 10250942 # Total number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.writebacks 532971 # number of writebacks
system.cpu0.decode.DECODE:BlockedCycles 30335443 # Number of cycles decode is blocked
system.cpu0.decode.DECODE:BranchMispred 32433 # Number of times decode detected a branch misprediction
system.cpu0.decode.DECODE:BranchResolved 467445 # Number of times decode resolved a branch
system.cpu0.decode.DECODE:DecodedInsts 58302731 # Number of instructions handled by decode
system.cpu0.decode.DECODE:IdleCycles 31236137 # Number of cycles decode is idle
system.cpu0.decode.DECODE:RunCycles 10506640 # Number of cycles decode is running
system.cpu0.decode.DECODE:SquashCycles 1085015 # Number of cycles decode is squashing
system.cpu0.decode.DECODE:SquashedInsts 96992 # Number of squashed instructions handled by decode
system.cpu0.decode.DECODE:UnblockCycles 874828 # Number of cycles decode is unblocking
system.cpu0.decode.BlockedCycles 30335443 # Number of cycles decode is blocked
system.cpu0.decode.BranchMispred 32433 # Number of times decode detected a branch misprediction
system.cpu0.decode.BranchResolved 467445 # Number of times decode resolved a branch
system.cpu0.decode.DecodedInsts 58302731 # Number of instructions handled by decode
system.cpu0.decode.IdleCycles 31236137 # Number of cycles decode is idle
system.cpu0.decode.RunCycles 10506640 # Number of cycles decode is running
system.cpu0.decode.SquashCycles 1085015 # Number of cycles decode is squashing
system.cpu0.decode.SquashedInsts 96992 # Number of squashed instructions handled by decode
system.cpu0.decode.UnblockCycles 874828 # Number of cycles decode is unblocking
system.cpu0.dtb.data_accesses 755162 # DTB accesses
system.cpu0.dtb.data_acv 768 # DTB access violations
system.cpu0.dtb.data_hits 13777358 # DTB hits
@ -305,8 +305,8 @@ system.cpu0.icache.demand_mshr_misses 839121 # nu
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.occ_%::0 0.995851 # Average percentage of cache occupancy
system.cpu0.icache.occ_blocks::0 509.875783 # Average occupied blocks per context
system.cpu0.icache.occ_percent::0 0.995851 # Average percentage of cache occupancy
system.cpu0.icache.overall_accesses::0 7276849 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 7276849 # number of overall (read+write) accesses
@ -341,21 +341,13 @@ system.cpu0.icache.total_refs 6407354 # To
system.cpu0.icache.warmup_cycle 23816238000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.writebacks 147 # number of writebacks
system.cpu0.idleCycles 30848962 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.iew.EXEC:branches 7463719 # Number of branches executed
system.cpu0.iew.EXEC:nop 2952874 # number of nop insts executed
system.cpu0.iew.EXEC:rate 0.449724 # Inst execution rate
system.cpu0.iew.EXEC:refs 13848442 # number of memory reference insts executed
system.cpu0.iew.EXEC:stores 5542976 # Number of stores executed
system.cpu0.iew.EXEC:swp 0 # number of swp insts executed
system.cpu0.iew.WB:consumers 29600256 # num instructions consuming a value
system.cpu0.iew.WB:count 46794498 # cumulative count of insts written-back
system.cpu0.iew.WB:fanout 0.755402 # average fanout of values written-back
system.cpu0.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu0.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.iew.WB:producers 22360092 # num instructions producing a value
system.cpu0.iew.WB:rate 0.446142 # insts written-back per cycle
system.cpu0.iew.WB:sent 46875004 # cumulative count of insts sent to commit
system.cpu0.iew.branchMispredicts 654991 # Number of branch mispredicts detected at execute
system.cpu0.iew.exec_branches 7463719 # Number of branches executed
system.cpu0.iew.exec_nop 2952874 # number of nop insts executed
system.cpu0.iew.exec_rate 0.449724 # Inst execution rate
system.cpu0.iew.exec_refs 13848442 # number of memory reference insts executed
system.cpu0.iew.exec_stores 5542976 # Number of stores executed
system.cpu0.iew.exec_swp 0 # number of swp insts executed
system.cpu0.iew.iewBlockCycles 7417251 # Number of cycles IEW is blocking
system.cpu0.iew.iewDispLoadInsts 8574378 # Number of dispatched load instructions
system.cpu0.iew.iewDispNonSpecInsts 1551984 # Number of dispatched non-speculative instructions
@ -383,103 +375,93 @@ system.cpu0.iew.lsq.thread.0.squashedStores 318301 #
system.cpu0.iew.memOrderViolationEvents 14768 # Number of memory order violations
system.cpu0.iew.predictedNotTakenIncorrect 331464 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.predictedTakenIncorrect 323527 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.wb_consumers 29600256 # num instructions consuming a value
system.cpu0.iew.wb_count 46794498 # cumulative count of insts written-back
system.cpu0.iew.wb_fanout 0.755402 # average fanout of values written-back
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.iew.wb_producers 22360092 # num instructions producing a value
system.cpu0.iew.wb_rate 0.446142 # insts written-back per cycle
system.cpu0.iew.wb_sent 46875004 # cumulative count of insts sent to commit
system.cpu0.int_regfile_reads 61873527 # number of integer regfile reads
system.cpu0.int_regfile_writes 33807346 # number of integer regfile writes
system.cpu0.ipc 0.422705 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.422705 # IPC: Total IPC of All Threads
system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 3310 0.01% 0.01% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::IntAlu 32518161 68.37% 68.38% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::IntMult 52150 0.11% 68.49% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 68.49% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 15557 0.03% 68.52% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 1653 0.00% 68.52% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::MemRead 8591465 18.06% 86.59% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::MemWrite 5582440 11.74% 98.32% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::IprAccess 797481 1.68% 100.00% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::total 47562217 # Type of FU issued
system.cpu0.iq.ISSUE:fu_busy_cnt 465945 # FU busy when requested
system.cpu0.iq.ISSUE:fu_busy_rate 0.009797 # FU busy rate (busy events/executed inst)
system.cpu0.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::IntAlu 32168 6.90% 6.90% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdAdd 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdAlu 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdCmp 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdCvt 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdMisc 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdMult 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdShift 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::MemRead 239318 51.36% 58.27% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::MemWrite 194459 41.73% 100.00% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.ISSUE:issued_per_cycle::samples 74038064 # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.642402 # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.245120 # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::0 51535584 69.61% 69.61% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::1 10789742 14.57% 84.18% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::2 4855288 6.56% 90.74% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::3 3076859 4.16% 94.89% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::4 2068166 2.79% 97.69% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::5 951116 1.28% 98.97% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::6 576531 0.78% 99.75% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::7 134332 0.18% 99.93% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::8 50446 0.07% 100.00% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::total 74038064 # Number of insts issued each cycle
system.cpu0.iq.ISSUE:rate 0.453461 # Inst issue rate
system.cpu0.iq.FU_type_0::No_OpClass 3310 0.01% 0.01% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 32518161 68.37% 68.38% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 52150 0.11% 68.49% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.49% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 15557 0.03% 68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 1653 0.00% 68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.52% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 8591465 18.06% 86.59% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 5582440 11.74% 98.32% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 797481 1.68% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total 47562217 # Type of FU issued
system.cpu0.iq.fp_alu_accesses 318343 # Number of floating point alu accesses
system.cpu0.iq.fp_inst_queue_reads 608219 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_wakeup_accesses 289004 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_writes 292979 # Number of floating instruction queue writes
system.cpu0.iq.fu_busy_cnt 465945 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.009797 # FU busy rate (busy events/executed inst)
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu 32168 6.90% 6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 6.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 239318 51.36% 58.27% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 194459 41.73% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.int_alu_accesses 47706509 # Number of integer alu accesses
system.cpu0.iq.int_inst_queue_reads 169046393 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_wakeup_accesses 46505494 # Number of integer instruction queue wakeup accesses
@ -491,6 +473,24 @@ system.cpu0.iq.iqSquashedInstsExamined 5493402 # Nu
system.cpu0.iq.iqSquashedInstsIssued 26169 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedNonSpecRemoved 1178887 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.iqSquashedOperandsExamined 2580822 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.issued_per_cycle::samples 74038064 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.642402 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.245120 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0 51535584 69.61% 69.61% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 10789742 14.57% 84.18% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 4855288 6.56% 90.74% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 3076859 4.16% 94.89% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 2068166 2.79% 97.69% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 951116 1.28% 98.97% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 576531 0.78% 99.75% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 134332 0.18% 99.93% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 50446 0.07% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total 74038064 # Number of insts issued each cycle
system.cpu0.iq.rate 0.453461 # Inst issue rate
system.cpu0.itb.data_accesses 0 # DTB accesses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_hits 0 # DTB hits
@ -604,25 +604,25 @@ system.cpu0.misc_regfile_writes 822223 # nu
system.cpu0.numCycles 104887026 # number of cpu cycles simulated
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.rename.RENAME:BlockCycles 10226952 # Number of cycles rename is blocking
system.cpu0.rename.RENAME:CommittedMaps 32010277 # Number of HB maps that are committed
system.cpu0.rename.RENAME:IQFullEvents 742771 # Number of times rename has blocked due to IQ full
system.cpu0.rename.RENAME:IdleCycles 32554760 # Number of cycles rename is idle
system.cpu0.rename.RENAME:LSQFullEvents 1133948 # Number of times rename has blocked due to LSQ full
system.cpu0.rename.RENAME:ROBFullEvents 1272 # Number of times rename has blocked due to ROB full
system.cpu0.rename.RENAME:RenameLookups 67011150 # Number of register rename lookups that rename has made
system.cpu0.rename.RENAME:RenamedInsts 55116446 # Number of instructions processed by rename
system.cpu0.rename.RENAME:RenamedOperands 36911598 # Number of destination operands rename has renamed
system.cpu0.rename.RENAME:RunCycles 10340148 # Number of cycles rename is running
system.cpu0.rename.RENAME:SquashCycles 1085015 # Number of cycles rename is squashing
system.cpu0.rename.RENAME:UnblockCycles 3374476 # Number of cycles rename is unblocking
system.cpu0.rename.RENAME:UndoneMaps 4901321 # Number of HB maps that are undone due to squashing
system.cpu0.rename.RENAME:fp_rename_lookups 420638 # Number of floating rename lookups
system.cpu0.rename.RENAME:int_rename_lookups 66590512 # Number of integer rename lookups
system.cpu0.rename.RENAME:serializeStallCycles 16456711 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RENAME:serializingInsts 1432211 # count of serializing insts renamed
system.cpu0.rename.RENAME:skidInsts 8924178 # count of insts added to the skid buffer
system.cpu0.rename.RENAME:tempSerializingInsts 217463 # count of temporary serializing insts renamed
system.cpu0.rename.BlockCycles 10226952 # Number of cycles rename is blocking
system.cpu0.rename.CommittedMaps 32010277 # Number of HB maps that are committed
system.cpu0.rename.IQFullEvents 742771 # Number of times rename has blocked due to IQ full
system.cpu0.rename.IdleCycles 32554760 # Number of cycles rename is idle
system.cpu0.rename.LSQFullEvents 1133948 # Number of times rename has blocked due to LSQ full
system.cpu0.rename.ROBFullEvents 1272 # Number of times rename has blocked due to ROB full
system.cpu0.rename.RenameLookups 67011150 # Number of register rename lookups that rename has made
system.cpu0.rename.RenamedInsts 55116446 # Number of instructions processed by rename
system.cpu0.rename.RenamedOperands 36911598 # Number of destination operands rename has renamed
system.cpu0.rename.RunCycles 10340148 # Number of cycles rename is running
system.cpu0.rename.SquashCycles 1085015 # Number of cycles rename is squashing
system.cpu0.rename.UnblockCycles 3374476 # Number of cycles rename is unblocking
system.cpu0.rename.UndoneMaps 4901321 # Number of HB maps that are undone due to squashing
system.cpu0.rename.fp_rename_lookups 420638 # Number of floating rename lookups
system.cpu0.rename.int_rename_lookups 66590512 # Number of integer rename lookups
system.cpu0.rename.serializeStallCycles 16456711 # count of cycles rename stalled for serializing inst
system.cpu0.rename.serializingInsts 1432211 # count of serializing insts renamed
system.cpu0.rename.skidInsts 8924178 # count of insts added to the skid buffer
system.cpu0.rename.tempSerializingInsts 217463 # count of temporary serializing insts renamed
system.cpu0.rob.rob_reads 124831913 # The number of ROB reads
system.cpu0.rob.rob_writes 107074537 # The number of ROB writes
system.cpu0.timesIdled 1083848 # Number of times that the entire CPU went into an idle state and unscheduled itself
@ -634,38 +634,38 @@ system.cpu1.BPredUnit.condIncorrect 156935 # Nu
system.cpu1.BPredUnit.condPredicted 2982175 # Number of conditional branches predicted
system.cpu1.BPredUnit.lookups 3622579 # Number of BP lookups
system.cpu1.BPredUnit.usedRAS 265553 # Number of times the RAS was used to get a target.
system.cpu1.commit.COM:branches 2030517 # Number of branches committed
system.cpu1.commit.COM:bw_lim_events 301379 # number cycles where commit BW limit reached
system.cpu1.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu1.commit.COM:committed_per_cycle::samples 21012360 # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::mean 0.640018 # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::stdev 1.474919 # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::0 15563519 74.07% 74.07% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::1 2436778 11.60% 85.67% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::2 1200178 5.71% 91.38% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::3 640529 3.05% 94.43% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::4 421093 2.00% 96.43% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::5 209093 1.00% 97.42% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::6 129842 0.62% 98.04% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::7 109949 0.52% 98.57% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::8 301379 1.43% 100.00% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::total 21012360 # Number of insts commited each cycle
system.cpu1.commit.COM:count 13448285 # Number of instructions committed
system.cpu1.commit.COM:fp_insts 77652 # Number of committed floating point instructions.
system.cpu1.commit.COM:function_calls 196980 # Number of function calls committed.
system.cpu1.commit.COM:int_insts 12472477 # Number of committed integer instructions.
system.cpu1.commit.COM:loads 2329401 # Number of loads committed
system.cpu1.commit.COM:membars 46552 # Number of memory barriers committed
system.cpu1.commit.COM:refs 3759357 # Number of memory references committed
system.cpu1.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu1.commit.branchMispredicts 207236 # The number of times a branch was mispredicted
system.cpu1.commit.branches 2030517 # Number of branches committed
system.cpu1.commit.bw_lim_events 301379 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu1.commit.commitCommittedInsts 13448285 # The number of committed instructions
system.cpu1.commit.commitNonSpecStalls 143621 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.commitSquashedInsts 2329974 # The number of squashed insts skipped by commit
system.cpu1.commit.committed_per_cycle::samples 21012360 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.640018 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.474919 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0 15563519 74.07% 74.07% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 2436778 11.60% 85.67% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 1200178 5.71% 91.38% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 640529 3.05% 94.43% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 421093 2.00% 96.43% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 209093 1.00% 97.42% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 129842 0.62% 98.04% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 109949 0.52% 98.57% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 301379 1.43% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total 21012360 # Number of insts commited each cycle
system.cpu1.commit.count 13448285 # Number of instructions committed
system.cpu1.commit.fp_insts 77652 # Number of committed floating point instructions.
system.cpu1.commit.function_calls 196980 # Number of function calls committed.
system.cpu1.commit.int_insts 12472477 # Number of committed integer instructions.
system.cpu1.commit.loads 2329401 # Number of loads committed
system.cpu1.commit.membars 46552 # Number of memory barriers committed
system.cpu1.commit.refs 3759357 # Number of memory references committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu1.committedInsts 12744286 # Number of Instructions Simulated
system.cpu1.committedInsts_total 12744286 # Number of Instructions Simulated
system.cpu1.cpi 1.922547 # CPI: Cycles Per Instruction
@ -779,8 +779,8 @@ system.cpu1.dcache.demand_mshr_misses 332240 # nu
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.occ_%::0 0.934780 # Average percentage of cache occupancy
system.cpu1.dcache.occ_blocks::0 478.607338 # Average occupied blocks per context
system.cpu1.dcache.occ_percent::0 0.934780 # Average percentage of cache occupancy
system.cpu1.dcache.overall_accesses::0 3867599 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 3867599 # number of overall (read+write) accesses
@ -814,15 +814,15 @@ system.cpu1.dcache.tagsinuse 478.607338 # Cy
system.cpu1.dcache.total_refs 3201172 # Total number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 38945924000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.writebacks 258747 # number of writebacks
system.cpu1.decode.DECODE:BlockedCycles 8810954 # Number of cycles decode is blocked
system.cpu1.decode.DECODE:BranchMispred 10399 # Number of times decode detected a branch misprediction
system.cpu1.decode.DECODE:BranchResolved 165542 # Number of times decode resolved a branch
system.cpu1.decode.DECODE:DecodedInsts 17654641 # Number of instructions handled by decode
system.cpu1.decode.DECODE:IdleCycles 8825966 # Number of cycles decode is idle
system.cpu1.decode.DECODE:RunCycles 3267842 # Number of cycles decode is running
system.cpu1.decode.DECODE:SquashCycles 401676 # Number of cycles decode is squashing
system.cpu1.decode.DECODE:SquashedInsts 25654 # Number of squashed instructions handled by decode
system.cpu1.decode.DECODE:UnblockCycles 107597 # Number of cycles decode is unblocking
system.cpu1.decode.BlockedCycles 8810954 # Number of cycles decode is blocked
system.cpu1.decode.BranchMispred 10399 # Number of times decode detected a branch misprediction
system.cpu1.decode.BranchResolved 165542 # Number of times decode resolved a branch
system.cpu1.decode.DecodedInsts 17654641 # Number of instructions handled by decode
system.cpu1.decode.IdleCycles 8825966 # Number of cycles decode is idle
system.cpu1.decode.RunCycles 3267842 # Number of cycles decode is running
system.cpu1.decode.SquashCycles 401676 # Number of cycles decode is squashing
system.cpu1.decode.SquashedInsts 25654 # Number of squashed instructions handled by decode
system.cpu1.decode.UnblockCycles 107597 # Number of cycles decode is unblocking
system.cpu1.dtb.data_accesses 513633 # DTB accesses
system.cpu1.dtb.data_acv 185 # DTB access violations
system.cpu1.dtb.data_hits 4112878 # DTB hits
@ -921,8 +921,8 @@ system.cpu1.icache.demand_mshr_misses 233675 # nu
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.icache.occ_%::0 0.980042 # Average percentage of cache occupancy
system.cpu1.icache.occ_blocks::0 501.781584 # Average occupied blocks per context
system.cpu1.icache.occ_percent::0 0.980042 # Average percentage of cache occupancy
system.cpu1.icache.overall_accesses::0 2099932 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 2099932 # number of overall (read+write) accesses
@ -957,21 +957,13 @@ system.cpu1.icache.total_refs 1856598 # To
system.cpu1.icache.warmup_cycle 1710247615000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.writebacks 27 # number of writebacks
system.cpu1.idleCycles 3087450 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.iew.EXEC:branches 2215124 # Number of branches executed
system.cpu1.iew.EXEC:nop 807214 # number of nop insts executed
system.cpu1.iew.EXEC:rate 0.568172 # Inst execution rate
system.cpu1.iew.EXEC:refs 4143059 # number of memory reference insts executed
system.cpu1.iew.EXEC:stores 1503378 # Number of stores executed
system.cpu1.iew.EXEC:swp 0 # number of swp insts executed
system.cpu1.iew.WB:consumers 9185033 # num instructions consuming a value
system.cpu1.iew.WB:count 13765716 # cumulative count of insts written-back
system.cpu1.iew.WB:fanout 0.723664 # average fanout of values written-back
system.cpu1.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu1.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.iew.WB:producers 6646874 # num instructions producing a value
system.cpu1.iew.WB:rate 0.561832 # insts written-back per cycle
system.cpu1.iew.WB:sent 13802747 # cumulative count of insts sent to commit
system.cpu1.iew.branchMispredicts 229368 # Number of branch mispredicts detected at execute
system.cpu1.iew.exec_branches 2215124 # Number of branches executed
system.cpu1.iew.exec_nop 807214 # number of nop insts executed
system.cpu1.iew.exec_rate 0.568172 # Inst execution rate
system.cpu1.iew.exec_refs 4143059 # number of memory reference insts executed
system.cpu1.iew.exec_stores 1503378 # Number of stores executed
system.cpu1.iew.exec_swp 0 # number of swp insts executed
system.cpu1.iew.iewBlockCycles 1971298 # Number of cycles IEW is blocking
system.cpu1.iew.iewDispLoadInsts 2745592 # Number of dispatched load instructions
system.cpu1.iew.iewDispNonSpecInsts 455487 # Number of dispatched non-speculative instructions
@ -999,103 +991,93 @@ system.cpu1.iew.lsq.thread.0.squashedStores 148395 #
system.cpu1.iew.memOrderViolationEvents 4299 # Number of memory order violations
system.cpu1.iew.predictedNotTakenIncorrect 105547 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.predictedTakenIncorrect 123821 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.wb_consumers 9185033 # num instructions consuming a value
system.cpu1.iew.wb_count 13765716 # cumulative count of insts written-back
system.cpu1.iew.wb_fanout 0.723664 # average fanout of values written-back
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.iew.wb_producers 6646874 # num instructions producing a value
system.cpu1.iew.wb_rate 0.561832 # insts written-back per cycle
system.cpu1.iew.wb_sent 13802747 # cumulative count of insts sent to commit
system.cpu1.int_regfile_reads 18282773 # number of integer regfile reads
system.cpu1.int_regfile_writes 9947337 # number of integer regfile writes
system.cpu1.ipc 0.520143 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.520143 # IPC: Total IPC of All Threads
system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 3979 0.03% 0.03% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::IntAlu 9510353 67.51% 67.54% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::IntMult 21826 0.15% 67.69% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.69% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 11300 0.08% 67.77% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.77% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.77% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.77% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 1989 0.01% 67.79% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.79% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.79% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.79% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.79% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.79% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.79% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.79% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.79% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.79% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.79% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.79% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.79% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.79% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.79% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.79% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.79% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.79% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 67.79% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.79% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.79% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.79% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::MemRead 2724274 19.34% 87.13% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::MemWrite 1523321 10.81% 97.94% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::IprAccess 290281 2.06% 100.00% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::total 14087323 # Type of FU issued
system.cpu1.iq.ISSUE:fu_busy_cnt 199599 # FU busy when requested
system.cpu1.iq.ISSUE:fu_busy_rate 0.014169 # FU busy rate (busy events/executed inst)
system.cpu1.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::IntAlu 10735 5.38% 5.38% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdAdd 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdAlu 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdCmp 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdCvt 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdMisc 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdMult 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdShift 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::MemRead 110682 55.45% 60.83% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::MemWrite 78182 39.17% 100.00% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.ISSUE:issued_per_cycle::samples 21414036 # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.657855 # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.314285 # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::0 15246065 71.20% 71.20% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::1 2762432 12.90% 84.10% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::2 1149877 5.37% 89.47% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::3 942390 4.40% 93.87% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::4 699267 3.27% 97.13% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::5 379191 1.77% 98.90% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::6 160390 0.75% 99.65% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::7 52788 0.25% 99.90% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::8 21636 0.10% 100.00% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::total 21414036 # Number of insts issued each cycle
system.cpu1.iq.ISSUE:rate 0.574958 # Inst issue rate
system.cpu1.iq.FU_type_0::No_OpClass 3979 0.03% 0.03% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu 9510353 67.51% 67.54% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 21826 0.15% 67.69% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 67.69% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 11300 0.08% 67.77% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 67.77% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 67.77% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 67.77% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 1989 0.01% 67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 2724274 19.34% 87.13% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 1523321 10.81% 97.94% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 290281 2.06% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total 14087323 # Type of FU issued
system.cpu1.iq.fp_alu_accesses 84267 # Number of floating point alu accesses
system.cpu1.iq.fp_inst_queue_reads 163543 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_wakeup_accesses 78913 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_writes 80927 # Number of floating instruction queue writes
system.cpu1.iq.fu_busy_cnt 199599 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.014169 # FU busy rate (busy events/executed inst)
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu 10735 5.38% 5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 5.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 110682 55.45% 60.83% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 78182 39.17% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.int_alu_accesses 14198676 # Number of integer alu accesses
system.cpu1.iq.int_inst_queue_reads 49640351 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_wakeup_accesses 13686803 # Number of integer instruction queue wakeup accesses
@ -1107,6 +1089,24 @@ system.cpu1.iq.iqSquashedInstsExamined 2199611 # Nu
system.cpu1.iq.iqSquashedInstsIssued 15615 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedNonSpecRemoved 360700 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.iqSquashedOperandsExamined 1165068 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.issued_per_cycle::samples 21414036 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.657855 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 1.314285 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0 15246065 71.20% 71.20% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 2762432 12.90% 84.10% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 1149877 5.37% 89.47% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 942390 4.40% 93.87% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 699267 3.27% 97.13% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 379191 1.77% 98.90% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 160390 0.75% 99.65% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 52788 0.25% 99.90% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 21636 0.10% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total 21414036 # Number of insts issued each cycle
system.cpu1.iq.rate 0.574958 # Inst issue rate
system.cpu1.itb.data_accesses 0 # DTB accesses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_hits 0 # DTB hits
@ -1209,25 +1209,25 @@ system.cpu1.misc_regfile_writes 221749 # nu
system.cpu1.numCycles 24501486 # number of cpu cycles simulated
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.rename.RENAME:BlockCycles 2575160 # Number of cycles rename is blocking
system.cpu1.rename.RENAME:CommittedMaps 9194083 # Number of HB maps that are committed
system.cpu1.rename.RENAME:IQFullEvents 253610 # Number of times rename has blocked due to IQ full
system.cpu1.rename.RENAME:IdleCycles 9125188 # Number of cycles rename is idle
system.cpu1.rename.RENAME:LSQFullEvents 96900 # Number of times rename has blocked due to LSQ full
system.cpu1.rename.RENAME:ROBFullEvents 103 # Number of times rename has blocked due to ROB full
system.cpu1.rename.RENAME:RenameLookups 20382349 # Number of register rename lookups that rename has made
system.cpu1.rename.RENAME:RenamedInsts 16583054 # Number of instructions processed by rename
system.cpu1.rename.RENAME:RenamedOperands 11154403 # Number of destination operands rename has renamed
system.cpu1.rename.RENAME:RunCycles 2970670 # Number of cycles rename is running
system.cpu1.rename.RENAME:SquashCycles 401676 # Number of cycles rename is squashing
system.cpu1.rename.RENAME:UnblockCycles 911632 # Number of cycles rename is unblocking
system.cpu1.rename.RENAME:UndoneMaps 1960318 # Number of HB maps that are undone due to squashing
system.cpu1.rename.RENAME:fp_rename_lookups 113596 # Number of floating rename lookups
system.cpu1.rename.RENAME:int_rename_lookups 20268753 # Number of integer rename lookups
system.cpu1.rename.RENAME:serializeStallCycles 5429708 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RENAME:serializingInsts 475094 # count of serializing insts renamed
system.cpu1.rename.RENAME:skidInsts 2839642 # count of insts added to the skid buffer
system.cpu1.rename.RENAME:tempSerializingInsts 40509 # count of temporary serializing insts renamed
system.cpu1.rename.BlockCycles 2575160 # Number of cycles rename is blocking
system.cpu1.rename.CommittedMaps 9194083 # Number of HB maps that are committed
system.cpu1.rename.IQFullEvents 253610 # Number of times rename has blocked due to IQ full
system.cpu1.rename.IdleCycles 9125188 # Number of cycles rename is idle
system.cpu1.rename.LSQFullEvents 96900 # Number of times rename has blocked due to LSQ full
system.cpu1.rename.ROBFullEvents 103 # Number of times rename has blocked due to ROB full
system.cpu1.rename.RenameLookups 20382349 # Number of register rename lookups that rename has made
system.cpu1.rename.RenamedInsts 16583054 # Number of instructions processed by rename
system.cpu1.rename.RenamedOperands 11154403 # Number of destination operands rename has renamed
system.cpu1.rename.RunCycles 2970670 # Number of cycles rename is running
system.cpu1.rename.SquashCycles 401676 # Number of cycles rename is squashing
system.cpu1.rename.UnblockCycles 911632 # Number of cycles rename is unblocking
system.cpu1.rename.UndoneMaps 1960318 # Number of HB maps that are undone due to squashing
system.cpu1.rename.fp_rename_lookups 113596 # Number of floating rename lookups
system.cpu1.rename.int_rename_lookups 20268753 # Number of integer rename lookups
system.cpu1.rename.serializeStallCycles 5429708 # count of cycles rename stalled for serializing inst
system.cpu1.rename.serializingInsts 475094 # count of serializing insts renamed
system.cpu1.rename.skidInsts 2839642 # count of insts added to the skid buffer
system.cpu1.rename.tempSerializingInsts 40509 # count of temporary serializing insts renamed
system.cpu1.rob.rob_reads 36377887 # The number of ROB reads
system.cpu1.rob.rob_writes 31956605 # The number of ROB writes
system.cpu1.timesIdled 286877 # Number of times that the entire CPU went into an idle state and unscheduled itself
@ -1307,8 +1307,8 @@ system.iocache.demand_mshr_misses 41727 # nu
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.occ_%::1 0.012954 # Average percentage of cache occupancy
system.iocache.occ_blocks::1 0.207263 # Average occupied blocks per context
system.iocache.occ_percent::1 0.012954 # Average percentage of cache occupancy
system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
system.iocache.overall_accesses::1 41727 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses
@ -1483,12 +1483,12 @@ system.l2c.demand_mshr_misses 434897 # nu
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.occ_%::0 0.158827 # Average percentage of cache occupancy
system.l2c.occ_%::1 0.036596 # Average percentage of cache occupancy
system.l2c.occ_%::2 0.351892 # Average percentage of cache occupancy
system.l2c.occ_blocks::0 10408.866153 # Average occupied blocks per context
system.l2c.occ_blocks::1 2398.359333 # Average occupied blocks per context
system.l2c.occ_blocks::2 23061.577659 # Average occupied blocks per context
system.l2c.occ_percent::0 0.158827 # Average percentage of cache occupancy
system.l2c.occ_percent::1 0.036596 # Average percentage of cache occupancy
system.l2c.occ_percent::2 0.351892 # Average percentage of cache occupancy
system.l2c.overall_accesses::0 1877438 # number of overall (read+write) accesses
system.l2c.overall_accesses::1 550694 # number of overall (read+write) accesses
system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses

2
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
View file

@ -50,6 +50,8 @@ BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
RASSize=16
SQEntries=32
SSITSize=1024

6
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
View file

@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Mar 17 2011 22:48:41
M5 started Mar 17 2011 22:50:11
M5 executing on zizzer
M5 compiled Apr 19 2011 12:17:36
M5 started Apr 19 2011 12:17:43
M5 executing on maize
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux

336
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 125213 # Simulator instruction rate (inst/s)
host_mem_usage 294244 # Number of bytes of host memory used
host_seconds 424.00 # Real time elapsed on the host
host_tick_rate 4395569700 # Simulator tick rate (ticks/s)
host_inst_rate 247292 # Simulator instruction rate (inst/s)
host_mem_usage 292024 # Number of bytes of host memory used
host_seconds 214.68 # Real time elapsed on the host
host_tick_rate 8681128138 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 53089625 # Number of instructions simulated
sim_seconds 1.863702 # Number of seconds simulated
@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 599479 # Nu
system.cpu.BPredUnit.condPredicted 11925971 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 14248722 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 975192 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 8461745 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 1125976 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 87254730 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 0.645057 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.459520 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 64129239 73.50% 73.50% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 10001511 11.46% 84.96% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 5794569 6.64% 91.60% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 2584226 2.96% 94.56% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 1856466 2.13% 96.69% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 706744 0.81% 97.50% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 418456 0.48% 97.98% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 637543 0.73% 98.71% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 1125976 1.29% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 87254730 # Number of insts commited each cycle
system.cpu.commit.COM:count 56284256 # Number of instructions committed
system.cpu.commit.COM:fp_insts 324451 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 744594 # Number of function calls committed.
system.cpu.commit.COM:int_insts 52122555 # Number of committed integer instructions.
system.cpu.commit.COM:loads 9113387 # Number of loads committed
system.cpu.commit.COM:membars 227959 # Number of memory barriers committed
system.cpu.commit.COM:refs 15505823 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 769874 # The number of times a branch was mispredicted
system.cpu.commit.branches 8461745 # Number of branches committed
system.cpu.commit.bw_lim_events 1125976 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.commitCommittedInsts 56284256 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 667734 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 8032073 # The number of squashed insts skipped by commit
system.cpu.commit.committed_per_cycle::samples 87254730 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.645057 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.459520 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 64129239 73.50% 73.50% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 10001511 11.46% 84.96% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 5794569 6.64% 91.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 2584226 2.96% 94.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 1856466 2.13% 96.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 706744 0.81% 97.50% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 418456 0.48% 97.98% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 637543 0.73% 98.71% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 1125976 1.29% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 87254730 # Number of insts commited each cycle
system.cpu.commit.count 56284256 # Number of instructions committed
system.cpu.commit.fp_insts 324451 # Number of committed floating point instructions.
system.cpu.commit.function_calls 744594 # Number of function calls committed.
system.cpu.commit.int_insts 52122555 # Number of committed integer instructions.
system.cpu.commit.loads 9113387 # Number of loads committed
system.cpu.commit.membars 227959 # Number of memory barriers committed
system.cpu.commit.refs 15505823 # Number of memory references committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.committedInsts 53089625 # Number of Instructions Simulated
system.cpu.committedInsts_total 53089625 # Number of Instructions Simulated
system.cpu.cpi 2.304358 # CPI: Cycles Per Instruction
@ -161,8 +161,8 @@ system.cpu.dcache.demand_mshr_misses 1384507 # nu
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.999992 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 511.995879 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.999992 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses::0 15419136 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 15419136 # number of overall (read+write) accesses
@ -196,15 +196,15 @@ system.cpu.dcache.tagsinuse 511.995879 # Cy
system.cpu.dcache.total_refs 12121656 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 19670000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 833416 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 36259760 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 44553 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 598925 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 70789187 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 37160222 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 12840041 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 1435065 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 134914 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 994706 # Number of cycles decode is unblocking
system.cpu.decode.BlockedCycles 36259760 # Number of cycles decode is blocked
system.cpu.decode.BranchMispred 44553 # Number of times decode detected a branch misprediction
system.cpu.decode.BranchResolved 598925 # Number of times decode resolved a branch
system.cpu.decode.DecodedInsts 70789187 # Number of instructions handled by decode
system.cpu.decode.IdleCycles 37160222 # Number of cycles decode is idle
system.cpu.decode.RunCycles 12840041 # Number of cycles decode is running
system.cpu.decode.SquashCycles 1435065 # Number of cycles decode is squashing
system.cpu.decode.SquashedInsts 134914 # Number of squashed instructions handled by decode
system.cpu.decode.UnblockCycles 994706 # Number of cycles decode is unblocking
system.cpu.dtb.data_accesses 1263492 # DTB accesses
system.cpu.dtb.data_acv 894 # DTB access violations
system.cpu.dtb.data_hits 16635681 # DTB hits
@ -303,8 +303,8 @@ system.cpu.icache.demand_mshr_misses 993440 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.995757 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 509.827441 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.995757 # Average percentage of cache occupancy
system.cpu.icache.overall_accesses::0 8770990 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 8770990 # number of overall (read+write) accesses
@ -339,21 +339,13 @@ system.cpu.icache.total_refs 7733869 # To
system.cpu.icache.warmup_cycle 23815676000 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 201 # number of writebacks
system.cpu.idleCycles 33647698 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 9077931 # Number of branches executed
system.cpu.iew.EXEC:nop 3561617 # number of nop insts executed
system.cpu.iew.EXEC:rate 0.466022 # Inst execution rate
system.cpu.iew.EXEC:refs 16730349 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 6619936 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 36206464 # num instructions consuming a value
system.cpu.iew.WB:count 56518708 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.749991 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 27154531 # num instructions producing a value
system.cpu.iew.WB:rate 0.461990 # insts written-back per cycle
system.cpu.iew.WB:sent 56632372 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 834392 # Number of branch mispredicts detected at execute
system.cpu.iew.exec_branches 9077931 # Number of branches executed
system.cpu.iew.exec_nop 3561617 # number of nop insts executed
system.cpu.iew.exec_rate 0.466022 # Inst execution rate
system.cpu.iew.exec_refs 16730349 # number of memory reference insts executed
system.cpu.iew.exec_stores 6619936 # Number of stores executed
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.iewBlockCycles 9479709 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 10494692 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 1785178 # Number of dispatched non-speculative instructions
@ -381,103 +373,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 456751 #
system.cpu.iew.memOrderViolationEvents 18985 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 404859 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 429533 # Number of branches that were predicted taken incorrectly
system.cpu.iew.wb_consumers 36206464 # num instructions consuming a value
system.cpu.iew.wb_count 56518708 # cumulative count of insts written-back
system.cpu.iew.wb_fanout 0.749991 # average fanout of values written-back
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_producers 27154531 # num instructions producing a value
system.cpu.iew.wb_rate 0.461990 # insts written-back per cycle
system.cpu.iew.wb_sent 56632372 # cumulative count of insts sent to commit
system.cpu.int_regfile_reads 74751539 # number of integer regfile reads
system.cpu.int_regfile_writes 40782350 # number of integer regfile writes
system.cpu.ipc 0.433960 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.433960 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 39349401 68.40% 68.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 62002 0.11% 68.52% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 68.52% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 25611 0.04% 68.56% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 68.56% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 68.56% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 68.56% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 3636 0.01% 68.57% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 68.57% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 68.57% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 68.57% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 68.57% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 68.57% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 68.57% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 68.57% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 68.57% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 68.57% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 68.57% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 68.57% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 68.57% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 68.57% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 68.57% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 68.57% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 68.57% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 68.57% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 68.57% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 68.57% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 68.57% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 68.57% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 10457735 18.18% 86.75% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 6670425 11.59% 98.34% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 952735 1.66% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 57528826 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 549270 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.009548 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 45293 8.25% 8.25% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 2 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 291133 53.00% 61.25% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 212842 38.75% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 88689795 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.648652 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.255048 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 61727681 69.60% 69.60% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 12782826 14.41% 84.01% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 5739308 6.47% 90.48% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 3779668 4.26% 94.75% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 2566031 2.89% 97.64% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 1197199 1.35% 98.99% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 667320 0.75% 99.74% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 163755 0.18% 99.93% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 66007 0.07% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 88689795 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 0.470247 # Inst issue rate
system.cpu.iq.FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 39349401 68.40% 68.41% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 62002 0.11% 68.52% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 25611 0.04% 68.56% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.56% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.56% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.56% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.57% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.57% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 10457735 18.18% 86.75% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 6670425 11.59% 98.34% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 952735 1.66% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 57528826 # Type of FU issued
system.cpu.iq.fp_alu_accesses 358048 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 686320 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 327228 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 333627 # Number of floating instruction queue writes
system.cpu.iq.fu_busy_cnt 549270 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.009548 # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 45293 8.25% 8.25% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 2 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.25% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 291133 53.00% 61.25% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 212842 38.75% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.int_alu_accesses 57712767 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 203646640 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 56191480 # Number of integer instruction queue wakeup accesses
@ -489,6 +471,24 @@ system.cpu.iq.iqSquashedInstsExamined 7361535 # Nu
system.cpu.iq.iqSquashedInstsIssued 36245 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 1361667 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 3591759 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.issued_per_cycle::samples 88689795 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.648652 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.255048 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 61727681 69.60% 69.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 12782826 14.41% 84.01% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 5739308 6.47% 90.48% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 3779668 4.26% 94.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 2566031 2.89% 97.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 1197199 1.35% 98.99% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 667320 0.75% 99.74% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 163755 0.18% 99.93% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 66007 0.07% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 88689795 # Number of insts issued each cycle
system.cpu.iq.rate 0.470247 # Inst issue rate
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
@ -598,25 +598,25 @@ system.cpu.misc_regfile_writes 949727 # nu
system.cpu.numCycles 122337493 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 12932543 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 38258765 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 1039474 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 38708983 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 1241691 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 1519 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 81518808 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 66985432 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 44869849 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 12449033 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 1435065 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 4145083 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 6611082 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 474213 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 81044595 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 19019086 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 1691185 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 11218533 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 244825 # count of temporary serializing insts renamed
system.cpu.rename.BlockCycles 12932543 # Number of cycles rename is blocking
system.cpu.rename.CommittedMaps 38258765 # Number of HB maps that are committed
system.cpu.rename.IQFullEvents 1039474 # Number of times rename has blocked due to IQ full
system.cpu.rename.IdleCycles 38708983 # Number of cycles rename is idle
system.cpu.rename.LSQFullEvents 1241691 # Number of times rename has blocked due to LSQ full
system.cpu.rename.ROBFullEvents 1519 # Number of times rename has blocked due to ROB full
system.cpu.rename.RenameLookups 81518808 # Number of register rename lookups that rename has made
system.cpu.rename.RenamedInsts 66985432 # Number of instructions processed by rename
system.cpu.rename.RenamedOperands 44869849 # Number of destination operands rename has renamed
system.cpu.rename.RunCycles 12449033 # Number of cycles rename is running
system.cpu.rename.SquashCycles 1435065 # Number of cycles rename is squashing
system.cpu.rename.UnblockCycles 4145083 # Number of cycles rename is unblocking
system.cpu.rename.UndoneMaps 6611082 # Number of HB maps that are undone due to squashing
system.cpu.rename.fp_rename_lookups 474213 # Number of floating rename lookups
system.cpu.rename.int_rename_lookups 81044595 # Number of integer rename lookups
system.cpu.rename.serializeStallCycles 19019086 # count of cycles rename stalled for serializing inst
system.cpu.rename.serializingInsts 1691185 # count of serializing insts renamed
system.cpu.rename.skidInsts 11218533 # count of insts added to the skid buffer
system.cpu.rename.tempSerializingInsts 244825 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 150193940 # The number of ROB reads
system.cpu.rob.rob_writes 130068170 # The number of ROB writes
system.cpu.timesIdled 1318957 # Number of times that the entire CPU went into an idle state and unscheduled itself
@ -696,8 +696,8 @@ system.iocache.demand_mshr_misses 41725 # nu
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.occ_%::1 0.080564 # Average percentage of cache occupancy
system.iocache.occ_blocks::1 1.289021 # Average occupied blocks per context
system.iocache.occ_percent::1 0.080564 # Average percentage of cache occupancy
system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
@ -838,10 +838,10 @@ system.l2c.demand_mshr_misses 424680 # nu
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.occ_%::0 0.185866 # Average percentage of cache occupancy
system.l2c.occ_%::1 0.343812 # Average percentage of cache occupancy
system.l2c.occ_blocks::0 12180.929780 # Average occupied blocks per context
system.l2c.occ_blocks::1 22532.084945 # Average occupied blocks per context
system.l2c.occ_percent::0 0.185866 # Average percentage of cache occupancy
system.l2c.occ_percent::1 0.343812 # Average percentage of cache occupancy
system.l2c.overall_accesses::0 2395045 # number of overall (read+write) accesses
system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2395045 # number of overall (read+write) accesses

4
tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini
View file

@ -11,7 +11,7 @@ children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview t
boot_cpu_frequency=500
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- root=/dev/mtdblock0
init_param=0
kernel=/chips/pd/randd/dist/binaries/vmlinux.arm
kernel=/dist/m5/system/binaries/vmlinux.arm
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
@ -495,7 +495,7 @@ type=ExeTracer
[system.diskmem]
type=PhysicalMemory
file=/chips/pd/randd/dist/disks/ael-arm.ext2
file=/dist/m5/system/disks/ael-arm.ext2
latency=30000
latency_var=0
null=false

10
tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 4 2011 11:17:23
M5 started Apr 4 2011 11:17:27
M5 executing on u200439-lin.austin.arm.com
command line: build/ARM_FS/m5.opt -d build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3
M5 compiled Apr 19 2011 13:41:05
M5 started Apr 19 2011 13:41:08
M5 executing on maize
command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 82662490500 because m5_exit instruction encountered

334
tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 92348 # Simulator instruction rate (inst/s)
host_mem_usage 389996 # Number of bytes of host memory used
host_seconds 562.86 # Real time elapsed on the host
host_tick_rate 146862568 # Simulator tick rate (ticks/s)
host_inst_rate 182620 # Simulator instruction rate (inst/s)
host_mem_usage 341656 # Number of bytes of host memory used
host_seconds 284.63 # Real time elapsed on the host
host_tick_rate 290422658 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 51978682 # Number of instructions simulated
sim_seconds 0.082662 # Number of seconds simulated
@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 665245 # Nu
system.cpu.BPredUnit.condPredicted 11246732 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 13229511 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 787550 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 8445621 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 801383 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 93507712 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 0.557193 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.351787 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 71892468 76.88% 76.88% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 10568988 11.30% 88.19% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 3427833 3.67% 91.85% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 1711600 1.83% 93.68% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 3527395 3.77% 97.46% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 741726 0.79% 98.25% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 541099 0.58% 98.83% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 295220 0.32% 99.14% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 801383 0.86% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 93507712 # Number of insts commited each cycle
system.cpu.commit.COM:count 52101862 # Number of instructions committed
system.cpu.commit.COM:fp_insts 6017 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 529734 # Number of function calls committed.
system.cpu.commit.COM:int_insts 42509491 # Number of committed integer instructions.
system.cpu.commit.COM:loads 9207015 # Number of loads committed
system.cpu.commit.COM:membars 3 # Number of memory barriers committed
system.cpu.commit.COM:refs 16293738 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 641726 # The number of times a branch was mispredicted
system.cpu.commit.branches 8445621 # Number of branches committed
system.cpu.commit.bw_lim_events 801383 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.commitCommittedInsts 52101862 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 2963383 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 16147201 # The number of squashed insts skipped by commit
system.cpu.commit.committed_per_cycle::samples 93507712 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.557193 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.351787 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 71892468 76.88% 76.88% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 10568988 11.30% 88.19% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 3427833 3.67% 91.85% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 1711600 1.83% 93.68% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 3527395 3.77% 97.46% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 741726 0.79% 98.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 541099 0.58% 98.83% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 295220 0.32% 99.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 801383 0.86% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 93507712 # Number of insts commited each cycle
system.cpu.commit.count 52101862 # Number of instructions committed
system.cpu.commit.fp_insts 6017 # Number of committed floating point instructions.
system.cpu.commit.function_calls 529734 # Number of function calls committed.
system.cpu.commit.int_insts 42509491 # Number of committed integer instructions.
system.cpu.commit.loads 9207015 # Number of loads committed
system.cpu.commit.membars 3 # Number of memory barriers committed
system.cpu.commit.refs 16293738 # Number of memory references committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.committedInsts 51978682 # Number of Instructions Simulated
system.cpu.committedInsts_total 51978682 # Number of Instructions Simulated
system.cpu.cpi 3.180631 # CPI: Cycles Per Instruction
@ -148,8 +148,8 @@ system.cpu.dcache.demand_mshr_misses 419458 # nu
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.999513 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 511.750765 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.999513 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses::0 16095916 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 16095916 # number of overall (read+write) accesses
@ -183,15 +183,15 @@ system.cpu.dcache.tagsinuse 511.750765 # Cy
system.cpu.dcache.total_refs 13775411 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 48224000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 391506 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 53936622 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 70601 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 1224137 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 76419738 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 23948605 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 14435253 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 2568567 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 235986 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 1187204 # Number of cycles decode is unblocking
system.cpu.decode.BlockedCycles 53936622 # Number of cycles decode is blocked
system.cpu.decode.BranchMispred 70601 # Number of times decode detected a branch misprediction
system.cpu.decode.BranchResolved 1224137 # Number of times decode resolved a branch
system.cpu.decode.DecodedInsts 76419738 # Number of instructions handled by decode
system.cpu.decode.IdleCycles 23948605 # Number of cycles decode is idle
system.cpu.decode.RunCycles 14435253 # Number of cycles decode is running
system.cpu.decode.SquashCycles 2568567 # Number of cycles decode is squashing
system.cpu.decode.SquashedInsts 235986 # Number of squashed instructions handled by decode
system.cpu.decode.UnblockCycles 1187204 # Number of cycles decode is unblocking
system.cpu.dtb.accesses 35246983 # DTB accesses
system.cpu.dtb.align_faults 1461 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
@ -299,8 +299,8 @@ system.cpu.icache.demand_mshr_misses 502982 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.970025 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 496.652768 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.970025 # Average percentage of cache occupancy
system.cpu.icache.overall_accesses::0 6553557 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 6553557 # number of overall (read+write) accesses
@ -335,21 +335,13 @@ system.cpu.icache.total_refs 6005950 # To
system.cpu.icache.warmup_cycle 6210686000 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 41369 # number of writebacks
system.cpu.idleCycles 69248731 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 10230019 # Number of branches executed
system.cpu.iew.EXEC:nop 166886 # number of nop insts executed
system.cpu.iew.EXEC:rate 0.475904 # Inst execution rate
system.cpu.iew.EXEC:refs 35985354 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 7801149 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 62345618 # num instructions consuming a value
system.cpu.iew.WB:count 60884415 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.509768 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 31781773 # num instructions producing a value
system.cpu.iew.WB:rate 0.368271 # insts written-back per cycle
system.cpu.iew.WB:sent 78152559 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 711242 # Number of branch mispredicts detected at execute
system.cpu.iew.exec_branches 10230019 # Number of branches executed
system.cpu.iew.exec_nop 166886 # number of nop insts executed
system.cpu.iew.exec_rate 0.475904 # Inst execution rate
system.cpu.iew.exec_refs 35985354 # number of memory reference insts executed
system.cpu.iew.exec_stores 7801149 # Number of stores executed
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.iewBlockCycles 21406073 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 12848037 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 4002488 # Number of dispatched non-speculative instructions
@ -377,103 +369,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 1649637 #
system.cpu.iew.memOrderViolationEvents 280540 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 186102 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 525140 # Number of branches that were predicted taken incorrectly
system.cpu.iew.wb_consumers 62345618 # num instructions consuming a value
system.cpu.iew.wb_count 60884415 # cumulative count of insts written-back
system.cpu.iew.wb_fanout 0.509768 # average fanout of values written-back
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_producers 31781773 # num instructions producing a value
system.cpu.iew.wb_rate 0.368271 # insts written-back per cycle
system.cpu.iew.wb_sent 78152559 # cumulative count of insts sent to commit
system.cpu.int_regfile_reads 182840055 # number of integer regfile reads
system.cpu.int_regfile_writes 43911822 # number of integer regfile writes
system.cpu.ipc 0.314403 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.314403 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2393207 3.00% 3.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 40767716 51.13% 54.13% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 71906 0.09% 54.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 10 0.00% 54.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 6 0.00% 54.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 895 0.00% 54.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 6 0.00% 54.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 28538408 35.79% 90.01% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 7966700 9.99% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 79738854 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 4821847 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.060470 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 5252 0.11% 0.11% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 1 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 4503965 93.41% 93.52% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 312629 6.48% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 96076251 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.829954 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.379344 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 59918658 62.37% 62.37% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 16598524 17.28% 79.64% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 7253913 7.55% 87.19% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 4126106 4.29% 91.49% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 5947858 6.19% 97.68% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 1304063 1.36% 99.04% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 619735 0.65% 99.68% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 235123 0.24% 99.92% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 72271 0.08% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 96076251 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 0.482316 # Inst issue rate
system.cpu.iq.FU_type_0::No_OpClass 2393207 3.00% 3.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 40767716 51.13% 54.13% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 71906 0.09% 54.22% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 10 0.00% 54.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 6 0.00% 54.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 895 0.00% 54.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 54.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.22% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 28538408 35.79% 90.01% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 7966700 9.99% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 79738854 # Type of FU issued
system.cpu.iq.fp_alu_accesses 8555 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 16356 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 6330 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 9324 # Number of floating instruction queue writes
system.cpu.iq.fu_busy_cnt 4821847 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.060470 # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 5252 0.11% 0.11% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 1 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 4503965 93.41% 93.52% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 312629 6.48% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.int_alu_accesses 82158939 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 260560114 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 60878085 # Number of integer instruction queue wakeup accesses
@ -485,6 +467,24 @@ system.cpu.iq.iqSquashedInstsExamined 17660461 # Nu
system.cpu.iq.iqSquashedInstsIssued 127886 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 1069030 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 22275203 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.issued_per_cycle::samples 96076251 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.829954 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.379344 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 59918658 62.37% 62.37% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 16598524 17.28% 79.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 7253913 7.55% 87.19% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 4126106 4.29% 91.49% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 5947858 6.19% 97.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 1304063 1.36% 99.04% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 619735 0.65% 99.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 235123 0.24% 99.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 72271 0.08% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 96076251 # Number of insts issued each cycle
system.cpu.iq.rate 0.482316 # Inst issue rate
system.cpu.itb.accesses 6566505 # DTB accesses
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
@ -517,25 +517,25 @@ system.cpu.misc_regfile_writes 505947 # nu
system.cpu.numCycles 165324982 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 33112132 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 36741742 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 775024 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 25585942 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 2464411 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 439406 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 190546426 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 73652077 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 53332963 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 13017560 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 2568567 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 5444932 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 16591220 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 49319 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 190497107 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 16347118 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 812559 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 14268469 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 662925 # count of temporary serializing insts renamed
system.cpu.rename.BlockCycles 33112132 # Number of cycles rename is blocking
system.cpu.rename.CommittedMaps 36741742 # Number of HB maps that are committed
system.cpu.rename.IQFullEvents 775024 # Number of times rename has blocked due to IQ full
system.cpu.rename.IdleCycles 25585942 # Number of cycles rename is idle
system.cpu.rename.LSQFullEvents 2464411 # Number of times rename has blocked due to LSQ full
system.cpu.rename.ROBFullEvents 439406 # Number of times rename has blocked due to ROB full
system.cpu.rename.RenameLookups 190546426 # Number of register rename lookups that rename has made
system.cpu.rename.RenamedInsts 73652077 # Number of instructions processed by rename
system.cpu.rename.RenamedOperands 53332963 # Number of destination operands rename has renamed
system.cpu.rename.RunCycles 13017560 # Number of cycles rename is running
system.cpu.rename.SquashCycles 2568567 # Number of cycles rename is squashing
system.cpu.rename.UnblockCycles 5444932 # Number of cycles rename is unblocking
system.cpu.rename.UndoneMaps 16591220 # Number of HB maps that are undone due to squashing
system.cpu.rename.fp_rename_lookups 49319 # Number of floating rename lookups
system.cpu.rename.int_rename_lookups 190497107 # Number of integer rename lookups
system.cpu.rename.serializeStallCycles 16347118 # count of cycles rename stalled for serializing inst
system.cpu.rename.serializingInsts 812559 # count of serializing insts renamed
system.cpu.rename.skidInsts 14268469 # count of insts added to the skid buffer
system.cpu.rename.tempSerializingInsts 662925 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 160015001 # The number of ROB reads
system.cpu.rob.rob_writes 139111158 # The number of ROB writes
system.cpu.timesIdled 1092841 # Number of times that the entire CPU went into an idle state and unscheduled itself
@ -705,10 +705,10 @@ system.l2c.demand_mshr_misses 128445 # nu
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.occ_%::0 0.099470 # Average percentage of cache occupancy
system.l2c.occ_%::1 0.481649 # Average percentage of cache occupancy
system.l2c.occ_blocks::0 6518.840874 # Average occupied blocks per context
system.l2c.occ_blocks::1 31565.358061 # Average occupied blocks per context
system.l2c.occ_percent::0 0.099470 # Average percentage of cache occupancy
system.l2c.occ_percent::1 0.481649 # Average percentage of cache occupancy
system.l2c.overall_accesses::0 923785 # number of overall (read+write) accesses
system.l2c.overall_accesses::1 102462 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 1026247 # number of overall (read+write) accesses

2
tests/long/10.linux-boot/ref/arm/linux/realview-o3/status
View file

@ -1 +1 @@
build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 FAILED!
build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 FAILED!

4
tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini
View file

@ -498,9 +498,9 @@ egid=100
env=
errout=cerr
euid=100
executable=/arm/scratch/alisai01/dist/cpu2000/binaries/arm/linux/mcf
executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
gid=100
input=/arm/scratch/alisai01/dist/cpu2000/data/mcf/smred/input/mcf.in
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100

8
tests/long/10.mcf/ref/arm/linux/o3-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Mar 30 2011 17:47:57
M5 started Mar 30 2011 17:54:33
M5 executing on u200439-lin.austin.arm.com
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing
M5 compiled Apr 19 2011 12:47:10
M5 started Apr 19 2011 12:49:23
M5 executing on maize
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

336
tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 190258 # Simulator instruction rate (inst/s)
host_mem_usage 391364 # Number of bytes of host memory used
host_seconds 479.61 # Real time elapsed on the host
host_tick_rate 93397782 # Simulator tick rate (ticks/s)
host_inst_rate 230945 # Simulator instruction rate (inst/s)
host_mem_usage 347768 # Number of bytes of host memory used
host_seconds 395.11 # Real time elapsed on the host
host_tick_rate 113371387 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 91249905 # Number of instructions simulated
sim_seconds 0.044795 # Number of seconds simulated
@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 1596208 # Nu
system.cpu.BPredUnit.condPredicted 23792873 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 29586235 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 63032 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 18722470 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 671558 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 84101876 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.085142 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.487392 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 39810013 47.34% 47.34% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 21942954 26.09% 73.43% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 9544341 11.35% 84.77% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 7643789 9.09% 93.86% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 2702545 3.21% 97.08% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 240327 0.29% 97.36% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 909211 1.08% 98.44% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 637138 0.76% 99.20% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 671558 0.80% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 84101876 # Number of insts commited each cycle
system.cpu.commit.COM:count 91262514 # Number of instructions committed
system.cpu.commit.COM:fp_insts 48 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 56148 # Number of function calls committed.
system.cpu.commit.COM:int_insts 72533318 # Number of committed integer instructions.
system.cpu.commit.COM:loads 22575876 # Number of loads committed
system.cpu.commit.COM:membars 3888 # Number of memory barriers committed
system.cpu.commit.COM:refs 27322629 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 1599456 # The number of times a branch was mispredicted
system.cpu.commit.branches 18722470 # Number of branches committed
system.cpu.commit.bw_lim_events 671558 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.commitCommittedInsts 91262514 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 554406 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 37771309 # The number of squashed insts skipped by commit
system.cpu.commit.committed_per_cycle::samples 84101876 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.085142 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.487392 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 39810013 47.34% 47.34% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 21942954 26.09% 73.43% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 9544341 11.35% 84.77% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 7643789 9.09% 93.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 2702545 3.21% 97.08% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 240327 0.29% 97.36% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 909211 1.08% 98.44% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 637138 0.76% 99.20% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 671558 0.80% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 84101876 # Number of insts commited each cycle
system.cpu.commit.count 91262514 # Number of instructions committed
system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
system.cpu.commit.function_calls 56148 # Number of function calls committed.
system.cpu.commit.int_insts 72533318 # Number of committed integer instructions.
system.cpu.commit.loads 22575876 # Number of loads committed
system.cpu.commit.membars 3888 # Number of memory barriers committed
system.cpu.commit.refs 27322629 # Number of memory references committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.committedInsts 91249905 # Number of Instructions Simulated
system.cpu.committedInsts_total 91249905 # Number of Instructions Simulated
system.cpu.cpi 0.981803 # CPI: Cycles Per Instruction
@ -105,8 +105,8 @@ system.cpu.dcache.demand_mshr_misses 950233 # nu
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.852828 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 3493.184851 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.852828 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses 29231190 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 8180.869220 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 3273.127173 # average overall mshr miss latency
@ -128,15 +128,15 @@ system.cpu.dcache.tagsinuse 3493.184851 # Cy
system.cpu.dcache.total_refs 28069666 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 18896443000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 943153 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 17588781 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 9537 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 4762375 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 139874563 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 32956661 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 32742845 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 5457924 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 30438 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 813588 # Number of cycles decode is unblocking
system.cpu.decode.BlockedCycles 17588781 # Number of cycles decode is blocked
system.cpu.decode.BranchMispred 9537 # Number of times decode detected a branch misprediction
system.cpu.decode.BranchResolved 4762375 # Number of times decode resolved a branch
system.cpu.decode.DecodedInsts 139874563 # Number of instructions handled by decode
system.cpu.decode.IdleCycles 32956661 # Number of cycles decode is idle
system.cpu.decode.RunCycles 32742845 # Number of cycles decode is running
system.cpu.decode.SquashCycles 5457924 # Number of cycles decode is squashing
system.cpu.decode.SquashedInsts 30438 # Number of squashed instructions handled by decode
system.cpu.decode.UnblockCycles 813588 # Number of cycles decode is unblocking
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
@ -221,8 +221,8 @@ system.cpu.icache.demand_mshr_misses 674 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.277518 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 568.356083 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.277518 # Average percentage of cache occupancy
system.cpu.icache.overall_accesses 15336543 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 35886.138614 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 34397.626113 # average overall mshr miss latency
@ -245,21 +245,13 @@ system.cpu.icache.total_refs 15335735 # To
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 29674 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 20951910 # Number of branches executed
system.cpu.iew.EXEC:nop 39919 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.157669 # Inst execution rate
system.cpu.iew.EXEC:refs 30258239 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 5196792 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 127150055 # num instructions consuming a value
system.cpu.iew.WB:count 102173263 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.489247 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 62207806 # num instructions producing a value
system.cpu.iew.WB:rate 1.140461 # insts written-back per cycle
system.cpu.iew.WB:sent 102563540 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 1809783 # Number of branch mispredicts detected at execute
system.cpu.iew.exec_branches 20951910 # Number of branches executed
system.cpu.iew.exec_nop 39919 # number of nop insts executed
system.cpu.iew.exec_rate 1.157669 # Inst execution rate
system.cpu.iew.exec_refs 30258239 # number of memory reference insts executed
system.cpu.iew.exec_stores 5196792 # Number of stores executed
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.iewBlockCycles 316819 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 31496278 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 689079 # Number of dispatched non-speculative instructions
@ -287,103 +279,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 1867594 #
system.cpu.iew.memOrderViolationEvents 14224 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 282853 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 1526930 # Number of branches that were predicted taken incorrectly
system.cpu.iew.wb_consumers 127150055 # num instructions consuming a value
system.cpu.iew.wb_count 102173263 # cumulative count of insts written-back
system.cpu.iew.wb_fanout 0.489247 # average fanout of values written-back
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_producers 62207806 # num instructions producing a value
system.cpu.iew.wb_rate 1.140461 # insts written-back per cycle
system.cpu.iew.wb_sent 102563540 # cumulative count of insts sent to commit
system.cpu.int_regfile_reads 259728905 # number of integer regfile reads
system.cpu.int_regfile_writes 80595212 # number of integer regfile writes
system.cpu.ipc 1.018534 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.018534 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 74250134 70.21% 70.21% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 10532 0.01% 70.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 1 0.00% 70.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 27 0.00% 70.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 46 0.00% 70.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 5 0.00% 70.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 26236363 24.81% 95.02% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 5264077 4.98% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 105761185 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 177153 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.001675 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 40759 23.01% 23.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 27 0.02% 23.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 78448 44.28% 67.31% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 57919 32.69% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 89559799 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.180900 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.457109 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 38412400 42.89% 42.89% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 23501864 26.24% 69.13% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 14299372 15.97% 85.10% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 6452092 7.20% 92.30% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 2377583 2.65% 94.96% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 2675567 2.99% 97.94% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 1597319 1.78% 99.73% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 116596 0.13% 99.86% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 127006 0.14% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 89559799 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.180509 # Inst issue rate
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 74250134 70.21% 70.21% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 10532 0.01% 70.22% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 27 0.00% 70.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 46 0.00% 70.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 70.22% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.22% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 26236363 24.81% 95.02% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 5264077 4.98% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 105761185 # Type of FU issued
system.cpu.iq.fp_alu_accesses 110 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 216 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 99 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 196 # Number of floating instruction queue writes
system.cpu.iq.fu_busy_cnt 177153 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.001675 # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 40759 23.01% 23.01% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 27 0.02% 23.02% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 23.02% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 78448 44.28% 67.31% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 57919 32.69% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.int_alu_accesses 105938228 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 301287282 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 102173164 # Number of integer instruction queue wakeup accesses
@ -395,6 +377,24 @@ system.cpu.iq.iqSquashedInstsExamined 37472339 # Nu
system.cpu.iq.iqSquashedInstsIssued 28176 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 139525 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 69343981 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.issued_per_cycle::samples 89559799 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.180900 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.457109 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 38412400 42.89% 42.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 23501864 26.24% 69.13% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 14299372 15.97% 85.10% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 6452092 7.20% 92.30% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 2377583 2.65% 94.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 2675567 2.99% 97.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 1597319 1.78% 99.73% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 116596 0.13% 99.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 127006 0.14% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 89559799 # Number of insts issued each cycle
system.cpu.iq.rate 1.180509 # Inst issue rate
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
@ -468,10 +468,10 @@ system.cpu.l2cache.demand_mshr_misses 15537 # nu
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.012381 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.250026 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 405.690928 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 8192.856570 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.012381 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.250026 # Average percentage of cache occupancy
system.cpu.l2cache.overall_accesses 950905 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34233.211115 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31042.833237 # average overall mshr miss latency
@ -502,28 +502,28 @@ system.cpu.misc_regfile_writes 11602 # nu
system.cpu.numCycles 89589473 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 2558009 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 71576967 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 2891853 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 35560664 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 1952065 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 58 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 350271207 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 135568411 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 105865304 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 30904016 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 5457924 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 5891977 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 34288334 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 787 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 350270420 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 9187209 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 701223 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 13035103 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 702184 # count of temporary serializing insts renamed
system.cpu.rename.BlockCycles 2558009 # Number of cycles rename is blocking
system.cpu.rename.CommittedMaps 71576967 # Number of HB maps that are committed
system.cpu.rename.IQFullEvents 2891853 # Number of times rename has blocked due to IQ full
system.cpu.rename.IdleCycles 35560664 # Number of cycles rename is idle
system.cpu.rename.LSQFullEvents 1952065 # Number of times rename has blocked due to LSQ full
system.cpu.rename.ROBFullEvents 58 # Number of times rename has blocked due to ROB full
system.cpu.rename.RenameLookups 350271207 # Number of register rename lookups that rename has made
system.cpu.rename.RenamedInsts 135568411 # Number of instructions processed by rename
system.cpu.rename.RenamedOperands 105865304 # Number of destination operands rename has renamed
system.cpu.rename.RunCycles 30904016 # Number of cycles rename is running
system.cpu.rename.SquashCycles 5457924 # Number of cycles rename is squashing
system.cpu.rename.UnblockCycles 5891977 # Number of cycles rename is unblocking
system.cpu.rename.UndoneMaps 34288334 # Number of HB maps that are undone due to squashing
system.cpu.rename.fp_rename_lookups 787 # Number of floating rename lookups
system.cpu.rename.int_rename_lookups 350270420 # Number of integer rename lookups
system.cpu.rename.serializeStallCycles 9187209 # count of cycles rename stalled for serializing inst
system.cpu.rename.serializingInsts 701223 # count of serializing insts renamed
system.cpu.rename.skidInsts 13035103 # count of insts added to the skid buffer
system.cpu.rename.tempSerializingInsts 702184 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 212458407 # The number of ROB reads
system.cpu.rob.rob_writes 263525841 # The number of ROB writes
system.cpu.timesIdled 1433 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 442 # Number of system calls
system.cpu.workload.num_syscalls 442 # Number of system calls
---------- End Simulation Statistics ----------

6
tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini
View file

@ -61,14 +61,14 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic
cwd=build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic
egid=100
env=
errout=cerr
euid=100
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/mcf
executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
gid=100
input=/chips/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100

8
tests/long/10.mcf/ref/arm/linux/simple-atomic/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Mar 30 2011 17:47:57
M5 started Mar 30 2011 17:54:34
M5 executing on u200439-lin.austin.arm.com
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic
M5 compiled Apr 19 2011 12:47:10
M5 started Apr 19 2011 12:50:38
M5 executing on maize
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

10
tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 950960 # Simulator instruction rate (inst/s)
host_mem_usage 379668 # Number of bytes of host memory used
host_seconds 95.96 # Real time elapsed on the host
host_tick_rate 565248287 # Simulator tick rate (ticks/s)
host_inst_rate 3623403 # Simulator instruction rate (inst/s)
host_mem_usage 338784 # Number of bytes of host memory used
host_seconds 25.18 # Real time elapsed on the host
host_tick_rate 2153732946 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 91252969 # Number of instructions simulated
sim_seconds 0.054241 # Number of seconds simulated
@ -71,6 +71,6 @@ system.cpu.num_int_register_writes 70993656 # nu
system.cpu.num_load_insts 22573967 # Number of load instructions
system.cpu.num_mem_refs 27318811 # number of memory refs
system.cpu.num_store_insts 4744844 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 442 # Number of system calls
system.cpu.workload.num_syscalls 442 # Number of system calls
---------- End Simulation Statistics ----------

6
tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini
View file

@ -164,14 +164,14 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing
cwd=build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing
egid=100
env=
errout=cerr
euid=100
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/mcf
executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
gid=100
input=/chips/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100

8
tests/long/10.mcf/ref/arm/linux/simple-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Mar 30 2011 17:47:57
M5 started Mar 30 2011 17:54:34
M5 executing on u200439-lin.austin.arm.com
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing
M5 compiled Apr 19 2011 12:47:10
M5 started Apr 19 2011 12:51:14
M5 executing on maize
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

18
tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 492863 # Simulator instruction rate (inst/s)
host_mem_usage 387392 # Number of bytes of host memory used
host_seconds 185.09 # Real time elapsed on the host
host_tick_rate 800055292 # Simulator tick rate (ticks/s)
host_inst_rate 2007081 # Simulator instruction rate (inst/s)
host_mem_usage 346528 # Number of bytes of host memory used
host_seconds 45.45 # Real time elapsed on the host
host_tick_rate 3258049978 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 91226321 # Number of instructions simulated
sim_seconds 0.148086 # Number of seconds simulated
@ -54,8 +54,8 @@ system.cpu.dcache.demand_mshr_misses 946798 # nu
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.871228 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 3568.549501 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.871228 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses 27284389 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 14657.859438 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 11657.859438 # average overall mshr miss latency
@ -130,8 +130,8 @@ system.cpu.icache.demand_mshr_misses 599 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.249187 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 510.335448 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.249187 # Average percentage of cache occupancy
system.cpu.icache.overall_accesses 107830780 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 54527.545910 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 51527.545910 # average overall mshr miss latency
@ -219,10 +219,10 @@ system.cpu.l2cache.demand_mshr_misses 15408 # nu
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.009921 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.271918 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 325.097811 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 8910.209882 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.009921 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.271918 # Average percentage of cache occupancy
system.cpu.l2cache.overall_accesses 947397 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
@ -264,6 +264,6 @@ system.cpu.num_int_register_writes 70993656 # nu
system.cpu.num_load_insts 22573967 # Number of load instructions
system.cpu.num_mem_refs 27318811 # number of memory refs
system.cpu.num_store_insts 4744844 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 442 # Number of system calls
system.cpu.workload.num_syscalls 442 # Number of system calls
---------- End Simulation Statistics ----------

7
tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout
View file

@ -5,10 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 7 2011 02:13:30
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Feb 7 2011 02:14:01
M5 executing on burrito
M5 compiled Apr 19 2011 12:19:46
M5 started Apr 19 2011 12:20:18
M5 executing on maize
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

10
tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1159873 # Simulator instruction rate (inst/s)
host_mem_usage 351876 # Number of bytes of host memory used
host_seconds 210.23 # Real time elapsed on the host
host_tick_rate 581353978 # Simulator tick rate (ticks/s)
host_inst_rate 4484533 # Simulator instruction rate (inst/s)
host_mem_usage 329760 # Number of bytes of host memory used
host_seconds 54.37 # Real time elapsed on the host
host_tick_rate 2247743371 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 243835278 # Number of instructions simulated
sim_seconds 0.122216 # Number of seconds simulated
@ -29,6 +29,6 @@ system.cpu.num_int_register_writes 215451609 # nu
system.cpu.num_load_insts 82803522 # Number of load instructions
system.cpu.num_mem_refs 105711442 # number of memory refs
system.cpu.num_store_insts 22907920 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 443 # Number of system calls
system.cpu.workload.num_syscalls 443 # Number of system calls
---------- End Simulation Statistics ----------

3
tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
View file

@ -51,6 +51,7 @@ assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
@ -86,6 +87,7 @@ assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
@ -121,6 +123,7 @@ assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=10000
max_miss_count=0
mshrs=10

7
tests/long/10.mcf/ref/sparc/linux/simple-timing/simout
View file

@ -5,10 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 7 2011 02:13:30
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Feb 7 2011 02:13:48
M5 executing on burrito
M5 compiled Apr 19 2011 12:19:46
M5 started Apr 19 2011 12:19:52
M5 executing on maize
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

18
tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 483058 # Simulator instruction rate (inst/s)
host_mem_usage 359588 # Number of bytes of host memory used
host_seconds 504.77 # Real time elapsed on the host
host_tick_rate 718005180 # Simulator tick rate (ticks/s)
host_inst_rate 2305909 # Simulator instruction rate (inst/s)
host_mem_usage 337512 # Number of bytes of host memory used
host_seconds 105.74 # Real time elapsed on the host
host_tick_rate 3427441926 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 243835278 # Number of instructions simulated
sim_seconds 0.362431 # Number of seconds simulated
@ -60,8 +60,8 @@ system.cpu.dcache.demand_mshr_misses 939567 # nu
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.870074 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 3563.824259 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.870074 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses 105122385 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 14660.150899 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 11660.150899 # average overall mshr miss latency
@ -115,8 +115,8 @@ system.cpu.icache.demand_mshr_misses 882 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.354281 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 725.567632 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.354281 # Average percentage of cache occupancy
system.cpu.icache.overall_accesses 244421512 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 55857.142857 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 52857.142857 # average overall mshr miss latency
@ -183,10 +183,10 @@ system.cpu.l2cache.demand_mshr_misses 15648 # nu
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.011460 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.270424 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 375.506440 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 8861.245791 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.011460 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.270424 # Average percentage of cache occupancy
system.cpu.l2cache.overall_accesses 940453 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
@ -228,6 +228,6 @@ system.cpu.num_int_register_writes 215451608 # nu
system.cpu.num_load_insts 82803522 # Number of load instructions
system.cpu.num_mem_refs 105711442 # number of memory refs
system.cpu.num_store_insts 22907920 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 443 # Number of system calls
system.cpu.workload.num_syscalls 443 # Number of system calls
---------- End Simulation Statistics ----------

2
tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini
View file

@ -25,6 +25,8 @@ BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
RASSize=16
SQEntries=32
SSITSize=1024

6
tests/long/10.mcf/ref/x86/linux/o3-timing/simout
View file

@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Mar 18 2011 20:12:06
M5 started Mar 18 2011 20:12:16
M5 executing on zizzer
M5 compiled Apr 19 2011 12:22:33
M5 started Apr 19 2011 12:30:19
M5 executing on maize
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

330
tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 173311 # Simulator instruction rate (inst/s)
host_mem_usage 350460 # Number of bytes of host memory used
host_seconds 1605.16 # Real time elapsed on the host
host_tick_rate 50708988 # Simulator tick rate (ticks/s)
host_inst_rate 265187 # Simulator instruction rate (inst/s)
host_mem_usage 346300 # Number of bytes of host memory used
host_seconds 1049.04 # Real time elapsed on the host
host_tick_rate 77591071 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 278192519 # Number of instructions simulated
sim_seconds 0.081396 # Number of seconds simulated
@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 2465320 # Nu
system.cpu.BPredUnit.condPredicted 43504790 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 43504790 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 29309710 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 13548841 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 149131695 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.865415 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 2.481905 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 63516016 42.59% 42.59% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 27005826 18.11% 60.70% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 19486009 13.07% 73.77% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 13132636 8.81% 82.57% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 4245933 2.85% 85.42% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 3434891 2.30% 87.72% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 3062949 2.05% 89.78% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 1698594 1.14% 90.91% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 13548841 9.09% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 149131695 # Number of insts commited each cycle
system.cpu.commit.COM:count 278192519 # Number of instructions committed
system.cpu.commit.COM:fp_insts 40 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
system.cpu.commit.COM:int_insts 278186227 # Number of committed integer instructions.
system.cpu.commit.COM:loads 90779388 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 122219139 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 2465329 # The number of times a branch was mispredicted
system.cpu.commit.branches 29309710 # Number of branches committed
system.cpu.commit.bw_lim_events 13548841 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.commitCommittedInsts 278192519 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 88842299 # The number of squashed insts skipped by commit
system.cpu.commit.committed_per_cycle::samples 149131695 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.865415 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.481905 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 63516016 42.59% 42.59% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 27005826 18.11% 60.70% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 19486009 13.07% 73.77% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 13132636 8.81% 82.57% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 4245933 2.85% 85.42% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 3434891 2.30% 87.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 3062949 2.05% 89.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 1698594 1.14% 90.91% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 13548841 9.09% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 149131695 # Number of insts commited each cycle
system.cpu.commit.count 278192519 # Number of instructions committed
system.cpu.commit.fp_insts 40 # Number of committed floating point instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
system.cpu.commit.int_insts 278186227 # Number of committed integer instructions.
system.cpu.commit.loads 90779388 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.refs 122219139 # Number of memory references committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.committedInsts 278192519 # Number of Instructions Simulated
system.cpu.committedInsts_total 278192519 # Number of Instructions Simulated
system.cpu.cpi 0.585179 # CPI: Cycles Per Instruction
@ -96,8 +96,8 @@ system.cpu.dcache.demand_mshr_misses 2078004 # nu
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.994940 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4075.274681 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.994940 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses 94785588 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 7490.439865 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 3562.354617 # average overall mshr miss latency
@ -119,12 +119,12 @@ system.cpu.dcache.tagsinuse 4075.274681 # Cy
system.cpu.dcache.total_refs 92329423 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 30396735000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 1448011 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 13645155 # Number of cycles decode is blocked
system.cpu.decode.DECODE:DecodedInsts 390459172 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 68124952 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 66154578 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 12492114 # Number of cycles decode is squashing
system.cpu.decode.DECODE:UnblockCycles 1207010 # Number of cycles decode is unblocking
system.cpu.decode.BlockedCycles 13645155 # Number of cycles decode is blocked
system.cpu.decode.DecodedInsts 390459172 # Number of instructions handled by decode
system.cpu.decode.IdleCycles 68124952 # Number of cycles decode is idle
system.cpu.decode.RunCycles 66154578 # Number of cycles decode is running
system.cpu.decode.SquashCycles 12492114 # Number of cycles decode is squashing
system.cpu.decode.UnblockCycles 1207010 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 43504790 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 30855910 # Number of cache lines fetched
system.cpu.fetch.Cycles 71218247 # Number of cycles fetch has run and was not squashing or blocked
@ -188,8 +188,8 @@ system.cpu.icache.demand_mshr_misses 1013 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.396500 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 812.031019 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.396500 # Average percentage of cache occupancy
system.cpu.icache.overall_accesses 30855910 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 36182.458888 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35209.772952 # average overall mshr miss latency
@ -212,21 +212,13 @@ system.cpu.icache.total_refs 30854633 # To
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 1168640 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 32808514 # Number of branches executed
system.cpu.iew.EXEC:nop 0 # number of nop insts executed
system.cpu.iew.EXEC:rate 2.009454 # Inst execution rate
system.cpu.iew.EXEC:refs 141715314 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 34352421 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 330470543 # num instructions consuming a value
system.cpu.iew.WB:count 324204287 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.735351 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 243011799 # num instructions producing a value
system.cpu.iew.WB:rate 1.991519 # insts written-back per cycle
system.cpu.iew.WB:sent 325408414 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 2866285 # Number of branch mispredicts detected at execute
system.cpu.iew.exec_branches 32808514 # Number of branches executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_rate 2.009454 # Inst execution rate
system.cpu.iew.exec_refs 141715314 # number of memory reference insts executed
system.cpu.iew.exec_stores 34352421 # Number of stores executed
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.iewBlockCycles 739357 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 121527888 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions
@ -254,103 +246,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 8203432 #
system.cpu.iew.memOrderViolationEvents 237293 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 582972 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 2283313 # Number of branches that were predicted taken incorrectly
system.cpu.iew.wb_consumers 330470543 # num instructions consuming a value
system.cpu.iew.wb_count 324204287 # cumulative count of insts written-back
system.cpu.iew.wb_fanout 0.735351 # average fanout of values written-back
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_producers 243011799 # num instructions producing a value
system.cpu.iew.wb_rate 1.991519 # insts written-back per cycle
system.cpu.iew.wb_sent 325408414 # cumulative count of insts sent to commit
system.cpu.int_regfile_reads 572686347 # number of integer regfile reads
system.cpu.int_regfile_writes 291536884 # number of integer regfile writes
system.cpu.ipc 1.708879 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.708879 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 16703 0.01% 0.01% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 188329198 56.76% 56.76% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 16 0.00% 56.76% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 108641887 32.74% 89.51% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 34821337 10.49% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 331809141 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 1744992 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.005259 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 20475 1.17% 1.17% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 1576903 90.37% 91.54% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 147614 8.46% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 161623809 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 2.052972 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.792191 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 44438080 27.49% 27.49% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 26560474 16.43% 43.93% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 27560184 17.05% 60.98% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 26726118 16.54% 77.52% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 19530475 12.08% 89.60% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 11104171 6.87% 96.47% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 3863575 2.39% 98.86% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 1600116 0.99% 99.85% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 240616 0.15% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 161623809 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 2.038234 # Inst issue rate
system.cpu.iq.FU_type_0::No_OpClass 16703 0.01% 0.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 188329198 56.76% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 16 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 108641887 32.74% 89.51% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 34821337 10.49% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 331809141 # Type of FU issued
system.cpu.iq.fp_alu_accesses 101 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 208 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 80 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 238 # Number of floating instruction queue writes
system.cpu.iq.fu_busy_cnt 1744992 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.005259 # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 20475 1.17% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 1576903 90.37% 91.54% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 147614 8.46% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.int_alu_accesses 333537329 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 827162429 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 324204207 # Number of integer instruction queue wakeup accesses
@ -362,6 +344,24 @@ system.cpu.iq.iqSquashedInstsExamined 88592670 # Nu
system.cpu.iq.iqSquashedInstsIssued 175554 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 19 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 124945161 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.issued_per_cycle::samples 161623809 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.052972 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.792191 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 44438080 27.49% 27.49% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 26560474 16.43% 43.93% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 27560184 17.05% 60.98% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 26726118 16.54% 77.52% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 19530475 12.08% 89.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 11104171 6.87% 96.47% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 3863575 2.39% 98.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 1600116 0.99% 99.85% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 240616 0.15% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 161623809 # Number of insts issued each cycle
system.cpu.iq.rate 2.038234 # Inst issue rate
system.cpu.l2cache.ReadExReq_accesses 106011 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34192.017786 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31115.893095 # average ReadExReq mshr miss latency
@ -413,10 +413,10 @@ system.cpu.l2cache.demand_mshr_misses 76519 # nu
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.196368 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.354446 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 6434.571377 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 11614.477696 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.196368 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.354446 # Average percentage of cache occupancy
system.cpu.l2cache.overall_accesses 2079015 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34202.596741 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31074.223395 # average overall mshr miss latency
@ -446,28 +446,28 @@ system.cpu.misc_regfile_reads 211169577 # nu
system.cpu.numCycles 162792449 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 3023364 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 248344192 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 130274 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 72054036 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 9710787 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 12 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 941229334 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 383108308 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 343773743 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 63044913 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 12492114 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 11002939 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 95429551 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 586 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 941228748 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 6443 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 468 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 25868384 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 462 # count of temporary serializing insts renamed
system.cpu.rename.BlockCycles 3023364 # Number of cycles rename is blocking
system.cpu.rename.CommittedMaps 248344192 # Number of HB maps that are committed
system.cpu.rename.IQFullEvents 130274 # Number of times rename has blocked due to IQ full
system.cpu.rename.IdleCycles 72054036 # Number of cycles rename is idle
system.cpu.rename.LSQFullEvents 9710787 # Number of times rename has blocked due to LSQ full
system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full
system.cpu.rename.RenameLookups 941229334 # Number of register rename lookups that rename has made
system.cpu.rename.RenamedInsts 383108308 # Number of instructions processed by rename
system.cpu.rename.RenamedOperands 343773743 # Number of destination operands rename has renamed
system.cpu.rename.RunCycles 63044913 # Number of cycles rename is running
system.cpu.rename.SquashCycles 12492114 # Number of cycles rename is squashing
system.cpu.rename.UnblockCycles 11002939 # Number of cycles rename is unblocking
system.cpu.rename.UndoneMaps 95429551 # Number of HB maps that are undone due to squashing
system.cpu.rename.fp_rename_lookups 586 # Number of floating rename lookups
system.cpu.rename.int_rename_lookups 941228748 # Number of integer rename lookups
system.cpu.rename.serializeStallCycles 6443 # count of cycles rename stalled for serializing inst
system.cpu.rename.serializingInsts 468 # count of serializing insts renamed
system.cpu.rename.skidInsts 25868384 # count of insts added to the skid buffer
system.cpu.rename.tempSerializingInsts 462 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 502617672 # The number of ROB reads
system.cpu.rob.rob_writes 746575877 # The number of ROB writes
system.cpu.timesIdled 40062 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 444 # Number of system calls
system.cpu.workload.num_syscalls 444 # Number of system calls
---------- End Simulation Statistics ----------

7
tests/long/10.mcf/ref/x86/linux/simple-atomic/simout
View file

@ -5,10 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 8 2011 00:58:32
M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip
M5 started Feb 8 2011 00:58:34
M5 executing on burrito
M5 compiled Apr 19 2011 12:22:33
M5 started Apr 19 2011 12:39:34
M5 executing on maize
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

10
tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1568972 # Simulator instruction rate (inst/s)
host_mem_usage 358500 # Number of bytes of host memory used
host_seconds 177.31 # Real time elapsed on the host
host_tick_rate 952856596 # Simulator tick rate (ticks/s)
host_inst_rate 3107267 # Simulator instruction rate (inst/s)
host_mem_usage 337076 # Number of bytes of host memory used
host_seconds 89.53 # Real time elapsed on the host
host_tick_rate 1887081425 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 278192520 # Number of instructions simulated
sim_seconds 0.168950 # Number of seconds simulated
@ -29,6 +29,6 @@ system.cpu.num_int_register_writes 248344166 # nu
system.cpu.num_load_insts 90779388 # Number of load instructions
system.cpu.num_mem_refs 122219139 # number of memory refs
system.cpu.num_store_insts 31439751 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 444 # Number of system calls
system.cpu.workload.num_syscalls 444 # Number of system calls
---------- End Simulation Statistics ----------

3
tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini
View file

@ -51,6 +51,7 @@ assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
@ -86,6 +87,7 @@ assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
@ -121,6 +123,7 @@ assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=10000
max_miss_count=0
mshrs=10

7
tests/long/10.mcf/ref/x86/linux/simple-timing/simout
View file

@ -5,10 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 8 2011 00:58:32
M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip
M5 started Feb 8 2011 00:58:34
M5 executing on burrito
M5 compiled Apr 19 2011 12:22:33
M5 started Apr 19 2011 12:41:14
M5 executing on maize
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

18
tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1018906 # Simulator instruction rate (inst/s)
host_mem_usage 366224 # Number of bytes of host memory used
host_seconds 273.03 # Real time elapsed on the host
host_tick_rate 1355197592 # Simulator tick rate (ticks/s)
host_inst_rate 1776708 # Simulator instruction rate (inst/s)
host_mem_usage 344820 # Number of bytes of host memory used
host_seconds 156.58 # Real time elapsed on the host
host_tick_rate 2363113199 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 278192520 # Number of instructions simulated
sim_seconds 0.370011 # Number of seconds simulated
@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses 2066829 # nu
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.995279 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4076.661903 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.995279 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses 122219201 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 15539.675029 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 12539.674303 # average overall mshr miss latency
@ -105,8 +105,8 @@ system.cpu.icache.demand_mshr_misses 808 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.325289 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 666.191948 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.325289 # Average percentage of cache occupancy
system.cpu.icache.overall_accesses 217696209 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
@ -173,10 +173,10 @@ system.cpu.l2cache.demand_mshr_misses 76575 # nu
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.199945 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.368128 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 6551.798271 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 12062.804989 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.199945 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.368128 # Average percentage of cache occupancy
system.cpu.l2cache.overall_accesses 2067637 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000.385243 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
@ -218,6 +218,6 @@ system.cpu.num_int_register_writes 248344166 # nu
system.cpu.num_load_insts 90779388 # Number of load instructions
system.cpu.num_mem_refs 122219139 # number of memory refs
system.cpu.num_store_insts 31439751 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 444 # Number of system calls
system.cpu.workload.num_syscalls 444 # Number of system calls
---------- End Simulation Statistics ----------

4
tests/long/20.parser/ref/arm/linux/o3-timing/config.ini
View file

@ -498,9 +498,9 @@ egid=100
env=
errout=cerr
euid=100
executable=/arm/scratch/alisai01/dist/cpu2000/binaries/arm/linux/parser
executable=/dist/m5/cpu2000/binaries/arm/linux/parser
gid=100
input=/arm/scratch/alisai01/dist/cpu2000/data/parser/mdred/input/parser.in
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100

8
tests/long/20.parser/ref/arm/linux/o3-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Mar 30 2011 17:47:57
M5 started Mar 30 2011 17:54:34
M5 executing on u200439-lin.austin.arm.com
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing
M5 compiled Apr 19 2011 12:47:10
M5 started Apr 19 2011 12:52:10
M5 executing on maize
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

336
tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 134709 # Simulator instruction rate (inst/s)
host_mem_usage 264692 # Number of bytes of host memory used
host_seconds 4256.17 # Real time elapsed on the host
host_tick_rate 78176241 # Simulator tick rate (ticks/s)
host_inst_rate 191028 # Simulator instruction rate (inst/s)
host_mem_usage 221120 # Number of bytes of host memory used
host_seconds 3001.36 # Real time elapsed on the host
host_tick_rate 110860138 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 573342397 # Number of instructions simulated
sim_seconds 0.332731 # Number of seconds simulated
@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 18809964 # Nu
system.cpu.BPredUnit.condPredicted 186338321 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 233659814 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 11860569 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 120192362 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 6858146 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 603587786 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 0.952117 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.448029 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 310030081 51.36% 51.36% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 161983498 26.84% 78.20% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 68757792 11.39% 89.59% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 25709435 4.26% 93.85% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 17326011 2.87% 96.72% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 5210197 0.86% 97.59% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 6149685 1.02% 98.60% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 1562941 0.26% 98.86% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 6858146 1.14% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 603587786 # Number of insts commited each cycle
system.cpu.commit.COM:count 574686281 # Number of instructions committed
system.cpu.commit.COM:fp_insts 16 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 9757362 # Number of function calls committed.
system.cpu.commit.COM:int_insts 473702185 # Number of committed integer instructions.
system.cpu.commit.COM:loads 126773177 # Number of loads committed
system.cpu.commit.COM:membars 1488542 # Number of memory barriers committed
system.cpu.commit.COM:refs 184377275 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 20926821 # The number of times a branch was mispredicted
system.cpu.commit.branches 120192362 # Number of branches committed
system.cpu.commit.bw_lim_events 6858146 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.commitCommittedInsts 574686281 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 3877893 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 381923221 # The number of squashed insts skipped by commit
system.cpu.commit.committed_per_cycle::samples 603587786 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.952117 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.448029 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 310030081 51.36% 51.36% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 161983498 26.84% 78.20% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 68757792 11.39% 89.59% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 25709435 4.26% 93.85% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 17326011 2.87% 96.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 5210197 0.86% 97.59% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 6149685 1.02% 98.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 1562941 0.26% 98.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 6858146 1.14% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 603587786 # Number of insts commited each cycle
system.cpu.commit.count 574686281 # Number of instructions committed
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
system.cpu.commit.function_calls 9757362 # Number of function calls committed.
system.cpu.commit.int_insts 473702185 # Number of committed integer instructions.
system.cpu.commit.loads 126773177 # Number of loads committed
system.cpu.commit.membars 1488542 # Number of memory barriers committed
system.cpu.commit.refs 184377275 # Number of memory references committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.committedInsts 573342397 # Number of Instructions Simulated
system.cpu.committedInsts_total 573342397 # Number of Instructions Simulated
system.cpu.cpi 1.160672 # CPI: Cycles Per Instruction
@ -105,8 +105,8 @@ system.cpu.dcache.demand_mshr_misses 1195995 # nu
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.991470 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4061.060335 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.991470 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses 197693380 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 13396.562604 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 8735.502239 # average overall mshr miss latency
@ -128,15 +128,15 @@ system.cpu.dcache.tagsinuse 4061.060335 # Cy
system.cpu.dcache.total_refs 200083704 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 6358781000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 1064793 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 85842380 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 76871 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 34367828 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 1126968144 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 277630014 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 236143765 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 57332647 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 218235 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 3971626 # Number of cycles decode is unblocking
system.cpu.decode.BlockedCycles 85842380 # Number of cycles decode is blocked
system.cpu.decode.BranchMispred 76871 # Number of times decode detected a branch misprediction
system.cpu.decode.BranchResolved 34367828 # Number of times decode resolved a branch
system.cpu.decode.DecodedInsts 1126968144 # Number of instructions handled by decode
system.cpu.decode.IdleCycles 277630014 # Number of cycles decode is idle
system.cpu.decode.RunCycles 236143765 # Number of cycles decode is running
system.cpu.decode.SquashCycles 57332647 # Number of cycles decode is squashing
system.cpu.decode.SquashedInsts 218235 # Number of squashed instructions handled by decode
system.cpu.decode.UnblockCycles 3971626 # Number of cycles decode is unblocking
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
@ -220,8 +220,8 @@ system.cpu.icache.demand_mshr_misses 13895 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.514415 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1053.520934 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.514415 # Average percentage of cache occupancy
system.cpu.icache.overall_accesses 132169265 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 14331.781024 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 10612.450522 # average overall mshr miss latency
@ -244,21 +244,13 @@ system.cpu.icache.total_refs 132154335 # To
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 4 # number of writebacks
system.cpu.idleCycles 4542007 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 142399885 # Number of branches executed
system.cpu.iew.EXEC:nop 9420990 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.051214 # Inst execution rate
system.cpu.iew.EXEC:refs 220838036 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 66554903 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 782273717 # num instructions consuming a value
system.cpu.iew.WB:count 680637923 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.486169 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 380317186 # num instructions producing a value
system.cpu.iew.WB:rate 1.022804 # insts written-back per cycle
system.cpu.iew.WB:sent 691183006 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 25100140 # Number of branch mispredicts detected at execute
system.cpu.iew.exec_branches 142399885 # Number of branches executed
system.cpu.iew.exec_nop 9420990 # number of nop insts executed
system.cpu.iew.exec_rate 1.051214 # Inst execution rate
system.cpu.iew.exec_refs 220838036 # number of memory reference insts executed
system.cpu.iew.exec_stores 66554903 # Number of stores executed
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.iewBlockCycles 2947924 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 196892006 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 2816035 # Number of dispatched non-speculative instructions
@ -286,103 +278,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 56769769 #
system.cpu.iew.memOrderViolationEvents 241250 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 6965983 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 18134157 # Number of branches that were predicted taken incorrectly
system.cpu.iew.wb_consumers 782273717 # num instructions consuming a value
system.cpu.iew.wb_count 680637923 # cumulative count of insts written-back
system.cpu.iew.wb_fanout 0.486169 # average fanout of values written-back
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_producers 380317186 # num instructions producing a value
system.cpu.iew.wb_rate 1.022804 # insts written-back per cycle
system.cpu.iew.wb_sent 691183006 # cumulative count of insts sent to commit
system.cpu.int_regfile_reads 1609052037 # number of integer regfile reads
system.cpu.int_regfile_writes 524399004 # number of integer regfile writes
system.cpu.ipc 0.861570 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.861570 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 491156775 67.76% 67.76% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 386013 0.05% 67.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 106 0.00% 67.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 3 0.00% 67.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 162458896 22.41% 90.23% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 70842385 9.77% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 724844178 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 8619148 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.011891 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 25536 0.30% 0.30% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 5445227 63.18% 63.47% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 3148385 36.53% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 660920432 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.096719 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.355430 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 305964281 46.29% 46.29% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 148313904 22.44% 68.73% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 112740957 17.06% 85.79% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 49799071 7.53% 93.33% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 29063149 4.40% 97.72% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 8262993 1.25% 98.97% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 4169807 0.63% 99.61% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 1785416 0.27% 99.88% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 820854 0.12% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 660920432 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.089234 # Inst issue rate
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 491156775 67.76% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 386013 0.05% 67.81% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 106 0.00% 67.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.81% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 162458896 22.41% 90.23% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 70842385 9.77% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 724844178 # Type of FU issued
system.cpu.iq.fp_alu_accesses 126 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 248 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 340 # Number of floating instruction queue writes
system.cpu.iq.fu_busy_cnt 8619148 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.011891 # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 25536 0.30% 0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 5445227 63.18% 63.47% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 3148385 36.53% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.int_alu_accesses 733463200 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 2121563604 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 680637907 # Number of integer instruction queue wakeup accesses
@ -394,6 +376,24 @@ system.cpu.iq.iqSquashedInstsExamined 371760121 # Nu
system.cpu.iq.iqSquashedInstsIssued 2335916 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 799068 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 680735331 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.issued_per_cycle::samples 660920432 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.096719 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.355430 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 305964281 46.29% 46.29% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 148313904 22.44% 68.73% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 112740957 17.06% 85.79% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 49799071 7.53% 93.33% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 29063149 4.40% 97.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 8262993 1.25% 98.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 4169807 0.63% 99.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 1785416 0.27% 99.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 820854 0.12% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 660920432 # Number of insts issued each cycle
system.cpu.iq.rate 1.089234 # Inst issue rate
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
@ -470,10 +470,10 @@ system.cpu.l2cache.demand_mshr_misses 236073 # nu
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.216648 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.421153 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 7099.133966 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 13800.334539 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.216648 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.421153 # Average percentage of cache occupancy
system.cpu.l2cache.overall_accesses 1209222 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34216.723072 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31016.778708 # average overall mshr miss latency
@ -504,28 +504,28 @@ system.cpu.misc_regfile_writes 4464326 # nu
system.cpu.numCycles 665462439 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 11783884 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 448493735 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 9081964 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 293899856 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 10512591 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 133 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 2673538298 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 1068521543 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 798521782 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 223635059 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 57332647 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 24492193 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 350028044 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 1141 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 2673537157 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 49776793 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 2837350 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 62579735 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 2837280 # count of temporary serializing insts renamed
system.cpu.rename.BlockCycles 11783884 # Number of cycles rename is blocking
system.cpu.rename.CommittedMaps 448493735 # Number of HB maps that are committed
system.cpu.rename.IQFullEvents 9081964 # Number of times rename has blocked due to IQ full
system.cpu.rename.IdleCycles 293899856 # Number of cycles rename is idle
system.cpu.rename.LSQFullEvents 10512591 # Number of times rename has blocked due to LSQ full
system.cpu.rename.ROBFullEvents 133 # Number of times rename has blocked due to ROB full
system.cpu.rename.RenameLookups 2673538298 # Number of register rename lookups that rename has made
system.cpu.rename.RenamedInsts 1068521543 # Number of instructions processed by rename
system.cpu.rename.RenamedOperands 798521782 # Number of destination operands rename has renamed
system.cpu.rename.RunCycles 223635059 # Number of cycles rename is running
system.cpu.rename.SquashCycles 57332647 # Number of cycles rename is squashing
system.cpu.rename.UnblockCycles 24492193 # Number of cycles rename is unblocking
system.cpu.rename.UndoneMaps 350028044 # Number of HB maps that are undone due to squashing
system.cpu.rename.fp_rename_lookups 1141 # Number of floating rename lookups
system.cpu.rename.int_rename_lookups 2673537157 # Number of integer rename lookups
system.cpu.rename.serializeStallCycles 49776793 # count of cycles rename stalled for serializing inst
system.cpu.rename.serializingInsts 2837350 # count of serializing insts renamed
system.cpu.rename.skidInsts 62579735 # count of insts added to the skid buffer
system.cpu.rename.tempSerializingInsts 2837280 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 1553332004 # The number of ROB reads
system.cpu.rob.rob_writes 1970603439 # The number of ROB writes
system.cpu.timesIdled 108463 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 548 # Number of system calls
system.cpu.workload.num_syscalls 548 # Number of system calls
---------- End Simulation Statistics ----------

6
tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini
View file

@ -61,14 +61,14 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=parser 2.1.dict -batch
cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic
cwd=build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic
egid=100
env=
errout=cerr
euid=100
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/parser
executable=/dist/m5/cpu2000/binaries/arm/linux/parser
gid=100
input=/chips/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100

8
tests/long/20.parser/ref/arm/linux/simple-atomic/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Mar 30 2011 17:47:57
M5 started Mar 30 2011 17:56:20
M5 executing on u200439-lin.austin.arm.com
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic
M5 compiled Apr 19 2011 12:47:10
M5 started Apr 19 2011 12:53:21
M5 executing on maize
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

10
tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1096990 # Simulator instruction rate (inst/s)
host_mem_usage 250472 # Number of bytes of host memory used
host_seconds 520.49 # Real time elapsed on the host
host_tick_rate 558129819 # Simulator tick rate (ticks/s)
host_inst_rate 4059400 # Simulator instruction rate (inst/s)
host_mem_usage 209588 # Number of bytes of host memory used
host_seconds 140.65 # Real time elapsed on the host
host_tick_rate 2065351773 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 570968176 # Number of instructions simulated
sim_seconds 0.290499 # Number of seconds simulated
@ -71,6 +71,6 @@ system.cpu.num_int_register_writes 425113002 # nu
system.cpu.num_load_insts 126029556 # Number of load instructions
system.cpu.num_mem_refs 182890035 # number of memory refs
system.cpu.num_store_insts 56860479 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 548 # Number of system calls
system.cpu.workload.num_syscalls 548 # Number of system calls
---------- End Simulation Statistics ----------

6
tests/long/20.parser/ref/arm/linux/simple-timing/config.ini
View file

@ -164,14 +164,14 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=parser 2.1.dict -batch
cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing
cwd=build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing
egid=100
env=
errout=cerr
euid=100
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/parser
executable=/dist/m5/cpu2000/binaries/arm/linux/parser
gid=100
input=/chips/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100

8
tests/long/20.parser/ref/arm/linux/simple-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Mar 30 2011 17:47:57
M5 started Mar 30 2011 17:57:49
M5 executing on u200439-lin.austin.arm.com
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing
M5 compiled Apr 19 2011 12:47:10
M5 started Apr 19 2011 12:55:52
M5 executing on maize
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

18
tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 577686 # Simulator instruction rate (inst/s)
host_mem_usage 258200 # Number of bytes of host memory used
host_seconds 985.02 # Real time elapsed on the host
host_tick_rate 733214267 # Simulator tick rate (ticks/s)
host_inst_rate 2210994 # Simulator instruction rate (inst/s)
host_mem_usage 217324 # Number of bytes of host memory used
host_seconds 257.37 # Real time elapsed on the host
host_tick_rate 2806251427 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 569034848 # Number of instructions simulated
sim_seconds 0.722234 # Number of seconds simulated
@ -54,8 +54,8 @@ system.cpu.dcache.demand_mshr_misses 1138918 # nu
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.992551 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4065.490059 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.992551 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses 177979623 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 22417.457622 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 19417.457622 # average overall mshr miss latency
@ -130,8 +130,8 @@ system.cpu.icache.demand_mshr_misses 11521 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.480677 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 984.426148 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.480677 # Average percentage of cache occupancy
system.cpu.icache.overall_accesses 516611385 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 24743.338252 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 21743.338252 # average overall mshr miss latency
@ -219,10 +219,10 @@ system.cpu.l2cache.demand_mshr_misses 231204 # nu
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.178502 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.445374 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 5849.157602 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 14594.006011 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.178502 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.445374 # Average percentage of cache occupancy
system.cpu.l2cache.overall_accesses 1150439 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
@ -264,6 +264,6 @@ system.cpu.num_int_register_writes 425113002 # nu
system.cpu.num_load_insts 126029556 # Number of load instructions
system.cpu.num_mem_refs 182890035 # number of memory refs
system.cpu.num_store_insts 56860479 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 548 # Number of system calls
system.cpu.workload.num_syscalls 548 # Number of system calls
---------- End Simulation Statistics ----------

2
tests/long/20.parser/ref/x86/linux/o3-timing/config.ini
View file

@ -25,6 +25,8 @@ BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
RASSize=16
SQEntries=32
SSITSize=1024

6
tests/long/20.parser/ref/x86/linux/o3-timing/simout
View file

@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Mar 18 2011 20:12:06
M5 started Mar 18 2011 20:27:45
M5 executing on zizzer
M5 compiled Apr 19 2011 12:22:33
M5 started Apr 19 2011 12:32:37
M5 executing on maize
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

330
tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 135575 # Simulator instruction rate (inst/s)
host_mem_usage 259672 # Number of bytes of host memory used
host_seconds 11277.84 # Real time elapsed on the host
host_tick_rate 51792019 # Simulator tick rate (ticks/s)
host_inst_rate 233996 # Simulator instruction rate (inst/s)
host_mem_usage 255168 # Number of bytes of host memory used
host_seconds 6534.25 # Real time elapsed on the host
host_tick_rate 89390880 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1528988756 # Number of instructions simulated
sim_seconds 0.584102 # Number of seconds simulated
@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 16731555 # Nu
system.cpu.BPredUnit.condPredicted 252612909 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 252612909 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 149758588 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 41097639 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 1035309655 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.476842 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.993609 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 433213212 41.84% 41.84% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 271303976 26.21% 68.05% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 102660477 9.92% 77.96% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 102477093 9.90% 87.86% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 38291141 3.70% 91.56% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 25044351 2.42% 93.98% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 10787246 1.04% 95.02% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 10434520 1.01% 96.03% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 41097639 3.97% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 1035309655 # Number of insts commited each cycle
system.cpu.commit.COM:count 1528988756 # Number of instructions committed
system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
system.cpu.commit.COM:int_insts 1528317614 # Number of committed integer instructions.
system.cpu.commit.COM:loads 384102160 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 533262345 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 16763223 # The number of times a branch was mispredicted
system.cpu.commit.branches 149758588 # Number of branches committed
system.cpu.commit.bw_lim_events 41097639 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.commitCommittedInsts 1528988756 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 795955462 # The number of squashed insts skipped by commit
system.cpu.commit.committed_per_cycle::samples 1035309655 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.476842 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.993609 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 433213212 41.84% 41.84% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 271303976 26.21% 68.05% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 102660477 9.92% 77.96% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 102477093 9.90% 87.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 38291141 3.70% 91.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 25044351 2.42% 93.98% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 10787246 1.04% 95.02% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 10434520 1.01% 96.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 41097639 3.97% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1035309655 # Number of insts commited each cycle
system.cpu.commit.count 1528988756 # Number of instructions committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions.
system.cpu.commit.loads 384102160 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.refs 533262345 # Number of memory references committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.committedInsts 1528988756 # Number of Instructions Simulated
system.cpu.committedInsts_total 1528988756 # Number of Instructions Simulated
system.cpu.cpi 0.764037 # CPI: Cycles Per Instruction
@ -96,8 +96,8 @@ system.cpu.dcache.demand_mshr_misses 2775377 # nu
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.998173 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4088.515779 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.998173 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses 472799393 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 18648.960228 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 11951.477943 # average overall mshr miss latency
@ -119,12 +119,12 @@ system.cpu.dcache.tagsinuse 4088.515779 # Cy
system.cpu.dcache.total_refs 469490463 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 2268948000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 2231104 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 187291575 # Number of cycles decode is blocked
system.cpu.decode.DECODE:DecodedInsts 2489806075 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 422005844 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 404270583 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 108207267 # Number of cycles decode is squashing
system.cpu.decode.DECODE:UnblockCycles 21741653 # Number of cycles decode is unblocking
system.cpu.decode.BlockedCycles 187291575 # Number of cycles decode is blocked
system.cpu.decode.DecodedInsts 2489806075 # Number of instructions handled by decode
system.cpu.decode.IdleCycles 422005844 # Number of cycles decode is idle
system.cpu.decode.RunCycles 404270583 # Number of cycles decode is running
system.cpu.decode.SquashCycles 108207267 # Number of cycles decode is squashing
system.cpu.decode.UnblockCycles 21741653 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 252612909 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 188594062 # Number of cache lines fetched
system.cpu.fetch.Cycles 440470513 # Number of cycles fetch has run and was not squashing or blocked
@ -187,8 +187,8 @@ system.cpu.icache.demand_mshr_misses 256130 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.469099 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 960.715295 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.469099 # Average percentage of cache occupancy
system.cpu.icache.overall_accesses 188594062 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 6510.591789 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 3406.338578 # average overall mshr miss latency
@ -211,21 +211,13 @@ system.cpu.icache.total_refs 188329447 # To
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 6 # number of writebacks
system.cpu.idleCycles 24687157 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 173444431 # Number of branches executed
system.cpu.iew.EXEC:nop 0 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.602205 # Inst execution rate
system.cpu.iew.EXEC:refs 612750445 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 165978925 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 2110704618 # num instructions consuming a value
system.cpu.iew.WB:count 1858331416 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.678632 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 1432391344 # num instructions producing a value
system.cpu.iew.WB:rate 1.590759 # insts written-back per cycle
system.cpu.iew.WB:sent 1864643959 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 18167511 # Number of branch mispredicts detected at execute
system.cpu.iew.exec_branches 173444431 # Number of branches executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_rate 1.602205 # Inst execution rate
system.cpu.iew.exec_refs 612750445 # number of memory reference insts executed
system.cpu.iew.exec_stores 165978925 # Number of stores executed
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.iewBlockCycles 9685611 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 586119276 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 9659 # Number of dispatched non-speculative instructions
@ -253,103 +245,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 73925179 #
system.cpu.iew.memOrderViolationEvents 2443893 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 2771097 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 15396414 # Number of branches that were predicted taken incorrectly
system.cpu.iew.wb_consumers 2110704618 # num instructions consuming a value
system.cpu.iew.wb_count 1858331416 # cumulative count of insts written-back
system.cpu.iew.wb_fanout 0.678632 # average fanout of values written-back
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_producers 1432391344 # num instructions producing a value
system.cpu.iew.wb_rate 1.590759 # insts written-back per cycle
system.cpu.iew.wb_sent 1864643959 # cumulative count of insts sent to commit
system.cpu.int_regfile_reads 3111234049 # number of integer regfile reads
system.cpu.int_regfile_writes 1733847214 # number of integer regfile writes
system.cpu.ipc 1.308837 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.308837 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2348064 0.12% 0.12% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1272739342 66.91% 67.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 456676516 24.01% 91.05% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 170264562 8.95% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 1902028484 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 11137895 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.005856 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 1120921 10.06% 10.06% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 7318318 65.71% 75.77% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 2698656 24.23% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 1143516922 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.663315 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.649679 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 363234856 31.76% 31.76% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 268152711 23.45% 55.21% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 190268701 16.64% 71.85% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 150184864 13.13% 84.99% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 96042571 8.40% 93.39% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 45507451 3.98% 97.37% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 20662852 1.81% 99.17% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 8604200 0.75% 99.92% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 858716 0.08% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 1143516922 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.628165 # Inst issue rate
system.cpu.iq.FU_type_0::No_OpClass 2348064 0.12% 0.12% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1272739342 66.91% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.04% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 456676516 24.01% 91.05% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 170264562 8.95% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 1902028484 # Type of FU issued
system.cpu.iq.fp_alu_accesses 77 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 156 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 40 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 7351 # Number of floating instruction queue writes
system.cpu.iq.fu_busy_cnt 11137895 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.005856 # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 1120921 10.06% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.06% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 7318318 65.71% 75.77% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 2698656 24.23% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.int_alu_accesses 1910818238 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 4959453857 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 1858331376 # Number of integer instruction queue wakeup accesses
@ -361,6 +343,24 @@ system.cpu.iq.iqSquashedInstsExamined 793159883 # Nu
system.cpu.iq.iqSquashedInstsIssued 742228 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 9106 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 1353359987 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.issued_per_cycle::samples 1143516922 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.663315 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.649679 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 363234856 31.76% 31.76% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 268152711 23.45% 55.21% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 190268701 16.64% 71.85% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 150184864 13.13% 84.99% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 96042571 8.40% 93.39% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 45507451 3.98% 97.37% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 20662852 1.81% 99.17% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 8604200 0.75% 99.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 858716 0.08% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 1143516922 # Number of insts issued each cycle
system.cpu.iq.rate 1.628165 # Inst issue rate
system.cpu.l2cache.ReadExReq_accesses 775816 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34258.394889 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31002.535640 # average ReadExReq mshr miss latency
@ -415,10 +415,10 @@ system.cpu.l2cache.demand_mshr_misses 586530 # nu
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.236559 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.418198 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 7751.549385 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 13703.522900 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.236559 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.418198 # Average percentage of cache occupancy
system.cpu.l2cache.overall_accesses 2544473 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34201.394643 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31004.134486 # average overall mshr miss latency
@ -448,28 +448,28 @@ system.cpu.misc_regfile_reads 1024751398 # nu
system.cpu.numCycles 1168204079 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 50725953 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 1427299027 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 53866080 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 461056510 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 71664979 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 8215 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 5693696762 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 2424853504 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 2263021553 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 385257729 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 108207267 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 138255029 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 835722526 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 18042 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 5693678720 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 14434 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 2322 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 301380597 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 2286 # count of temporary serializing insts renamed
system.cpu.rename.BlockCycles 50725953 # Number of cycles rename is blocking
system.cpu.rename.CommittedMaps 1427299027 # Number of HB maps that are committed
system.cpu.rename.IQFullEvents 53866080 # Number of times rename has blocked due to IQ full
system.cpu.rename.IdleCycles 461056510 # Number of cycles rename is idle
system.cpu.rename.LSQFullEvents 71664979 # Number of times rename has blocked due to LSQ full
system.cpu.rename.ROBFullEvents 8215 # Number of times rename has blocked due to ROB full
system.cpu.rename.RenameLookups 5693696762 # Number of register rename lookups that rename has made
system.cpu.rename.RenamedInsts 2424853504 # Number of instructions processed by rename
system.cpu.rename.RenamedOperands 2263021553 # Number of destination operands rename has renamed
system.cpu.rename.RunCycles 385257729 # Number of cycles rename is running
system.cpu.rename.SquashCycles 108207267 # Number of cycles rename is squashing
system.cpu.rename.UnblockCycles 138255029 # Number of cycles rename is unblocking
system.cpu.rename.UndoneMaps 835722526 # Number of HB maps that are undone due to squashing
system.cpu.rename.fp_rename_lookups 18042 # Number of floating rename lookups
system.cpu.rename.int_rename_lookups 5693678720 # Number of integer rename lookups
system.cpu.rename.serializeStallCycles 14434 # count of cycles rename stalled for serializing inst
system.cpu.rename.serializingInsts 2322 # count of serializing insts renamed
system.cpu.rename.skidInsts 301380597 # count of insts added to the skid buffer
system.cpu.rename.tempSerializingInsts 2286 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 3319156234 # The number of ROB reads
system.cpu.rob.rob_writes 4758159890 # The number of ROB writes
system.cpu.timesIdled 639156 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 551 # Number of system calls
system.cpu.workload.num_syscalls 551 # Number of system calls
---------- End Simulation Statistics ----------

2
tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini
View file

@ -61,7 +61,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=parser 2.1.dict -batch
cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic
cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic
egid=100
env=
errout=cerr

9
tests/long/20.parser/ref/x86/linux/simple-atomic/simout
View file

@ -5,11 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 11 2011 23:35:10
M5 revision c3deaa585dd3 7949 default qtip resforflagsstats.patch tip
M5 started Feb 11 2011 23:35:13
M5 executing on burrito
command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic
M5 compiled Apr 19 2011 12:22:33
M5 started Apr 19 2011 12:30:34
M5 executing on maize
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

10
tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1866600 # Simulator instruction rate (inst/s)
host_mem_usage 231212 # Number of bytes of host memory used
host_seconds 819.13 # Real time elapsed on the host
host_tick_rate 1080693863 # Simulator tick rate (ticks/s)
host_inst_rate 3416660 # Simulator instruction rate (inst/s)
host_mem_usage 206360 # Number of bytes of host memory used
host_seconds 447.51 # Real time elapsed on the host
host_tick_rate 1978121798 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1528988757 # Number of instructions simulated
sim_seconds 0.885229 # Number of seconds simulated
@ -29,6 +29,6 @@ system.cpu.num_int_register_writes 1427299027 # nu
system.cpu.num_load_insts 384102160 # Number of load instructions
system.cpu.num_mem_refs 533262345 # number of memory refs
system.cpu.num_store_insts 149160185 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 551 # Number of system calls
system.cpu.workload.num_syscalls 551 # Number of system calls
---------- End Simulation Statistics ----------

5
tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
View file

@ -51,6 +51,7 @@ assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
@ -86,6 +87,7 @@ assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
@ -121,6 +123,7 @@ assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=10000
max_miss_count=0
mshrs=10
@ -161,7 +164,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=parser 2.1.dict -batch
cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing
cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing
egid=100
env=
errout=cerr

9
tests/long/20.parser/ref/x86/linux/simple-timing/simout
View file

@ -5,11 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 11 2011 23:35:10
M5 revision c3deaa585dd3 7949 default qtip resforflagsstats.patch tip
M5 started Feb 11 2011 23:35:13
M5 executing on burrito
command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing
M5 compiled Apr 19 2011 12:22:33
M5 started Apr 19 2011 12:27:05
M5 executing on maize
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

18
tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1188316 # Simulator instruction rate (inst/s)
host_mem_usage 238940 # Number of bytes of host memory used
host_seconds 1286.69 # Real time elapsed on the host
host_tick_rate 1289149200 # Simulator tick rate (ticks/s)
host_inst_rate 2070048 # Simulator instruction rate (inst/s)
host_mem_usage 214112 # Number of bytes of host memory used
host_seconds 738.62 # Real time elapsed on the host
host_tick_rate 2245699490 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1528988757 # Number of instructions simulated
sim_seconds 1.658730 # Number of seconds simulated
@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses 2518458 # nu
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.997674 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4086.472055 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.997674 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses 533262390 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 23627.363053 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 20627.360075 # average overall mshr miss latency
@ -105,8 +105,8 @@ system.cpu.icache.demand_mshr_misses 2814 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.430777 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 882.231489 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.430777 # Average percentage of cache occupancy
system.cpu.icache.overall_accesses 1068347110 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 48641.791045 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 45641.791045 # average overall mshr miss latency
@ -173,10 +173,10 @@ system.cpu.l2cache.demand_mshr_misses 579609 # nu
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.230381 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.417452 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 7549.128601 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 13679.064710 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.230381 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.417452 # Average percentage of cache occupancy
system.cpu.l2cache.overall_accesses 2521272 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000.010352 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
@ -218,6 +218,6 @@ system.cpu.num_int_register_writes 1427299027 # nu
system.cpu.num_load_insts 384102160 # Number of load instructions
system.cpu.num_mem_refs 533262345 # number of memory refs
system.cpu.num_store_insts 149160185 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 551 # Number of system calls
system.cpu.workload.num_syscalls 551 # Number of system calls
---------- End Simulation Statistics ----------

2
tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
View file

@ -25,6 +25,8 @@ BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
RASSize=16
SQEntries=32
SSITSize=1024

6
tests/long/30.eon/ref/alpha/tru64/o3-timing/simout
View file

@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Mar 17 2011 21:44:37
M5 started Mar 17 2011 21:58:43
M5 executing on zizzer
M5 compiled Apr 19 2011 11:52:53
M5 started Apr 19 2011 11:58:24
M5 executing on maize
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

336
tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 169900 # Simulator instruction rate (inst/s)
host_mem_usage 215004 # Number of bytes of host memory used
host_seconds 2210.56 # Real time elapsed on the host
host_tick_rate 51124064 # Simulator tick rate (ticks/s)
host_inst_rate 334419 # Simulator instruction rate (inst/s)
host_mem_usage 210864 # Number of bytes of host memory used
host_seconds 1123.07 # Real time elapsed on the host
host_tick_rate 100628798 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 375574812 # Number of instructions simulated
sim_seconds 0.113013 # Number of seconds simulated
@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 5223677 # Nu
system.cpu.BPredUnit.condPredicted 31927422 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 56786170 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 11422526 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 44587533 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 16035403 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 216073988 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.845037 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 2.480996 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 99774969 46.18% 46.18% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 35667629 16.51% 62.68% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 19281907 8.92% 71.61% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 16238513 7.52% 79.12% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 11569134 5.35% 84.48% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 7732170 3.58% 88.06% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 5922846 2.74% 90.80% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 3851417 1.78% 92.58% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 16035403 7.42% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 216073988 # Number of insts commited each cycle
system.cpu.commit.COM:count 398664587 # Number of instructions committed
system.cpu.commit.COM:fp_insts 155295106 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 8007752 # Number of function calls committed.
system.cpu.commit.COM:int_insts 316365844 # Number of committed integer instructions.
system.cpu.commit.COM:loads 94754489 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 168275218 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 5219312 # The number of times a branch was mispredicted
system.cpu.commit.branches 44587533 # Number of branches committed
system.cpu.commit.bw_lim_events 16035403 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.commitCommittedInsts 398664587 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 56265161 # The number of squashed insts skipped by commit
system.cpu.commit.committed_per_cycle::samples 216073988 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.845037 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.480996 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 99774969 46.18% 46.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 35667629 16.51% 62.68% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 19281907 8.92% 71.61% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 16238513 7.52% 79.12% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 11569134 5.35% 84.48% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 7732170 3.58% 88.06% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 5922846 2.74% 90.80% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 3851417 1.78% 92.58% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 16035403 7.42% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 216073988 # Number of insts commited each cycle
system.cpu.commit.count 398664587 # Number of instructions committed
system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions.
system.cpu.commit.function_calls 8007752 # Number of function calls committed.
system.cpu.commit.int_insts 316365844 # Number of committed integer instructions.
system.cpu.commit.loads 94754489 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.refs 168275218 # Number of memory references committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.committedInsts 375574812 # Number of Instructions Simulated
system.cpu.committedInsts_total 375574812 # Number of Instructions Simulated
system.cpu.cpi 0.601812 # CPI: Cycles Per Instruction
@ -98,8 +98,8 @@ system.cpu.dcache.demand_mshr_misses 4182 # nu
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.803985 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 3293.121210 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.803985 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses 166720564 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 30468.976321 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 34627.570540 # average overall mshr miss latency
@ -121,15 +121,15 @@ system.cpu.dcache.tagsinuse 3293.121210 # Cy
system.cpu.dcache.total_refs 166701099 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 664 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 5613634 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 4438 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 10679460 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 490538381 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 118863884 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 90994213 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 9813191 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 13275 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 602257 # Number of cycles decode is unblocking
system.cpu.decode.BlockedCycles 5613634 # Number of cycles decode is blocked
system.cpu.decode.BranchMispred 4438 # Number of times decode detected a branch misprediction
system.cpu.decode.BranchResolved 10679460 # Number of times decode resolved a branch
system.cpu.decode.DecodedInsts 490538381 # Number of instructions handled by decode
system.cpu.decode.IdleCycles 118863884 # Number of cycles decode is idle
system.cpu.decode.RunCycles 90994213 # Number of cycles decode is running
system.cpu.decode.SquashCycles 9813191 # Number of cycles decode is squashing
system.cpu.decode.SquashedInsts 13275 # Number of squashed instructions handled by decode
system.cpu.decode.UnblockCycles 602257 # Number of cycles decode is unblocking
system.cpu.dtb.data_accesses 183645342 # DTB accesses
system.cpu.dtb.data_acv 48603 # DTB access violations
system.cpu.dtb.data_hits 183566296 # DTB hits
@ -209,8 +209,8 @@ system.cpu.icache.demand_mshr_misses 3907 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.890605 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1823.959859 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.890605 # Average percentage of cache occupancy
system.cpu.icache.overall_accesses 58423687 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 32309.424084 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 30830.816483 # average overall mshr miss latency
@ -233,21 +233,13 @@ system.cpu.icache.total_refs 58418912 # To
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 138291 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 48687009 # Number of branches executed
system.cpu.iew.EXEC:nop 26082950 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.805331 # Inst execution rate
system.cpu.iew.EXEC:refs 183693980 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 79967080 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 258989364 # num instructions consuming a value
system.cpu.iew.WB:count 404042671 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.726642 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 188192474 # num instructions producing a value
system.cpu.iew.WB:rate 1.787598 # insts written-back per cycle
system.cpu.iew.WB:sent 405020447 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 5625617 # Number of branch mispredicts detected at execute
system.cpu.iew.exec_branches 48687009 # Number of branches executed
system.cpu.iew.exec_nop 26082950 # number of nop insts executed
system.cpu.iew.exec_rate 1.805331 # Inst execution rate
system.cpu.iew.exec_refs 183693980 # number of memory reference insts executed
system.cpu.iew.exec_stores 79967080 # Number of stores executed
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.iewBlockCycles 1911401 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 106982646 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 239 # Number of dispatched non-speculative instructions
@ -275,103 +267,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 12856211 #
system.cpu.iew.memOrderViolationEvents 5629 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 886790 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 4738827 # Number of branches that were predicted taken incorrectly
system.cpu.iew.wb_consumers 258989364 # num instructions consuming a value
system.cpu.iew.wb_count 404042671 # cumulative count of insts written-back
system.cpu.iew.wb_fanout 0.726642 # average fanout of values written-back
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_producers 188192474 # num instructions producing a value
system.cpu.iew.wb_rate 1.787598 # insts written-back per cycle
system.cpu.iew.wb_sent 405020447 # cumulative count of insts sent to commit
system.cpu.int_regfile_reads 406883956 # number of integer regfile reads
system.cpu.int_regfile_writes 173490032 # number of integer regfile writes
system.cpu.ipc 1.661648 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.661648 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 165161738 39.53% 39.53% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 2124398 0.51% 40.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 40.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 33524704 8.02% 48.07% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 7711996 1.85% 49.91% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2967896 0.71% 50.62% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 16674434 3.99% 54.61% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 1571336 0.38% 54.99% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 105669831 25.29% 80.28% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 82413056 19.72% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 417852970 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 10358398 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.024790 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 4298 0.04% 0.04% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.04% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.04% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 768 0.01% 0.05% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 7 0.00% 0.05% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 10130 0.10% 0.15% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 1743113 16.83% 16.97% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 627758 6.06% 23.04% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 5427565 52.40% 75.43% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 2544759 24.57% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 225887179 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.849830 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.928832 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 80384230 35.59% 35.59% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 40475639 17.92% 53.50% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 30160734 13.35% 66.86% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 26305410 11.65% 78.50% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 21278104 9.42% 87.92% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 14868616 6.58% 94.50% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 9130443 4.04% 98.55% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 2370545 1.05% 99.60% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 913458 0.40% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 225887179 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.848699 # Inst issue rate
system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 165161738 39.53% 39.53% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 2124398 0.51% 40.04% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 40.04% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 33524704 8.02% 48.07% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 7711996 1.85% 49.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 2967896 0.71% 50.62% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 16674434 3.99% 54.61% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 1571336 0.38% 54.99% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 105669831 25.29% 80.28% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 82413056 19.72% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 417852970 # Type of FU issued
system.cpu.iq.fp_alu_accesses 175354000 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 344883249 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 164390765 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 192579711 # Number of floating instruction queue writes
system.cpu.iq.fu_busy_cnt 10358398 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.024790 # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 4298 0.04% 0.04% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 0.04% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 768 0.01% 0.05% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 7 0.00% 0.05% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 10130 0.10% 0.15% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 1743113 16.83% 16.97% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 627758 6.06% 23.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 5427565 52.40% 75.43% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 2544759 24.57% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.int_alu_accesses 252823787 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 727796795 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 239651906 # Number of integer instruction queue wakeup accesses
@ -383,6 +365,24 @@ system.cpu.iq.iqSquashedInstsExamined 47599271 # Nu
system.cpu.iq.iqSquashedInstsIssued 728527 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 28893091 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.issued_per_cycle::samples 225887179 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.849830 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.928832 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 80384230 35.59% 35.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 40475639 17.92% 53.50% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 30160734 13.35% 66.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 26305410 11.65% 78.50% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 21278104 9.42% 87.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 14868616 6.58% 94.50% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 9130443 4.04% 98.55% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 2370545 1.05% 99.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 913458 0.40% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 225887179 # Number of insts issued each cycle
system.cpu.iq.rate 1.848699 # Inst issue rate
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
@ -443,10 +443,10 @@ system.cpu.l2cache.demand_mshr_misses 7364 # nu
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.108576 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.011590 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 3557.826949 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 379.777727 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.108576 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.011590 # Average percentage of cache occupancy
system.cpu.l2cache.overall_accesses 8089 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34457.903313 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31289.109180 # average overall mshr miss latency
@ -477,28 +477,28 @@ system.cpu.misc_regfile_writes 1 # nu
system.cpu.numCycles 226025470 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 3360184 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 259532333 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 311 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 122116498 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 1529212 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 625408393 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 477751875 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 306658733 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 88296359 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 9813191 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 1960754 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 47126400 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 292973848 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 332434545 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 340193 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 36156 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 5383709 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 253 # count of temporary serializing insts renamed
system.cpu.rename.BlockCycles 3360184 # Number of cycles rename is blocking
system.cpu.rename.CommittedMaps 259532333 # Number of HB maps that are committed
system.cpu.rename.IQFullEvents 311 # Number of times rename has blocked due to IQ full
system.cpu.rename.IdleCycles 122116498 # Number of cycles rename is idle
system.cpu.rename.LSQFullEvents 1529212 # Number of times rename has blocked due to LSQ full
system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full
system.cpu.rename.RenameLookups 625408393 # Number of register rename lookups that rename has made
system.cpu.rename.RenamedInsts 477751875 # Number of instructions processed by rename
system.cpu.rename.RenamedOperands 306658733 # Number of destination operands rename has renamed
system.cpu.rename.RunCycles 88296359 # Number of cycles rename is running
system.cpu.rename.SquashCycles 9813191 # Number of cycles rename is squashing
system.cpu.rename.UnblockCycles 1960754 # Number of cycles rename is unblocking
system.cpu.rename.UndoneMaps 47126400 # Number of HB maps that are undone due to squashing
system.cpu.rename.fp_rename_lookups 292973848 # Number of floating rename lookups
system.cpu.rename.int_rename_lookups 332434545 # Number of integer rename lookups
system.cpu.rename.serializeStallCycles 340193 # count of cycles rename stalled for serializing inst
system.cpu.rename.serializingInsts 36156 # count of serializing insts renamed
system.cpu.rename.skidInsts 5383709 # count of insts added to the skid buffer
system.cpu.rename.tempSerializingInsts 253 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 654965356 # The number of ROB reads
system.cpu.rob.rob_writes 919674888 # The number of ROB writes
system.cpu.timesIdled 3011 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
system.cpu.workload.num_syscalls 215 # Number of system calls
---------- End Simulation Statistics ----------

7
tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout
View file

@ -5,10 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 7 2011 01:47:18
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Feb 7 2011 01:47:38
M5 executing on burrito
M5 compiled Apr 19 2011 11:52:53
M5 started Apr 19 2011 12:03:34
M5 executing on maize
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

10
tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1382202 # Simulator instruction rate (inst/s)
host_mem_usage 224632 # Number of bytes of host memory used
host_seconds 288.43 # Real time elapsed on the host
host_tick_rate 691100750 # Simulator tick rate (ticks/s)
host_inst_rate 5567399 # Simulator instruction rate (inst/s)
host_mem_usage 202284 # Number of bytes of host memory used
host_seconds 71.61 # Real time elapsed on the host
host_tick_rate 2783694716 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 398664595 # Number of instructions simulated
sim_seconds 0.199332 # Number of seconds simulated
@ -61,6 +61,6 @@ system.cpu.num_int_register_writes 159335860 # nu
system.cpu.num_load_insts 94754510 # Number of load instructions
system.cpu.num_mem_refs 168275274 # number of memory refs
system.cpu.num_store_insts 73520764 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
system.cpu.workload.num_syscalls 215 # Number of system calls
---------- End Simulation Statistics ----------

3
tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
View file

@ -51,6 +51,7 @@ assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
@ -86,6 +87,7 @@ assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
@ -121,6 +123,7 @@ assoc=2
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=10000
max_miss_count=0
mshrs=10

7
tests/long/30.eon/ref/alpha/tru64/simple-timing/simout
View file

@ -5,10 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 7 2011 01:47:18
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Feb 7 2011 01:47:38
M5 executing on burrito
M5 compiled Apr 19 2011 11:52:53
M5 started Apr 19 2011 12:04:03
M5 executing on maize
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

18
tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 531142 # Simulator instruction rate (inst/s)
host_mem_usage 232344 # Number of bytes of host memory used
host_seconds 750.58 # Real time elapsed on the host
host_tick_rate 755872580 # Simulator tick rate (ticks/s)
host_inst_rate 2583171 # Simulator instruction rate (inst/s)
host_mem_usage 210032 # Number of bytes of host memory used
host_seconds 154.33 # Real time elapsed on the host
host_tick_rate 3676130341 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 398664609 # Number of instructions simulated
sim_seconds 0.567343 # Number of seconds simulated
@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses 4152 # nu
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.802957 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 3288.912598 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.802957 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses 168275220 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 54209.537572 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 51209.537572 # average overall mshr miss latency
@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses 3673 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.876529 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1795.131074 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.876529 # Average percentage of cache occupancy
system.cpu.icache.overall_accesses 398664666 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 50648.516199 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 47648.516199 # average overall mshr miss latency
@ -205,10 +205,10 @@ system.cpu.l2cache.demand_mshr_misses 7180 # nu
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.103674 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.011338 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 3397.175455 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 371.536808 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.103674 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.011338 # Average percentage of cache occupancy
system.cpu.l2cache.overall_accesses 7825 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
@ -250,6 +250,6 @@ system.cpu.num_int_register_writes 159335870 # nu
system.cpu.num_load_insts 94754511 # Number of load instructions
system.cpu.num_mem_refs 168275276 # number of memory refs
system.cpu.num_store_insts 73520765 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
system.cpu.workload.num_syscalls 215 # Number of system calls
---------- End Simulation Statistics ----------

2
tests/long/30.eon/ref/arm/linux/o3-timing/config.ini
View file

@ -498,7 +498,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/arm/scratch/alisai01/dist/cpu2000/binaries/arm/linux/eon
executable=/dist/m5/cpu2000/binaries/arm/linux/eon
gid=100
input=cin
max_stack_size=67108864

8
tests/long/30.eon/ref/arm/linux/o3-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Mar 30 2011 17:47:57
M5 started Mar 30 2011 18:04:19
M5 executing on u200439-lin.austin.arm.com
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing
M5 compiled Apr 19 2011 12:47:10
M5 started Apr 19 2011 12:56:09
M5 executing on maize
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

336
tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 203026 # Simulator instruction rate (inst/s)
host_mem_usage 267492 # Number of bytes of host memory used
host_seconds 1719.32 # Real time elapsed on the host
host_tick_rate 88254289 # Simulator tick rate (ticks/s)
host_inst_rate 250845 # Simulator instruction rate (inst/s)
host_mem_usage 223896 # Number of bytes of host memory used
host_seconds 1391.56 # Real time elapsed on the host
host_tick_rate 109041329 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 349065985 # Number of instructions simulated
sim_seconds 0.151737 # Number of seconds simulated
@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 3421912 # Nu
system.cpu.BPredUnit.condPredicted 20033400 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 36581771 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 7288333 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 30521887 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 7594485 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 297396946 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.173740 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.829368 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 153798947 51.72% 51.72% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 68683080 23.09% 74.81% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 27481761 9.24% 84.05% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 16045950 5.40% 89.45% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 11196284 3.76% 93.21% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 6591467 2.22% 95.43% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 3251010 1.09% 96.52% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 2753962 0.93% 97.45% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 7594485 2.55% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 297396946 # Number of insts commited each cycle
system.cpu.commit.COM:count 349066597 # Number of instructions committed
system.cpu.commit.COM:fp_insts 114216705 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 6225112 # Number of function calls committed.
system.cpu.commit.COM:int_insts 287529375 # Number of committed integer instructions.
system.cpu.commit.COM:loads 94648997 # Number of loads committed
system.cpu.commit.COM:membars 11033 # Number of memory barriers committed
system.cpu.commit.COM:refs 177024839 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 3392850 # The number of times a branch was mispredicted
system.cpu.commit.branches 30521887 # Number of branches committed
system.cpu.commit.bw_lim_events 7594485 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.commitCommittedInsts 349066597 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 3555476 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 29812251 # The number of squashed insts skipped by commit
system.cpu.commit.committed_per_cycle::samples 297396946 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.173740 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.829368 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 153798947 51.72% 51.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 68683080 23.09% 74.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 27481761 9.24% 84.05% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 16045950 5.40% 89.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 11196284 3.76% 93.21% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 6591467 2.22% 95.43% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 3251010 1.09% 96.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 2753962 0.93% 97.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 7594485 2.55% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 297396946 # Number of insts commited each cycle
system.cpu.commit.count 349066597 # Number of instructions committed
system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions.
system.cpu.commit.function_calls 6225112 # Number of function calls committed.
system.cpu.commit.int_insts 287529375 # Number of committed integer instructions.
system.cpu.commit.loads 94648997 # Number of loads committed
system.cpu.commit.membars 11033 # Number of memory barriers committed
system.cpu.commit.refs 177024839 # Number of memory references committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.committedInsts 349065985 # Number of Instructions Simulated
system.cpu.committedInsts_total 349065985 # Number of Instructions Simulated
system.cpu.cpi 0.869391 # CPI: Cycles Per Instruction
@ -105,8 +105,8 @@ system.cpu.dcache.demand_mshr_misses 4561 # nu
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.753211 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 3085.152893 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.753211 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses 177564090 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 32354.475913 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 33694.694146 # average overall mshr miss latency
@ -128,15 +128,15 @@ system.cpu.dcache.tagsinuse 3085.152893 # Cy
system.cpu.dcache.total_refs 177564704 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 1021 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 139649394 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 71446 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 7239931 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 408881420 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 85142692 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 69995506 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 5956648 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 202337 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 2609353 # Number of cycles decode is unblocking
system.cpu.decode.BlockedCycles 139649394 # Number of cycles decode is blocked
system.cpu.decode.BranchMispred 71446 # Number of times decode detected a branch misprediction
system.cpu.decode.BranchResolved 7239931 # Number of times decode resolved a branch
system.cpu.decode.DecodedInsts 408881420 # Number of instructions handled by decode
system.cpu.decode.IdleCycles 85142692 # Number of cycles decode is idle
system.cpu.decode.RunCycles 69995506 # Number of cycles decode is running
system.cpu.decode.SquashCycles 5956648 # Number of cycles decode is squashing
system.cpu.decode.SquashedInsts 202337 # Number of squashed instructions handled by decode
system.cpu.decode.UnblockCycles 2609353 # Number of cycles decode is unblocking
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
@ -221,8 +221,8 @@ system.cpu.icache.demand_mshr_misses 15647 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.891809 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1826.425729 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.891809 # Average percentage of cache occupancy
system.cpu.icache.overall_accesses 38750811 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 11739.616414 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 8345.912955 # average overall mshr miss latency
@ -245,21 +245,13 @@ system.cpu.icache.total_refs 38734752 # To
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 121166 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 31598497 # Number of branches executed
system.cpu.iew.EXEC:nop 47916 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.198862 # Inst execution rate
system.cpu.iew.EXEC:refs 183613240 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 84389722 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 302337892 # num instructions consuming a value
system.cpu.iew.WB:count 361679600 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.513512 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 155254133 # num instructions producing a value
system.cpu.iew.WB:rate 1.191795 # insts written-back per cycle
system.cpu.iew.WB:sent 362096434 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 3575174 # Number of branch mispredicts detected at execute
system.cpu.iew.exec_branches 31598497 # Number of branches executed
system.cpu.iew.exec_nop 47916 # number of nop insts executed
system.cpu.iew.exec_rate 1.198862 # Inst execution rate
system.cpu.iew.exec_refs 183613240 # number of memory reference insts executed
system.cpu.iew.exec_stores 84389722 # Number of stores executed
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.iewBlockCycles 6232 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 104118233 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 3634513 # Number of dispatched non-speculative instructions
@ -287,103 +279,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 6767279 #
system.cpu.iew.memOrderViolationEvents 165832 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 360118 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 3215056 # Number of branches that were predicted taken incorrectly
system.cpu.iew.wb_consumers 302337892 # num instructions consuming a value
system.cpu.iew.wb_count 361679600 # cumulative count of insts written-back
system.cpu.iew.wb_fanout 0.513512 # average fanout of values written-back
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_producers 155254133 # num instructions producing a value
system.cpu.iew.wb_rate 1.191795 # insts written-back per cycle
system.cpu.iew.wb_sent 362096434 # cumulative count of insts sent to commit
system.cpu.int_regfile_reads 845155916 # number of integer regfile reads
system.cpu.int_regfile_writes 184404886 # number of integer regfile writes
system.cpu.ipc 1.150231 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.150231 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 125135876 34.07% 34.07% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 2147375 0.58% 34.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 34.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 3 0.00% 34.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 34.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 34.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 34.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 34.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 34.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 34.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 34.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 34.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 34.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 34.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 34.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 34.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 34.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 34.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 34.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 34.65% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 6684118 1.82% 36.47% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 36.47% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 8302383 2.26% 38.73% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 3402331 0.93% 39.66% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 1567187 0.43% 40.09% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 20210889 5.50% 45.59% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 7197544 1.96% 47.55% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 7077346 1.93% 49.48% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 175286 0.05% 49.52% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 100106815 27.25% 76.78% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 85290782 23.22% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 367297935 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 12277552 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.033427 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 1371 0.01% 0.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 5040 0.04% 0.05% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.05% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.05% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.05% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.05% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.05% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.05% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.05% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.05% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.05% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.05% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.05% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.05% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.05% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.05% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.05% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.05% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.05% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.05% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 66 0.00% 0.05% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.05% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.05% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 1306 0.01% 0.06% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 3 0.00% 0.06% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 233643 1.90% 1.97% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 626 0.01% 1.97% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 321940 2.62% 4.59% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 4.59% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 7517293 61.23% 65.82% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 4196264 34.18% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 303353593 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.210791 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.640692 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 151157606 49.83% 49.83% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 63646504 20.98% 70.81% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 27917034 9.20% 80.01% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 21656943 7.14% 87.15% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 21437631 7.07% 94.22% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 10744150 3.54% 97.76% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 4648214 1.53% 99.29% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 1678112 0.55% 99.85% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 467399 0.15% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 303353593 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.210308 # Inst issue rate
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 125135876 34.07% 34.07% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 2147375 0.58% 34.65% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.65% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 34.65% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.65% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.65% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.65% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.65% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.65% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.65% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.65% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.65% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 34.65% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.65% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.65% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.65% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.65% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.65% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.65% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.65% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 6684118 1.82% 36.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 8302383 2.26% 38.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 3402331 0.93% 39.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 1567187 0.43% 40.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 20210889 5.50% 45.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 7197544 1.96% 47.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 7077346 1.93% 49.48% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.52% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 100106815 27.25% 76.78% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 85290782 23.22% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 367297935 # Type of FU issued
system.cpu.iq.fp_alu_accesses 125160042 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 243629757 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 116471069 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 124289037 # Number of floating instruction queue writes
system.cpu.iq.fu_busy_cnt 12277552 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.033427 # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 1371 0.01% 0.01% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 5040 0.04% 0.05% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.05% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.05% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.05% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.05% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 0.05% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.05% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.05% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.05% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.05% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.05% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.05% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.05% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.05% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 0.05% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.05% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.05% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.05% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.05% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 66 0.00% 0.05% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.05% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.05% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 1306 0.01% 0.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 233643 1.90% 1.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 626 0.01% 1.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 321940 2.62% 4.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.59% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 7517293 61.23% 65.82% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 4196264 34.18% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.int_alu_accesses 254415445 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 807801978 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 245208531 # Number of integer instruction queue wakeup accesses
@ -395,6 +377,24 @@ system.cpu.iq.iqSquashedInstsExamined 27882412 # Nu
system.cpu.iq.iqSquashedInstsIssued 1204720 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 90285 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 56560737 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.issued_per_cycle::samples 303353593 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.210791 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.640692 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 151157606 49.83% 49.83% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 63646504 20.98% 70.81% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 27917034 9.20% 80.01% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 21656943 7.14% 87.15% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 21437631 7.07% 94.22% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 10744150 3.54% 97.76% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 4648214 1.53% 99.29% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 1678112 0.55% 99.85% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 467399 0.15% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 303353593 # Number of insts issued each cycle
system.cpu.iq.rate 1.210308 # Inst issue rate
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
@ -468,10 +468,10 @@ system.cpu.l2cache.demand_mshr_misses 7094 # nu
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.103738 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.011318 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 3399.287353 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 370.862974 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.103738 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.011318 # Average percentage of cache occupancy
system.cpu.l2cache.overall_accesses 20201 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34371.098670 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31194.530589 # average overall mshr miss latency
@ -502,28 +502,28 @@ system.cpu.misc_regfile_writes 34422259 # nu
system.cpu.numCycles 303474759 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 833030 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 340927172 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 47966 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 92085018 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 4772387 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 1 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 1568873073 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 396996902 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 382623172 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 66169446 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 5956648 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 17891726 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 41695997 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 798025803 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 770847270 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 120417725 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 12413036 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 58729283 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 3692499 # count of temporary serializing insts renamed
system.cpu.rename.BlockCycles 833030 # Number of cycles rename is blocking
system.cpu.rename.CommittedMaps 340927172 # Number of HB maps that are committed
system.cpu.rename.IQFullEvents 47966 # Number of times rename has blocked due to IQ full
system.cpu.rename.IdleCycles 92085018 # Number of cycles rename is idle
system.cpu.rename.LSQFullEvents 4772387 # Number of times rename has blocked due to LSQ full
system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full
system.cpu.rename.RenameLookups 1568873073 # Number of register rename lookups that rename has made
system.cpu.rename.RenamedInsts 396996902 # Number of instructions processed by rename
system.cpu.rename.RenamedOperands 382623172 # Number of destination operands rename has renamed
system.cpu.rename.RunCycles 66169446 # Number of cycles rename is running
system.cpu.rename.SquashCycles 5956648 # Number of cycles rename is squashing
system.cpu.rename.UnblockCycles 17891726 # Number of cycles rename is unblocking
system.cpu.rename.UndoneMaps 41695997 # Number of HB maps that are undone due to squashing
system.cpu.rename.fp_rename_lookups 798025803 # Number of floating rename lookups
system.cpu.rename.int_rename_lookups 770847270 # Number of integer rename lookups
system.cpu.rename.serializeStallCycles 120417725 # count of cycles rename stalled for serializing inst
system.cpu.rename.serializingInsts 12413036 # count of serializing insts renamed
system.cpu.rename.skidInsts 58729283 # count of insts added to the skid buffer
system.cpu.rename.tempSerializingInsts 3692499 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 668678786 # The number of ROB reads
system.cpu.rob.rob_writes 763715026 # The number of ROB writes
system.cpu.timesIdled 2617 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 191 # Number of system calls
system.cpu.workload.num_syscalls 191 # Number of system calls
---------- End Simulation Statistics ----------

4
tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini
View file

@ -61,12 +61,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
cwd=build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic
cwd=build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-atomic
egid=100
env=
errout=cerr
euid=100
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/eon
executable=/dist/m5/cpu2000/binaries/arm/linux/eon
gid=100
input=cin
max_stack_size=67108864

8
tests/long/30.eon/ref/arm/linux/simple-atomic/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Mar 30 2011 17:47:57
M5 started Mar 30 2011 18:05:11
M5 executing on u200439-lin.austin.arm.com
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic
M5 compiled Apr 19 2011 12:47:10
M5 started Apr 19 2011 12:58:30
M5 executing on maize
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

10
tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 854402 # Simulator instruction rate (inst/s)
host_mem_usage 255368 # Number of bytes of host memory used
host_seconds 408.55 # Real time elapsed on the host
host_tick_rate 519751077 # Simulator tick rate (ticks/s)
host_inst_rate 3277679 # Simulator instruction rate (inst/s)
host_mem_usage 214524 # Number of bytes of host memory used
host_seconds 106.50 # Real time elapsed on the host
host_tick_rate 1993879698 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 349065408 # Number of instructions simulated
sim_seconds 0.212344 # Number of seconds simulated
@ -71,6 +71,6 @@ system.cpu.num_int_register_writes 207564016 # nu
system.cpu.num_load_insts 94648758 # Number of load instructions
system.cpu.num_mem_refs 177024357 # number of memory refs
system.cpu.num_store_insts 82375599 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 191 # Number of system calls
system.cpu.workload.num_syscalls 191 # Number of system calls
---------- End Simulation Statistics ----------

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