4580 commits

Author	SHA1	Message	Date
Gabe Black	0fe0390f73	ARM: Clean up the implementation of the VFP instructions.	2010-06-02 12:58:16 -05:00
Gabe Black	c919ab5b4f	ARM: Fix double precision load/store multiple decrement. ... When decrementing, the higher addressed half of a double word is at a 4 byte smaller displacement.	2010-06-02 12:58:15 -05:00
Gabe Black	92bdf57be4	ARM: Even though writes to MVFR0/1 should be unpredictable, we need to make them to do nothing.	2010-06-02 12:58:15 -05:00
Gabe Black	4398075254	ARM: Make various bits of the FP control registers read only.	2010-06-02 12:58:15 -05:00
Gabe Black	2d08b8de91	ARM: Implement the version of VMRS that writes to the APSR.	2010-06-02 12:58:15 -05:00
Gabe Black	57c4d37c10	ARM: Ignore reads and writes to DCIMVAC.	2010-06-02 12:58:15 -05:00
Gabe Black	fd37095fa6	ARM: Make MPIDR return 0 and ignore writes.	2010-06-02 12:58:15 -05:00
Gabe Black	49b7088b91	ARM: Implement the VCMPE instruction.	2010-06-02 12:58:15 -05:00
Gabe Black	23ba9c7b96	ARM: Fix vcvtr so that it uses the rounding mode in the FPSCR.	2010-06-02 12:58:15 -05:00
Gabe Black	1fda944716	ARM: Fix saturation of VCVT from fp to integer.	2010-06-02 12:58:15 -05:00
Gabe Black	347ab6c704	ARM: Compensate for ARM's underflow coming from -before- rounding, but x86's after.	2010-06-02 12:58:15 -05:00
Gabe Black	fd82a47b96	ARM: Implement flush to zero for destinations as well.	2010-06-02 12:58:15 -05:00
Gabe Black	186273e5f3	ARM: Fix up nans to match ARM's expected behavior.	2010-06-02 12:58:15 -05:00
Gabe Black	98e2315f1c	ARM: Set the value of the MVFR0 and MVFR1 registers.	2010-06-02 12:58:15 -05:00
Gabe Black	8466999aef	ARM: Implement flush to zero mode for VFP, and clean up some corner cases.	2010-06-02 12:58:15 -05:00
Gabe Black	efbceff96a	ARM: Add barriers that make sure FP operations happen where they're supposed to.	2010-06-02 12:58:15 -05:00
Gabe Black	1b3b75ee68	ARM: Implement the version of VCVT float to int that rounds towards zero.	2010-06-02 12:58:15 -05:00
Gabe Black	aa05e5401c	ARM: Implement the floating/fixed point VCVT instructions.	2010-06-02 12:58:15 -05:00
Gabe Black	86a1093992	ARM: Add code to extract and record VFP exceptions.	2010-06-02 12:58:14 -05:00
Gabe Black	e478df35f5	ARM: Implement the VFP version of VCMP.	2010-06-02 12:58:14 -05:00
Gabe Black	c1f7bf7f0e	ARM: Add support for VFP vector mode.	2010-06-02 12:58:14 -05:00
Gabe Black	f245f4937b	ARM: Introduce new VFP base classes that are optionally microops.	2010-06-02 12:58:14 -05:00
Gabe Black	41012d2418	ARM: Implement VCVT between double and single width FP.	2010-06-02 12:58:14 -05:00
Gabe Black	a430f749ce	ARM: Implement vcvt between int and fp. Ignore rounding.	2010-06-02 12:58:14 -05:00
Gabe Black	a9d1de4769	ARM: Consolidate the VFP register index computation code.	2010-06-02 12:58:14 -05:00
Gabe Black	80fa3a7ccf	ARM: Implement the VFP negated multiplies.	2010-06-02 12:58:14 -05:00
Gabe Black	3111a62169	ARM: Implement the VFP versions of VMLA and VMLS.	2010-06-02 12:58:14 -05:00
Gabe Black	90d70a22cb	ARM: Implement the VFP version of vdiv and vsqrt.	2010-06-02 12:58:14 -05:00
Gabe Black	cc665240a4	ARM: Implement the VFP version of vsub.	2010-06-02 12:58:14 -05:00
Gabe Black	44759669aa	ARM: Implement the VFP version of vadd.	2010-06-02 12:58:14 -05:00
Gabe Black	9e32ff3491	ARM: Implement the VFP version of vabs.	2010-06-02 12:58:14 -05:00
Gabe Black	cd0a6a1303	ARM: Implement the VFP version of vneg.	2010-06-02 12:58:14 -05:00
Gabe Black	65f5204325	ARM: Implement the VFP version of vmul.	2010-06-02 12:58:14 -05:00
Gabe Black	19e05d7e8d	ARM: Move the VFP data operation decode into a function.	2010-06-02 12:58:14 -05:00
Gabe Black	527b735cfc	ARM: Implement and update the DFSR and IFSR registers on faults.	2010-06-02 12:58:14 -05:00
Gabe Black	4491170df6	ARM: Make integer division by zero return a fault.	2010-06-02 12:58:13 -05:00
Gabe Black	cd86e34187	ARM: Add in some missing SCTLR fields.	2010-06-02 12:58:13 -05:00
Gabe Black	c5a8a1d673	ARM: Decode ARM unconditional MRC and MCR instructions.	2010-06-02 12:58:13 -05:00
Gabe Black	98fe7b0fbe	ARM: Move the CP15 decode block into a function.	2010-06-02 12:58:13 -05:00
Gabe Black	5d9191a428	ARM: Decode the unconditional version of ARM fp instructions.	2010-06-02 12:58:13 -05:00
Gabe Black	81b7c3d264	ARM: Move the FP decode blocks into functions.	2010-06-02 12:58:13 -05:00
Gabe Black	e21f93702a	ARM: Warn/ignore when TLB maintenance operations are performed.	2010-06-02 12:58:13 -05:00
Gabe Black	eac239b4d6	ARM: Handle accesses to TLBTR.	2010-06-02 12:58:13 -05:00
Gabe Black	9fb573d91e	ARM: Handle accesses to the DACR.	2010-06-02 12:58:13 -05:00
Gabe Black	951b7edaba	ARM: Handle accesses to TTBR0 and TTBR1.	2010-06-02 12:58:13 -05:00
Gabe Black	b5cfa9361b	ARM: Convert the CP15 registers from MPU to MMU.	2010-06-02 12:58:13 -05:00
Ali Saidi	556ea0ee57	ARM: Add some support for wfi/wfe/yield/etc	2010-06-02 12:58:13 -05:00
Ali Saidi	5e6d28996a	ARM: Move PC mode bits around so they can be used for exectrace	2010-06-02 12:58:13 -05:00
Ali Saidi	aec73ba6af	ARM: Add a traceflag to print cpsr	2010-06-02 12:58:13 -05:00
Ali Saidi	65a5177b53	ARM: Undef instruction on invalid user CP15 access	2010-06-02 12:58:13 -05:00
Gabe Black	2e4ddbd234	ARM: Decode the VSTR instruction.	2010-06-02 12:58:12 -05:00
Gabe Black	6106bd18cd	ARM: Implement the vstr instruction.	2010-06-02 12:58:12 -05:00
Ali Saidi	f64c8bafd2	ARM: BXJ should be BX when there is no J support	2010-06-02 12:58:12 -05:00
Gabe Black	1fcd389fa3	ARM: Make sure macroops aren't interrupted midinstruction. ... Do this by setting the delayed commit flag for all but the last microop.	2010-06-02 12:58:12 -05:00
Gabe Black	67766cbf17	ARM: Fix the implementation of the VFP ldm and stm macroops. ... There were four bugs in these instructions. First, the loaded value was being stored into a floating point register as floating point, changing the value as it was transfered. Second, the meaning of the "up" bit had been reversed. Third, the statically sized microop array wasn't bit enough for all possible inputs. It's now dynamically sized and should always be big enough. Fourth, the offset was stored as an unsigned 8 bit value. Negative offsets would look like moderately large positive offsets.	2010-06-02 12:58:12 -05:00
Gabe Black	d149e43c41	Simple CPU: Make the FloatRegs trace flag do something.	2010-06-02 12:58:12 -05:00
Gabe Black	ad9c5af945	ARM: Fix up thumb decoding of coproc instructions.	2010-06-02 12:58:12 -05:00
Gabe Black	dea707704f	ARM: Clean up some redundancy and fault behavior for unimplemented thumb MCR, MRC.	2010-06-02 12:58:12 -05:00
Ali Saidi	b504b44b2f	CPU: Reset fetch offset after a exception	2010-06-02 12:58:12 -05:00
Gabe Black	943b77b9bb	ARM: Decode the VLDR instruction.	2010-06-02 12:58:12 -05:00
Gabe Black	4f130683e0	ARM: Implement the VLDR instruction.	2010-06-02 12:58:12 -05:00
Gabe Black	dbec303864	ARM: Decode all the various forms of vmov.	2010-06-02 12:58:12 -05:00
Gabe Black	ff3996b24d	ARM: Make VFP load/store and 64 bit move decode correspond with CP10 and CP11.	2010-06-02 12:58:12 -05:00
Gabe Black	dd1aedc98b	ARM: Implement the various versions of VMOV.	2010-06-02 12:58:12 -05:00
Gabe Black	1f059541d6	ARM: Add a new RegImmOp base class.	2010-06-02 12:58:12 -05:00
Gabe Black	6976b4890a	ARM: Add a RegRegImmOp base class.	2010-06-02 12:58:12 -05:00
Gabe Black	186cfe3ae3	ARM: Widen the immediate fields in the misc instruction classes.	2010-06-02 12:58:12 -05:00
Gabe Black	b87ebf382f	ARM: Add a function to decode VFP modified immediate constants.	2010-06-02 12:58:12 -05:00
Gabe Black	7eb4d02dd9	ARM: Add a function to decode SIMD modified immediate constants.	2010-06-02 12:58:12 -05:00
Gabe Black	abda50173c	ARM: Add fp operands to operands.isa.	2010-06-02 12:58:12 -05:00
Gabe Black	6365d29c21	ARM: Decode the VMRS instruction.	2010-06-02 12:58:11 -05:00
Gabe Black	fbf2ad5ae8	ARM: Update the set of FP related miscregs.	2010-06-02 12:58:11 -05:00
Gabe Black	aade63a8fe	ARM: Implement the VMRS instruction.	2010-06-02 12:58:11 -05:00
Gabe Black	a8b56b452c	ARM: Decode the VMSR instruction.	2010-06-02 12:58:11 -05:00
Gabe Black	06008c54eb	ARM: Implement the VMSR instruction.	2010-06-02 12:58:11 -05:00
Gabe Black	0ff71c7c34	ARM: Decode 8, 16, and 32 bit transfers between core and extension (fp) registers.	2010-06-02 12:58:11 -05:00
Gabe Black	c9c4dfc09d	ARM: Ignore attempts to disable coprocessors that aren't implemented anyway.	2010-06-02 12:58:11 -05:00
Gabe Black	c3bf29bbea	ARM: Implement the udiv instruction.	2010-06-02 12:58:11 -05:00
Gabe Black	f3e65c2de2	ARM: Implement the sdiv instruction.	2010-06-02 12:58:11 -05:00
Gabe Black	5943f0fc84	ARM: Ignore writing a bad mode to CPSR with MSR.	2010-06-02 12:58:11 -05:00
Gabe Black	ba33db8fd6	ARM: Decode the CPS instruction.	2010-06-02 12:58:11 -05:00
Gabe Black	7861b084f6	ARM: Implement the CPS instruction.	2010-06-02 12:58:11 -05:00
Gabe Black	eb1447302d	ARM: Decode the SRS instruction.	2010-06-02 12:58:11 -05:00
Gabe Black	bb6fea91da	ARM: Implement the SRS instruction.	2010-06-02 12:58:11 -05:00
Gabe Black	dbee6e0c54	ARM: Add a base class for SRS.	2010-06-02 12:58:11 -05:00
Gabe Black	239c9af90d	ARM: Implement a badMode function that says whether a mode is legal.	2010-06-02 12:58:11 -05:00
Gabe Black	a5ea52bb45	ARM: Allow flattening into any mode.	2010-06-02 12:58:11 -05:00
Gabe Black	698ee26c6b	ARM: Decode TBB and TBH.	2010-06-02 12:58:11 -05:00
Gabe Black	6fa713a66c	ARM: Decode the setend instruction.	2010-06-02 12:58:11 -05:00
Gabe Black	4683cd1655	ARM: Define the setend instruction.	2010-06-02 12:58:10 -05:00
Gabe Black	fb23297914	ARM: Make a base class for instructions that use only an immediate.	2010-06-02 12:58:10 -05:00
Gabe Black	247acd93c4	ARM: Decode the arm version of ldrexd.	2010-06-02 12:58:10 -05:00
Gabe Black	3ad31f61c2	ARM: Decode the strex instructions.	2010-06-02 12:58:10 -05:00
Gabe Black	54ab07e636	ARM: Implement the strex instructions.	2010-06-02 12:58:10 -05:00
Gabe Black	524a8195e1	ARM: Set CPSR.E to SCTLR.EE on faults.	2010-06-02 12:58:10 -05:00
Gabe Black	683421e0c6	ARM: Warn about not implementing MPU translation, not panic about MMU. ... We'll start out with a stbu version of PMSA and switch over to VMSA for the full implementation.	2010-06-02 12:58:10 -05:00
Gabe Black	6fb5189c47	ARM: Ignore/warn on accesses to the DRBAR, DRACR, and DRSR registers.	2010-06-02 12:58:10 -05:00
Gabe Black	89b1dd5582	ARM: Allow access to the RGNR register.	2010-06-02 12:58:10 -05:00
Gabe Black	c3381167c9	ARM: Make the MPUIR register report that 1 unified data region is supported.	2010-06-02 12:58:10 -05:00
Gabe Black	3aa8faf177	ARM: Ignore/warn on accesses to the BPIALLIS and BPIALL registers.	2010-06-02 12:58:10 -05:00
Gabe Black	faf6c727f6	ARM: Respect the E bit of the CPSR when doing loads and stores.	2010-06-02 12:58:10 -05:00
Gabe Black	b6cb6f1874	ARM: Zero the micropc when vectoring to a fault.	2010-06-02 12:58:10 -05:00
Gabe Black	1d5233958a	ARM: Implement the V7 version of alignment checking.	2010-06-02 12:58:10 -05:00
Gabe Black	7b397925af	ARM: Decode the RFE instruction.	2010-06-02 12:58:10 -05:00
Gabe Black	a2cb503ba6	ARM: Implement the RFE instruction.	2010-06-02 12:58:10 -05:00
Gabe Black	ec4cd00b11	ARM: Add a base class for the RFE instruction.	2010-06-02 12:58:10 -05:00
Gabe Black	1ada9d4880	ARM: Make sure some undefined thumb32 instructions fault.	2010-06-02 12:58:10 -05:00
Gabe Black	3caa75d53a	ARM: Squash the low order bits of the PC when performing a regular branch.	2010-06-02 12:58:10 -05:00
Gabe Black	36eeee0133	ARM: When changing the CPSR and branching, make sure the branch is second.	2010-06-02 12:58:09 -05:00
Gabe Black	68f2908a70	ARM: Ignore/warn when CSSELR or CCSIDR are accessed. ... These registers provide information about the caches. Since we can't provide that information, these will be harmlessly inert.	2010-06-02 12:58:09 -05:00
Gabe Black	741b243260	ARM: Ignore/warn access to the bpimva registers.	2010-06-02 12:58:09 -05:00
Gabe Black	8a7f60194e	ARM: Ignore/warn on accesses to the dccmvac register.	2010-06-02 12:58:09 -05:00
Gabe Black	89133b15da	ARM: Decode the enterx and leavex instructions.	2010-06-02 12:58:09 -05:00
Gabe Black	6a4ea7cca9	ARM: Implement the enterx and leavex instructions. ... These enter and leave thumbEE mode. Currently thumbEE mode behaves exactly the same as Thumb mode, but at least this will make it -look- like we're enter and leaving it. The actual behavioral changes will be implemented in future changes.	2010-06-02 12:58:09 -05:00
Gabe Black	eb0823c4f2	ARM: Fix the implementation of BX to work in thumbEE mode.	2010-06-02 12:58:09 -05:00
Gabe Black	bb0d390105	ARM: When an instruction is intentionally undefined, fault on it.	2010-06-02 12:58:09 -05:00
Gabe Black	61a5e71be7	ARM: Decode the thumb version of the ldrd and strd instructions.	2010-06-02 12:58:09 -05:00
Gabe Black	9d4a1bf2ba	ARM: Explicitly keep track of the second destination for double loads/stores.	2010-06-02 12:58:09 -05:00
Gabe Black	28023f6f3d	ARM: Decode the thumb32 load byte/memory hint instructions.	2010-06-02 12:58:09 -05:00
Gabe Black	7a9dcdf99f	ARM: Decode the load halfword, memory hints instructions for 32 bit Thumb.	2010-06-02 12:58:09 -05:00
Gabe Black	a483d44d9f	ARM: Ignore/warn on accesses to icimvau.	2010-06-02 12:58:09 -05:00
Gabe Black	630f309a77	ARM: Ignore/warn on iciallu.	2010-06-02 12:58:09 -05:00
Gabe Black	d618121670	ARM: Ignore/warn on ICIALLUIS.	2010-06-02 12:58:09 -05:00
Gabe Black	e658b6fed4	ARM: Add support for the clidr register. ... This register will always report 0 caches as implemented. It's not clear how to find out how many there really are when dealing with an arbitrary hierarchy.	2010-06-02 12:58:09 -05:00
Gabe Black	896c7617c4	ARM: Decode the unimplemented data barrier CP15 accesses. ... These are CP15DSB (Data Synchronization Barrier), and CP15DMB (Data Memory Barrier).	2010-06-02 12:58:09 -05:00
Gabe Black	af6b1667e9	ARM: Implement a stub of CPACR. ... This register controls access to the coprocessors. This doesn't actually implement it, it allows writes which don't turn anything off. In other words, it allows the simulated program to ask for what it already has.	2010-06-02 12:58:09 -05:00
Gabe Black	660270746b	ARM: Actually write the value of sctlr in ISA.clear().	2010-06-02 12:58:08 -05:00
Gabe Black	6c9ab5d898	ARM: Replace the ARM decode of CP15 MCR and MRC instructions.	2010-06-02 12:58:08 -05:00
Gabe Black	35f0c01fea	ARM: Decode the unimplemented cp15 instruction barrier.	2010-06-02 12:58:08 -05:00
Gabe Black	7932b86298	ARM: Ignore accesses to DCCIMVAC.	2010-06-02 12:58:08 -05:00
Gabe Black	6ae4d34a12	ARM: Allow accesses to the software thread id registers.	2010-06-02 12:58:08 -05:00
Gabe Black	54850e4d23	ARM: Allow accesses to the contextidr register.	2010-06-02 12:58:08 -05:00
Gabe Black	221e0ac523	ARM: Warn about and ignore accesses to DCCISW. ... This register is supposed to "Clean and invalidate data or unified cache line by set/way." Since there isn't a good way to do that, we'll just ignore these and warn about it.	2010-06-02 12:58:08 -05:00
Gabe Black	8c1be04af6	ARM: Decode the thumb versions of the mcr and mrc instructions.	2010-06-02 12:58:08 -05:00
Gabe Black	625a43e7c7	ARM: Implement the mrc and mcr instructions.	2010-06-02 12:58:08 -05:00
Gabe Black	6c1b10043f	ARM: Rename the RevOp base class to something more generic.	2010-06-02 12:58:08 -05:00
Gabe Black	f9d1bba22a	ARM: Add a version of the Dest and Op1 operands for accessing the MiscRegs.	2010-06-02 12:58:08 -05:00
Gabe Black	6aa229386d	ARM: Implement a function to decode CP15 registers to MiscReg indices.	2010-06-02 12:58:08 -05:00
Gabe Black	7ff24c8777	ARM: Decode the bfi and bfc instructions.	2010-06-02 12:58:08 -05:00
Gabe Black	a37b6b6bce	ARM: Implement the bfc and bfi instructions.	2010-06-02 12:58:08 -05:00
Gabe Black	5a63887617	ARM: Decode the ubfx and sbfx instructions.	2010-06-02 12:58:08 -05:00
Gabe Black	2e717558e2	ARM: Decode miscellaneous arm mode media instructions.	2010-06-02 12:58:08 -05:00
Gabe Black	09cc401848	ARM: Implement the ubfx and sbfx instructions.	2010-06-02 12:58:08 -05:00
Gabe Black	b1158e4938	ARM: Add a register, immediate, immediate to register base for [su]bfx.	2010-06-02 12:58:08 -05:00
Gabe Black	504ac6518b	ARM: Decode the clz instruction.	2010-06-02 12:58:08 -05:00
Gabe Black	2c94bf7f30	ARM: Implement the clz instruction.	2010-06-02 12:58:08 -05:00
Gabe Black	00320a53ab	ARM: Decode the rbit instruction.	2010-06-02 12:58:07 -05:00
Gabe Black	5cc1bb6842	ARM: Implement the rbit instruction.	2010-06-02 12:58:07 -05:00
Gabe Black	566b2ff20c	ARM: Decode the nop instruction.	2010-06-02 12:58:07 -05:00
Gabe Black	b9cfe9a3db	ARM: Implement nop.	2010-06-02 12:58:07 -05:00
Gabe Black	a2d8dcebba	ARM: Decode the ldrex instruction.	2010-06-02 12:58:07 -05:00
Gabe Black	952253483b	ARM: Rearrange the load/store double/exclusive, table branch thumb decoding.	2010-06-02 12:58:07 -05:00
Gabe Black	f7f75ad053	ARM: Implement the ldrex instruction.	2010-06-02 12:58:07 -05:00
Gabe Black	00baeb742d	ARM: Decode the usad8 and usada8 instructions.	2010-06-02 12:58:07 -05:00
Gabe Black	8f566e5ee3	ARM: Implement the usad8 and usada8 instructions.	2010-06-02 12:58:07 -05:00
Gabe Black	c643b1c274	ARM: Add a base class to support usada8.	2010-06-02 12:58:07 -05:00
Gabe Black	64ade8316e	ARM: Decode the sel instruction.	2010-06-02 12:58:07 -05:00
Gabe Black	7fa6835a0c	ARM: Implement the sel instruction.	2010-06-02 12:58:07 -05:00
Gabe Black	498f9d925e	ARM: Add a base class for the sel instruction.	2010-06-02 12:58:07 -05:00
Gabe Black	f581fd3f89	ARM: Decode pkh instructions.	2010-06-02 12:58:07 -05:00
Gabe Black	9ffc5e2ae6	ARM: Implement the pkh instruction.	2010-06-02 12:58:07 -05:00
Gabe Black	c4d09747a5	ARM: Decode the sign/zero extend instructions.	2010-06-02 12:58:07 -05:00
Gabe Black	69365876d8	ARM: Implement zero/sign extend instructions.	2010-06-02 12:58:07 -05:00
Gabe Black	554fb3774e	ARM: Add a base class for extend and add instructions.	2010-06-02 12:58:07 -05:00
Gabe Black	cb2e3b0ace	ARM: Generalize the saturation instruction bases for use in other instructions.	2010-06-02 12:58:07 -05:00
Gabe Black	a1208aa66d	ARM: Decode the 8/16 bit signed/unsigned add/subtract half instructions.	2010-06-02 12:58:07 -05:00
Gabe Black	cabf766a06	ARM: Implement the 8/16 bit signed/unsigned add/subtract half instructions.	2010-06-02 12:58:06 -05:00
Gabe Black	82614b6f3a	ARM: Fix signed most significant multiply instructions.	2010-06-02 12:58:06 -05:00
Gabe Black	3cff58602a	ARM: Fix multiply overflow flag setting.	2010-06-02 12:58:06 -05:00
Gabe Black	90c2284714	ARM: Decode the saturation instructions.	2010-06-02 12:58:06 -05:00
Gabe Black	61b8e33225	ARM: Implement the saturation instructions.	2010-06-02 12:58:06 -05:00
Gabe Black	c96f03a250	ARM: Implement base classes for the saturation instructions.	2010-06-02 12:58:06 -05:00
Gabe Black	0aff168f1a	ARM: Decode the signed add/subtract and subtract/add instructions.	2010-06-02 12:58:06 -05:00
Gabe Black	8ba812f1fb	ARM: Implement signed add/subtract and subtract/add.	2010-06-02 12:58:06 -05:00
Gabe Black	a895514d35	ARM: Decode the unsigned 8 and 16 bit add and subtract instructions.	2010-06-02 12:58:06 -05:00
Gabe Black	3f12eb02ab	ARM: Implement the unsigned 8 bit and 16 bit vector adds and subtracts.	2010-06-02 12:58:06 -05:00
Gabe Black	29acf9516c	ARM: Decode the unsigned saturating instructions.	2010-06-02 12:58:06 -05:00
Gabe Black	be888e67e7	ARM: Implement the unsigned saturating instructions.	2010-06-02 12:58:06 -05:00
Gabe Black	5495ebd68d	ARM: Decode the ssub instructions.	2010-06-02 12:58:06 -05:00
Gabe Black	fd6e9f304e	ARM: Implement the ssub instructions.	2010-06-02 12:58:06 -05:00
Gabe Black	bcf0454864	ARM: Decode the SADD8 and SADD16 instructions.	2010-06-02 12:58:06 -05:00
Gabe Black	87975aa691	ARM: Implement the SADD8 and SADD16 instructions.	2010-06-02 12:58:06 -05:00
Gabe Black	d70c31437a	ARM: Support instructions that set the GE bits when they write the condition codes.	2010-06-02 12:58:06 -05:00
Gabe Black	e32aaefe8c	ARM: Decode 32 bit thumb data processing register instructions.	2010-06-02 12:58:06 -05:00
Gabe Black	f19b605aed	ARM: Decode the 16 bit thumb versions of the REV* instructions.	2010-06-02 12:58:06 -05:00
Gabe Black	15356af288	ARM: Decode the ARM version of the REV* instructions.	2010-06-02 12:58:05 -05:00
Gabe Black	59c726b6f4	ARM: Pull decoding of ARM pack, unpack, saturate and reverse instructions into a format.	2010-06-02 12:58:05 -05:00
Gabe Black	aa8493d7d1	ARM: Implement the REV* instructions.	2010-06-02 12:58:05 -05:00
Gabe Black	c981a4de2b	ARM: Add base classes suitable for the REV* instructions.	2010-06-02 12:58:05 -05:00
Gabe Black	57443a2144	ARM: Make LDM that loads the PC perform an interworking branch.	2010-06-02 12:58:05 -05:00
Gabe Black	1344fc2668	ARM: Decode the swp and swpb instructions.	2010-06-02 12:58:05 -05:00
Gabe Black	e157b1f52a	ARM: Implement the swp and swpb instructions.	2010-06-02 12:58:05 -05:00
Gabe Black	1884ed65bd	ARM: Decode MRS and MSR for thumb.	2010-06-02 12:58:05 -05:00
Gabe Black	ff3b21bc2b	ARM: Replace the versions of MRS and MSR in the ARM decoder with the new ones.	2010-06-02 12:58:05 -05:00
Gabe Black	f0811eb208	ARM: Define versions of MSR and MRS outside the decoder.	2010-06-02 12:58:05 -05:00
Gabe Black	f61bb9adb9	ARM: Hook up the push/pop versions of stm/ldm in thumb.	2010-06-02 12:58:05 -05:00
Gabe Black	a76ab8e040	ARM: Hook SVC into the thumb decoder.	2010-06-02 12:58:05 -05:00
Gabe Black	cbdebf852e	ARM: Implement SVC (was SWI) outside of the decoder.	2010-06-02 12:58:05 -05:00
Gabe Black	34032f97d6	ARM: Trigger system calls from the SupervisorCall invoke method. ... This simplifies the decoder slightly, and makes the system call mechanism very slightly more realistic.	2010-06-02 12:58:05 -05:00
Gabe Black	52460938cb	ARM: Fix multiply operations. ... These fixes were provided by Ali and fix the saturation condition code and various multiply instructions.	2010-06-02 12:58:05 -05:00
Gabe Black	4fb6fcd82d	ARM: Decode the scalar saturating add/subtract instructions.	2010-06-02 12:58:05 -05:00
Gabe Black	30dd622622	ARM: Decode the parallel add and subtract instructions.	2010-06-02 12:58:05 -05:00
Gabe Black	62e8487d57	ARM: Implement signed saturating add and/or subtract instructions.	2010-06-02 12:58:05 -05:00
Gabe Black	a1253ec644	ARM: Implemented prefetch instructions/decoding (pli, pld, pldw).	2010-06-02 12:58:05 -05:00
Gabe Black	61b00d3224	ARM: Decode unconditional ARM instructions.	2010-06-02 12:58:04 -05:00
Gabe Black	b6e2f5d33f	ARM: Make sure ldm exception return writes back its base in the right mode. ... This change moves the writeback of load multiple instructions to the beginning of the macroop. That way, the MicroLdrRetUop that changes the mode will necessarily happen later, ensuring the writeback happens in the original mode. The actual value in the base register if it also shows up in the register list is undefined, so it's fine if it gets clobbered by one of the loads. For stores where the base register is the lowest numbered in the register list, the original value should be written back. That means stores can't write back at the beginning, but the mode changing problem doesn't affect them so they can continue to write back at the end.	2010-06-02 12:58:04 -05:00
Gabe Black	89060f1fd8	ARM: Rework how unrecognized/unimplemented instructions are handled. ... Instead of panic immediately when these instructions are executed, an UndefinedInstruction fault is returned. In FS mode (not currently implemented), this is the fault that should, to my knowledge, be triggered in these situations and should be handled using the normal architected mechanisms. In SE mode, the fault causes a panic when it's invoked that gives the same information as the instruction did. When/if support for speculative execution of ARM is supported, this will allow a mispeculated and unrecognized and/or unimplemented instruction from causing a panic. Only once the instruction is going to be committed will the fault be invoked, triggering the panic.	2010-06-02 12:58:04 -05:00
Gabe Black	aa45fafb2e	ARM: Add support for "SUBS PC, LR and related instructions".	2010-06-02 12:58:04 -05:00
Gabe Black	2419903dc0	ARM: Make ldrs into the PC and ldm exception return do interworking branches.	2010-06-02 12:58:04 -05:00
Gabe Black	28227440a7	ARM: Align the PC when using it as the base for a load.	2010-06-02 12:58:04 -05:00
Gabe Black	d63f748b53	ARM: Implement ADR as separate from ADD.	2010-06-02 12:58:04 -05:00
Gabe Black	e92dc21fde	ARM: Add support for interworking branch ALU instructions.	2010-06-02 12:58:04 -05:00
Gabe Black	11c3361be4	ARM: Fix when the flag bits are updated for thumb.	2010-06-02 12:58:04 -05:00
Gabe Black	14d25fbad0	ARM: Don't rely on undefined behavior to get arithmetic right shift. ... Shifting to the right of a signed value when the MSB is one is technically undefined behavior, even though in my experience it's done the "right thing" and sign extended the value. This replaces the arithmetic right shift code in ARM that uses that coincidence with some code that relies on bit math.	2010-06-02 12:58:04 -05:00
Gabe Black	05d880f7a1	ARM: Restrict the shift amount from a register to 8 bits. ... The shift amount when taken from a register is supposed to be truncated to an 8 bit value.	2010-06-02 12:58:04 -05:00
Gabe Black	9ebaf8ecd5	ARM: Define the VFP load/store multiple instructions.	2010-06-02 12:58:04 -05:00
Gabe Black	3f83094af2	ARM: Decode the VFP load/store multiple instructions.	2010-06-02 12:58:04 -05:00
Gabe Black	647edea970	ARM: Fix the constant describing the number of floating point registers.	2010-06-02 12:58:04 -05:00
Gabe Black	2f3102f1ef	ARM: Add templates for VFP load/store multiple instructions.	2010-06-02 12:58:04 -05:00
Gabe Black	739f23c64c	ARM: Add base classes for VFP load/store multiple.	2010-06-02 12:58:04 -05:00
Gabe Black	cb631d87c3	ARM: Add floating point load/store microops.	2010-06-02 12:58:04 -05:00
Gabe Black	3a11412c99	ARM: Add an fp version of one of the microop indexed registers.	2010-06-02 12:58:04 -05:00
Gabe Black	d5aee75efe	ARM: Move the mmap region to where Linux actually has it.	2010-06-02 12:58:04 -05:00
Gabe Black	a8eb9d521c	ARM: Eliminate the unused rhi and rlo operands.	2010-06-02 12:58:03 -05:00
Gabe Black	b02c7f1bcd	ARM: Move the macro mem constructor out of the isa desc. ... This code doesn't use the parser at all, and moving it out reduces the conceptual complexity of that code.	2010-06-02 12:58:03 -05:00
Gabe Black	7b62e9ad71	ARM: Make macroops panic if executed directly. ... The macroop should never be executed, only it's microops will.	2010-06-02 12:58:03 -05:00
Ali Saidi	8fadf2691d	ARM: GCC < 4.3 has some issues with attribute no return on some functions. Fix so it works for older gccs.	2010-06-02 12:58:03 -05:00
Gabe Black	f18040a205	ARM: Split out the "basic" templates and format. ... --HG-- rename : src/arch/arm/isa/formats/basic.isa => src/arch/arm/isa/templates/basic.isa	2010-06-02 12:58:03 -05:00
Gabe Black	c175f1b993	ARM: Remove unnecessary cruft from includes.isa.	2010-06-02 12:58:03 -05:00
Gabe Black	e29ec7d2ed	ARM: Move the inst2string function out of the isa_desc. ... Delete the now empty formats/util.isa.	2010-06-02 12:58:03 -05:00
Gabe Black	ae135228fc	ARM: Get rid of the unused ArmGenericCodeSubs.	2010-06-02 12:58:03 -05:00
Gabe Black	8c012e9571	ARM: Make the predecoder print out the ExtMachInst it gathered when traced.	2010-06-02 12:58:03 -05:00
Gabe Black	458bd025d4	ARM: Remove special naming for the new version of multiply.	2010-06-02 12:58:03 -05:00
Gabe Black	2196f75a25	ARM: Hook the new multiply instructions into all the decoders.	2010-06-02 12:58:03 -05:00
Gabe Black	33da368e99	ARM: Implement all integer multiply instructions.	2010-06-02 12:58:03 -05:00
Gabe Black	50229be27f	ARM: Add templates for multiply instructions.	2010-06-02 12:58:03 -05:00
Gabe Black	3430b34cff	ARM: Add base classes for multiply instructions.	2010-06-02 12:58:03 -05:00
Gabe Black	c7d2f43641	ARM: Decode plain binary immediate thumb data processing instructions.	2010-06-02 12:58:03 -05:00
Gabe Black	dcf218155d	ARM: Define a new "movt" data processing instruction.	2010-06-02 12:58:03 -05:00
Gabe Black	b615ed1470	ARM: Hook the new branch instructions into the 32 bit thumb decoder.	2010-06-02 12:58:03 -05:00
Gabe Black	274badd201	ARM: Hook the new branch instructions into the 16 bit thumb decoder.	2010-06-02 12:58:03 -05:00
Gabe Black	b6b2f8891a	ARM: Eliminate the old style branch instructions.	2010-06-02 12:58:03 -05:00
Gabe Black	d082705b01	ARM: Hook the new branch instructions into the ARM decoder.	2010-06-02 12:58:02 -05:00
Gabe Black	9869343636	ARM: Implement branch instructions external to the decoder.	2010-06-02 12:58:02 -05:00
Gabe Black	a6c1c8debb	ARM: Add new templates for branch instructions.	2010-06-02 12:58:02 -05:00
Gabe Black	ef3972eaae	ARM: Implement new base classes for branches.	2010-06-02 12:58:02 -05:00
Gabe Black	769f3406fe	ARM: Replace the interworking branch base class with a special operand.	2010-06-02 12:58:02 -05:00
Gabe Black	b6e7029dd5	ARM: Fix PC operand handling.	2010-06-02 12:58:02 -05:00
Gabe Black	7eb3ea2798	ARM: Remove the special naming from the new version of data processing instructions.	2010-06-02 12:58:02 -05:00
Gabe Black	4f08b52af2	ARM: Get rid of unnecessary flag calculating functions.	2010-06-02 12:58:02 -05:00
Gabe Black	bf903ec9a1	ARM: Get rid of the unused Jump format.	2010-06-02 12:58:02 -05:00
Gabe Black	36ca0658a4	ARM: Get rid of obsoleted predicated inst formats, etc.	2010-06-02 12:58:02 -05:00
Gabe Black	7939b48265	ARM: Implement disassembly for the new data processing classes.	2010-06-02 12:58:02 -05:00
Gabe Black	b66e3aec43	ARM: Hook the external data processing instructions into the Thumb decoder.	2010-06-02 12:58:02 -05:00
Gabe Black	beb759912b	ARM: Move the modified_imm function from all ARM instructions to just data processing ones.	2010-06-02 12:58:02 -05:00
Gabe Black	8136cb3605	ARM: Hook the new external data processing instructions to the ARM decoder.	2010-06-02 12:58:02 -05:00
Gabe Black	bf45d44cbe	ARM: Implement data processing instructions external to the decoder.	2010-06-02 12:58:02 -05:00
Gabe Black	c02f9cdddf	ARM: Add new base classes for data processing instructions.	2010-06-02 12:58:02 -05:00
Gabe Black	1e7b317a98	ARM: Hook up 32 bit thumb load/store multiple.	2010-06-02 12:58:02 -05:00
Gabe Black	64d6b6ebfd	ARM: Hook up 16 bit thumb load/store multiple.	2010-06-02 12:58:02 -05:00
Gabe Black	51bde086d5	ARM: Reimplement load/store multiple external to the decoder. ... --HG-- rename : src/arch/arm/isa/formats/macromem.isa => src/arch/arm/isa/insts/macromem.isa rename : src/arch/arm/isa/formats/macromem.isa => src/arch/arm/isa/templates/macromem.isa	2010-06-02 12:58:02 -05:00
Gabe Black	93a3714816	ARM: Move the templates for predicated instructions into a separate file. ... This allows the templates to all be available at the same time before any of the formats, etc. This breaks an artificial circular dependence. --HG-- rename : src/arch/arm/isa/formats/pred.isa => src/arch/arm/isa/templates/pred.isa	2010-06-02 12:58:01 -05:00
Gabe Black	04300e33d4	ARM: Remove the special naming for the new memory instructions. ... These are the only memory instructions now.	2010-06-02 12:58:01 -05:00
Gabe Black	deb6e8f805	ARM: Eliminate the old memory formats which are no longer used.	2010-06-02 12:58:01 -05:00
Gabe Black	1905024766	ARM: Eliminate decoding for the very deprecated FPA instructions.	2010-06-02 12:58:01 -05:00
Gabe Black	55465844dc	ARM: Make the addressing mode 3 loads/stores use the externally defined instructions.	2010-06-02 12:58:01 -05:00
Gabe Black	36b6ca2ce3	ARM: Pull double memory instructions out of the decoder.	2010-06-02 12:58:01 -05:00
Gabe Black	79b288f7b5	ARM: Force the condition code for 16 bit thumb instructions to be unconditional. ... Before, because 16 bit thumb instructions didn't set the upper 16 bits of the ExtMachInst, that field would be interpretted as "equals".	2010-06-02 12:58:01 -05:00
Gabe Black	a86491fbf2	ARM: Decode 16 bit thumb PC relative memory instructions.	2010-06-02 12:58:01 -05:00
Gabe Black	dc8af1b211	ARM: Decode 16 bit thumb immediate addressed memory instructions.	2010-06-02 12:58:01 -05:00
Gabe Black	4bbd73649d	ARM: Decode 16 bit thumb register addressed memory instructions.	2010-06-02 12:58:01 -05:00
Gabe Black	462cf6f49b	ARM: Make single stores decode to the new external store instructions.	2010-06-02 12:58:01 -05:00
Gabe Black	3b0f3b1ee2	ARM: Add a .w to the disassembly of 32 bit thumb instructions. ... This isn't technically correct since the .w should only be added if there are 32 and 16 bit encodings, but always having it always is better than never having it.	2010-06-02 12:58:01 -05:00
Gabe Black	fde3c8f41d	ARM: Make 32 bit thumb use the new, external load instructions.	2010-06-02 12:58:01 -05:00
Gabe Black	3b93015304	ARM: Define the store instructions from outside the decoder. ... --HG-- rename : src/arch/arm/isa/insts/ldr.isa => src/arch/arm/isa/insts/str.isa	2010-06-02 12:58:01 -05:00
Gabe Black	81fdced83f	ARM: Define the load instructions from outside the decoder.	2010-06-02 12:58:01 -05:00
Gabe Black	321d3a6e8c	ARM: Implement a new set of base classes for non macro memory instructions.	2010-06-02 12:58:01 -05:00
Gabe Black	8933857af7	ARM: Create a "decoder" directory for the files implementing the decoder. ... --HG-- rename : src/arch/arm/isa/armdecode.isa => src/arch/arm/isa/decoder/arm.isa rename : src/arch/arm/isa/decoder.isa => src/arch/arm/isa/decoder/decoder.isa rename : src/arch/arm/isa/thumbdecode.isa => src/arch/arm/isa/decoder/thumb.isa rename : src/arch/arm/isa/vfpdecode.isa => src/arch/arm/isa/decoder/vfp.isa	2010-06-02 12:58:01 -05:00
Gabe Black	4ebd44dc4f	ARM: Flesh out the 32 bit thumb store single instructions.	2010-06-02 12:58:01 -05:00
Gabe Black	386424ccb5	ARM: Implement the 32 bit thumb load word instructions.	2010-06-02 12:58:01 -05:00
Gabe Black	292b8a3c91	ARM: Add an operand for accessing the current PC.	2010-06-02 12:58:00 -05:00
Gabe Black	003346077f	ARM: Flesh out 32 bit thumb load word decoding.	2010-06-02 12:58:00 -05:00
Gabe Black	0d4c4cacab	ARM: Implement some 32 bit thumb data processing immediate instructions.	2010-06-02 12:58:00 -05:00
Gabe Black	bd8812cf99	ARM: Replace the "never" condition with the "unconditional" condition.	2010-06-02 12:58:00 -05:00
Gabe Black	af91d27271	ARM: Add a base class for 32 bit thumb data processing immediate instructions.	2010-06-02 12:58:00 -05:00
Gabe Black	bfe1a194dd	ARM: Add a function to decode 32 bit thumb immediate values.	2010-06-02 12:58:00 -05:00
Gabe Black	0116655674	ARM: Expand the decoding for 32 bit thumb data processing immediate instructions.	2010-06-02 12:58:00 -05:00
Gabe Black	cef2e8ecee	ARM: Stub out the 32 bit Thumb portion of the decoder.	2010-06-02 12:58:00 -05:00
Gabe Black	659f8d021f	ARM: Add bitfields for 32 bit thumb.	2010-06-02 12:58:00 -05:00
Gabe Black	bc6ae010c9	ARM: Decode VFP instructions.	2010-06-02 12:58:00 -05:00
Gabe Black	7b8525287d	ARM: Stub out the 16 bit thumb decoder.	2010-06-02 12:58:00 -05:00
Gabe Black	aaa619ea23	ARM: Add thumb bitfields to the ExtMachInst and the isa definition.	2010-06-02 12:58:00 -05:00
Gabe Black	a1838f2c79	ARM: Make the decoder handle thumb instructions separately. ... --HG-- rename : src/arch/arm/isa/decoder.isa => src/arch/arm/isa/armdecode.isa rename : src/arch/arm/isa/decoder.isa => src/arch/arm/isa/thumbdecode.isa	2010-06-02 12:58:00 -05:00
Gabe Black	0dffd8ce79	ARM: Add a thumb bit bitfield.	2010-06-02 12:58:00 -05:00
Gabe Black	96be7e16c1	ARM: Make the predecoder handle Thumb instructions.	2010-06-02 12:58:00 -05:00
Gabe Black	f49cdb4f5d	ARM: Make sure ExtMachInst is used consistently instead of regular MachInst.	2010-06-02 12:58:00 -05:00
Gabe Black	330d9d4dbc	ARM: Add a bitfield for setting the regular, inst bits of an ExtMachInst.	2010-06-02 12:58:00 -05:00
Gabe Black	a59d219989	ARM: Add a bit to the ExtMachInst to select thumb mode.	2010-06-02 12:58:00 -05:00
Gabe Black	4ddeceba96	ARM: Allow ARM processes to start in Thumb mode.	2010-06-02 12:58:00 -05:00
Gabe Black	3951afd2fa	ARM: Detect thumb mode elf images.	2010-06-02 12:58:00 -05:00
Gabe Black	ebb273bb7b	ARM: Add a new base class for instructions that can do an interworking branch.	2010-06-02 12:57:59 -05:00
Gabe Black	9ef82c0bc4	ARM: Track the current ISA mode using the PC.	2010-06-02 12:57:59 -05:00
Gabe Black	1c0d9806e5	ARM: Fix custom writer/reader code for non indexed operands.	2010-06-02 12:57:59 -05:00
Gabe Black	4b87bc887a	ARM: Remove IsControl from operands that don't imply control transfers. ... Also remove IsInteger from CondCodes.	2010-06-02 12:57:59 -05:00
Ali Saidi	322f345b51	ARM: Adjust some copyrights	2010-06-02 12:57:59 -05:00
Nathan Binkert	c1aabe8172	style: clean up ruby's Set class ... Further cleanup should probably be done to make this class be non-Ruby specific and put it in src/base. There are probably several cases where this class is used, std::bitset could be used instead.	2010-06-01 11:38:56 -07:00
Nathan Binkert	bb589d463b	x86: put back code that I accidentally deleted	2010-05-25 20:15:44 -07:00
Nathan Binkert	13d64906c2	copyright: Change HP copyright on x86 code to be more friendly	2010-05-23 22:44:15 -07:00
Gabe Black	c5c559b6ab	SPARC: Implement the version of movcc that uses the fp condition codes.	2010-05-14 14:22:51 -07:00
Ali Saidi	72071690e7	Automated merge with ssh://m5sim.org//repo/m5	2010-05-13 23:48:06 -04:00
Maximilien Breughe	fc746c2268	BPRED: Fixed the treshold-bug in the tournament predictor. ... Suppose the saturating counters of a branch predictor contain n bits. When the counter is between 0 and (2^(n-1) - 1), boundaries included, the branch is predicted as not taken. When the counter is between 2^(n-1) and (2^n - 1), boundaries included, the branch is predicted as taken.	2010-05-13 23:45:57 -04:00
Gabe Black	c4497dbf03	X86: Make the cvti2f microop sign extend its integer source correctly. ... The code was using the wrong bit as the sign bit. Other similar bits of code seem to be correct.	2010-05-12 00:51:35 -07:00
Gabe Black	cc76842f83	X86: Actual change that fixes div. How did that happen?	2010-05-12 00:49:12 -07:00
Nathan Binkert	c4057a13f1	macos: MacOS has deprecated getdirentries, so just disable the code. ... Hopefully it isn't used much	2010-05-06 08:42:21 -07:00
Nathan Binkert	f07ee128cc	compile: don't #include unnecessary stuff ... Time from base/time.hh has a name clash with Time from Ruby's TypeDefines.hh. Eventually Ruby's Time should go away, so instead of fixing this properly just try to avoid the clash.	2010-05-06 08:42:18 -07:00
Gabe Black	2ee7a89209	X86: Update the base aux vector X86 processes install.	2010-05-03 00:44:08 -07:00
Gabe Black	7524fdda6a	X86: Sometimes CPUID depends on ecx, so pass that in.	2010-05-02 00:40:17 -07:00
Gabe Black	51a3d65e25	X86: Finally fix a division corner case. ... When doing an unsigned 64 bit division with a divisor that has its most significant bit set, the division code would spill a bit off of the end of a uint64_t trying to shift the dividend into position. This change adds code that handles that case specially by purposefully letting it spill and then going ahead assuming there was a 65th one bit.	2010-05-02 00:39:29 -07:00
Nathan Binkert	82fb350f9a	stats: make simTicks and simFreq accessible from stats.hh	2010-04-18 13:23:25 -07:00
Nathan Binkert	50bf3895b0	callback: Make helper functions that create callback objects for you ... clean up callback stuff a little bit while we're at it.	2010-04-18 13:23:25 -07:00
Nathan Binkert	12fc22571c	event: Allow EventWrapper to take an object reference	2010-04-18 13:23:24 -07:00
Nathan Binkert	4225a68a95	scons: don't maintain files in sorted order ... This causes builds to happen in sorted order rather than in declaration order. This gets annoying when you make a global change and then you notice that the files that are being compiled are jumping around the directory hierarchy.	2010-04-15 16:25:14 -07:00
Nathan Binkert	e99828b06a	tick: rename Clock namespace to SimClock	2010-04-15 16:24:12 -07:00
Nathan Binkert	f7e6f19ada	eventq: move EventQueue constructor to cc file ... Also make copy constructor and assignment operator private.	2010-04-15 16:24:10 -07:00
Korey Sewell	b49511ae48	inorder: timing for inst forwarding ... when insts execute, they mark the time they finish to be used for subsequent isnts they may need forwarding of data. However, the regdepmap was using the wrong value to index into the destination operands of the instruction to be forwarded. Thus, in some cases, we are checking to see if the 3rd destination register for an instruction is executed at a certain time, when there is only 1 dest. register valid. Thus, we get a bad, uninitialized time value that will stall forwarding causing performance loss but still the correct execution.	2010-04-10 23:31:36 -04:00
Nathan Binkert	d71f9712b3	eventq: allow an implicit cast from an EventManager to an EventQueue *	2010-04-02 15:28:22 -07:00
Nathan Binkert	f32674d9bc	eventq: Clean up some flags ... - Make the initialized flag always available, not just in debug mode. - Make the Initialized flag actually use several bits so it is very unlikely that something that's uninitialized accidentally looks initialized. - Add an initialized() function that tells you if the current event is indeed initialized. - Clear the flags on delete so it can't be accidentally thought of as initialized. - Fix getFlags assert statement. "How did this ever work?"	2010-04-02 15:28:22 -07:00
Nathan Binkert	2ee3edba8e	eventq: Make priorities just an integer instead of an enum. ... Symbolic names should still be used, but this makes it easier to do things like: Event::Priority MyObject_Pri = Event::Default_Pri + 1 Remember that higher numbers are lower priority (should we fix this?)	2010-04-02 15:28:21 -07:00
Nathan Binkert	01dffaa32f	refcnt: no default copy contructor or copy operator ... We shouldn't allow these because the default versions will copy the reference count which is definitely not what we want.	2010-04-02 11:20:32 -07:00
Nathan Binkert	141f61d83a	ruby: get rid of gems_common/util.hh and .cc and use stuff in src/base	2010-04-02 11:20:32 -07:00
Nathan Binkert	f1c3f3044b	ruby: get "using namespace" out of headers ... In addition to obvious changes, this required a slight change to the slicc grammar to allow types with :: in them. Otherwise slicc barfs on std::string which we need for the headers that slicc generates.	2010-04-02 11:20:32 -07:00
Nathan Binkert	be10204729	style: another ruby style pass	2010-03-31 16:56:45 -07:00
Nathan Binkert	60ae1d2b10	style: cleanup the Ruby Tester	2010-03-29 20:39:02 -04:00
Korey Sewell	1c98bc5a56	m5: merge inorder updates	2010-03-27 02:23:00 -04:00
Korey Sewell	ac316d45e8	inorder: write-hints bug fix ... make sure to only read 1 src reg. for write-hint and any other similar 'store' instruction. Reading the source reg when its not necessary can cause the simulator to read from uninitialized values	2010-03-27 01:40:05 -04:00
Timothy M. Jones	6b293c73fd	CPU: Added comments to address translation classes.	2010-03-25 12:43:52 +00:00
Nathan Binkert	a2652a048a	ruby: continue style pass	2010-03-23 22:49:43 -07:00
Steve Reinhardt	f066bfc2f5	cpu: get rid of uncached access "events" ... These recordEvent() calls could cause crashes since they access the req pointer after it's potentially been deleted during a failed translation call. (Similar problem to the traceData bug fixed in the previous cset.) Moving them above the translation call (as was done recentlyi in cset 8b2b8e5e7d35) avoids the crash but doesn't work, since at that point we don't know if the access is uncached or not. It's not clear why these calls are there, and no one seems to use them, so we'll just delete them. If they are needed, they should be moved to somewhere that's guaranteed to be after the translation completes but before the request is possibly deleted, e.g., in finishTranslation().	2010-03-23 08:50:59 -07:00
Steve Reinhardt	4d77ea7a57	cpu: fix exec tracing memory corruption bug ... Accessing traceData (to call setAddress() and/or setData()) after initiating a timing translation was causing crashes, since a failed translation could delete the traceData object before returning. It turns out that there was never a need to access traceData after initiating the translation, as the traced data was always available earlier; this ordering was merely historical. Furthermore, traceData->setAddress() and traceData->setData() were being called both from the CPU model and the ISA definition, often redundantly. This patch standardizes all setAddress and setData calls for memory instructions to be in the CPU models and not in the ISA definition. It also moves those calls above the translation calls to eliminate the crashes.	2010-03-23 08:50:57 -07:00
Nathan Binkert	5ab13e2deb	ruby: style pass	2010-03-22 18:43:53 -07:00
Korey Sewell	2620e08722	inorder: import name for addtl. bpred stats	2010-03-22 17:19:48 -04:00
Maximilien Breughe	0170e851de	inorder: fix squash bug in branch predictor	2010-03-22 16:59:12 -04:00
Korey Sewell	4ac245737d	inorder: fix address list bug	2010-03-22 15:38:28 -04:00
Brad Beckmann	66632539b6	ruby: improved isReadWrite fix me comment	2010-03-22 11:19:17 -07:00
Brad Beckmann	b55e69ccac	ruby: Removed the unnecessary MachineType message fields	2010-03-21 21:22:22 -07:00
Brad Beckmann	898f1fc4a4	ruby: Reorganized Ruby topology and protocol files ... --HG-- rename : configs/ruby/MESI_CMP_directory.py => configs/ruby/protocols/MESI_CMP_directory.py rename : configs/ruby/MI_example.py => configs/ruby/protocols/MI_example.py rename : configs/ruby/MOESI_CMP_directory.py => configs/ruby/protocols/MOESI_CMP_directory.py rename : configs/ruby/MOESI_CMP_token.py => configs/ruby/protocols/MOESI_CMP_token.py rename : configs/ruby/MOESI_hammer.py => configs/ruby/protocols/MOESI_hammer.py rename : configs/ruby/networks/MeshDirCorners.py => src/mem/ruby/network/topologies/MeshDirCorners.py	2010-03-21 21:22:22 -07:00
Brad Beckmann	f3cdc0d5a3	ruby: Disable adaptive routing by for faster simulation perf.	2010-03-21 21:22:21 -07:00
Brad Beckmann	f9408f984f	ruby: Changed the default set size to 1 ... Previously, the set size was set to 4. This was mostly do to the fact that a crazy graduate student use to create networks with 256 l2 cache banks. Now it is far more likely that users will create systems with less than 64 of any particular controller type. Therefore Ruby should be optimized for a set size of 1.	2010-03-21 21:22:21 -07:00
Brad Beckmann	61f1d9a3d7	ruby: Reordered protocol buffers ... Reordered vnet priorities to agree with PerfectSwitch for protocols MI_example, MOESI_CMP_token, and MOESI_hammer	2010-03-21 21:22:21 -07:00
Brad Beckmann	4f044605e8	ruby: Adds configurable bit selection for numa mapping	2010-03-21 21:22:21 -07:00
Brad Beckmann	8b15ed7ebf	ruby: Added flag to disable mem_vec allocation ... The RubySystem flag no_mem_vec will disable Ruby from allocating it's memory data array.	2010-03-21 21:22:21 -07:00
Brad Beckmann	92cfd1cac7	ruby: Ruby support for sparse memory ... The patch includes direct support for the MI example protocol.	2010-03-21 21:22:21 -07:00
Brad Beckmann	b5e4c3cbf2	ruby: Finally removed bash code cira. 2001ish!	2010-03-21 21:22:21 -07:00
Brad Beckmann	6d22db4eaa	ruby: Ruby support for LLSC	2010-03-21 21:22:21 -07:00
Brad Beckmann	f53287f9ad	ruby: Minor dma latency initialization fix	2010-03-21 21:22:21 -07:00
Tushar Krishna	7c20d5511a	ruby: Fix multiple wakeups in Ruby Eventqueue ... Fix bug in Ruby Event queue to avoid multiple wakeups of same consumer in same cycle	2010-03-21 21:22:21 -07:00
Brad Beckmann	103f5a2c94	ruby: Removed the obsolete file specified network files	2010-03-21 21:22:21 -07:00
Brad Beckmann	d464087101	ruby: Added copyright to many Ruby *.py files	2010-03-21 21:22:20 -07:00
Brad Beckmann	378fbce911	ruby: Fixed small data msg bug in MOESI_hammer-dir	2010-03-21 21:22:20 -07:00
Brad Beckmann	4ee3b0da45	TimingSimpleCPU: Fixed uncacacheable request read bug ... Previously the recording of an uncached read occurred after the request was possibly deleted within the translateTiming function.	2010-03-21 21:22:20 -07:00
Brad Beckmann	0368ef915a	ruby: Removed the no longer used rubymem files	2010-03-21 21:22:20 -07:00
Brad Beckmann	c48a735336	ruby: Fix MOESI_hammer cache profiler calls for L2 misses	2010-03-21 21:22:20 -07:00
Brad Beckmann	391b4e64e6	ruby: Removed deprecated stats from the main profiler	2010-03-21 21:22:20 -07:00
Nathan Binkert	86207a69e4	orion: Make declarations match definition	2010-03-16 08:15:16 -07:00
Nathan Binkert	edb59ed263	ruby: Fix copyrights on files ... Mostly files missed during import or screwed up during import	2010-03-14 20:58:45 -07:00
Nathan Binkert	0bbf63f17a	slicc: Change the code generation so that the generated code is easier to read	2010-03-12 18:42:56 -08:00
Nathan Binkert	c8f296bca0	packet: add a method to set the size	2010-03-12 17:31:08 -08:00
Nathan Binkert	671faf3316	eventq: rearrange a little bit so I can add some stuff	2010-03-12 17:31:04 -08:00
Nathan Binkert	402f42ebfa	eventq: remove some unused includes	2010-03-12 17:31:02 -08:00
Nathan Binkert	fce7c820f4	bugfix: since pow() causes a bug don't use it ... It's a power of two anyway, so why use it in the first place.	2010-03-12 15:11:09 -08:00
Nathan Binkert	140785d24c	ruby: get rid of std-includes.hh ... Do not use "using namespace std;" in headers Include header files as needed	2010-03-10 18:33:11 -08:00
Nathan Binkert	1badec39a9	ruby: remove calc_host.diff since we don't use it	2010-03-10 16:22:27 -08:00
Nathan Binkert	226eaf9ddf	ruby: get rid of the ioutil stuff since it isn't used anymore	2010-03-10 16:22:26 -08:00
Nathan Binkert	cf86532857	slicc: have a central mechanism for creating a code_formatter. ... This makes it easier to add global variables like protocol	2010-03-10 16:22:26 -08:00
Nathan Binkert	1068ca85d0	scons: import ply to work around scons sys.path weirdness	2010-03-10 15:39:34 -08:00
Nathan Binkert	25aac791de	SmartDict: Make SmartDict an attrdict	2010-02-28 19:28:09 -08:00
Nathan Binkert	ebdd004eb2	uart: use integer versions of time instead of messing around with floats	2010-02-28 19:28:09 -08:00
Nathan Binkert	f0b4259e98	cpu_models: get rid of cpu_models.py and move the stuff into SCons	2010-02-26 18:14:48 -08:00
Nathan Binkert	ac106767c8	isa_parser: Make SCons import the isa_parser ... this is instead of forking a new interpreter	2010-02-26 18:14:48 -08:00
Nathan Binkert	629e8df196	isa_parser: move the operand map stuff into the ISAParser class.	2010-02-26 18:14:48 -08:00
Nathan Binkert	4db57edade	isa_parser: move more support functions into the ISAParser class	2010-02-26 18:14:48 -08:00
Nathan Binkert	5ad139375e	isa_parser: move more stuff into the ISAParser class	2010-02-26 18:14:48 -08:00
Nathan Binkert	4ef6e129d6	isa_parser: move the formatMap and exportContext into the ISAParser class	2010-02-26 18:14:48 -08:00
Nathan Binkert	4e105f6fe1	isa_parser: Make stack objects class members instead of globals	2010-02-26 18:14:48 -08:00
Nathan Binkert	b4178b1ae7	isa_parser: add a debug variable that changes how errors are reported. ... This allows us to get tracebacks in certain cases where they're more useful than our error message.	2010-02-26 18:14:48 -08:00
Nathan Binkert	40a05f04fb	isa_parser: Use an exception to flag error ... This allows the error to propagate more easily	2010-02-26 18:14:48 -08:00
Nathan Binkert	f82a92925c	isa_parser: Move more stuff into the ISAParser class	2010-02-26 18:14:48 -08:00
Nathan Binkert	f7a627338c	isa_parser: move code around to prepare for putting more stuff in the class	2010-02-26 18:14:48 -08:00
Nathan Binkert	eb4ce01056	isa_parser: simple fixes, formatting and style	2010-02-26 18:14:48 -08:00
Nathan Binkert	a9f6c8edc3	events: Give EventWrapped a default name and description	2010-02-26 18:09:41 -08:00
Lisa Hsu	7f3cd9a9fd	cache stats: account for writebacks and/or device occupancy in the cache. ... Plus, a minor bugfix that neglects to update blk->contextSrc in certain cases on a cache insert.	2010-02-24 13:46:55 -08:00
Lisa Hsu	1d3228481f	cache: Make caches sharing aware and add occupancy stats. ... On the config end, if a shared L2 is created for the system, it is parameterized to have n sharers as defined by option.num_cpus. In addition to making the cache sharing aware so that discriminating tag policies can make use of context_ids to make decisions, I added an occupancy AverageStat and an occ % stat to each cache so that you could know which contexts are occupying how much cache on average, both in terms of blocks and percentage. Note that since devices have context_id -1, having an array of occ stats that correspond to each context_id will break here, so in FS mode I add an extra bucket for device blocks. This bucket is explicitly not added in SE mode in order to not only avoid ugliness in the stats.txt file, but to avoid broken stats (some formulas break when a bucket is 0).	2010-02-23 09:34:22 -08:00
Lisa Hsu	be4cf50c5a	stats: this makes some fixes to AverageStat and AverageVector. ... Also, make Formulas work on AverageVector. First, Stat::Average (and thus Stats::AverageVector) was broken when coming out of a checkpoint and on resets, this fixes that. Formulas also didn't work with AverageVector, but added support for that.	2010-02-23 09:33:18 -08:00
Lisa Hsu	2ad386f104	cache: pull CacheSet out of LRU so that other tags can use associative sets.	2010-02-23 09:33:09 -08:00
Timothy M. Jones	a5feaa6a69	BaseDynInst: Preserve the faults returned from read and write. ... When implementing timing address translations instead of atomic, I forgot to preserve the faults that are returned from the read and write calls. This patch reinstates them.	2010-02-20 20:11:58 +00:00
Timothy M. Jones	29e8bcead5	O3PCU: Split loads and stores that cross cache line boundaries. ... When each load or store is sent to the LSQ, we check whether it will cross a cache line boundary and, if so, split it in two. This creates two TLB translations and two memory requests. Care has to be taken if the first packet of a split load is sent but the second blocks the cache. Similarly, for a store, if the first packet cannot be sent, we must store the second one somewhere to retry later. This modifies the LSQSenderState class to record both packets in a split load or store. Finally, a new const variable, HasUnalignedMemAcc, is added to each ISA to indicate whether unaligned memory accesses are allowed. This is used throughout the changed code so that compiler can optimise away code dealing with split requests for ISAs that don't need them.	2010-02-12 19:53:20 +00:00
Timothy M. Jones	7fe9f92cfc	BaseDynInst: Make the TLB translation timing instead of atomic. ... This initiates a timing translation and passes the read or write on to the processor before waiting for it to finish. Once the translation is finished, the instruction's state is updated via the 'finish' function. A new DataTranslation class is created to handle this. The idea is taken from the implementation of timing translations in TimingSimpleCPU by Gabe Black. This patch also separates out the timing translations from this CPU and uses the new DataTranslation class.	2010-02-12 19:53:19 +00:00
Timothy M. Jones	dd60902152	Power ISA: Add an alignment fault to Power ISA and check alignment in TLB.	2010-02-12 19:53:19 +00:00
Brad Beckmann	64999b4343	ruby: fixed data block assignment fix ... Fixed data block assignment to not delete if not internally allocated.	2010-02-10 16:40:54 -08:00
Brad Beckmann	714865e4a4	ruby: Initialize sender in MI_example-dir	2010-02-10 16:40:54 -08:00
Brad Beckmann	a407675106	ruby: Fixed slicc to initialize the m_is_blocking flag	2010-02-10 16:40:54 -08:00
Brad Beckmann	1d4c3ecdc3	ruby: Added FS support to the simple mesh topology ... Added full-system support to the simple mesh toplogy by allowing dma contrllers to be attached to router zero in the network.	2010-02-01 14:27:16 -08:00
Brad Beckmann	db2ecbb6b6	ruby: Set default protocol back to MI_example	2010-02-01 11:07:38 -08:00
Korey Sewell	c7f6e2661c	inorder: double delete inst bug ... Make sure that instructions are dereferenced/deleted twice by marking they are on the remove list	2010-01-31 18:30:59 -05:00
Korey Sewell	9357e353fc	inorder: inst count mgmt	2010-01-31 18:30:48 -05:00
Korey Sewell	be6724f7e7	inorder: implement split stores	2010-01-31 18:30:43 -05:00
Korey Sewell	6939482c49	inorder: implement split loads	2010-01-31 18:30:35 -05:00
Korey Sewell	ea8909925f	inorder: add activity stats	2010-01-31 18:30:24 -05:00
Korey Sewell	f3bc2df663	inorder: object cleanup in destructors	2010-01-31 18:30:08 -05:00
Korey Sewell	1a89e8f4cb	inorder: user per-thread dummy insts/reqs	2010-01-31 18:29:59 -05:00
Korey Sewell	002f1b8b7e	inorder: add execution unit stats	2010-01-31 18:29:49 -05:00
Korey Sewell	82c5a754e6	inorder: recvRetry bug fix ... - on certain retry requests you can get an assertion failure - fix by allowing the request to literally "Retry" itself if it wasnt successful before, and then block any requests through cache port while waiting for the cache to be made available for access	2010-01-31 18:29:18 -05:00
Korey Sewell	349d86c0e4	inorder-stats: add prereq to basic stat ... only show requests processed when the resource is actually in use	2010-01-31 18:29:06 -05:00
Korey Sewell	0b29c2d057	inorder: ctxt switch stats ... - m5 line enforcement on use_def.cc,hh	2010-01-31 18:28:59 -05:00
Korey Sewell	ffa9ecb1fa	inorder: pipeline stage stats ... add idle/run/utilization stats for each pipeline stage	2010-01-31 18:28:51 -05:00
Korey Sewell	4d749472e3	inorder: enforce stage bandwidth ... each stage keeps track of insts_processed on a per_thread basis but we should be keeping that on a total basis inorder to enforce stage width limits	2010-01-31 18:28:31 -05:00
Korey Sewell	b4e0ef7837	inorder: set thread status' ... set Active/Suspended/Halted status for threads. useful for system when determining if/when to exit simulation	2010-01-31 18:28:12 -05:00
Korey Sewell	5e0b8337ed	inorder: add/remove halt/deallocate context respectively ... Halt is called from the exit() system call while deallocate is unused. So to clear up things, just use halt and remove deallocate.	2010-01-31 18:28:05 -05:00
Korey Sewell	069b38c0d5	inorder: track last branch committed ... when threads are switching in/out the CPU, we need to keep track of special cases like branches. Add appropriate variables in ThreadState t track this and then use these variables when updating pc after context switch	2010-01-31 18:27:58 -05:00
Korey Sewell	aacc5cb205	inorder: add updatePC event to resPool ... this will be used for when a thread comes back from a cache miss, it needs to update the PCs because the inst might of been a branch or delayslot in which the next PC isnt always a straight addition	2010-01-31 18:27:49 -05:00
Korey Sewell	90d3b45a56	inorder: ready thread wakeup ... allow a thread to wakeup and be activated after it has been in suspended state and another thread is switched out. Need to give pipeline stages a "activateThread" function so that can get to their suspended instruction when the time is right.	2010-01-31 18:27:38 -05:00
Korey Sewell	3eb04b4ad7	inorder: add threadmodel flag ... this prints out messages relative to what threading model is being used (smt, switch-on-miss, single, etc.)	2010-01-31 18:27:25 -05:00
Korey Sewell	611a8642c2	inorder: mem. mgmt. update ... update address List and address Map to take into account multiple threads	2010-01-31 18:27:12 -05:00
Korey Sewell	4dbc2f1718	inorder: suspend in respool ... give resources their own specific activity to do for a "suspend" event instead of defaulting to deactivating the thread for a suspend thread event. This really matters for the fetch sequence unit which wants to remove the thread from fetching while other units want to ignore a thread suspension. If you deactivate a thread in a resource then you may lose some of the allotted bandwidth that the thread is taking up...	2010-01-31 18:27:02 -05:00
Korey Sewell	4ea296e296	inorder: fetch thread bug ... dont check total # of threads but instead all active threads	2010-01-31 18:26:54 -05:00
Korey Sewell	96b493d315	inorder: ready/suspend status fns ... update/add in the use of isThreadReady & isThreadSuspended functions.Check in activateThread what list a thread is on so it can be managed accordingly.	2010-01-31 18:26:47 -05:00
Korey Sewell	d9eaa2fe21	inorder-cleanup: remove unused thread functions	2010-01-31 18:26:40 -05:00
Korey Sewell	e1fcc64980	inorder: activate thread on cache miss ... -Support ability to activate next ready thread after a cache miss through the activateNextReadyContext/Thread() functions -To support this a "readyList" of thread ids is added -After a cache miss, thread will suspend and then call activitynextreadythread	2010-01-31 18:26:32 -05:00
Korey Sewell	4a945aab19	inorder: add event priority offset ... allow for events to schedule themselves later if desired. this is important because of cases like where you need to activate a thread only after the previous thread has been deactivated. The ordering there has to be enforced	2010-01-31 18:26:26 -05:00
Korey Sewell	eac5eac67a	inorder: squash on memory stall ... add code to recognize memory stalls in resources and the pipeline as well as squash a thread if there is a stall and we are in the switch on cache miss model	2010-01-31 18:26:13 -05:00
Korey Sewell	d8e0935af2	inorder: add insts to cpu event ... some events are going to need instruction data when they process, so just include the instruction in the event construction	2010-01-31 18:26:03 -05:00
Korey Sewell	e8312ab6f7	inorder: switch out buffer ... add buffer for instructions to switch out to in a pipeline stage can't squash the instruction and remove the pipeline so we kind of need to 'suspend' an instruction at the stage while the memory stall resolves for the switch on cache miss model	2010-01-31 18:25:48 -05:00
Korey Sewell	a892af7b26	inorder: dont allow early loads ... - loads were happening on same cycle as the address was generated which is slightly unrealistic. Instead, force address generation to be on separate cycle from load initiation - also, mark the stages in a more traditional way (F-D-X-M-W)	2010-01-31 18:25:27 -05:00
Korey Sewell	0e96798fe0	configs/inorder: add options for switch-on-miss to inorder cpu	2010-01-31 18:25:13 -05:00
Korey Sewell	7b3b362ba5	inorder: init internal debug cpu counters ... - cpuEventNum - resReqCount	2010-01-31 17:18:15 -05:00
Brad Beckmann	ab2f864af2	m5: Regression Tester Update ... This patch includes the necessary regression updates to test the new ruby configuration system. The patch includes support for multiple ruby protocols and adds the ruby random tester. The patch removes atomic mode test for ruby since ruby does not support atomic mode acceses. These tests can be added back in when ruby supports atomic mode for real. --HG-- rename : tests/quick/50.memtest/test.py => tests/quick/60.rubytest/test.py	2010-01-29 20:29:40 -08:00
Brad Beckmann	ceae8383ff	ruby: Replaced gems_common debug statements ... Replaced Ruby debug statements with M5 statements.	2010-01-29 20:29:34 -08:00
Brad Beckmann	143d8ea698	ruby: removed last level cache support ... Removed the last level cache support and MOESI_hammer's dependency on it. Replaces the LLC support with the more generic MachineType count.	2010-01-29 20:29:34 -08:00
Brad Beckmann	90aab239a1	ruby: Added a Scons option to prevent HTML file creation	2010-01-29 20:29:33 -08:00
Brad Beckmann	1feae85017	ruby: Removed static members in RubyPort including hitcallback ... Removed static members in RubyPort and removed the ruby request unique id.	2010-01-29 20:29:33 -08:00
Brad Beckmann	a579d3e43c	ruby: Removed the old config interface ... Removed the old config interface from RubySystem and libruby.	2010-01-29 20:29:33 -08:00
Brad Beckmann	e4218dd08f	ruby: Re-enabled orion power models ... Removed the dummy power function implementations so that Orion can implement them correctly. Since Orion lacks modular design, this patch simply enables scons to compile it. There are no python configuration changes in this patch.	2010-01-29 20:29:33 -08:00
Brad Beckmann	8dd45674ae	ruby: Converted Garnet to M5 configuration	2010-01-29 20:29:32 -08:00
Steve Reinhardt	b544462505	Garnet: reorganize directory tree. ... Rename the ruby/network/garnet-foo directories to garnet/foo. Move the common NetworkHeader.hh file from garnet-fixed-pipeline up to the common garnet directory. Fix up include paths. --HG-- rename : src/mem/ruby/network/garnet-fixed-pipeline/NetworkHeader.hh => src/mem/ruby/network/garnet/NetworkHeader.hh rename : src/mem/ruby/network/garnet-fixed-pipeline/CreditLink_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/CreditLink_d.hh rename : src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc rename : src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh rename : src/mem/ruby/network/garnet-fixed-pipeline/InputUnit_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.cc rename : src/mem/ruby/network/garnet-fixed-pipeline/InputUnit_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh rename : src/mem/ruby/network/garnet-fixed-pipeline/NetworkInterface_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc rename : src/mem/ruby/network/garnet-fixed-pipeline/NetworkInterface_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.hh rename : src/mem/ruby/network/garnet-fixed-pipeline/NetworkLink_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc rename : src/mem/ruby/network/garnet-fixed-pipeline/NetworkLink_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh rename : src/mem/ruby/network/garnet-fixed-pipeline/OutVcState_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/OutVcState_d.cc rename : src/mem/ruby/network/garnet-fixed-pipeline/OutVcState_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/OutVcState_d.hh rename : src/mem/ruby/network/garnet-fixed-pipeline/OutputUnit_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.cc rename : src/mem/ruby/network/garnet-fixed-pipeline/OutputUnit_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh rename : src/mem/ruby/network/garnet-fixed-pipeline/Router_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc rename : src/mem/ruby/network/garnet-fixed-pipeline/Router_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh rename : src/mem/ruby/network/garnet-fixed-pipeline/RoutingUnit_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/RoutingUnit_d.cc rename : src/mem/ruby/network/garnet-fixed-pipeline/RoutingUnit_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/RoutingUnit_d.hh rename : src/mem/ruby/network/garnet-fixed-pipeline/SConscript => src/mem/ruby/network/garnet/fixed-pipeline/SConscript rename : src/mem/ruby/network/garnet-fixed-pipeline/SWallocator_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc rename : src/mem/ruby/network/garnet-fixed-pipeline/SWallocator_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.hh rename : src/mem/ruby/network/garnet-fixed-pipeline/Switch_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc rename : src/mem/ruby/network/garnet-fixed-pipeline/Switch_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.hh rename : src/mem/ruby/network/garnet-fixed-pipeline/VCallocator_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/VCallocator_d.cc rename : src/mem/ruby/network/garnet-fixed-pipeline/VCallocator_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/VCallocator_d.hh rename : src/mem/ruby/network/garnet-fixed-pipeline/VirtualChannel_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.cc rename : src/mem/ruby/network/garnet-fixed-pipeline/VirtualChannel_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.hh rename : src/mem/ruby/network/garnet-fixed-pipeline/flitBuffer_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.cc rename : src/mem/ruby/network/garnet-fixed-pipeline/flitBuffer_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.hh rename : src/mem/ruby/network/garnet-fixed-pipeline/flit_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/flit_d.cc rename : src/mem/ruby/network/garnet-fixed-pipeline/flit_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/flit_d.hh rename : src/mem/ruby/network/garnet-flexible-pipeline/FlexibleConsumer.hh => src/mem/ruby/network/garnet/flexible-pipeline/FlexibleConsumer.hh rename : src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.cc => src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc rename : src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.hh => src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh rename : src/mem/ruby/network/garnet-flexible-pipeline/InVcState.cc => src/mem/ruby/network/garnet/flexible-pipeline/InVcState.cc rename : src/mem/ruby/network/garnet-flexible-pipeline/InVcState.hh => src/mem/ruby/network/garnet/flexible-pipeline/InVcState.hh rename : src/mem/ruby/network/garnet-flexible-pipeline/NetworkConfig.hh => src/mem/ruby/network/garnet/flexible-pipeline/NetworkConfig.hh rename : src/mem/ruby/network/garnet-flexible-pipeline/NetworkInterface.cc => src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc rename : src/mem/ruby/network/garnet-flexible-pipeline/NetworkInterface.hh => src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.hh rename : src/mem/ruby/network/garnet-flexible-pipeline/NetworkLink.cc => src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.cc rename : src/mem/ruby/network/garnet-flexible-pipeline/NetworkLink.hh => src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.hh rename : src/mem/ruby/network/garnet-flexible-pipeline/OutVcState.cc => src/mem/ruby/network/garnet/flexible-pipeline/OutVcState.cc rename : src/mem/ruby/network/garnet-flexible-pipeline/OutVcState.hh => src/mem/ruby/network/garnet/flexible-pipeline/OutVcState.hh rename : src/mem/ruby/network/garnet-flexible-pipeline/Router.cc => src/mem/ruby/network/garnet/flexible-pipeline/Router.cc rename : src/mem/ruby/network/garnet-flexible-pipeline/Router.hh => src/mem/ruby/network/garnet/flexible-pipeline/Router.hh rename : src/mem/ruby/network/garnet-flexible-pipeline/SConscript => src/mem/ruby/network/garnet/flexible-pipeline/SConscript rename : src/mem/ruby/network/garnet-flexible-pipeline/VCarbiter.cc => src/mem/ruby/network/garnet/flexible-pipeline/VCarbiter.cc rename : src/mem/ruby/network/garnet-flexible-pipeline/VCarbiter.hh => src/mem/ruby/network/garnet/flexible-pipeline/VCarbiter.hh rename : src/mem/ruby/network/garnet-flexible-pipeline/flit.cc => src/mem/ruby/network/garnet/flexible-pipeline/flit.cc rename : src/mem/ruby/network/garnet-flexible-pipeline/flit.hh => src/mem/ruby/network/garnet/flexible-pipeline/flit.hh rename : src/mem/ruby/network/garnet-flexible-pipeline/flitBuffer.cc => src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.cc rename : src/mem/ruby/network/garnet-flexible-pipeline/flitBuffer.hh => src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.hh rename : src/mem/ruby/network/garnet-flexible-pipeline/netconfig.defaults => src/mem/ruby/network/garnet/flexible-pipeline/netconfig.defaults	2010-01-29 20:29:30 -08:00
Brad Beckmann	6c867f8263	ruby: Added a mesh topology	2010-01-29 20:29:27 -08:00
Brad Beckmann	faa76fc248	ruby: MESI_CMP_directory updated to the new config system	2010-01-29 20:29:27 -08:00
Brad Beckmann	3e286d825d	ruby: Sorted the file includes to maintain consistency	2010-01-29 20:29:26 -08:00
Brad Beckmann	5fb1f5c72b	ruby: Renamed the MESI directory sm file ... Renamed the MESI directory file to be consistent with all other protocols. --HG-- rename : src/mem/protocol/MESI_CMP_directory-mem.sm => src/mem/protocol/MESI_CMP_directory-dir.sm	2010-01-29 20:29:26 -08:00
Brad Beckmann	79f354466e	ruby: Removed the GPL header in MESI_CMP_directory-msg ... I'm not sure how this got past our initial ruby code import, but this obviously needed to be removed.	2010-01-29 20:29:26 -08:00
Brad Beckmann	31fcf09a68	ruby: MOESI_CMP_directory updated to the new config system	2010-01-29 20:29:26 -08:00
Brad Beckmann	1c4405ad5e	ruby: Added atomic support to MOESI_CMP_token	2010-01-29 20:29:25 -08:00
Brad Beckmann	042d5b87a4	ruby: fixed memory fetch bug for persistent requests	2010-01-29 20:29:25 -08:00
Brad Beckmann	d77a9df3c1	ruby: MOESI_CMP_token updates to use the new config system	2010-01-29 20:29:25 -08:00
Brad Beckmann	d42152742b	ruby: Allows boolean and string defaults for StateMachine parameters	2010-01-29 20:29:24 -08:00
Brad Beckmann	b3d195153e	ruby: MI_example updates to use the new config system	2010-01-29 20:29:24 -08:00
Brad Beckmann	134cc3d48d	ruby: convert to M5 MemorySize ... Converted both ruby caches and directory memory to use the M5 MemorySize python type.	2010-01-29 20:29:23 -08:00
Brad Beckmann	3a835c7cbb	ruby: Added Cache and MemCntrl profiler calls	2010-01-29 20:29:23 -08:00
Brad Beckmann	47502163b7	ruby: added data print to ruby request	2010-01-29 20:29:23 -08:00
Brad Beckmann	66279fac3f	ruby: Added atomic support to MOESI_hammer	2010-01-29 20:29:23 -08:00
Brad Beckmann	45230a4f6b	ruby: added the GEMS ruby tester	2010-01-29 20:29:23 -08:00
Brad Beckmann	4eb3bfc31b	ruby: fixed MOESI_hammer data writebacks to the directory	2010-01-29 20:29:22 -08:00
Brad Beckmann	f88faa6c11	ruby: cleaned up ruby profilers ... Cleaned up the ruby profilers by moving the memory controller profiling code out of the main profiler object and into a separate object similar to the current CacheProfiler. Both the CacheProfiler and MemCntrlProfiler are specific to a particular Ruby object, CacheMemory and MemoryControl respectively. Therefore, these profilers should not be SimObjects and created by the python configuration system, but instead private objects. This simplifies the creation of these profilers.	2010-01-29 20:29:22 -08:00
Brad Beckmann	cfe41d0a1b	ruby: Removed RubySystem::getNumberOfSequencers ... removed the static function RubySystem::getNumberOfSequencers and replaced it with a python config variable	2010-01-29 20:29:21 -08:00
Brad Beckmann	1907e39fd2	ruby: added ruby stats print ... Moved the previous rubymem stats print feature to ruby System so that ruby stats are printed on simulation exit.	2010-01-29 20:29:21 -08:00
Brad Beckmann	020716cab3	ruby: fixed Set.cc bug to allow zero sized sets ... This is necessary for example when no dma sequencers are necessary in the simulated system.	2010-01-29 20:29:21 -08:00
Brad Beckmann	ce2d13195b	ruby: FS support using the new configuration system	2010-01-29 20:29:21 -08:00
Brad Beckmann	dc758641c9	ruby: reorganized ruby python configuration ... Reorganized ruby python configuration so that protocol and ruby memory system configuration code can be shared by multiple front-end configuration files (i.e. memory tester, full system, and hopefully the regression tester). This code works for memory tester, but have not tested fs mode.	2010-01-29 20:29:20 -08:00
Brad Beckmann	e735ca7c77	ruby: Removed out_link_vec from Consumer ... Removed the out_line_vec data structure from the Consumer. I'm not sure what this did before, but currently it has no usefulness.	2010-01-29 20:29:20 -08:00
Brad Beckmann	0f6535dba1	ruby: Convered ruby tracing support usage of sequencer ... Modified ruby's tracing support to no longer rely on the RubySystem map to convert a sequencer string name to a sequencer pointer. As a temporary solution, the code uses the sim_object find function. Eventually, we should develop a better fix.	2010-01-29 20:29:20 -08:00
Brad Beckmann	2c9ca672df	ruby: Memory Controller Profiler with new config system ... This patch includes a rather substantial change to the memory controller profiler in order to work with the new configuration system. Most noteably, the mem_cntrl_profiler no longer uses a string map, but instead a vector. Eventually this support should be removed from the main profiler and go into a separate object. Each memory controller should have a pointer to that new mem_cntrl profile object.	2010-01-29 20:29:20 -08:00
Brad Beckmann	2a0555470c	ruby: Converted MOESI_hammer dma cntrl to new config system	2010-01-29 20:29:19 -08:00
Brad Beckmann	3b290a35ac	ruby: Added the cache profiler to the new config system	2010-01-29 20:29:19 -08:00
Brad Beckmann	4e5f4b5074	ruby: Converted the sequencer deadlock event to m5 eventq	2010-01-29 20:29:19 -08:00
Brad Beckmann	e15abd17f9	ruby: Wrapped ruby events into m5 events ... Wrapped ruby events using the m5 event object. Removed the prio_heap from ruby's event queue and instead schedule ruby events on the m5 event queue.	2010-01-29 20:29:19 -08:00
Brad Beckmann	63a60cc81e	ruby: Removed the tech_nm variable from RubySystem	2010-01-29 20:29:19 -08:00
Brad Beckmann	12daaed84a	ruby: Added clock to ruby system ... As a first step to migrate ruby to the M5 eventqueue, added a clock variable to the ruby system.	2010-01-29 20:29:19 -08:00
Brad Beckmann	ed81489954	ruby: Ruby changes required to use the python config system ... This patch includes the necessary changes to connect ruby objects using the python configuration system. Mainly it consists of removing unnecessary ruby object pointers and connecting the necessary object pointers using the generated param objects. This patch includes the slicc changes necessary to connect generated ruby objects together using the python configuraiton system.	2010-01-29 20:29:19 -08:00
Brad Beckmann	42bebab779	ruby: connects sm queues to the network	2010-01-29 20:29:18 -08:00
Steve Reinhardt	a8ea70dac6	ruby: Calculate system total memory capacity in Python ... rather than in RubySystem object.	2010-01-29 20:29:18 -08:00
Steve Reinhardt	0b54f1db8e	ruby: Add support for generating topologies in Python.	2010-01-29 20:29:17 -08:00
Steve Reinhardt	184cf4db5b	scons: ignore blank lines in .slicc files	2010-01-29 20:29:17 -08:00
Steve Reinhardt	c6f1d959be	ruby: Make SLICC-generated objects SimObjects. ... Also add SLICC support for state-machine parameter defaults (passed through to Python as SimObject Param defaults).	2010-01-29 20:29:17 -08:00
Steve Reinhardt	98c94cfe3c	ruby: Convert most Ruby objects to M5 SimObjects. ... The necessary companion conversion of Ruby objects generated by SLICC are converted to M5 SimObjects in the following patch, so this patch alone does not compile. Conversion of Garnet network models is also handled in a separate patch; that code is temporarily disabled from compiling to allow testing of interim code.	2010-01-29 20:29:17 -08:00
Steve Reinhardt	b43994ba45	ruby: get rid of obsolete, unused CustomTopology class.	2010-01-29 20:29:14 -08:00
Brad Beckmann	7f03dce012	ruby: fix out_port declaration	2010-01-29 20:29:14 -08:00
Brad Beckmann	43e4f59e4f	ruby: Added message type check to OutPortDeclAST.py ... Though OutPort's message type is not used to generate code, this fix checks that the programmer's intent is correct. Eventually, we may want to remove the message type from the OutPort declaration statement.	2010-01-29 20:29:13 -08:00
Nathan Binkert	5b90934dd2	build: need to include cstdio	2010-01-23 14:02:03 -08:00
Nathan Binkert	8a3fbbd8d9	compile: compile on 32 bit hardware	2009-11-05 17:21:26 -08:00
Nathan Binkert	52ccfde2cd	isa_parser: allow negative integer literals	2009-11-05 17:21:25 -08:00
Derek Hower	589218168c	Automated merge with ssh://hg@m5sim.org/m5	2010-01-22 17:23:21 -06:00
Lisa Hsu	d6da172517	util: do checkpoint aggregation more cleanly, fix last changeset. ... 1) Move alpha-specific code out of page_table.cc:serialize(). 2) Begin serializing M5_pid and unserializing it, but adding an function to do optional paramIn so that old checkpoints don't need to be fixed up. 3) Fix up alpha startup code so that the unserialized M5_pid value is properly written to DTB_IPR_ASN. 4) Fix the memory unserialize that I forgot somehow in the last changeset. 5) Add in an agg_se.py to handle aggregated checkpoints. --bench foo-bar plus positional arguments foo bar are the only changes in usage from se.py. Note this aggregation stuff has only been tested for Alpha and nothing else, though it should take a very minimal amount of work to get it to work with another ISA.	2010-01-19 22:03:44 -08:00
Derek Hower	07ea0891f1	ruby: new atomics implementation ... This patch changes the way that Ruby handles atomic RMW instructions. This implementation, unlike the prior one, is protocol independent. It works by locking an address from the sequencer immediately after the read portion of an RMW completes. When that address is locked, the coherence controller will only satisfy requests coming from one port (e.g., the mandatory queue) and will ignore all others. After the write portion completed, the line is unlocked. This should also work with multi-line atomics, as long as the blocks are always acquired in the same order.	2010-01-19 17:11:36 -06:00
Derek Hower	279f179bab	merge	2010-01-19 15:48:12 -06:00
Lisa Hsu	4a40ac71f8	util: make a generic checkpoint aggregator that can aggregate different cpts into one multi-programmed cpt. Make minor changes to serialization/unserialization to get it to work properly. Note that checkpoints were made with a comment at the beginning with // - this must be changed to ## to work properly with the python config parser in the aggregator.	2010-01-18 14:30:31 -08:00
Lisa Hsu	8b4e8690b7	cache: make tags->insertBlock() and tags->accessBlock() context aware so that the cache can make context-specific decisions within their various tag policy implementations.	2010-01-12 10:53:02 -08:00
Lisa Hsu	9f63548478	since totalInstructions() is impl'ed by all the cpus, make it an abstract base class.	2010-01-12 10:22:46 -08:00
Lisa Hsu	daebe18e89	faults: i think these fault invocations should be panic and not fatal. it definitely made implementing a trace cpu easier this way.	2010-01-12 10:17:19 -08:00
Matt DeVuyst	18dc80e07b	MIPS: Beef up process initialization.	2009-12-31 15:30:51 -05:00
Gabe Black	ecaa7070e6	MIPS: Implement the SE mode version of rdhwr.	2009-12-31 15:30:51 -05:00
Gabe Black	c70f3c93af	MIPS: Fix decoding of the rdhwr instruction.	2009-12-31 15:30:51 -05:00
Gabe Black	134937b594	MIPS: Implement the set_thread_area system call.	2009-12-31 15:30:50 -05:00
Gabe Black	d3ed32b989	MIPS: Create an artificial control register to hold the thread pointer. ... In Linux, the set_thread_area system call stores the address of the thread local storage area into a field of the current thread_info structure. Later, to access that value, the program uses the rdhwr instruction to read a "hardware register" with index 29. The 64 bit MIPS manual, volume II, says that index 29 is reserved for a future ABI extension and should cause a "Reserved Instruction Exception". In Linux (and potentially other ISAs) that exception is trapped and emulated to return the value stored by set_thread_area as if that were actually stored by a physical register. The tp_value address (as named in the Linux kernel) is ironically stored as a control register so that it goes with a particular ThreadContext. Syscall emulation will use that to emulate storing to the OS's thread info structure, and rdhwr will emulate faulting and returning that value from software by returning the value itself, as if it was in hardware. In other words, we fake faking the register in SE mode. In an FS mode implementation it should work as specified in the manual.	2009-12-31 15:30:50 -05:00
Gabe Black	cc07dcf026	MIPS: Extract CPU pointer from the thread context in scheduleCP0 setMiscReg. ... The MIPS ISA object expects to be constructed with a CPU pointer it uses to look at other thread contexts and allow them to be manipulated with control registers. Unfortunately, that differs from all the other ISA classes and would complicate their implementation. This change makes the event constructor use a CPU pointer pulled out of the thread context passed to setMiscReg instead.	2009-12-31 15:30:50 -05:00
Gabe Black	1261f1d8db	MIPS: Add missing syscall slots. ... These are all after the existing ones, suggesting they were added after the original list was created.	2009-12-21 14:59:40 -08:00
Soumyaroop Roy	1bd0f772f1	Alpha: Implement MVI and remaining BWX instructions.	2009-12-20 15:03:23 -06:00
Gabe Black	3e1cda5080	X86: Add a latency that describes how long an interrupt takes to propagate through the IO APIC.	2009-12-19 01:50:06 -08:00
Gabe Black	c7ca1d3c8a	X86: Add a common named flag for signed media operations.	2009-12-19 01:48:31 -08:00
Gabe Black	2554511533	X86: Create a common flag with a name to indicate high multiplies.	2009-12-19 01:48:07 -08:00
Gabe Black	e474079ddc	X86: Create a common flag with a name to indicate scalar media instructions.	2009-12-19 01:47:30 -08:00
Derek Hower	5aa104e072	ruby: cleaned up ruby-lang configuration	2009-12-04 13:12:40 -06:00
Brad Beckmann	5d8a669539	Resurrection of the CMP token protocol to GEM5	2009-11-18 16:34:33 -08:00
Brad Beckmann	dcac2ec24c	ruby: removed the chip pointer from MessageBuffer ... The Chip object no longer exists and thus is removed from the MessageBuffer constructor.	2009-11-18 16:34:32 -08:00
Brad Beckmann	c9764b1ff1	ruby: added error message to isinstance check ... Added error message when a symbol is not an instance of a particular expected type.	2009-11-18 16:34:32 -08:00
Brad Beckmann	20f872ed2a	ruby: Added boolean to State Machine parameters ... * * * ruby: Removed primitive .hh includes	2009-11-18 16:34:32 -08:00
Brad Beckmann	8011e80725	ruby: The persistent table files from GEMS ... These files are need by the MOESI_CMP_token protocol.	2009-11-18 16:34:32 -08:00
Brad Beckmann	cef3c56163	ruby: MOESI hammer support for DMA reads and writes	2009-11-18 16:34:32 -08:00
Brad Beckmann	dbb2c111cc	ruby: Added a memory controller feature to MOESI hammer	2009-11-18 16:34:32 -08:00
Brad Beckmann	bc12b8432d	ruby: Hammer ruby configuration support	2009-11-18 16:34:32 -08:00
Brad Beckmann	877be2009c	ruby: Changes necessary to get the hammer protocol to work in GEM5	2009-11-18 16:34:32 -08:00
Brad Beckmann	b0973035b4	ruby: added the original hammer protocols from old ruby	2009-11-18 16:34:31 -08:00
Brad Beckmann	2783a7b9ad	ruby: returns the number of LLC needed for broadcast ... Added feature to CacheMemory to return the number of last level caches. This count is need for broadcast protocols such as MOESI_hammer.	2009-11-18 16:34:31 -08:00
Brad Beckmann	7b8fcecf11	ruby: cache configuration fix to use bytes ... Changed cache size to be in bytes instead of kb so that testers can use very small caches and increase the chance of writeback races.	2009-11-18 16:34:31 -08:00
Brad Beckmann	99338a7460	ruby: fix CacheMemory destructor	2009-11-18 16:33:35 -08:00
Brad Beckmann	7ab484624f	ruby: split CacheMemory.hh into a .hh and a .cc	2009-11-18 16:33:35 -08:00
Brad Beckmann	8b0f970084	ruby: Added default names to message buffers ... Added default names to message buffers created by the simple network.	2009-11-18 13:55:58 -08:00
Brad Beckmann	ed54ecf1c8	ruby: slicc method error fix ... Added error message when a method call is not supported by an object.	2009-11-18 13:55:58 -08:00
Brad Beckmann	994169327a	ruby: slicc action error fix ... Small fix to the State Machine error message when duplicate actions are defined.	2009-11-18 13:55:58 -08:00
Brad Beckmann	cc2db929cb	ruby: slicc state machine error fixes ... Added error messages when: - a state does not exist in a machine's list of known states. - an event does not exist in a machine - the actions of a certain machine have not been declared	2009-11-18 13:55:58 -08:00
Brad Beckmann	e84881b7a3	ruby: Removed unused action z_stall	2009-11-18 13:55:58 -08:00
Brad Beckmann	b5d2052fa0	m5: Fixed bug in atomic cpu destructor	2009-11-18 13:55:58 -08:00
Brad Beckmann	faf1d97f24	ruby: fixed dma mi example to work with multiple dma ports	2009-11-18 13:55:58 -08:00
Brad Beckmann	f54790977b	m5: removed master and slave deletions. ... The unresolved destructor call caused a seg fault when called.	2009-11-18 13:55:58 -08:00
Brad Beckmann	4d731a522d	m5: fixed destructor to deschedule the tickEvent and event	2009-11-18 13:55:58 -08:00
Brad Beckmann	93f0069dd5	ruby: getPort function fix ... Fixed RubyMemory::getPort function to not pass in a -1 for the idx parameter	2009-11-18 13:55:58 -08:00
Brad Beckmann	204d1776ca	ruby: Fixed Directory memory destructor	2009-11-18 13:55:58 -08:00
Brad Beckmann	6e1dc2546c	m5: Added isValidSrc and isValidDest calls to packet.hh	2009-11-18 13:55:58 -08:00
Brad Beckmann	90d6e2652f	ruby: included ruby config parameter ports per core ... Slightly improved the major hack need to correctly assign the number of ports per core. CPUs have two ports: icache + dcache. MemTester has one port.	2009-11-18 13:55:58 -08:00
Brad Beckmann	dce53610c3	ruby: Added error check for openning the ruby config file	2009-11-18 13:55:58 -08:00
Brad Beckmann	3cf24f9716	ruby: Support for merging ALPHA_FS and ruby ... Connects M5 cpu and dma ports directly to ruby sequencers and dma sequencers. Rubymem also includes a pio port so that pio requests and be forwarded to a special pio bus connecting to device pio ports.	2009-11-18 13:55:58 -08:00
Brad Beckmann	d7a4f665ed	ruby: Added more info to bridge error message	2009-11-18 13:55:57 -08:00
Brad Beckmann	17e14efa7e	ruby: Ruby 64-bit address output fixes.	2009-11-18 13:55:57 -08:00
Brad Beckmann	b7cc66af31	ruby: Ruby destruction fix.	2009-11-18 13:55:57 -08:00
Brad Beckmann	5492f71755	ruby: Ruby debug print fixes.	2009-11-18 13:55:57 -08:00
Derek Hower	9ef5e72917	ruby: added sequencer stats to track what requests are waiting on	2009-11-18 11:55:30 -06:00
Derek Hower	d11dd6ed2c	ruby: turned off randomization by default, turned on memory controller random arbitrate	2009-11-18 11:53:43 -06:00
Ali Saidi	422f0d9f10	ARM: Begin implementing CP15	2009-11-17 18:02:09 -06:00
Ali Saidi	0916c376a9	ARM: Differentiate between LDM exception return and LDM user regs.	2009-11-17 18:02:08 -06:00
Ali Saidi	1470dae8e9	ARM: Boilerplate full-system code. ... --HG-- rename : src/arch/sparc/interrupts.hh => src/arch/arm/interrupts.hh rename : src/arch/sparc/kernel_stats.hh => src/arch/arm/kernel_stats.hh rename : src/arch/sparc/stacktrace.cc => src/arch/arm/stacktrace.cc rename : src/arch/sparc/system.cc => src/arch/arm/system.cc rename : src/arch/sparc/system.hh => src/arch/arm/system.hh rename : src/dev/sparc/T1000.py => src/dev/arm/Versatile.py rename : src/dev/sparc/t1000.cc => src/dev/arm/versatile.cc rename : src/dev/sparc/t1000.hh => src/dev/arm/versatile.hh	2009-11-17 18:02:08 -06:00
Ali Saidi	171e7f7b24	imported patch isa_fixes2.diff	2009-11-16 11:37:03 -06:00
Gabe Black	9127ee5ac8	ARM: Make the exception return form of ldm restore CPSR.	2009-11-15 00:23:14 -08:00
Gabe Black	903fb8c73d	ARM: Create a new type of load uop that restores spsr into cpsr.	2009-11-15 00:15:42 -08:00
Gabe Black	b41725f723	ARM: Check in the actual change from the last commit. ... The last commit was somehow empty. This was what was supposed to go in it.	2009-11-14 21:03:10 -08:00
Gabe Black	c4042985d7	ARM: Fix up the implmentation of the msr instruction.	2009-11-14 19:22:30 -08:00
Gabe Black	e2ab64543b	ARM: Define a mask to differentiate purely CPSR bits from CondCodes bits.	2009-11-14 19:22:30 -08:00
Gabe Black	425ebf6bd7	ARM: Add a bitfield to indicate if an immediate should be used.	2009-11-14 19:22:30 -08:00
Gabe Black	e543f16247	ARM: Write some functions to write to the CPSR and SPSR for instructions.	2009-11-14 19:22:30 -08:00
Gabe Black	812e390693	ARM: Fix up the implmentation of the mrs instruction.	2009-11-14 19:22:29 -08:00
Gabe Black	1df0025e28	ARM: More accurately describe the effects of using the control operands.	2009-11-14 19:22:29 -08:00
Gabe Black	50b9149c75	ARM: Hook up the moded versions of the SPSR. ... These registers can be accessed directly, or through MISCREG_SPSR which will act as whichever SPSR is appropriate for the current mode.	2009-11-14 19:22:29 -08:00
Ali Saidi	4e9ce1805e	SE: Fix SE mode OS X compilation.	2009-11-14 11:49:01 -06:00
Ali Saidi	48bc573f5f	ARM: Move around decoder to properly decode CP15	2009-11-14 11:25:00 -06:00
Derek Hower	2f5839832e	ruby: added -A option to TwoLevel_SplitL1UnifiedL2 to set the L1 cache size	2009-11-13 09:45:23 -06:00
Derek Hower	f7f475a6f4	ruby: gave ALIASED_REQUEST priority over BUFFER_FULL in sequencer	2009-11-13 09:44:51 -06:00
Derek Hower	2ee04d6587	ruby: reduce the memory usage of ruby by making memory vector page based	2009-11-13 09:43:39 -06:00
Derek Hower	ceb8fde914	ruby: cache memory bugfix	2009-11-13 09:42:47 -06:00
Vince Weaver	8f6744c19c	X86: add ULL to 1's being shifted in 64-bit values ... Some of the micro-ops weren't casting 1 to ULL before shifting, which can cause problems. On the perl makerand input this caused some values to be negative that shouldn't have been. The casts are done as ULL(1) instead of 1ULL to match others in the m5 code base.	2009-11-11 17:49:09 -05:00
Gabe Black	5524af83ef	ARM: Fix some bugs in the ISA desc and fill out some instructions.	2009-11-10 23:44:05 -08:00
Gabe Black	850eb54a7c	Merge with the head.	2009-11-10 21:12:53 -08:00
Gabe Black	b8120f6c38	Mem: Eliminate the NO_FAULT request flag.	2009-11-10 21:10:18 -08:00
Gabe Black	2e28da5583	ARM: Implement fault classes. ... Implement some fault classes using the curriously recurring template pattern, similar to SPARCs.	2009-11-10 20:34:38 -08:00
Gabe Black	4779020e13	ARM: Fix the integer register indexes. ... The PC indexes in the various register sets was defined in the section for unaliased registers which was throwing off the indexing. This moves those where they belong. Also, to make detecting accesses to the PC easier and because it's in the same place in all modes, the intRegForceUser function now passes it through as index 15.	2009-11-10 20:19:55 -08:00
Vince Weaver	53e27c0277	X86: Fix bugs in movd implementation. ... Unfortunately my implementation of the movd instruction had two bugs. In one case, when moving a 32-bit value into an xmm register, the lower half of the xmm register was not zero extended. The other case is that xmm was used instead of xmmlm as the source for a register move. My test case didn't notice this at first as it moved xmm0 to eax, which both have the same register number.	2009-11-10 11:29:30 -05:00
Vince Weaver	e81cc233a6	X86: Remove double-cast in Cvtf2i micro-op ... This double cast led to rounding errors which caused some benchmarks to get the wrong values, most notably lucas which failed spectacularly due to CVTTSD2SI returning an off-by-one value. equake was also broken.	2009-11-10 11:18:23 -05:00
Vince Weaver	7da221ca82	syscall: missing initializer in getcwd call ... This one case was missed during the update to stack-based arguments. Without this fix, m5 will crash during a gwtcwd call, at least with X86.	2009-11-09 10:02:55 -05:00
Gabe Black	bbbfdee2ed	X86: Don't panic on faults on prefetches in SE mode.	2009-11-08 22:49:58 -08:00
Gabe Black	44e912c6bd	X86: Explain what really didn't work with unmapped addresses in SE mode.	2009-11-08 22:49:57 -08:00
Gabe Black	53086dfefe	X86: Make x86 use PREFETCH instead of PF_EXCLUSIVE.	2009-11-08 22:49:57 -08:00
Nathan Binkert	b1a1f9aec8	automerge	2009-11-08 20:15:54 -08:00
Steve Reinhardt	374d337693	scons: deal with generated .py files properly	2009-11-08 17:35:49 -08:00
Gabe Black	8a4af3668d	ARM: Support forcing load/store multiple to use user registers.	2009-11-08 15:49:03 -08:00
Gabe Black	bb903b6514	ARM: Simplify the load/store multiple generation code. ... Specifically, get rid of the big switch statement so more cases can be handled. Enumerating all the possible settings doesn't scale well. Also do some minor style clean up.	2009-11-08 15:16:59 -08:00
Nathan Binkert	708faa7677	compile: wrap 64bit numbers with ULL() so 32bit compiles work ... In the isa_parser, we need to check case statements.	2009-11-08 13:31:59 -08:00
Gabe Black	48525f581c	ARM: Split the condition codes out of the CPSR. ... This allows those bits to be renamed while allowing the other fields to control the behavior of the processor.	2009-11-08 02:08:40 -08:00
Gabe Black	d188821d37	ARM: Add in more bits for the mon mode.	2009-11-08 02:01:02 -08:00
Gabe Black	3a3e846151	ARM: Get rid of NumInternalProcRegs. ... That constant is a carry over from Alpha and doesn't do anything in ARM.	2009-11-08 02:00:55 -08:00
Gabe Black	78bd8fe44f	ARM: Add back in spots for Rhi and Rlo, and use a named constant for LR.	2009-11-08 01:59:20 -08:00
Gabe Black	f63c260d89	ARM: Get rid of the Raddr operand.	2009-11-08 01:57:34 -08:00
Gabe Black	43e9209c21	ARM: Initialize processes in user mode. ... I accidentally left in a change to test using int registers in system mode. This change reverts that.	2009-11-08 00:54:32 -08:00
Gabe Black	a2b76516c4	ARM: Implement the shadow registers using register flattening.	2009-11-08 00:07:49 -08:00
Gabe Black	4a454c4f47	ARM: Set up an intregs.hh for ARM. ... Add constants for all the modes and registers, maps for aliasing, functions that use the maps and range check, and use a named constant instead of a magic number for the microcode register.	2009-11-08 00:07:35 -08:00
Gabe Black	18b21c1eca	ARM: Get rid of some unneeded register indexes.	2009-11-07 22:34:33 -08:00
Vince Weaver	5cf2e7ccf0	X86: Fix problem with movhps instruction ... This problem is like the one fixed with movhpd a few weeks ago. A +8 displacement is used to access memory when there should be none. This fix is needed for the perlbmk spec2k benchmark to run.	2009-11-04 13:22:15 -05:00
Steve Reinhardt	9098010e3f	slicc: tweak file enumeration for scons ... Right now .cc and .hh files are handled separately, but then they're just munged together at the end by scons, so it doesn't buy us anything. Might as well munge from the start since we'll eventually be adding generated Python files to the list too.	2009-11-05 11:11:06 -08:00
Steve Reinhardt	058ccfc7fe	slicc: whack some of Nate's leftover debug code	2009-11-05 11:11:05 -08:00
Nathan Binkert	2c5fe6f95e	build: fix compile problems pointed out by gcc 4.4	2009-11-04 16:57:01 -08:00
Steve Reinhardt	fbfe92b5b8	o3: get rid of unused physmem pointer	2009-11-04 14:23:25 -08:00
Vince Weaver	a1042db290	X86: Enable x86_64 vsyscall support ... 64-bit vsyscall is different than 32-bit. There are only two syscalls, time and gettimeofday. On a real system, there is complicated code that implements these without entering the kernel. That would be complicated to implement in m5. Instead we just place code that calls the regular syscalls (this is how tools such as valgrind handle this case). This is needed for the perlbmk spec2k benchmark.	2009-11-04 00:47:12 -05:00
Vince Weaver	9b0a747dd4	X86: Hook up time syscall on X86 ... This has been tested and verified that it works.	2009-11-04 00:19:15 -05:00
Vince Weaver	a12557439b	X86: Add support for x86 psrldq and pslldq instructions ... These are complicated instructions and the micro-code might be suboptimal. This has been tested with some small sample programs (attached) The psrldq instruction is needed by various spec2k programs.	2009-10-30 12:49:37 -04:00
Vince Weaver	5873ec2238	X86: Implement movd_Vo_Edp on X86 ... This patch implements the movd_Vo_Edp series of instructions. It addresses various concerns by Gabe Black about which file the instruction belonged in, as well as supporting REX prefixed instructions properly. This instruction is needed for some of the spec2k benchmarks, most notably bzip2.	2009-10-30 15:52:33 -04:00