sanchayanmaity/gem5 - Sanchayan Maity's repositories

Author	SHA1	Message	Date
Nathan Binkert	4523741c1c	quell gcc 4.3 warning	2009-02-27 17:29:58 -08:00
Gabe Black	b69a9ad45a	X86: Install the exit system call.	2009-02-27 09:26:41 -08:00
Gabe Black	9265b3d598	X86: Install the 32 bit write system call.	2009-02-27 09:26:32 -08:00
Gabe Black	b36f28472d	X86: Implement shrd.	2009-02-27 09:26:26 -08:00
Gabe Black	2fe87e62ba	X86: Add a structure to allow mapping between the host and guest fstat formats.	2009-02-27 09:26:17 -08:00
Gabe Black	27b751ec46	X86: Don't treat the REX prefixes as prefixes in 32 bit modes. These are inc/dec instructions.	2009-02-27 09:26:09 -08:00
Gabe Black	aa51c01d69	X86: Set address size to 64 bits when generating addresses internally.	2009-02-27 09:26:01 -08:00
Gabe Black	db3c51d3a0	X86: Add a vsyscall page for 32 bit processes to use.	2009-02-27 09:25:51 -08:00
Gabe Black	c3d7d7ed0e	X86: Implement sysenter as a system call interface.	2009-02-27 09:25:43 -08:00
Gabe Black	5c1cc99d48	X86: Add a 32 bit mmap2 system call.	2009-02-27 09:25:33 -08:00
Gabe Black	04dbed79f8	X86: Install a 32 bit fstat64 system call.	2009-02-27 09:25:26 -08:00
Gabe Black	8a1eb7e8be	X86: Take address size into account when computing an effective address.	2009-02-27 09:25:16 -08:00
Gabe Black	1d18eb9043	X86: Make instructions that use intseg preserve all 8 bytes of their addresses.	2009-02-27 09:25:02 -08:00
Gabe Black	79bc1b3740	X86: Fix a decoder bug and add in some missing instructions.	2009-02-27 09:24:10 -08:00
Gabe Black	3dfa564e70	X86: Respect segment override prefixes even when there's no ModRM byte.	2009-02-27 09:23:58 -08:00
Gabe Black	9dfa3f7f73	X86: Fix segment limit checks.	2009-02-27 09:23:50 -08:00
Gabe Black	9491debaa6	X86: Implement the 32 bit set_thread_area system call.	2009-02-27 09:23:42 -08:00
Gabe Black	1786f20058	X86: Set an initial value for the LDT selector.	2009-02-27 09:23:27 -08:00
Gabe Black	e23d688d8f	X86: Set up a space for a GDT in SE so we can set up TLS or LDT segments.	2009-02-27 09:23:17 -08:00
Gabe Black	281ef8111a	X86: Compute shift instruction flags correctly.	2009-02-27 09:23:00 -08:00
Gabe Black	14fc06640e	X86: Install some 32 bit system calls.	2009-02-27 09:22:50 -08:00
Gabe Black	6ca53f8675	X86: Handle 32 bit system call arguments.	2009-02-27 09:22:30 -08:00
Gabe Black	9a000c5173	Processes: Make getting and setting system call arguments part of a process object.	2009-02-27 09:22:14 -08:00
Gabe Black	60aab03e85	X86: Implement the int system call interface in the decoder.	2009-02-27 09:21:58 -08:00
Gabe Black	05de9f4e2c	X86: Distinguish the width of values on the stack between 32 and 64 bit processes.	2009-02-27 09:21:36 -08:00
Gabe Black	932f6440a1	X86: Add a class to support 32 bit x86 linux process.	2009-02-27 09:21:14 -08:00
Ali Saidi	bebbc9dc89	CPA: Add annotations to IGbE and CopyEngine device models.	2009-02-26 19:29:17 -05:00
Ali Saidi	d447ccb2c6	CPA: Add code to automatically record function symbols as CPU executes.	2009-02-26 19:29:17 -05:00
Ali Saidi	6fd4bc34a1	CPA: Add new object for gathering critical path annotations.	2009-02-26 19:29:17 -05:00
Ali Saidi	894925f135	Trace: fix the --trace-start option	2009-02-26 19:29:16 -05:00
Gabe Black	4a64493158	Devices: Make the RTC device reflect the use of BCD in its status registers.	2009-02-25 10:22:49 -08:00
Gabe Black	7400769768	X86: Implement IST stack switching.	2009-02-25 10:22:43 -08:00
Gabe Black	5c546e3504	CPU: Only look up the nearest symbol in the kernel if you're actually in kernel code.	2009-02-25 10:22:36 -08:00
Gabe Black	437b02884d	ISA: Get rid of the get*RegName functions.	2009-02-25 10:22:31 -08:00
Gabe Black	3b01535ec1	SPARC: Get rid of the state keeping track of register frames.	2009-02-25 10:22:25 -08:00
Gabe Black	4633677145	ISA: Set up common trace flags for tracing registers.	2009-02-25 10:22:17 -08:00
Gabe Black	44d5351071	ISA: Get rid of FlattenIntIndex function.	2009-02-25 10:22:09 -08:00
Gabe Black	c1c61d52a0	SPARC: Get rid of flattenIndex in the int register file.	2009-02-25 10:21:59 -08:00
Gabe Black	ce2e50a64c	ISA: Use the "Stack" traceflag for DPRINTFs about the initial stack frame.	2009-02-25 10:21:52 -08:00
Gabe Black	9d5b6e377f	SPARC: Get rid of the setGlobals function.	2009-02-25 10:21:46 -08:00
Gabe Black	f41ce6b5e9	SPARC: Get rid of the setCWP function.	2009-02-25 10:21:40 -08:00
Gabe Black	88ee7d4c32	SPARC: Add a traceflag for register windows.	2009-02-25 10:21:33 -08:00
Gabe Black	7aa875f4f3	X86: Implement the lldt instruction.	2009-02-25 10:21:27 -08:00
Gabe Black	bda7077c64	X86: Add segmentation checks for ldt related descriptors and selectors.	2009-02-25 10:21:21 -08:00
Gabe Black	e08d60389d	X86: Make the TSS type check actually return a fault if it fails.	2009-02-25 10:21:14 -08:00
Gabe Black	68300cfb8c	X86: Make rdcr use merge and the mov to control register instructions use the right operand size.	2009-02-25 10:21:08 -08:00
Gabe Black	9842f1ca9d	X86: Implement CLTS.	2009-02-25 10:21:02 -08:00
Gabe Black	b035c917a5	X86: Make the segment register reading microops use merge.	2009-02-25 10:20:47 -08:00
Gabe Black	28efb3c6e3	X86: Implement the mov to debug register intructions.	2009-02-25 10:20:42 -08:00
Gabe Black	c39ed53d05	X86: Rename oszForPseudoDesc maxOsz to reflect its more general use.	2009-02-25 10:20:30 -08:00
Gabe Black	3ca2451d81	X86: Add code to interpret debug register values.	2009-02-25 10:20:25 -08:00
Gabe Black	1e70401c08	X86: Fix a few bugs with the segment register instructions in real mode. Fix a few instances where the register form of zext was used where zexti was intended. Also get rid of the 64 bit only rip relative addressed version since 64 bit and real mode are mutually exclusive.	2009-02-25 10:20:19 -08:00
Gabe Black	8813168b5a	X86: Do a merge for the zero extension microop.	2009-02-25 10:20:10 -08:00
Gabe Black	28a35a6adb	X86: Add microops for reading/writing debug registers.	2009-02-25 10:20:01 -08:00
Gabe Black	11fbed02ea	X86: Add classes that break out the bits of the DR6 and DR7 registers.	2009-02-25 10:19:54 -08:00
Gabe Black	cb4141f6e6	X86: Check src1 for illegal values since that's the index we actually use.	2009-02-25 10:19:47 -08:00
Gabe Black	d48214a656	X86: Implement the fence instructions. These are not microcoded.	2009-02-25 10:19:41 -08:00
Gabe Black	9940e21fa9	CPU: Add a flag to identify a read barrier to the static inst class.	2009-02-25 10:19:33 -08:00
Gabe Black	06ff83e1b9	X86: Implement a basic prefetch instruction.	2009-02-25 10:19:22 -08:00
Gabe Black	5f0428ef9f	X86: Use the right portion of a register for stores.	2009-02-25 10:19:14 -08:00
Gabe Black	c849ef58c0	X86: Actually check page protections.	2009-02-25 10:18:58 -08:00
Gabe Black	f35a37ca9e	X86: Update CS later so stack accesses have the right permission checks.	2009-02-25 10:18:51 -08:00
Gabe Black	da61c4b3ee	CPU: Don't fetch when executing a macroop. If the CPL changes mid macroop, the end of the instruction might not be priveleged enough to execute the beginning.	2009-02-25 10:18:36 -08:00
Gabe Black	ba69184630	X86: Use atCPL0 for accesses that are part of CPU machinery.	2009-02-25 10:18:29 -08:00
Gabe Black	dc53ca89f6	X86: Add a flag to force memory accesses to happen at CPL 0.	2009-02-25 10:18:22 -08:00
Gabe Black	897c374892	X86: Move where CS is set so CPL checks work out.	2009-02-25 10:18:16 -08:00
Gabe Black	710b43dfbd	X86: Implement inUserMode for x86.	2009-02-25 10:18:06 -08:00
Gabe Black	1cedc748d4	X86: Add a trace flag for tracing faults.	2009-02-25 10:17:59 -08:00
Gabe Black	eec3f49a57	X86: Implement the sysret instruction in long mode.	2009-02-25 10:17:54 -08:00
Gabe Black	6325245e3e	X86: Implement the longmode versions of the syscall instruction.	2009-02-25 10:17:49 -08:00
Gabe Black	dadc30b0a4	X86: Make the microcode assembler recognize r8-r15.	2009-02-25 10:17:43 -08:00
Gabe Black	fcad6e3b13	X86: Add a wrattr microop.	2009-02-25 10:17:38 -08:00
Gabe Black	e4ede69b2f	X86: Add a trace flag for the page table walker.	2009-02-25 10:17:27 -08:00
Gabe Black	99aa121fca	X86: Make exceptions handle stack switching.	2009-02-25 10:17:19 -08:00
Gabe Black	aa7bc1be74	X86: Implement the LTR instruction.	2009-02-25 10:17:14 -08:00
Gabe Black	08f3a126d5	X86: Fix segment limit checking.	2009-02-25 10:17:08 -08:00
Gabe Black	2f31643db5	X86: Add a check to chks to verify a task state segment descriptor.	2009-02-25 10:17:02 -08:00
Gabe Black	7b1cb74ac3	X86: Add a check to chks which raises #GP(selector) if selector is NULL or not in the GDT.	2009-02-25 10:16:54 -08:00
Gabe Black	82288e7c3e	X86: Add makeAtomicResponse to the read/write functions of x86 devices.	2009-02-25 10:16:43 -08:00
Gabe Black	7462cb0842	X86: Fix the timing mode of the page table walker.	2009-02-25 10:16:34 -08:00
Gabe Black	40fdba2454	X86: Make the X86 TLB take advantage of delayed translations, and get rid of the fake TLB miss faults.	2009-02-25 10:16:21 -08:00
Gabe Black	6ed47e9464	CPU: Implement translateTiming which defers to translateAtomic, and convert the timing simple CPU to use it.	2009-02-25 10:16:15 -08:00
Gabe Black	15940d06b5	SPARC: Adjust a few instructions to not write registers in initiateAcc.	2009-02-25 10:16:04 -08:00
Gabe Black	1b336a8fe7	X86: Make the stupd microop not update registers in initiateAcc.	2009-02-25 10:15:56 -08:00
Gabe Black	5605079b1f	ISA: Replace the translate functions in the TLBs with translateAtomic.	2009-02-25 10:15:44 -08:00
Gabe Black	a1aba01a02	CPU: Get rid of translate... functions from various interface classes.	2009-02-25 10:15:34 -08:00
Nathan Binkert	f3090e5b70	stats: reorganize how parameters are stored and accessed.	2009-02-23 12:22:19 -08:00
Nathan Binkert	aaf98aaa32	stats: move the limits stuff into the types.hh file	2009-02-23 12:22:18 -08:00
Nathan Binkert	80d5f34da6	stats: get rid of the convoluted 'database' code. Just use the stuff directly and things ought to be more clear	2009-02-23 12:22:17 -08:00
Nathan Binkert	fb74987c52	stats: Try to make the names of things more intuitive. Basically, this means renaming several things called data to info, which is information about the statistics. Things that are named data now are actual data stored for the statistic.	2009-02-23 12:22:15 -08:00
Nathan Binkert	bcb7e70178	stats: clean up the statistics unittest	2009-02-23 12:04:52 -08:00
Nathan Binkert	d940a2b741	stats: fix text printout for distributions	2009-02-23 12:04:50 -08:00
Nathan Binkert	f69ea20fc6	stats: cleanup static stats to make startup work. This is mainly to allow the unit test to run without requiring the standard M5 stats from being initialized (e.g. sim_seconds, sim_ticks, host_seconds)	2009-02-23 12:03:06 -08:00
Nathan Binkert	3fa9812e1d	debug: Move debug_break into src/base	2009-02-23 11:48:40 -08:00
Gabe Black	e8c1c3e72e	X86: Pass whether an access was a read/write/fetch so faults can behave accordingly.	2009-02-23 00:20:34 -08:00
Korey Sewell	6c5afe6346	Remove unnecessary building of FreeList/RenameMap in InOrder. Clean-up comments and O3 extensions InOrder Thread Context	2009-02-20 11:02:48 -05:00
Nathan Binkert	c41c9cf3a6	events: Make trace events happen at the right priority. Also, while we're at it, remember that priorities are in the Event class and add a disable method to disable tracing.	2009-02-18 10:00:15 -08:00
Steve Reinhardt	6cfff91d43	Make etherdump timestamps zero-based. We previously used the actual wall time for the base timestamps, making etherdumps non-deterministic. This fixes that problem and gets rid of the "malformed packet" at the front that we needed to provide the right base timestamp to wireshark/tcpdump.	2009-02-17 19:24:46 -08:00
Lisa Hsu	5d029ff11e	sycalls: implement mremap() and add DATA flag for getrlimit(). mremap has been tested on Alpha, compiles for the rest but not tested. I don't see why it wouldn't work though.	2009-02-16 17:47:39 -05:00
Steve Reinhardt	89a7fb0393	Fixes to get prefetching working again. Apparently we broke it with the cache rewrite and never noticed. Thanks to Bao Yungang <baoyungang@gmail.com> for a significant part of these changes (and for inspiring me to work on the rest). Some other overdue cleanup on the prefetch code too.	2009-02-16 08:56:40 -08:00
Gabe Black	6923282fb5	X86: Make the loader recognize 32 bit x86 processes.	2009-02-15 23:43:39 -08:00
Nathan Binkert	e0f425bb94	traceflags: fix --trace-help	2009-02-15 20:39:12 -08:00
Nathan Binkert	f255957b90	style	2009-02-10 22:19:27 -08:00
Korey Sewell	cf4a00ca41	Configs: Add support for the InOrder CPU model	2009-02-10 15:49:29 -08:00
Korey Sewell	973d8b8b13	InOrder: Import new inorder CPU model from MIPS. This model currently only works in MIPS_SE mode, so it will take some effort to clean it up and make it generally useful. Hopefully people are willing to help make that happen!	2009-02-10 15:49:29 -08:00
Korey Sewell	36d9065f5f	syscall: Expose ioctl for MIPS	2009-02-10 15:49:29 -08:00
Korey Sewell	34a5cd8870	ExeTrace: Allow subclasses of the tracer to define their own prefix to dump	2009-02-10 15:49:29 -08:00
Korey Sewell	2d0a66cbc1	CPU: Prepare CPU models for the new in-order CPU model. Some new functions and forward declarations are necessary to make things work	2009-02-10 15:49:29 -08:00
Nathan Binkert	20c5ec6e1c	copyright: This file need not have had the more restrictive copyright.	2009-02-09 20:10:15 -08:00
Nathan Binkert	dd6ea8797f	scons: Require SCons version 0.98.1 This allows me to clean things up so we are up to date with respect to deprecated features. There are many features scheduled for permanent failure in scons 2.0 and 0.98.1 provides the most compatability for that. It also paves the way for some nice new features that I will add soon	2009-02-09 20:10:14 -08:00
Nathan Binkert	9e268ae63f	scons: Don't build the intermediate static library unless explicitly requested. This means that similar to libm5_fast.so, you need to explicitly build build/ALPHA_SE/libm5_fast.a if you want it.	2009-02-09 20:10:12 -08:00
Nathan Binkert	e1798d063e	Quell g++ 4.3 warning about operator ambiguity	2009-02-06 20:55:50 -08:00
Nathan Binkert	64eb0dc9cd	some new files are missing copyright notices	2009-02-04 16:26:15 -08:00
Gabe Black	73f579a804	X86: Add some missing default arguments.	2009-02-01 22:40:51 -08:00
Gabe Black	5a4eed5d34	X86: All x86 fault classes now attempt to do something useful.	2009-02-01 17:09:08 -08:00
Gabe Black	923a14dde7	X86: Make the fault classes handle error codes better.	2009-02-01 17:08:32 -08:00
Gabe Black	2f8cec849d	X86: Make the long mode interrupt/exception microcode handle an error code.	2009-02-01 17:07:43 -08:00
Gabe Black	9b4d1e0f9a	X86: Distinguish between hardware and software interrupts/exceptions	2009-02-01 17:07:18 -08:00
Gabe Black	041402a949	X86: Fix the upper bound on some ranges that were setting up the micro code assembler.	2009-02-01 17:06:25 -08:00
Gabe Black	6b53b8387e	X86: Make the chks microop check for the right int descriptor type.	2009-02-01 17:05:37 -08:00
Gabe Black	c0cd58812e	X86: Touch up the interrupt entering microcode.	2009-02-01 17:04:21 -08:00
Gabe Black	03a00735c2	X86: Keep track of the vector for all exceptions/faults.	2009-02-01 17:03:11 -08:00
Gabe Black	7b58511470	CPU: Don't always reset the micro pc on faults. Let the faults handle it.	2009-02-01 00:30:54 -08:00
Gabe Black	6b60a29706	X86: Fix the time keeping of the Local APIC timer.	2009-02-01 00:30:11 -08:00
Gabe Black	ca6e0d75c8	X86: Fix the microcode for the LODS instruction.	2009-02-01 00:28:28 -08:00
Gabe Black	57be1dfe48	X86: Implement pciToDma.	2009-02-01 00:27:15 -08:00
Gabe Black	70cd5bfce5	X86: Configure the first PCI interrupt.	2009-02-01 00:26:10 -08:00
Gabe Black	f1b43b39a7	X86: Hook up the IDE controller interrupt line.	2009-02-01 00:25:15 -08:00
Gabe Black	d432bd13b2	X86: Fix some incorrect register widths.	2009-02-01 00:18:13 -08:00
Gabe Black	f3b8371dfc	X86: Add extended Intel MP entries correctly.	2009-02-01 00:15:38 -08:00
Gabe Black	06cdbe5ea7	X86: Compute PCI config addresses correctly.	2009-02-01 00:11:49 -08:00
Gabe Black	483c3e96b7	X86: Calculate flags based on the actual result.	2009-02-01 00:08:16 -08:00
Gabe Black	7720968949	X86: Make sure the predecoder is cleared out for interrupts.	2009-02-01 00:04:34 -08:00
Gabe Black	3ecc38cb8b	Devices: Add support for legacy fixed IO locations in BARs.	2009-02-01 00:02:21 -08:00
Gabe Black	bb7ad80bbe	X86: Plug in an IDE controller.	2009-02-01 00:00:03 -08:00
Gabe Black	c2c5740b98	X86: Refactor and clean up the keyboard controller.	2009-01-31 23:59:25 -08:00
Gabe Black	7cf276bed3	X86: Add a keyboard controller device.	2009-01-31 23:59:01 -08:00
Gabe Black	0287f19ede	X86: Set up the console interrupt and add some DPRINTFs.	2009-01-31 23:56:46 -08:00
Gabe Black	e1c412cec6	X86: Configure the IO APIC more.	2009-01-31 23:44:05 -08:00
Gabe Black	6a3f255a84	X86: Rework interrupt pins to allow one to many connections.	2009-01-31 23:33:54 -08:00
Gabe Black	64b663c607	X86: Initialize the value behind port 61 so unused bits are consistent.	2009-01-31 23:26:43 -08:00
Gabe Black	953e4bba59	X86: Set/correct some default values for x86 parameters.	2009-02-01 16:59:34 -08:00
Ali Saidi	be5d350afc	SCons: Fix how we get Mercurial revision information since internals keep changing.	2009-01-30 20:04:57 -05:00
Ali Saidi	e7293dd24e	Errors: Use the correct panic/warn/fatal/info message in some places.	2009-01-30 20:04:17 -05:00
Ali Saidi	f4291aac25	Errors: Print a URL with a hash of the format string to find more information about an error.	2009-01-30 20:04:15 -05:00
Ali Saidi	35a85a4e86	Config: Cause a fatal() when a parameter without a default value isn't set(FS #315 ).	2009-01-30 19:08:13 -05:00
Nathan Binkert	0b228fc1ab	Fix typo	2009-01-29 22:27:11 -08:00
Gabe Black	56e182a6a9	X86: Add a dummy minimal DMA controller that doesn't do anything.	2009-01-25 20:35:00 -08:00
Gabe Black	151bc018dd	X86: Add a device to back the non-existant floppy drive controller.	2009-01-25 20:34:17 -08:00
Gabe Black	dbe28da1be	X86: Add fake devices for non-existant serial ports.	2009-01-25 20:33:52 -08:00
Gabe Black	52defeb4e7	X86: Implement the xadd instruction.	2009-01-25 20:33:27 -08:00
Gabe Black	3c5988b86c	X86: Implement the bswap instruction.	2009-01-25 20:32:43 -08:00
Gabe Black	919c3e7fb6	Dev: Make the RTC device ignore writes to a read only bit.	2009-01-25 20:32:26 -08:00
Gabe Black	0449fb2b7a	X86: Fix a bug in the iret microcode.	2009-01-25 20:31:17 -08:00
Gabe Black	389fbfdab1	X86: Make the interrupt object wake up the CPU when something becomes pending.	2009-01-25 20:30:51 -08:00
Gabe Black	d9794784ba	CPU: Add a setCPU function to the interrupt objects.	2009-01-25 20:29:03 -08:00
Gabe Black	3f9e2350a1	Devices: Make the destructor virtual on the CopyEnginChannel object. This fixes a compile warning which becomes an error.	2009-01-25 20:26:53 -08:00
Nathan Binkert	64ed39f61b	pseudo inst: Add new wake cpu instruction for sending a message to wake a cpu. It's instantaneous and so it's somewhat bogus, but it's a first step.	2009-01-24 07:27:22 -08:00
Nathan Binkert	f0fb3ac060	cpu: provide a wakeup mechanism that can be used to pull CPUs out of sleep. Make interrupts use the new wakeup method, and pull all of the interrupt stuff into the cpu base class so that only the wakeup code needs to be updated. I tried to make wakeup, wakeCPU, and the various other mechanisms for waking and sleeping a little more sane, but I couldn't understand why the statistics were changing the way they were. Maybe we'll try again some day.	2009-01-24 07:27:21 -08:00
Ali Saidi	56d5212ba7	Trace: Add DPRINTFS macro that takes parameter to call name() for trace printing.	2009-01-23 17:19:48 -05:00
Ali Saidi	37ffe52ca4	IGbE: Fix two e1000 driver bugs that I missed before.	2009-01-23 17:19:47 -05:00
Nathan Binkert	10fc45da27	o3cpu: give a name to the activity recorder for better tracing	2009-01-21 14:56:18 -08:00
Nathan Binkert	dbac448b08	thread_context: move getSystemPtr so SE mode can get to it. There was really no reason that it should be FS only.	2009-01-19 20:36:49 -08:00
Nathan Binkert	81b8c0c79a	python: add fatal() function to the m5 package and use it	2009-01-19 14:43:09 -08:00
Nathan Binkert	da14789c32	python: Try to isolate the stuff that's in the m5.internal package a bit more.	2009-01-19 09:59:15 -08:00
Nathan Binkert	c9d3113015	tracing: Add help strings for some of the trace flags	2009-01-19 09:59:14 -08:00
Nathan Binkert	0876c822dd	tracing: panic() if people try to use tracing, but TRACING_ON is not set. Also clean things up so that help strings can more easily be added. Move the help function into trace.py	2009-01-19 09:59:13 -08:00
Nathan Binkert	f15f252d4e	python: Rework how things are imported	2009-01-19 09:59:13 -08:00
Nathan Binkert	51d780fa4d	scons: Don't add all objects to the library twice	2009-01-19 09:03:41 -08:00
Ali Saidi	b4227bd7f6	Fix issue 326: glibc non-deterministic because it reads /proc	2009-01-17 18:56:46 -05:00
Ali Saidi	140b4b891e	CopyEngine: Implement a I/OAT-like copy engine.	2009-01-17 18:55:09 -05:00
Nathan Binkert	8153790d00	SCons: centralize the Dir() workaround for newer versions of scons. Scons bug id: 2006 M5 Bug id: 308	2009-01-13 14:17:50 -08:00
Richard Strong	81180a3bf0	This fix addresses an ill formed if statement that fails to compile. The fix was the simple addition of another set of parenthesis to ensure the correct condition resolution.	2009-01-11 22:45:03 -08:00
Steve Reinhardt	c370a9cb98	FastAlloc: track allocation tick in debug mode, minor enhancements to debug output	2009-01-08 14:13:33 -08:00
Gabe Black	b23633ad1b	X86: Hook in the M5 pseudo insts.	2009-01-06 23:55:46 -08:00
Gabe Black	115b1a7ed3	X86: Autogenerate macroop generateDisassemble function.	2009-01-06 22:55:27 -08:00
Gabe Black	8cab1805f9	X86: Move the function that prints memory args into the inst base class.	2009-01-06 22:46:28 -08:00
Gabe Black	9e24d8c599	X86: Move the macroop class out of the isa description into C++.	2009-01-06 22:44:59 -08:00
Gabe Black	7b7a72158a	X86: Change indentation on microop disassembly.	2009-01-06 22:40:41 -08:00
Gabe Black	b0ab5c894d	Tracing: Make tracing aware of macro and micro ops.	2009-01-06 22:34:18 -08:00
Ali Saidi	2adc60795b	IGbE: Implement header splitting with large MTU	2009-01-06 10:36:57 -05:00
Ali Saidi	11ac0c7acf	INET: Add functions to header types to get offset in packet and start of payload; add function to split packet at last known header	2009-01-06 10:36:56 -05:00
Ali Saidi	9f89d43b65	IGbE: Remove is8257 variable	2009-01-06 10:36:55 -05:00
Steve Reinhardt	1704ba2273	Make Alpha pseudo-insts available from SE mode.	2008-12-17 09:51:18 -08:00
Gabe Black	02cd18f536	SPARC: Truncate syscall args and return values appropriately.	2008-12-16 23:06:37 -08:00
Gabe Black	f0d1a20971	PCI: Add some missing breaks to a couple case statements.	2008-12-15 00:47:01 -08:00
Author Name	13f7fdcf67	The ide_ctrl serialize and unserialize were broken. Multiple channels were saving their state under the same name. This patch separates the saved state of the primary and secondary channel.	2008-12-14 23:29:49 -08:00
Richard Strong	dae531c049	IDE: Fix serialization for the IDE controller.	2008-12-09 10:34:08 -08:00
Nathan Binkert	d0c0c25ebc	eventq: Add some debugging code to the eventq.	2008-12-08 07:17:48 -08:00
Nathan Binkert	19273164da	output: Change default output directory and files and update tests. --HG-- rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr => tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout => tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr => tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout => tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr => tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout => tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr => tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout => tests/long/00.gzip/ref/sparc/linux/o3-timing/simout rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt => tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr => tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout => tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt => tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr => tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout => tests/long/00.gzip/ref/sparc/linux/simple-timing/simout rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt => tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr => tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout => tests/long/00.gzip/ref/x86/linux/simple-atomic/simout rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/x86/linux/simple-timing/stderr => tests/long/00.gzip/ref/x86/linux/simple-timing/simerr rename : tests/long/00.gzip/ref/x86/linux/simple-timing/stdout => tests/long/00.gzip/ref/x86/linux/simple-timing/simout rename : tests/long/00.gzip/ref/x86/linux/simple-timing/m5stats.txt => tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stderr => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stdout => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/m5stats.txt => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stderr => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stdout => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/m5stats.txt => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr => tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout => tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt => tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr => tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout => tests/long/10.mcf/ref/sparc/linux/simple-timing/simout rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt => tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/stderr => tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout => tests/long/10.mcf/ref/x86/linux/simple-atomic/simout rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/10.mcf/ref/x86/linux/simple-timing/stderr => tests/long/10.mcf/ref/x86/linux/simple-timing/simerr rename : tests/long/10.mcf/ref/x86/linux/simple-timing/stdout => tests/long/10.mcf/ref/x86/linux/simple-timing/simout rename : tests/long/10.mcf/ref/x86/linux/simple-timing/m5stats.txt => tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt rename : tests/long/20.parser/ref/x86/linux/simple-atomic/stderr => tests/long/20.parser/ref/x86/linux/simple-atomic/simerr rename : tests/long/20.parser/ref/x86/linux/simple-atomic/stdout => tests/long/20.parser/ref/x86/linux/simple-atomic/simout rename : tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/20.parser/ref/x86/linux/simple-timing/stderr => tests/long/20.parser/ref/x86/linux/simple-timing/simerr rename : tests/long/20.parser/ref/x86/linux/simple-timing/stdout => tests/long/20.parser/ref/x86/linux/simple-timing/simout rename : tests/long/20.parser/ref/x86/linux/simple-timing/m5stats.txt => tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt rename : tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr => tests/long/30.eon/ref/alpha/tru64/o3-timing/simerr rename : tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout => tests/long/30.eon/ref/alpha/tru64/o3-timing/simout rename : tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr => tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout => tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr => tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout => tests/long/30.eon/ref/alpha/tru64/simple-timing/simout rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stderr => tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simerr rename : tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stdout => tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout rename : tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr => tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout => tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr => tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout => tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr => tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout => tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr => tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout => tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr => tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout => tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr => tests/long/50.vortex/ref/sparc/linux/simple-atomic/simerr rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout => tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt => tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr => tests/long/50.vortex/ref/sparc/linux/simple-timing/simerr rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout => tests/long/50.vortex/ref/sparc/linux/simple-timing/simout rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt => tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr => tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simerr rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout => tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr => tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout => tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout rename : tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr => tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr rename : tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout => tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout rename : tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/stderr => tests/long/60.bzip2/ref/x86/linux/simple-atomic/simerr rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout => tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/60.bzip2/ref/x86/linux/simple-timing/stderr => tests/long/60.bzip2/ref/x86/linux/simple-timing/simerr rename : tests/long/60.bzip2/ref/x86/linux/simple-timing/stdout => tests/long/60.bzip2/ref/x86/linux/simple-timing/simout rename : tests/long/60.bzip2/ref/x86/linux/simple-timing/m5stats.txt => tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr => tests/long/70.twolf/ref/alpha/tru64/o3-timing/simerr rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout => tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr => tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout => tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr => tests/long/70.twolf/ref/sparc/linux/simple-atomic/simerr rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout => tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt => tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr => tests/long/70.twolf/ref/sparc/linux/simple-timing/simerr rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout => tests/long/70.twolf/ref/sparc/linux/simple-timing/simout rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt => tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/stderr => tests/long/70.twolf/ref/x86/linux/simple-atomic/simerr rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout => tests/long/70.twolf/ref/x86/linux/simple-atomic/simout rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/70.twolf/ref/x86/linux/simple-timing/stderr => tests/long/70.twolf/ref/x86/linux/simple-timing/simerr rename : tests/long/70.twolf/ref/x86/linux/simple-timing/stdout => tests/long/70.twolf/ref/x86/linux/simple-timing/simout rename : tests/long/70.twolf/ref/x86/linux/simple-timing/m5stats.txt => tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stderr => tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout => tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/m5stats.txt => tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr => tests/quick/00.hello/ref/alpha/linux/o3-timing/simerr rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout => tests/quick/00.hello/ref/alpha/linux/o3-timing/simout rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt => tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr => tests/quick/00.hello/ref/alpha/linux/simple-atomic/simerr rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout => tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt => tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr => tests/quick/00.hello/ref/alpha/linux/simple-timing/simerr rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout => tests/quick/00.hello/ref/alpha/linux/simple-timing/simout rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt => tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr => tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout => tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt => tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr => tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout => tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr => tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout => tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt => tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/stderr => tests/quick/00.hello/ref/mips/linux/simple-atomic/simerr rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout => tests/quick/00.hello/ref/mips/linux/simple-atomic/simout rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt => tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/mips/linux/simple-timing/stderr => tests/quick/00.hello/ref/mips/linux/simple-timing/simerr rename : tests/quick/00.hello/ref/mips/linux/simple-timing/stdout => tests/quick/00.hello/ref/mips/linux/simple-timing/simout rename : tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt => tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/stderr => tests/quick/00.hello/ref/sparc/linux/simple-atomic/simerr rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout => tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt => tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr => tests/quick/00.hello/ref/sparc/linux/simple-timing/simerr rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout => tests/quick/00.hello/ref/sparc/linux/simple-timing/simout rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt => tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/stderr => tests/quick/00.hello/ref/x86/linux/simple-atomic/simerr rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout => tests/quick/00.hello/ref/x86/linux/simple-atomic/simout rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt => tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/x86/linux/simple-timing/stderr => tests/quick/00.hello/ref/x86/linux/simple-timing/simerr rename : tests/quick/00.hello/ref/x86/linux/simple-timing/stdout => tests/quick/00.hello/ref/x86/linux/simple-timing/simout rename : tests/quick/00.hello/ref/x86/linux/simple-timing/m5stats.txt => tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr => tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout => tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt => tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr => tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout => tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt => tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr => tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout => tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt => tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr => tests/quick/02.insttest/ref/sparc/linux/simple-timing/simerr rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout => tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt => tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/stderr => tests/quick/20.eio-short/ref/alpha/eio/detailed/simerr rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/stdout => tests/quick/20.eio-short/ref/alpha/eio/detailed/simout rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/m5stats.txt => tests/quick/20.eio-short/ref/alpha/eio/detailed/stats.txt rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stderr => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stderr => tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stdout => tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/m5stats.txt => tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stderr => tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stdout => tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/m5stats.txt => tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt rename : tests/quick/50.memtest/ref/alpha/linux/memtest/stderr => tests/quick/50.memtest/ref/alpha/linux/memtest/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest/stdout => tests/quick/50.memtest/ref/alpha/linux/memtest/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt => tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt	2008-12-08 07:16:40 -08:00
Gabe Black	9192b7f1ef	Devices: Clean up the IDE controller.	2008-12-07 12:59:48 -08:00
Lisa Hsu	993b7be4bb	imported patch aux-fix.patch	2008-12-07 15:07:42 -05:00
Gabe Black	e4790bcbe2	X86: Add add_entry back in.	2008-12-06 14:48:59 -08:00
Nathan Binkert	489e3e7381	eventq: use the flags data structure	2008-12-06 14:18:18 -08:00
Nathan Binkert	cbbc4501c8	eventq: move virtual function definitiions to the .cc file.	2008-12-06 14:18:18 -08:00
Nathan Binkert	a0d322be40	traceflags: Make "All" a valid trace flag.	2008-12-06 14:18:18 -08:00
Nathan Binkert	e08c6be9fe	SimObject: change naming of vectors so there are the same numbers of digits. i.e. we used to have Foo0, Foo1, ..., Foo10, Foo11, ..., Foo100 now we have Foo000, Foo001, ..., Foo010, Foo011, ..., Foo100	2008-12-06 14:18:18 -08:00
Nathan Binkert	e141cb7441	flags: Change naming of functions to be clearer	2008-12-06 14:18:18 -08:00
Ali Saidi	dd788a23c9	IGbE: Add support for newer 8257x based Intel NICs	2008-12-05 13:58:22 -05:00
Ali Saidi	400e516261	IGbE: Add support for TCP segment offload	2008-12-05 13:58:21 -05:00
Ali Saidi	aab595a306	INet: Allow updating on id, len, seq, and flag field for TCP segment offload	2008-12-05 13:58:21 -05:00
Lisa Hsu	854aa60fdc	Automated merge with ssh://m5sim.org//repo/m5	2008-12-05 12:11:46 -05:00
Lisa Hsu	f1430941cf	This brings M5 closer to modernity - the kernel being advertised is newer so it won't die on binaries compiled with newer glibc's, and enables use of TLS-toolchain built binaries for ALPHA_SE by putting auxiliary vectors on the stack. There are some comments in the code to help. Finally, stats changes for ALPHA are from slight perturbations to the initial stack frame, all minimal diffs.	2008-12-05 12:09:29 -05:00
Lisa Hsu	e2c7618e50	This patch pulls out the auxiliary vector struct from individual ISA LiveProcesses to the base LiveProcess definition so anyone can use them.	2008-12-04 18:03:35 -05:00
Nathan Binkert	74f10be526	cprintf: support a configurable width and precision ("*" in printf)	2008-12-03 04:57:54 -08:00
Steve Reinhardt	041ca19edc	Assume files w/o obvious OS are Linux (with warning) instead of giving a fatal error.	2008-11-20 19:08:46 -08:00
Steve Reinhardt	ce4c9a7c10	Sort trace flags before printing them.	2008-11-17 12:41:50 -08:00
Clint Smullen	3087be945d	Output: Include gzstream package to allow automatically-gzipped output The gzstream package provides an ostream-interface for writing gzipped files. The package comes from: http://www.cs.unc.edu/Research/compgeom/gzstream/ And is distributed under the LGPL license. Both the license and version information has been preservered, though all other files in the package have been purged. Minor modifications to the code have been made. The output module detects when a filename ends in .gz and constructs an ogzstream object instead of an ofstream object. This works for both the create(...) and find(...) commands. Additionally, since gzstream objects needs to be closed to ensure proper file termination, I have the output deconstructor deleting all ostream's that it manages on behalf of find(...). At the moment, the only output file that I know this functionality works for is stats, i.e. by specifying "--stats-file=m5stats.txt.gz" on the command line.	2008-11-15 23:42:11 -05:00
Steve Reinhardt	4514f565e3	syscalls: fix latent brk/obreak bug. Bogus calls to ChunkGenerator with negative size were triggering a new assertion that was added there. Also did a little renaming and cleanup in the process.	2008-11-15 09:30:10 -08:00
Steve Reinhardt	640b415688	Cache: get rid of obsolete Tag methods. I think readData() and writeData() were used for Erik's compression work, but that code is gone, these aren't called anymore, and they don't even really do what their names imply.	2008-11-14 14:14:35 -08:00
Nathan Binkert	5711282f87	Fix a bunch of bugs I introduced when I changed the flags stuff for packets. I did some of the flags and assertions wrong. Thanks to Brad Beckmann for pointing this out. I should have run the opt regressions instead of the fast. I also screwed up some of the logical functions in the Flags class.	2008-11-14 04:55:30 -08:00
Gabe Black	7a4d75bae3	CPU: Refactor read/write in the simple timing CPU.	2008-11-13 23:30:37 -08:00
Nathan Binkert	4d64d7664c	SCons: Allow top level directory of EXTRAS able to contain SConscripts. The current EXTRAS will fail if the top level directory pointed to by EXTRAS has a SConscript file in it. We allow this by including the directory name of the EXTRA in the build directory which prevents a clash between src/SConscript and extra/SConscript. Maintain compatibility with older uses of EXTRAS by adding a -I for each top level extra directory.	2008-11-10 11:51:18 -08:00
Nathan Binkert	eb5d9ba72b	pseudo inst: Add rpns (read processor nanoseconds) instruction. This instruction basically returns the number of nanoseconds that the CPU has been running.	2008-11-10 11:51:18 -08:00
Nathan Binkert	c25d966b06	Clean up the SimpleTimingPort class a little bit. Move the constructor into the .cc file and get rid of the typedef for SendEvent.	2008-11-10 11:51:18 -08:00
Nathan Binkert	ea70a44c9f	clean: Move some stuff from the hh file to the cc file.	2008-11-10 11:51:18 -08:00
Nathan Binkert	4e02e7c217	python: Fix the reference counting for python events placed on the eventq. We need to add a reference when an object is put on the C++ queue, and remove a reference when the object is removed from the queue. This was not happening before and caused a memory problem.	2008-11-10 11:51:18 -08:00
Clint Smullen	1adfe5c7f3	O3CPU: Make the instcount debugging stuff per-cpu. This is to prevent the assertion from firing if you have a large multicore. Also make sure that it's not compiled in when NDEBUG is defined	2008-11-10 11:51:18 -08:00
Nathan Binkert	9c49bc7b00	mem: update stuff for changes to Packet and Request	2008-11-10 11:51:17 -08:00
Nathan Binkert	3535d746ab	style: clean up the Packet stuff	2008-11-10 11:51:17 -08:00
Nathan Binkert	2dd699ed3d	flags: Provide an object for managing boolean flags for an object. In many cases it might be preferable to use bitset, but this object allows the user more easily manipulate groups of flags because the underlying type (e.g. uint64_t) is exposed.	2008-11-10 11:51:17 -08:00
Nathan Binkert	194f0310d3	safe_cast: add a new cast function for casts that should always succeed. In DEBUG mode, this does a dynamic_cast and asserts that the result is non null. Otherwise, it just does a static_cast. Again, this is only intended for cases where the cast should always succeed and what's desired is a debugging check to make sure.	2008-11-10 11:51:17 -08:00
Steve Reinhardt	27e8f3c98a	DmaDevice: fix minor type in error message.	2008-11-10 14:45:31 -08:00
Steve Reinhardt	63127cbf37	mem: Assert that requests have non-negative size. Would have saved me much debugging time if these had been in there previously.	2008-11-10 14:11:07 -08:00
Steve Reinhardt	42bd460d7f	Cache: Refactor packet forwarding a bit. Makes adding write-through operations easier.	2008-11-10 14:10:28 -08:00
Gabe Black	846cb450f9	CPU: Make unaligned accesses work in the timing simple CPU.	2008-11-09 21:56:28 -08:00
Gabe Black	8c15518f30	X86: Fix completeAcc get call.	2008-11-09 21:55:43 -08:00
Gabe Black	909380f3ee	X86: Make the timing simple CPU handle variable length instructions.	2008-11-09 21:55:01 -08:00
Nathan Binkert	44839d6b71	Fix a few more places where the context stuff wasn't changed	2008-11-05 07:20:03 -08:00
Lisa Hsu	46b56bb7b6	Fix SPARC_FS compile	2008-11-05 16:19:17 -05:00
Lisa Hsu	07969dbbf1	Right now a single thread cpu 1 could get assigned context Id != 1, depending on the order in which it's registered with the system. To make them match, here is a little change.	2008-11-05 15:30:49 -05:00
Lisa Hsu	c68032ddcb	decouple eviction from insertion in the cache.	2008-11-04 11:35:58 -05:00
Lisa Hsu	4ab52cb986	Change the findBlock(addr, lat) to accessBlock, which I think has better connotations for what is really happening and how it should be used.	2008-11-04 11:35:57 -05:00
Lisa Hsu	dd99ff23c6	get rid of all instances of readTid() and getThreadNum(). Unify and eliminate redundancies with threadId() as their replacement.	2008-11-04 11:35:42 -05:00
Lisa Hsu	d857faf073	Add in Context IDs to the simulator. From now on, cpuId is almost never used, the primary identifier for a hardware context should be contextId(). The concept of threads within a CPU remains, in the form of threadId() because sometimes you need to know which context within a cpu to manipulate.	2008-11-02 21:57:07 -05:00
Lisa Hsu	67fda02dda	Make it so that all thread contexts are registered with the System, even in SE. Process still keeps track of the tc's it owns, but registration occurs with the System, this eases the way for system-wide context Ids based on registration.	2008-11-02 21:57:06 -05:00
Lisa Hsu	c55a467a06	make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered across the subclasses. generally make it so that member data is _cpuId and accessor functions are cpuId(). The ID val comes from the python (default -1 if none provided), and if it is -1, the index of cpuList will be given. this has passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard switch.	2008-11-02 21:56:57 -05:00
Clint Smullen	95af120e60	CPU: The API change to EventWrapper did not get propagated to the entirety of TimingSimpleCPU. The constructor no-longer schedules an event at construction and the implict conversion between int and bool was allowing the old code to compile without warning. Signed-off By: Ali Saidi	2008-10-27 18:18:04 -04:00
Clint Smullen	cfa32d8de7	Checkpointing: createCountedDrain function, it was only returning an Event, which does not expose a setCount method to Python. Signed-off By: Ali Saidi	2008-10-27 19:46:01 -04:00
Lisa Hsu	8788d703f8	s/cpu_id/cpuId in o3 (to be consistent and match style), also fix some typos in comments.	2008-10-23 16:49:17 -04:00
Lisa Hsu	546a6c0c1b	probe function no longer used anywhere.	2008-10-23 16:49:13 -04:00
Lisa Hsu	7a28ab2d18	remove the totally obsolete split cache	2008-10-23 16:11:28 -04:00
Nathan Binkert	9836d81c2b	style: Use the correct m5 style for things relating to interrupts.	2008-10-21 07:12:53 -07:00
Ali Saidi	b760b99f4d	O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. Removing hwrei causes the instruction after the hwrei to be fetched before the ITB/DTB_CM register is updated in a call pal call sys and thus the translation fails because the user is attempting to access a super page address. Minimally, it seems as though some sort of fetch stall or refetch after a hwrei is required. I think this works currently because the hwrei uses the exec context interface, and the o3 stalls when that occurs. Additionally, these changes don't update the LOCK register and probably break ll/sc. Both o3 changes were removed since a great deal of manual patching would be required to only remove the hwrei change.	2008-10-20 16:22:59 -04:00
Lisa Hsu	4fac54f227	Automated merge with ssh://daystrom.m5sim.org//z/repo/m5	2008-10-19 22:50:53 -04:00
Nathan Binkert	9b8011e255	need to add packet_access.hh in order to get tempalte definition	2008-10-16 22:22:47 -07:00
Nathan Binkert	81f5da1e89	get rid of local variable that's only used in an assert so fast compiles	2008-10-16 22:22:17 -07:00
Lisa Hsu	101c2d9174	Automated merge with ssh://daystrom.m5sim.org//z/repo/m5	2008-10-16 14:16:26 -04:00
Lisa Hsu	90e40ca982	This function declaration isn't used anywhere. HG: user: Lisa Hsu <hsul@eecs.umich.edu> HG: branch default HG: changed src/mem/cache/cache.hh	2008-10-14 17:22:03 -04:00
Nathan Binkert	5b07448cf1	eventq: make python events actually work	2008-10-14 09:34:11 -07:00
Nathan Binkert	ff2eea1ba3	eventq: revert code for unserializing events. Since I never implemented a proper solution, put it back to something that at least works for now. Once I add more event queues, I'll have to really fix this though	2008-10-14 09:33:52 -07:00
Gabe Black	809f6cb6d1	CPU: Explain why some code is commented out.	2008-10-12 23:52:02 -07:00
Gabe Black	34ca72d16d	Get rid of some commented out code.	2008-10-12 23:50:22 -07:00
Gabe Black	3c4567f2a6	X86: Set the delayed commit flag in x86 microops appropriately.	2008-10-12 23:29:10 -07:00
Gabe Black	33ebd04474	X86: Make the local APIC timer event generate an interrupt.	2008-10-12 23:28:49 -07:00
Gabe Black	bdc28d793d	X86: Implement the EOI register in the local APIC.	2008-10-12 23:28:11 -07:00
Gabe Black	fd37688294	X86: Add some DPRINTFs to the local APIC.	2008-10-12 23:27:45 -07:00
Gabe Black	be6055e0f2	X86: Make auto eoi mode work in the I8259 PIC.	2008-10-12 23:27:08 -07:00
Gabe Black	fb5bb434a9	X86: Make non-specific EOI commands work.	2008-10-12 23:25:48 -07:00
Gabe Black	8e664f3959	X86: Make the I8259 PIC accept a specific EOI command.	2008-10-12 23:22:58 -07:00
Gabe Black	e3004c579f	X86: Fix the segment setting code in IRET, and make it restore the flags.	2008-10-12 23:05:22 -07:00
Gabe Black	349a155b6e	X86: Panic when an unimplemented fault is invoked, rather than spinning forever	2008-10-12 23:00:28 -07:00
Gabe Black	564eda827b	X86: Implement the swapgs instruction.	2008-10-12 23:00:07 -07:00
Gabe Black	a2e0d539d8	X86: Add wrval/rdval microops for reading significant miscregs.	2008-10-12 22:55:55 -07:00
Gabe Black	9e8e2f9ec6	X86: Make the x86 interrupt fault kick off the interrupt microcode.	2008-10-12 22:42:10 -07:00
Gabe Black	4c19c56a77	X86: Implement entering an interrupt in microcode.	2008-10-12 22:42:03 -07:00
Gabe Black	f813a4be49	X86: Make sure register microops set fault rather than returning one.	2008-10-12 22:24:06 -07:00
Gabe Black	961b40cdb5	X86: Implement an wrdh microop which loads bases/offsets from 16 byte descriptors.	2008-10-12 22:16:53 -07:00
Gabe Black	989fa4fc0f	X86: Make the MicroPC type 16 bit.	2008-10-12 20:48:24 -07:00
Gabe Black	6074b1abf2	X86: Implement local labels for the ROM that actually refer into the ROM.	2008-10-12 20:44:11 -07:00
Gabe Black	6b46e5204d	X86: Implement the chks check of interrupt gate target code segments.	2008-10-12 20:38:22 -07:00
Gabe Black	30feb90c1c	X86: Add a check type for interrupt gates.	2008-10-12 20:33:37 -07:00
Gabe Black	15f5bb3055	X86: Fix chks checking the submode for stack segments.	2008-10-12 20:29:52 -07:00
Gabe Black	9e1fe2050a	X86: Let segment manipulation microops be conditional.	2008-10-12 20:25:06 -07:00
Gabe Black	e9158d763a	X86: Let the microassembler know about the microcode only H segment.	2008-10-12 20:17:38 -07:00
Gabe Black	223fc41c07	X86: Fix the rdbase microop	2008-10-12 20:07:46 -07:00
Gabe Black	0756dbb37a	X86: Don't fetch in the simple CPU if you're in the ROM.	2008-10-12 19:32:06 -07:00
Gabe Black	f245358343	Get rid of old RegContext code.	2008-10-12 17:57:46 -07:00
Gabe Black	cefb768131	X86: Create a handy way to access labels from the ROM in microcode.	2008-10-12 17:52:51 -07:00
Gabe Black	e5f8092467	X86: Make X86's microcode ROM actually do something.	2008-10-12 17:48:44 -07:00
Gabe Black	c9ea0b7349	CPU: Make the highest order bit in the micro pc determine if it's combinational or from the ROM.	2008-10-12 16:59:55 -07:00
Gabe Black	2736086d7c	CPU: Create a microcode ROM object in the CPU which is defined by the ISA.	2008-10-12 15:59:21 -07:00
Gabe Black	6fd4eff68f	X86: Create an eret microop which returns from ROM to combinational decoding.	2008-10-12 15:53:04 -07:00
Gabe Black	4aa18aa800	X86: Make Br never report itself as the last microop.	2008-10-12 15:43:35 -07:00
Gabe Black	77c0e1d110	X86: Create a SeqOp class of microops and make Br one of them.	2008-10-12 15:33:17 -07:00
Gabe Black	a76c4b8ca1	X86: Implement CPUID with a magical function instead of microcode.	2008-10-12 15:31:28 -07:00
Gabe Black	d0a43ce2b2	X86: Fix the ordering of special physical address ranges.	2008-10-12 14:01:06 -07:00
Gabe Black	3a1905157e	X86: Create a mechanism for the IO APIC to access I8259 vectors.	2008-10-12 13:54:57 -07:00
Gabe Black	c35da8e495	X86: Actually use the extra vector bits we get from ICW2.	2008-10-12 13:51:48 -07:00
Gabe Black	ec9d3aad71	X86: Make the local APIC process interrupts and send them to the CPU.	2008-10-12 13:45:21 -07:00
Gabe Black	876f4845f2	X86: Make the local APIC handle interrupt messages from the IO APIC.	2008-10-12 13:44:24 -07:00
Gabe Black	4d5c7f7038	X86: Change the default value for the IO APIC redirection table.	2008-10-12 13:35:26 -07:00
Gabe Black	3420ad7644	X86: Make the bases for x86 fault class public.	2008-10-12 13:29:26 -07:00
Gabe Black	557bde43c3	X86: Make APICs communicate through the memory system.	2008-10-12 13:28:54 -07:00
Gabe Black	e459013182	Create a message port for sending messages as apposed to reading/writing a memory range.	2008-10-12 12:08:51 -07:00
Gabe Black	e0f137a87c	X86: Add a LocalApic trace flag.	2008-10-12 12:07:25 -07:00
Gabe Black	42ebebf99a	X86: Make the local APIC accessible through the memory system directly, and make the timer work.	2008-10-12 11:08:00 -07:00
Gabe Black	d9f9c967fb	Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object.	2008-10-12 09:09:56 -07:00
Gabe Black	c4f1cc3b48	CPU: Eliminate the get_vec function.	2008-10-12 08:24:09 -07:00
Gabe Black	0c3848732e	CPU: Add a getInterruptController function	2008-10-11 16:13:58 -07:00
Gabe Black	168e524b9b	X86: Create an IO APIC device.	2008-10-11 16:08:14 -07:00
Gabe Black	a2599e4fc1	X86: Set up a mechanism for the I8254 timer to cause interrupts.	2008-10-11 15:15:34 -07:00
Gabe Black	526933e5d0	X86: Add an Intel MP table to the simulation.	2008-10-11 15:14:37 -07:00
Gabe Black	f621b7b81f	CPU: Eliminate the simPalCheck funciton.	2008-10-11 12:17:24 -07:00
Gabe Black	da7209ec93	CPU: Eliminate the hwrei function.	2008-10-11 02:27:21 -07:00
Gabe Black	3af428606a	X86: Rename the PC device to Pc. --HG-- rename : src/dev/x86/PC.py => src/dev/x86/Pc.py	2008-10-11 02:23:40 -07:00
Gabe Black	826621eb17	X86: Bring the South Bridge device into dev/x86 and get rid of south_bridge directory. --HG-- rename : src/dev/x86/south_bridge/SouthBridge.py => src/dev/x86/SouthBridge.py rename : src/dev/x86/south_bridge/south_bridge.cc => src/dev/x86/south_bridge.cc rename : src/dev/x86/south_bridge/south_bridge.hh => src/dev/x86/south_bridge.hh	2008-10-11 02:21:44 -07:00
Gabe Black	bc2217eefc	X86: Change I8254 and PCSpeaker devices from subdevices to SimObjects and eliminate subdevices. --HG-- rename : src/dev/x86/south_bridge/i8254.cc => src/dev/x86/i8254.cc rename : src/dev/x86/south_bridge/i8254.hh => src/dev/x86/i8254.hh rename : src/dev/x86/south_bridge/speaker.cc => src/dev/x86/speaker.cc rename : src/dev/x86/south_bridge/speaker.hh => src/dev/x86/speaker.hh	2008-10-11 02:16:11 -07:00
Gabe Black	a6600fdd88	Devices: Make the Intel8254Timer device only use pointers to its counters.	2008-10-11 01:49:39 -07:00
Gabe Black	539563e04b	X86: Make the CMOS and I8259 devices use IntDev and IntPin.	2008-10-11 01:45:25 -07:00
Gabe Black	119e127d71	X86: Create the IntDev and IntPin system. The IntDev class is a base for anything that supports IntPins. IntPins allow devices to generically trigger interrupts on a particular pin of an IntDev device without having to know what the device is or what pin they're attached to.	2008-10-11 01:37:04 -07:00
Gabe Black	8c532d6297	X86: Hook the CMOS device to the I8259 PICs.	2008-10-11 01:31:32 -07:00
Gabe Black	cf9afbba51	X86: Make the I8259 decipher the commands it's given, and add some of it's registers.	2008-10-11 01:28:35 -07:00
Gabe Black	2753c07dc5	X86: Change the I8259 from a subdevice into a real SimObject. --HG-- rename : src/dev/x86/south_bridge/i8259.cc => src/dev/x86/i8259.cc rename : src/dev/x86/south_bridge/i8259.hh => src/dev/x86/i8259.hh	2008-10-11 01:22:20 -07:00
Gabe Black	f22c7d48f3	X86: Change the CMOS from a sub-device to a real SimObject --HG-- rename : src/dev/x86/south_bridge/cmos.cc => src/dev/x86/cmos.cc rename : src/dev/x86/south_bridge/cmos.hh => src/dev/x86/cmos.hh	2008-10-11 01:13:11 -07:00
Gabe Black	8c5dfa4532	TLB: Make all tlbs derive from a common base class in both python and C++.	2008-10-10 23:47:42 -07:00
Gabe Black	3d1734ec29	X86: Create SimObjects in python and C++ to represent the ACPI system description tables.	2008-10-10 23:43:33 -07:00
Gabe Black	f85a7f00c0	X86: Make the time on the RTC configurable.	2008-10-10 23:42:31 -07:00
Gabe Black	b03c95d075	X86: Create SimObjects in python and C++ to represent the Intel MP tables.	2008-10-10 23:39:53 -07:00
Nathan Binkert	89f016aacb	cprintf: properly deal with pointer types	2008-10-10 21:45:35 -07:00
Nathan Binkert	1f57193439	swig: Add in a %rename to allow the same name to appear in multiple namespaces.	2008-10-10 21:45:34 -07:00
Nathan Binkert	96936c6bf5	Rename the info function to inform to avoid likely name conflicts	2008-10-10 12:17:53 -07:00
Nathan Binkert	8ac63c48a4	automerge	2008-10-10 10:38:53 -07:00
Nathan Binkert	afb279b1bb	output: Make panic/fatal/warn more flexible so we can add some new ones. The major thrust of this change is to limit the amount of code duplication surrounding the code for these functions. This code also adds two new message types called info and hack. Info is meant to be less harsh than warn so people don't get confused and start thinking that the simulator is broken. Hack is a way for people to add runtime messages indicating that the simulator just executed a code "hack" that should probably be fixed. The benefit of knowing about these code hacks is that it will let people know what sorts of inaccuracies or potential bugs might be entering their experiments. Finally, I've added some flags to turn on and off these message types so command line options can change them.	2008-10-10 10:18:28 -07:00
Nathan Binkert	b25e56b32a	gdb: add a debugging function that enters the python interpreter.	2008-10-10 10:15:01 -07:00
Nathan Binkert	70dbe61ffc	jobfile: Add support for dictionaries as jobfile options. If the same dictionary option is seen in several options, those dictionaries are composed. If you define the same dictionary key in multiple options, the system flags an error. Also, clean up the jobfile code so that it is more debuggable.	2008-10-10 10:15:01 -07:00
Nathan Binkert	84364f36d0	python: Add a utility for nested attribute dicts. Change attrdict so that attributes that begin with an underscore don't go into the dict.	2008-10-10 10:15:00 -07:00
Nathan Binkert	5586b1539b	misc: remove #include <cassert> from misc.hh since not everyone needs it.	2008-10-10 10:15:00 -07:00
Gabe Black	ec0fb05d64	X86: Turn SMBios structures into simobjects.	2008-10-10 03:50:51 -07:00
Gabe Black	9be6e08227	X86: Add a couple comments to the bios SConscript	2008-10-10 03:50:42 -07:00
Gabe Black	d897aa939f	X86: Move the smbios objects into a folder for BIOS objects.	2008-10-10 03:50:18 -07:00
Gabe Black	57d663877e	X86: Fix compilation with new eventq API.	2008-10-10 03:50:07 -07:00
Nathan Binkert	94b08bed07	SimObjects: Clean up handling of C++ namespaces. Make them easier to express by only having the cxx_type parameter which has the full namespace name, and drop the cxx_namespace thing. Add support for multiple levels of namespace.	2008-10-09 22:19:39 -07:00
Nathan Binkert	4ecc5d53a3	range_map: Add a method to find which range a single value falls into.	2008-10-09 22:19:38 -07:00
Nathan Binkert	6ccf28c896	style: conform to M5 style.	2008-10-09 09:25:41 -07:00
Nathan Binkert	b556dc4119	mem: Add a method for setting the time on a packet.	2008-10-09 04:58:24 -07:00
Nathan Binkert	e06321091d	eventq: convert all usage of events to use the new API. For now, there is still a single global event queue, but this is necessary for making the steps towards a parallelized m5.	2008-10-09 04:58:24 -07:00
Nathan Binkert	8291d9db0a	eventq: Major API change for the Event and EventQueue structures. Since the early days of M5, an event needed to know which event queue it was on, and that data was required at the time of construction of the event object. In the future parallelized M5, this sort of requirement does not work well since the proper event queue will not always be known at the time of construction of an event. Now, events are created, and the EventQueue itself has the schedule function, e.g. eventq->schedule(event, when). To simplify the syntax, I created a class called EventManager which holds a pointer to an EventQueue and provides the schedule interface that is a proxy for the EventQueue. The intent is that objects that frequently schedule events can be derived from EventManager and then they have the schedule interface. SimObject and Port are examples of objects that will become EventManagers. The end result is that any SimObject can just call schedule(event, when) and it will just call that SimObject's eventq->schedule function. Of course, some objects may have more than one EventQueue, so this interface might not be perfect for those, but they should be relatively few.	2008-10-09 04:58:23 -07:00
Nathan Binkert	68c75c589b	pdb: Try to make pdb work better. I've done a few things here. First, I invoke the script a little bit differently so that pdb doesn't get confused. Second, I've stored the actual filename in the module's __file__ so that pdb can find the source file on your machine.	2008-10-09 04:58:23 -07:00
Nathan Binkert	886c5f8fe5	SINIC: Commit old code from ASPLOS 2006 studies. NOTE: This code was written by Nathan Binkert in 2006 and is properly copyright "The Regents of the University of Michigan"	2008-10-09 04:58:23 -07:00
Nathan Binkert	eb89a23556	eventq: Don't use inline friend function when a static function will do. Another good reason to avoid this is that swig will try to wrap the friend, but it won't try to wrap a private static function.	2008-10-09 04:58:23 -07:00
Nathan Binkert	a589eb4053	SCons: add code to provide a libm5 shared library. Targets look like libm5_debug.so. This target can be dynamically linked into another C++ program and provide just about all of the M5 features. Additionally, this library is a standalone module that can be imported into python with an "import libm5_debug" type command line.	2008-10-09 04:58:23 -07:00
Nathan Binkert	0b83563a9c	eventq: I'm sick of the warning about MaxTick being unused.	2008-10-09 04:58:23 -07:00
Nathan Binkert	7cc2a88038	stats: use properly signed types for looping and comparison	2008-10-09 04:58:23 -07:00
Nathan Binkert	a52dce6d62	style: Bring statistics code in line with the proper style.	2008-10-09 04:58:23 -07:00
Gabe Black	b66eb3b8d1	O3: Generaize the O3 IMPL class so it isn't split out by ISA. --HG-- rename : src/cpu/o3/sparc/cpu_builder.cc => src/cpu/o3/cpu_builder.cc rename : src/cpu/o3/sparc/dyn_inst.cc => src/cpu/o3/dyn_inst.cc rename : src/cpu/o3/sparc/impl.hh => src/cpu/o3/impl.hh rename : src/cpu/o3/sparc/thread_context.cc => src/cpu/o3/thread_context.cc	2008-10-09 00:10:02 -07:00
Gabe Black	f57c286d2c	O3: Generaize the O3 dynamic instruction class so it isn't split out by ISA. --HG-- rename : src/cpu/o3/dyn_inst.hh => src/cpu/o3/dyn_inst_decl.hh rename : src/cpu/o3/alpha/dyn_inst_impl.hh => src/cpu/o3/dyn_inst_impl.hh	2008-10-09 00:09:26 -07:00
Gabe Black	e09c403d32	O3: Generalize the O3 CPU object so it isn't split out by ISA.	2008-10-09 00:08:50 -07:00
Gabe Black	975c9e3af8	Microcode: Fix a silent typo error in the microcode assembler.	2008-10-09 00:07:38 -07:00
Gabe Black	523531a40e	Microcode: Fix a very old bug with parsing external labels in microcode.	2008-10-09 00:07:21 -07:00
Gabe Black	c5c6ad7ed6	CPU: Fix where setMicroPC was being called instead of setNextMicroPC.	2008-10-09 00:06:05 -07:00
Gabe Black	e1b306fa53	X86: Fix the debugging microops. The debug functions can't handle a string object format.	2008-10-09 00:05:39 -07:00
Gabe Black	569db520ad	X86: Make far ret modify CS instead of some random selector.	2008-10-09 00:04:36 -07:00
Nathan Binkert	6b2bb53fd6	python: cleanup options parsing stuff so that it properly deals with defaults. While we're at it, make it possible to run main.py in a somewhat standalone mode again so that we can test things without compiling.	2008-10-06 09:31:51 -07:00
Korey Sewell	6c046a28dc	fix shadow set bugs in MIPS code that caused out of bounds access... panic rdpgpr/wrpgpr instructions until a better impl. of MIPS shadow sets is available.	2008-10-06 02:07:04 -04:00
Nathan Binkert	b25755993b	unittest: Add unit tests to the scons framework. Also fix the unit tests so they actually compile correctly.	2008-10-02 11:27:01 -07:00
Nathan Binkert	52493b2720	unittest: Cleanup unit tests. Follow style. Garbage Collect. --HG-- rename : src/unittest/rangemaptest2.cc => src/unittest/rangemultimaptest.cc	2008-10-02 11:26:59 -07:00
Nathan Binkert	67a2918abc	stats: Fix small bug pointed out by unit testing.	2008-10-02 11:26:59 -07:00
Ali Saidi	0a1613abe1	Output: Verify output files are open after opening them.	2008-10-02 12:46:57 -04:00
Steve Reinhardt	7bf6a219db	Make overriding port assignments in Python work, and print better error messages when it doesn't.	2008-09-29 23:30:14 -07:00
Steve Reinhardt	45cba35fc1	Fix EVENTQ_DEBUG vs DEBUG_EVENTQ #define inconsistency.	2008-09-29 23:30:14 -07:00
Nathan Binkert	1e9c428522	alpha: Need to include cstring so that g++ 4.3 works.	2008-09-29 07:15:30 -07:00
Nathan Binkert	80d9be86e6	gcc: Add extra parens to quell warnings. Even though we're not incorrect about operator precedence, let's add some parens in some particularly confusing places to placate GCC 4.3 so that we don't have to turn the warning off. Agreed that this is a bit of a pain for those users who get the order of operations correct, but it is likely to prevent bugs in certain cases.	2008-09-27 21:03:49 -07:00
Nathan Binkert	cf7ddd8e8a	style: Make a style pass over the whole arch/alpha directory.	2008-09-27 21:03:48 -07:00
Nathan Binkert	82f5723c7a	alpha: Clean up namespace usage.	2008-09-27 21:03:47 -07:00
Nathan Binkert	8ea5176b7f	arch: TheISA shouldn't really ever be used in the arch directory. We should always refer to the specific ISA in that arch directory. This is especially necessary if we're ever going to make it to the point where we actually have heterogeneous systems.	2008-09-27 21:03:46 -07:00
Nathan Binkert	0b30c345f1	alpha: Get rid fo the namespace called EV5. We're never going to do an alpha platform other than the one we've got.	2008-09-27 21:03:45 -07:00
Nathan Binkert	819023b8e2	style	2008-09-27 07:25:04 -07:00
Nathan Binkert	83f3bff643	add a bit of style	2008-09-27 00:15:45 -07:00
Nathan Binkert	ca4baf3871	style: missed space after switch	2008-09-26 09:37:21 -07:00
Nathan Binkert	9838be2521	When nesting if statements, use braces to avoid ambiguous else clauses.	2008-09-26 08:18:57 -07:00
Nathan Binkert	abca171e24	Use logical operator instead of bitwise operator for correctness.	2008-09-26 08:18:56 -07:00
Nathan Binkert	6798aa14ed	style: bring this file into M5 style, use the new pte translate function.	2008-09-26 08:18:55 -07:00
Nathan Binkert	a053055e17	scons: disable several gcc warnings for swig autogenerated wrapper code.	2008-09-26 08:18:54 -07:00
Nathan Binkert	0309c877f3	style: These files didn't even come close to following the M5 style guide.	2008-09-26 08:18:53 -07:00
Kevin Lim	b784903207	O3CPU: Fix thread writeback logic. Fix the logic in the LSQ that determines if there are any stores to write back. In the commit stage, check for thread specific writebacks instead of just any writeback.	2008-09-26 07:44:07 -07:00
Kevin Lim	712a8ee700	O3CPU: Add a hack to ensure that nextPC is set correctly after syscalls. Just check CPU's nextPC before and after syscall and if it changes, update this instruction's nextPC because the syscall must have changed the nextPC.	2008-09-26 07:44:06 -07:00
Nathan Binkert	70ec46de17	sparc: Fix style, create a helper function for translation. The translate function simplifies code and removes some compiler warnings in gcc 3.4	2008-09-23 20:38:02 -07:00
Nathan Binkert	38dd9687ce	scons: Separate swig environment so we can have different flags. Swig code isn't quite perfect, so let's not turn on all of the warnings.	2008-09-22 08:25:58 -07:00
Nathan Binkert	6efb930e19	gcc: Version 4.3 is pretty anal about shadowing types, placate it. In the future, it would be nice to put the O3CPU into its own namespace so that we don't end up hardcoding pointers to the global namespace.	2008-09-22 08:25:57 -07:00
Nathan Binkert	f3f4b17c5b	style	2008-09-22 08:21:47 -07:00
Nathan Binkert	4826610d86	We're using the static keyword improperly in some cases.	2008-09-19 09:42:54 -07:00
Nathan Binkert	ce3d8c2b03	atomicio: provide atomic read and write functions. These functions keep trying to read and write until all data has been transferred, or an error occurrs. In the case where an end of file hasn't been reached, but all of the bytes have not been read/written, try again. On EINTR, try again.	2008-09-19 09:42:31 -07:00
Nathan Binkert	af9c5e05f7	Use C++ limits where applicable for portability	2008-09-19 09:11:43 -07:00
Nathan Binkert	befae3c0b0	Use the proper version of C++ headers	2008-09-19 09:11:43 -07:00
Nathan Binkert	ea83cedcf6	Check the return value of I/O operations for failure	2008-09-19 09:11:42 -07:00
Nathan Binkert	f066db7fcd	inifile: Whack preprocessor access. We haven't used the preprocessor feature of the inifile stuff in a very long time, so let's get rid of it since it would otherwise take effort to maintain.	2008-09-19 09:11:40 -07:00
Ali Saidi	3a3e356f4e	style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs	2008-09-10 14:26:15 -04:00
Nathan Binkert	09a8fb0b52	style: this file did not conform to style	2008-09-09 16:27:17 -07:00
Nathan Binkert	496d3f2789	style: This file hugely violated the M5 style. Remove a bunch of unused cruft from the interface while we're at it	2008-09-08 18:03:52 -07:00
Gabe Black	30bc897613	X86: Fix the microcode for sign/zero extending moves that use high byte registers.	2008-09-03 00:52:54 -04:00
Clint Smullen	4aa017affc	Device: Fix bug in DmaPort::recvRetry. The interface attempts to send the same packet again. It doesn't cause a problem currently, however with a different Memory Object it could cause problems	2008-08-26 02:37:26 -04:00
Ali Saidi	3d5fe0c372	IGbE: Patches I neglected to apply before pushing the previous igbe changeset	2008-08-24 15:27:49 -04:00
Gabe Black	3633a916c2	CPU: Get rid of two more duplicated CPU params.	2008-08-19 21:59:09 -07:00
Richard Strong	8d018aef0f	Changed BaseCPU::ProfileEvent's interval member to be of type Tick. This was done to be consistent with its python type of a latency. In addition, the multiple definitions of profile in the different cpu models caused problems for intialization of the interval value. If a child class's profile value was defined, the parent BaseCPU::ProfileEvent interval field would be initialized with a garbage value. The fix was to remove the multiple redifitions of profile in the child CPU classes.	2008-08-18 10:50:58 -07:00
Ali Saidi	6248e12704	Add the ability to specify a think time before descriptor fetch/writeback starts/ends as well as after read/write dmas	2008-08-13 17:41:58 -04:00
Ali Saidi	549c43b2d0	Add the ability for a DMA to tack on an extra delay after the DMA is actually finished.	2008-08-13 17:41:56 -04:00
Ali Saidi	05954e1ba7	More subtle fixes to how interrupts are supposed to work in the device. Fix postedInterrupts statistics.	2008-08-13 16:30:30 -04:00
Ali Saidi	91d968783e	Return an UnimpFault for an ITB translation of an uncachable address. We don't support fetching from uncached addresses in Alpha and it means that a speculative fetch can clobber device registers.	2008-08-13 16:29:59 -04:00
Nathan Binkert	1b1a7e33e7	style	2008-08-11 14:47:49 -07:00
Nathan Binkert	9cf8ad3a17	params: Get rid of the remnants of the old style parameter configuration stuff.	2008-08-11 12:22:17 -07:00
Nathan Binkert	ee62a0fec8	params: Convert the CPU objects to use the auto generated param structs. A whole bunch of stuff has been converted to use the new params stuff, but the CPU wasn't one of them. While we're at it, make some things a bit more stylish. Most of the work was done by Gabe, I just cleaned stuff up a bit more at the end.	2008-08-11 12:22:16 -07:00
Steve Reinhardt	3448a12208	Make time format in 'started' line same as 'compiled'. Also make -B output consistent with normal header, and only include actual build options.	2008-08-04 01:46:46 -04:00
Steve Reinhardt	58c63ea8b1	Get rid of outputStream... wasn't really being used (except for warn()) and new -r/-e options make it not worth fixing.	2008-08-04 01:45:12 -04:00
Steve Reinhardt	fe8aeff362	Add -r/-e options to redirect stdout/stderr. Better than using shell since it automatically uses -d directory for output files (creating it as needed).	2008-08-04 00:40:31 -04:00
Nathan Binkert	50ef39af82	sockets: Add a function to disable all listening sockets. When invoking several copies of m5 on the same machine at the same time, there can be a race for TCP ports for the terminal connections or remote gdb. Expose a function to disable those ports, and have the regression scripts disable them. There are some SimObjects that have no other function than to be used with ports (NativeTrace and EtherTap), so they will panic if the ports are disabled.	2008-08-03 18:19:55 -07:00
Nathan Binkert	ede89c2d54	libm5: Create a libm5 static library for embedding m5. This should allow m5 to be more easily embedded into other simulators. The m5 binary adds a simple main function which then calls into the m5 libarary to start the simulation. In order to make this work correctly, it was necessary embed python code directly into the library instead of the zipfile hack. This is because you can't just append the zipfile to the end of a library the way you can a binary. As a result, Python files that are part of the m5 simulator are now compile, marshalled, compressed, and then inserted into the library's data section with a certain symbol name. Additionally, a new Importer was needed to allow python to get at the embedded python code. Small additional changes include: - Get rid of the PYTHONHOME stuff since I don't think anyone ever used it, and it just confuses things. Easy enough to add back if I'm wrong. - Create a few new functions that are key to initializing and running the simulator: initSignals, initM5Python, m5Main. The original code for creating libm5 was inspired by a patch Michael Adler, though the code here was done by me.	2008-08-03 18:19:54 -07:00
Nathan Binkert	678abbc364	syscall: Avoid a compiler warning which turns into a bug. Simply cast the result to an int and life is good.	2008-08-03 18:19:53 -07:00
Steve Reinhardt	62c08a75ad	Make default PhysicalMemory latency slightly more realistic. Also update stats to reflect change.	2008-08-03 18:13:29 -04:00
Gabe Black	b179c3f4cd	X86: Make hint nops consume their modrm byte.	2008-08-03 14:43:24 -07:00
Nathan Binkert	e98ccd309b	kill unused code	2008-08-02 20:42:15 -07:00
Nathan Binkert	4b1e0d235d	scons: Get rid of generate.py in the build system. I decided that separating some of the scons code into generate.py was just a bad idea because it caused the dependency system to get all messed up. If separation is the right way to go in the future, we should probably use the sconscript mechanism, not the mechanism that I just removed.	2008-07-31 08:01:38 -07:00
Michael Adler	f3a3ab7f2c	syscall: Fix TTY emulation in fstat() user-mode simulation for fd 1 (stdout). The code didn't set S_IFCHR in the st_mode	2008-07-24 16:31:33 -07:00
Michael Adler	5f42bfcd56	process: separate stderr from stdout - Add the option of redirecting stderr to a file. With the old behaviour, stderr would follow stdout if stdout was to a file, but stderr went to the host stderr if stdout went to the host stdout. The new default maintains stdout and stderr going to the host. Now the two can specify different files, but they will share a file descriptor if the name of the files is the same. - Add --output and --errout options to se.py to go with --input.	2008-07-23 14:41:34 -07:00
Michael Adler	2cd04fd6da	syscalls: Add a bunch of missing system calls. readlink, umask, truncate, ftruncate, mkdir, and getcwd.	2008-07-23 14:41:33 -07:00
Michael Adler	8c4f18f6f5	RemoteGDB: add an m5 command line option for setting or disabling remote gdb.	2008-07-23 14:41:33 -07:00
Steve Reinhardt	aa2bb4f7b9	Get rid of useless m5_assert macro. Its only purpose was to print the cycle number but that already happens in the SIGABRT handler. No one used it anyway.	2008-07-15 14:38:51 -04:00
Steve Reinhardt	8e7ddce284	Use ReadResp instead of LoadLockedResp for LoadLockedReq responses.	2008-07-15 14:38:51 -04:00
Steve Reinhardt	6262e0d909	Add missing newlines to Bus DPRINTFs.	2008-07-15 14:38:51 -04:00
Nathan Binkert	f9a597ddf3	m5ops: clean up the m5ops stuff. - insert warnings for deprecated m5ops - reserve opcodes for Ali's stuff - remove code for stuff that has been deprecated forever - simplify m5op_alpha	2008-07-11 08:52:50 -07:00
Nathan Binkert	88766f7c71	style: fix indentation and formatting of the pseudo insts.	2008-07-11 08:52:50 -07:00
Nathan Binkert	f90b08a5cc	eventq: change the event datastructure back to LIFO. The status quo is preferred since it is less likely that people will rely on LIFO than FIFO, and when we move to a parallelized M5, no ordering between events of the same time/priority will be guaranteed.	2008-07-11 08:48:50 -07:00
Nathan Binkert	10df68dd72	eventq: new eventq data structure. The new data structure is singly linked list sorted by time and priority. For things of the same time and priority, a second, circularly linked list maintains the data structure. Events of the same time and priority are now inserted in FIFO order instead of LIFO order. This dramatically improves the performance of systems that schedule multiple events at the same time. The FIFO order version is not preferred to LIFO (because it may cause people to rely on it), but I'm going to commit it anyway and immediately commit the preferred LIFO version on top.	2008-07-11 08:38:31 -07:00
Nathan Binkert	93517dd90c	eventq: Clean up the Event class so that it uses fewer bytes. This will hopefullly allow it to fit in a cache line.	2008-07-10 21:35:42 -07:00
Ali Saidi	7a83c50a59	Fix cases where RADV interrupt timer is used and make ITR interrupt moderation not always delay if no interrupts have been posted for the ITR value.	2008-07-01 10:30:08 -04:00
Ali Saidi	a4a7a09e96	Remove delVirtPort() and make getVirtPort() only return cached version.	2008-07-01 10:25:07 -04:00
Ali Saidi	c5fbbf376a	Change everything to use the cached virtPort rather than created their own each time. This appears to work, but I don't want to commit it until it gets tested a lot more. I haven't deleted the functionality in this patch that will come later, but one question is how to enforce encourage objects that call getVirtPort() to not cache the virtual port since if the CPU changes out from under them it will be worse than useless. Perhaps a null function like delVirtPort() is still useful in that case.	2008-07-01 10:24:19 -04:00
Ali Saidi	50e3e50e1a	Make the cached virtPort have a thread context so it can do everything that a newly created one can.	2008-07-01 10:24:16 -04:00
Ali Saidi	9bd0bfe559	After a checkpoint (and thus a stats reset), the not_idle_fraction/notIdleFraction statistic is really wrong. The notIdleFraction statistic isn't updated when the statistics reset, probably because the cpu Status information was pulled into the atomic and timing cpus. This changeset pulls Status back into the BaseSimpleCPU object. Anyone care to comment on the odd naming of the Status instance? It shouldn't just be status because that is confusing with Port::Status, but _status seems a bit strage too.	2008-07-01 10:24:09 -04:00
Steve Reinhardt	96bbccc36b	Automated merge after backout.	2008-06-28 13:20:00 -04:00
Steve Reinhardt	caaac16803	Backed out changeset 94a7bb476fca: caused memory leak.	2008-06-28 13:19:38 -04:00
Ali Saidi	3205768ea5	Automated merge with http://repo.m5sim.org/m5-stable	2008-06-24 15:51:12 -04:00
Ali Saidi	57b5de6b9f	Checkpoinging/SWIG: Undo part of changeset 5464 since it broke checkpointing.	2008-06-24 15:48:45 -04:00
Gabe Black	18c83be507	SimObject: Add in missing includes of <string> and fix minor style problem.	2008-06-21 14:23:58 -04:00
Steve Reinhardt	1434b86943	Make bus address conflict error more informative	2008-06-21 01:06:27 -04:00
Steve Reinhardt	6b45238316	Generate more useful error messages for unconnected ports. Force all non-default ports to provide a name and an owner in the constructor.	2008-06-21 01:04:43 -04:00
Nathan Binkert	c1584e4227	imported patch sim_object_params.diff	2008-06-18 12:07:15 -07:00
Nathan Binkert	67a33eed40	AtomicSimpleCPU: Separate data stalls from instruction stalls. Separate simulation of icache stalls and dat stalls.	2008-06-18 10:15:21 -07:00
Nathan Binkert	1099a9838a	Ethernet: share statistics between all ethernet devices and apply some of those statistics to the e1000 model.	2008-06-17 22:22:44 -07:00
Nathan Binkert	87d03d00cd	inet: initialization fixes. Make sure variables are properly initialized and also make sure that truth testing works properly.	2008-06-17 22:14:12 -07:00
Nathan Binkert	8042b8f4c7	PacketFifo: Get slack out of the EthPacketData structure. This allows a packet to exist in multiple FIFOs if desired.	2008-06-17 21:34:27 -07:00
Nathan Binkert	163465ac08	ThreadState: Ensure that kernelStats is properly initialized	2008-06-17 21:11:20 -07:00
Nathan Binkert	9dc4e2952c	rename MipsConsole to MipsBackdoor --HG-- rename : src/dev/mips/MipsConsole.py => src/dev/mips/MipsBackdoor.py rename : src/dev/mips/console.cc => src/dev/mips/backdoor.cc rename : src/dev/mips/console.hh => src/dev/mips/backdoor.hh	2008-06-17 20:39:51 -07:00
Nathan Binkert	934523c3a0	rename AlphaConsole to AlphaBackdoor --HG-- rename : src/dev/alpha/AlphaConsole.py => src/dev/alpha/AlphaBackdoor.py rename : src/dev/alpha/console.cc => src/dev/alpha/backdoor.cc rename : src/dev/alpha/console.hh => src/dev/alpha/backdoor.hh	2008-06-17 20:36:39 -07:00
Nathan Binkert	6ff4539901	Change the default output filename for the terminal so it's more obvious. --HG-- rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal	2008-06-17 20:30:37 -07:00
Nathan Binkert	00df9016fe	Rename SimConsole to Terminal since it makes more sense --HG-- rename : src/dev/SimConsole.py => src/dev/Terminal.py rename : src/dev/simconsole.cc => src/dev/terminal.cc rename : src/dev/simconsole.hh => src/dev/terminal.hh	2008-06-17 20:29:06 -07:00
Nathan Binkert	fa8f91fdc0	physmem: Add a null option to physical memory so it doesn't store data.	2008-06-15 21:39:29 -07:00
Nathan Binkert	e3c267a3db	port: Clean up default port setup and port switchover code.	2008-06-15 21:34:32 -07:00
Nathan Binkert	b429b1759d	params: Prevent people from setting attributes on vector params.	2008-06-15 21:26:33 -07:00
Nathan Binkert	6dedc645f7	add compile flags to m5	2008-06-15 20:56:35 -07:00
Nathan Binkert	b2036bfda8	Command line option to print out List of SimObjects and their parameters	2008-06-14 21:51:08 -07:00
Nathan Binkert	bbeb8082a5	main: add .m5/options.py processing. This file is processed before arguments are parsed so that they can change the default options for various config parameters.	2008-06-14 21:16:00 -07:00
Nathan Binkert	fc48d1dcf5	Add .m5 configuration directory	2008-06-14 21:15:59 -07:00
Nathan Binkert	779c31077c	python: Separate the options parsing stuff. Remove options parsing stuff from main.py so things are a bit more obvious.	2008-06-14 21:15:58 -07:00
Nathan Binkert	4afdc40d70	params: Fix the memory bandwidth parameter	2008-06-14 20:42:45 -07:00
Nathan Binkert	3d2e7797cc	params: Fix floating point parameters	2008-06-14 20:39:31 -07:00
Nathan Binkert	f82d4e2364	python: Move various utility classes into a new m5.util package so they're all in the same place. This also involves having just one jobfile.py and moving it into the utils directory to avoid duplication. Lots of improvements to the utility as well. --HG-- rename : src/python/m5/attrdict.py => src/python/m5/util/attrdict.py rename : util/pbs/jobfile.py => src/python/m5/util/jobfile.py rename : src/python/m5/util.py => src/python/m5/util/misc.py rename : src/python/m5/multidict.py => src/python/m5/util/multidict.py rename : util/stats/orderdict.py => src/python/m5/util/orderdict.py	2008-06-14 20:19:49 -07:00
Nathan Binkert	fe325c7f43	MemReq: Add option to reset the time on a request.	2008-06-14 19:39:01 -07:00
Nathan Binkert	ce43e46576	Fix various SWIG warnings	2008-06-14 12:57:21 -07:00
Nathan Binkert	7a58b5a38a	Add missing dependencies on .i files	2008-06-14 12:10:50 -07:00
Nathan Binkert	2d037682ff	scons: proper fix for hg version stuff	2008-06-14 10:30:18 -07:00
Nathan Binkert	fe4fd9f414	scons: fix program_info.cc generation	2008-06-13 17:34:22 -07:00
Steve Reinhardt	dace77dc4a	Automated merge with ssh://m5sim.org//repo/m5	2008-06-13 01:59:10 -04:00
Steve Reinhardt	caccbd1edc	Get rid of bogus bus assertion. It runs out that if a MemObject turns around and does a send in its receive callback, and there are other sends already scheduled, then it could observe a state where it's not at the head of the list but the bus's sendEvent is not scheduled (because we're still in the middle of processing the prior sendEvent).	2008-06-13 01:33:49 -04:00
Steve Reinhardt	024ec4c5c3	Get rid of bogus cache assertion. I was asserting that the only reason you would defer targets is if a write came in while you had an outstanding read miss, but there's another case where you could get a read access after you've snooped an invalidation and buffered it because it applies to a prior outstanding miss.	2008-06-13 01:29:20 -04:00
Ali Saidi	907b28cc62	HG: Add compiled hg revision and date to the standard M5 output.	2008-06-13 01:09:04 -04:00
Gabe Black	2b4874449c	Alpha: Get rid of an old include of a non-existant file.	2008-06-12 01:54:21 -04:00
Gabe Black	7be8e671f1	Params: Allow nested namespaces in cxx_namespace	2008-06-12 01:00:29 -04:00
Gabe Black	5b5875341c	X86: Make the cpuid processor identifier return a real string.	2008-06-12 01:00:19 -04:00
Gabe Black	c625cf0ae1	X86: Make the code compile as 32 bit.	2008-06-12 01:00:05 -04:00
Gabe Black	23c04b8c66	Params: Remove an unnecessary include.	2008-06-12 00:59:58 -04:00
Gabe Black	bceaa257a3	X86: Make the e820 table manually or automatically configurable from python.	2008-06-12 00:58:36 -04:00
Gabe Black	4f4ff17578	X86: Make the disassembly for halt conform with the other microops.	2008-06-12 00:58:27 -04:00
Gabe Black	31d40ad7c2	X86: Implement and hook up STI and CLI instructions.	2008-06-12 00:58:19 -04:00
Gabe Black	da20c0ec54	X86: Make sure there's something to catch when the kernel messes with ports "behind" the pci config magic ports.	2008-06-12 00:58:13 -04:00
Gabe Black	1f5b992b58	X86: Make the platform object initialize channel 0 of the PIT.	2008-06-12 00:56:54 -04:00
Gabe Black	16e26fbf03	X86: Hook the speaker device to the pit device.	2008-06-12 00:56:17 -04:00
Gabe Black	da7f512067	Timer: Fill out the periodic modes a little.	2008-06-12 00:56:07 -04:00
Gabe Black	4f9a0402f6	Dev: Seperate the 8254 timer from tsunami and use it in that and the PC.	2008-06-12 00:54:48 -04:00
Gabe Black	0368ccdeda	BitUnion: Take out namespace declaration so bitunions can be declared inside classes.	2008-06-12 00:54:32 -04:00
Gabe Black	81936ae2ed	X86: Add an event for the apic timer timeout. It doesn't get used yet.	2008-06-12 00:54:19 -04:00
Gabe Black	6b8d0363ee	X86: Rename the divide count register to divide configuration.	2008-06-12 00:54:12 -04:00
Gabe Black	b10742ee2b	X86: Make the apic isr and irr work.	2008-06-12 00:54:05 -04:00
Gabe Black	69000baef3	X86: Make the apic task priority register work.	2008-06-12 00:54:01 -04:00
Gabe Black	e9c481ea4a	X86: Make the logical destination and destination format work.	2008-06-12 00:53:50 -04:00
Gabe Black	ed23a4970b	X86: Make the apic ID register work.	2008-06-12 00:53:43 -04:00
Gabe Black	8a6723e038	X86: Make the apic version register work.	2008-06-12 00:53:37 -04:00
Gabe Black	8d2416c6e9	X86: Implement a partial, sort of correct version of the protected mode variant of iret.	2008-06-12 00:53:01 -04:00
Gabe Black	66f54a6037	X86: Change how segment loading is performed.	2008-06-12 00:52:12 -04:00
Gabe Black	129831c116	X86: Make pushes and pops use the stack size instead of the data size.	2008-06-12 00:51:57 -04:00
Gabe Black	b05299253f	X86: In non 64bit mode, throw a fault when a NULL segment is accessed.	2008-06-12 00:51:50 -04:00
Gabe Black	a8384311d5	X86: Take advantage of the new meta register.	2008-06-12 00:51:14 -04:00
Gabe Black	d4e7c7edd3	X86: Keep handy values like the operating mode in one register.	2008-06-12 00:50:25 -04:00
Gabe Black	fa7c81c6df	X86: Change what the microop chks does. Instead of computing the segment descriptor address, this now checks if a selector value/descriptor are legal for a particular purpose.	2008-06-12 00:50:10 -04:00
Gabe Black	6bd9cf3594	X86: Add a microop to read a segments attribute register.	2008-06-12 00:50:05 -04:00
Gabe Black	e0c20386ac	X86: Add microops and supporting code to manipulate the whole rflags register.	2008-06-12 00:49:50 -04:00
Gabe Black	2bb8933f78	X86: Add microops which panic, fatal, warn, and warn_once.	2008-06-12 00:49:25 -04:00
Gabe Black	bbc1f394ff	X86: Truncate descriptors to 16 bits.	2008-06-12 00:49:16 -04:00
Gabe Black	6106b05b6e	X86: Redo BSF.	2008-06-12 00:48:58 -04:00
Gabe Black	dfc2d44ea3	X86: Flesh out 3dnow instruction decoding a bit and grab the byte immediate.	2008-06-12 00:48:46 -04:00
Gabe Black	de6eeaaa27	X86: Make string instructions work when rcx=0.	2008-06-12 00:48:15 -04:00
Gabe Black	8688ef3fe5	X86: Have all 8 machine check registers since the kernel assumes they're there.	2008-06-12 00:48:02 -04:00
Gabe Black	a8e3001df8	X86: Bypass unaligned access support for register addressed MSRs.	2008-06-12 00:47:25 -04:00
Gabe Black	b3e55339f9	X86: Remove enforcement of APIC register access alignment. Panic if more than one register is accessed at a time.	2008-06-12 00:46:22 -04:00
Gabe Black	8e2991b529	X86: Fix the implementation of BSF.	2008-06-12 00:46:04 -04:00
Gabe Black	16e189fad2	X86: Bit scan forward/reverse were accidentally transposed.	2008-06-12 00:45:52 -04:00
Gabe Black	254cc07650	X86: Fix a byte register indexing issue in the sign extending move from memory microcode.	2008-06-12 00:45:22 -04:00
Gabe Black	8501a90f59	X86: Add in some support for the tsc register.	2008-06-12 00:39:10 -04:00
Gabe Black	d093fcb079	CPU: Make the simple cpu trace data for loads/stores.	2008-06-12 00:35:50 -04:00
Ali Saidi	5797ff1016	X86: Fix building on *BSD hosts	2008-06-11 10:54:12 -04:00
Ali Saidi	fd3e661cd3	SCons: Fix more SCons version issues	2008-06-11 10:54:08 -04:00
Ali Saidi	f5e36d156d	IGbE: Implement sending packet that is contained in more than 2 descriptors. --HG-- extra : convert_revision : 8fb7d5fad5cb840f69c31aa8b331dbe09e46ee9d	2008-05-20 16:06:56 -04:00
Stephen Hines	b7af65f414	SCons: Fixing SCons bug 2006 issues for non-alpha ISAs --HG-- extra : convert_revision : 26e3edef06d6f82aaf162825c151d18faadd6e72	2008-05-20 14:04:53 -04:00
Ali Saidi	e71a5270a2	Make sure that output files are always checked success before they're used. Make OutputDirectory::resolve() private and change the functions using resolve() to instead use create(). --HG-- extra : convert_revision : 36d4be629764d0c4c708cec8aa712cd15f966453	2008-05-15 19:10:26 -04:00
Ali Saidi	4a4317ae18	SCons: More scons fixing for SCons bug 2006 --HG-- extra : convert_revision : d3656ab1e3c18251d4bcf6f5a31103d4b2dfdc43	2008-05-06 16:22:14 -04:00
Ali Saidi	8af6dc118c	SCons: add comments to SConscript documenting bug workaround --HG-- extra : convert_revision : e6cdffe953d56b96c76c7ff14d2dcc3de3ccfcc3	2008-04-10 15:38:10 -04:00
Ali Saidi	fe12f38353	PhysicalMemory: Add parameter for variance in memory delay. --HG-- extra : convert_revision : b931472e81dedb650b7accb9061cb426f1c32e66	2008-04-10 14:44:52 -04:00
Ali Saidi	ed27c4c521	SCons: Manually specifying header only directories with Dir() works around the problem --HG-- extra : convert_revision : d9713228d934cf4a45114a972603b8bca2bd27d3	2008-04-08 11:08:26 -04:00
Ali Saidi	1605fbebc8	IGbE: Fix bug that limits wire performance a bit --HG-- extra : convert_revision : 3f93c17f647a6955dab861da211174de856ee02c	2008-03-25 15:58:54 -04:00
Steve Reinhardt	ba1f7d31e0	Automated merge with ssh://daystrom.m5sim.org//repo/m5 --HG-- extra : convert_revision : 7922848bb1145bcb2ee07d672d21cfe2dd98fc03	2008-03-25 10:04:52 -04:00
Steve Reinhardt	29be31ce31	Fix handling of writeback-induced writebacks in atomic mode. --HG-- extra : convert_revision : 4fa64f8a929f1aa36a9d5a71b8d1816b497aca4c	2008-03-25 10:01:21 -04:00
Gabe Black	93dd1978a7	X86: Put an RTC into the CMOS part of the southbridge. --HG-- extra : convert_revision : a614373236fe75db6e6181fc152a02b541a131f3	2008-03-25 02:15:23 -04:00
Gabe Black	e5bdae15f3	Devices: Separate out the MC146818 RTC so both Alpha and X86 can use it. --HG-- extra : convert_revision : 1e7f5185654ed0845678c2169c702d3b977159ed	2008-03-25 02:15:06 -04:00
Gabe Black	af9a57566a	X86: Turn #defines into consts. --HG-- extra : convert_revision : c0416de5d88ca39f54494418768e68a93aa4f2aa	2008-03-25 02:09:18 -04:00
Gabe Black	48409ca512	X86: Start implementing the south bridge stuff. --HG-- extra : convert_revision : 92918c05eb3363155d78889bdab17baa8eae9dca	2008-03-25 02:08:54 -04:00
Gabe Black	b0c52885ce	X86: Change the Opteron platform to be the PC platform. --HG-- extra : convert_revision : 2c6ffebbad04a21cef6ba3fbc1803218908a6c37	2008-03-25 02:06:53 -04:00
Steve Reinhardt	623dd7ed3a	Delete the Request for a no-response Packet when the Packet is deleted, since the requester can't possibly do it. --HG-- extra : convert_revision : 8571b144ecb3c70efc06d09faa8b3161fb58352d	2008-03-24 01:08:02 -04:00
Steve Reinhardt	93ab43288a	Don't FastAlloc MSHRs since we don't allocate them on the fly. --HG-- extra : convert_revision : 02775cfb460afe6df0df0938c62cccd93a71e775	2008-03-24 01:08:02 -04:00
Steve Reinhardt	627592c2f2	Add FAST_ALLOC_DEBUG and FAST_ALLOC_STATS as SConstruct options. --HG-- extra : convert_revision : 56a7f646f2ac87019c78ba7fa62c5f4bdc00ba44	2008-03-24 01:08:02 -04:00
Steve Reinhardt	407710d387	Fix cache problem with writes to tempBlock getting wrong writeback address. --HG-- extra : convert_revision : 023dfb69c227c13a69bfe2744c6af75a45828b0b	2008-03-22 22:17:15 -04:00
Gabe Black	3fe1af7952	MIPS: Check endianness of binaries in SE mode. --HG-- extra : convert_revision : e6c4bda6078eb68a26f8834411f744078c6bf5a9	2008-03-20 02:10:21 -04:00
Steve Reinhardt	b051ae6acc	Fix a few Packet memory leaks. --HG-- extra : convert_revision : 00db19f0698c0786f0dff561eea9217860a5a05a	2008-03-17 03:08:28 -04:00
Steve Reinhardt	131c65f429	Restructure bus timing calcs to cope with pkt being deleted by target. --HG-- extra : convert_revision : db8497e73a44f2a06aab121e797e88b4c0c31330	2008-03-17 03:07:38 -04:00
Steve Reinhardt	19c367fa8f	Fix subtle cache bug where read could return stale data if a prior write miss arrived while an even earlier read miss was still outstanding. --HG-- extra : convert_revision : 4924e145829b2ecf4610b88d33f4773510c6801a	2008-03-15 05:03:55 -07:00
Gabe Black	50946b1673	Merge --HG-- extra : convert_revision : ec5f41b2007ade15f6f4c4a1533e50f9cba2798e	2008-03-06 21:09:15 -05:00
Gabe Black	a245b0eedf	X86: Refine the local APIC. --HG-- extra : convert_revision : 2789c54ed555fed2f2a333fcc7dc6454f294ebf2	2008-03-06 20:37:28 -05:00
Vilas Sridharan	21fd15ad9a	O3CPU: Don't call dumpInsts if DEBUG is not defined --HG-- extra : convert_revision : 3194bde4c624d118969bfbf92282539963a72245	2008-03-06 00:27:09 -05:00
Gabe Black	66aaabf4ae	X86: Don't map the local APIC into the physical address space in SE mode. --HG-- extra : convert_revision : b7103974b12130bbf43583c4cb5294b808add208	2008-03-01 00:05:12 -05:00
Steve Reinhardt	19dfde2317	Automated merge with ssh://daystrom.m5sim.org//repo/m5 --HG-- extra : convert_revision : f4bcd342e7abb86ca83840b723e6ab0b861ecf5b	2008-02-27 18:18:56 -05:00
Korey Sewell	8fb74c238c	Add comments in code to describe bug conditions. This should help if somebody gets to the bug fix before me (or someone else)... --HG-- extra : convert_revision : 0ae64c58ef4f7b02996f31e9e9e6bfad344719e2	2008-02-27 17:50:29 -05:00
Korey Sewell	b45cf21a8e	Fix Load/Store Queue squashing after a SMT thread is removed but ensuring you are squashing from the current instruction # causing the thread exit. --HG-- extra : convert_revision : ccbeece7dd1d5fee43f30ab19370908972113473	2008-02-27 16:53:08 -05:00
Korey Sewell	34715cc691	Fix offset in removeThread() function so that float registers start freeing up from the right point (#32 usually) instead of restarting at 0 and double-freeing. Commented out assert line in free_list.hh that will check for when double-free condition goes bad. --HG-- extra : convert_revision : 08d5f9b6a874736e487d101e85c22aaa67bf59ae	2008-02-27 16:48:33 -05:00
Steve Reinhardt	e6d6adc731	Revamp cache timing access mshr check to make stats sane again. --HG-- extra : convert_revision : 37009b8ee536807073b5a5ca07ed1d097a496aea	2008-02-26 22:03:28 -08:00
Rick Strong	fcfc8b8c4f	Configs: Make using Simpoints easier with some config files that support them easily --HG-- extra : convert_revision : 0f21829306eb68b332f03da410e6c341c8595bdd	2008-02-27 00:35:09 -05:00
Gabe Black	43ecce5fda	X86: Put in initial implementation of the local APIC. --HG-- extra : convert_revision : 1708a93d96b819e64ed456c75dbb5325ac8114a8	2008-02-26 23:39:53 -05:00
Gabe Black	98d2ca403e	X86: Implement the INVLPG instruction and the TIA microop. --HG-- extra : convert_revision : 31db1ee082f6c3ca5443cba1eb335e408661ead2	2008-02-26 23:39:22 -05:00
Gabe Black	8b4796a367	TLB: Make a TLB base class and put a virtual demapPage function in it. --HG-- extra : convert_revision : cc0e62a5a337fd5bf332ad33bed61c0d505a936f	2008-02-26 23:38:51 -05:00
Gabe Black	7bde0285e5	X86: Get PCI config space to work, and adjust address space prefix numbering scheme. --HG-- extra : convert_revision : 2b382f478ee8cde3a35aa4c105196f200bc7afa6	2008-02-26 23:38:01 -05:00
Steve Reinhardt	bdf3323915	Cache: better comments particularly regarding writeback situation. --HG-- extra : convert_revision : 59ff9ee63ee0fec5a7dfc27b485b737455ccf362	2008-02-26 20:17:26 -08:00
Gabe Black	ec1a4cbbc7	Bus: Fix the bus timing to be more realistic. --HG-- extra : convert_revision : acd70dc98ab840e55b114706fbb6afb2a95e54bc	2008-02-26 02:20:08 -05:00
Steve Reinhardt	4597a71cef	Make L2+ caches allocate new block for writeback misses instead of forwarding down the line. --HG-- extra : convert_revision : b0d6e7862c92ea7a2d21f817d30398735e7bb8ba	2008-02-16 14:58:03 -05:00
Ali Saidi	9faec83ac5	CPU: move the PC Events code to a place where the code won't be executed multiple times if an instruction faults. --HG-- extra : convert_revision : 19c8e46a4eea206517be7ed4131ab9df0fe00e68	2008-02-14 16:14:35 -05:00
Ali Saidi	a33a3f7c55	Update copyright dates --HG-- extra : convert_revision : 547e7ddff6b8005a9eaad60970bc51984e84fcd1	2008-02-11 12:35:28 -05:00
Steve Reinhardt	71835d42df	Automated merge with file:/home/stever/hg/m5-orig --HG-- extra : convert_revision : 86a55cd98a9704f756a70aa0cbd2820cf92c821d	2008-02-11 08:31:26 -08:00
Steve Reinhardt	2f7421b12b	EXTRAS now points to src instead of needing 'src' subdir. --HG-- extra : convert_revision : 8e7e4516ace8c7852eeea3c479bfd567839a8061	2008-02-11 08:04:01 -08:00
Nicolas Zea	4c7eb21119	Bus: Only update port cache when there is an item to update it with. --HG-- extra : convert_revision : 84848fd48bb9e6693a0518c862364142b1969aa8	2008-02-10 19:41:03 -05:00
Ali Saidi	d167e2bb97	IGbE: Fix a couple of bugs. --HG-- extra : convert_revision : a1f16bd82b6fbd5b6b5dc0f08b9e69858bea86ca	2008-02-10 19:32:12 -05:00
Steve Reinhardt	9d7a69c582	Fix #include lines for renamed cache files. --HG-- extra : convert_revision : b5008115dc5b34958246608757e69a3fa43b85c5	2008-02-10 14:45:25 -08:00
Steve Reinhardt	d56e77c180	Rename cache files for brevity and consistency with rest of tree. --HG-- rename : src/mem/cache/base_cache.cc => src/mem/cache/base.cc rename : src/mem/cache/base_cache.hh => src/mem/cache/base.hh rename : src/mem/cache/cache_blk.cc => src/mem/cache/blk.cc rename : src/mem/cache/cache_blk.hh => src/mem/cache/blk.hh rename : src/mem/cache/cache_builder.cc => src/mem/cache/builder.cc rename : src/mem/cache/miss/mshr.cc => src/mem/cache/mshr.cc rename : src/mem/cache/miss/mshr.hh => src/mem/cache/mshr.hh rename : src/mem/cache/miss/mshr_queue.cc => src/mem/cache/mshr_queue.cc rename : src/mem/cache/miss/mshr_queue.hh => src/mem/cache/mshr_queue.hh rename : src/mem/cache/prefetch/base_prefetcher.cc => src/mem/cache/prefetch/base.cc rename : src/mem/cache/prefetch/base_prefetcher.hh => src/mem/cache/prefetch/base.hh rename : src/mem/cache/prefetch/ghb_prefetcher.cc => src/mem/cache/prefetch/ghb.cc rename : src/mem/cache/prefetch/ghb_prefetcher.hh => src/mem/cache/prefetch/ghb.hh rename : src/mem/cache/prefetch/stride_prefetcher.cc => src/mem/cache/prefetch/stride.cc rename : src/mem/cache/prefetch/stride_prefetcher.hh => src/mem/cache/prefetch/stride.hh rename : src/mem/cache/prefetch/tagged_prefetcher.cc => src/mem/cache/prefetch/tagged.cc rename : src/mem/cache/prefetch/tagged_prefetcher.hh => src/mem/cache/prefetch/tagged.hh rename : src/mem/cache/tags/base_tags.cc => src/mem/cache/tags/base.cc rename : src/mem/cache/tags/base_tags.hh => src/mem/cache/tags/base.hh rename : src/mem/cache/tags/Repl.py => src/mem/cache/tags/iic_repl/Repl.py rename : src/mem/cache/tags/repl/gen.cc => src/mem/cache/tags/iic_repl/gen.cc rename : src/mem/cache/tags/repl/gen.hh => src/mem/cache/tags/iic_repl/gen.hh rename : src/mem/cache/tags/repl/repl.hh => src/mem/cache/tags/iic_repl/repl.hh extra : convert_revision : ff7a35cc155a8d80317563c45cebe405984eac62	2008-02-10 14:15:42 -08:00
Stephen Hines	6cc1573923	Make the Event::description() a const function --HG-- extra : convert_revision : c7768d54d3f78685e93920069f5485083ca989c0	2008-02-06 16:32:40 -05:00
Stephen Hines	0ccf9a2c37	Add base ARM code to M5 --HG-- extra : convert_revision : d811bf87d1a0bfc712942ecd3db1b48fc75257af	2008-02-05 23:44:13 -05:00
Steve Reinhardt	b96631e1a0	Cleaned up os.path imports a bit. --HG-- extra : convert_revision : ee75bf9abd249ab053e804739cc50972475cd5b6	2008-02-05 17:43:45 -08:00
Steve Reinhardt	d725ff450d	Make EXTRAS work for SConsopts too. Requires pushing source files down into 'src' subdir relative to directory listed in EXTRAS. --HG-- extra : convert_revision : ca04adc3e24c60bd3e7b63ca5770b31333d76729	2008-02-05 17:40:08 -08:00
Gabe Black	ca313e2303	X86: Put an SMBios/DMI table in memory. This is basically just the header right now, but there's an untested mechanism in place to fill out the table and make sure everything is updated correctly. --HG-- extra : convert_revision : c1610c0dfa211b7e0d091a04133695d84f500a1c	2008-01-23 15:28:54 -05:00
Gabe Black	423bbe6499	X86: Optomize the bit scanning instruction microassembly a little. More can be done. --HG-- extra : convert_revision : 3cf6e972f0e41e3529a633ecbb31289e1bd17f0f	2008-01-23 08:18:27 -05:00
Gabe Black	60c2d98fc0	X86: Implement and attach the BSR and BSF instructions. --HG-- extra : convert_revision : be7e11980092e5d1baff0e05d4ec910305966908	2008-01-22 00:10:33 -05:00
Gabe Black	f809637011	X86: Fill out group17 in the decoder. --HG-- extra : convert_revision : 66ab9c0fc3086f66e3d6d82d47964ecf406c3a8a	2008-01-21 16:27:40 -05:00
Gabe Black	657b52fea1	X86: Use the existing boot_osflags instead of duplicating it. --HG-- extra : convert_revision : e04e438d7d261a61c52b946c23cd126ed648814a	2008-01-21 04:32:34 -05:00
Ke Meng	0b6876a0c0	The reason is that the event is supposed to put the instructions ready to execute for next cycle. And the FUCompletion event has a lower priority than CPU tick event. It is called after the iew->tick() for current cycle has already been executed and the issueToExecuteQueue has already advanced this time. And assume the issueToExecuteLatency is 1, to catch up, the increasement should be made at access(-1) instead of access(0). Otherwise I found it could increase the actual op_latency of the instructions to execute by 1 cycle and potentially put the simulated CPU into a permanent idle state. Signed-off by: Ali Saidi <saidi@eecs.umich.edu> --HG-- extra : convert_revision : dafc16814383e8e8f8320845edf6ab2bcfed1e1d	2008-01-14 11:47:32 -05:00
Gabe Black	c08b7802a9	X86: Redo the bit test instructions. --HG-- extra : convert_revision : 433c2a9f3675ed02f3be5ce759a440f2686d2ccd	2008-01-12 06:41:32 -05:00
Gabe Black	b705eba6e5	X86: Fix the wrmsr instruction. --HG-- extra : convert_revision : 12bc7e71226ebafb8eedadf6a3db82929e15e722	2008-01-12 06:40:55 -05:00
Gabe Black	0ee67d4210	X86: Make the effective segment base shadow the regular one, not the selector. --HG-- extra : convert_revision : 498c7c16d664c784b196885b1f35c3c6386c9cfc	2008-01-12 06:40:10 -05:00
Gabe Black	223e48e6ae	X86: Make the IO ports work using extra physical address lines. Add a serial port. --HG-- extra : convert_revision : a14cb4fc9afedfc0ff58b11a7f8fb5516d462cc6	2008-01-12 06:39:15 -05:00
Gabe Black	0e394fdfa4	X86: Fix the general IO instructions dataSize. --HG-- extra : convert_revision : 9774a52cb6a8e7632d1b1dc0706e5791cc18d238	2008-01-12 06:37:35 -05:00
Geoffrey Blake	f9c54d5a4b	Temporary fix for ll/sc bug see flyspray task for more info: http://www.m5sim.org/flyspray/task/197 Signed-off by: Ali Saidi <saidi@eecs.umich.edu> --HG-- extra : convert_revision : cdeece7e3163de9abf2c6c7435f1bc93570fab81	2008-01-06 00:19:45 -05:00
Steve Reinhardt	6c5a3ab8b2	Add ReadRespWithInvalidate to handle multi-level coherence situation where we defer a response to a read from a far-away cache A, then later defer a ReadExcl from a cache B on the same bus as us. We'll assert MemInhibit in both cases, but in the latter case MemInhibit will keep the invalidation from reaching cache A. This special response tells cache A that it gets the block to satisfy its read, but must immediately invalidate it. --HG-- extra : convert_revision : f85c8b47bb30232da37ac861b50a6539dc81161b	2008-01-02 15:22:38 -08:00
Steve Reinhardt	bf9b3821bd	Mark cache-to-cache MSHRs as downstreamPending when necessary. Don't mark upstream MSHR as pending if downstream MSHR is already in service. --HG-- extra : convert_revision : e1c135ff00217291db58ce8a06ccde34c403d37f	2008-01-02 15:18:33 -08:00
Steve Reinhardt	538da9e24d	Don't DPRINTF in the middle of a PrintReq. --HG-- extra : convert_revision : 6358c014d14a19a34111c39827b05987507544bb	2008-01-02 14:42:42 -08:00
Steve Reinhardt	87e5fd1755	Bug fix: functional cache port now needs otherPort set. --HG-- extra : convert_revision : fb007df73a77535a5dba19341f7b0b32e8c99548	2008-01-02 14:42:24 -08:00
Steve Reinhardt	cde5a79eab	Additional comments and helper functions for PrintReq. --HG-- extra : convert_revision : 7eadf9b7db8c0289480f771271b6efe2400006d4	2008-01-02 13:46:22 -08:00
Steve Reinhardt	3952e41ab1	Add functional PrintReq command for memory-system debugging. --HG-- extra : convert_revision : 73b753e57c355b7e6873f047ddc8cb371c3136b7	2008-01-02 12:20:15 -08:00
Steve Reinhardt	659aef3eb8	Fix formatting and comments in cache_impl.hh --HG-- extra : convert_revision : 26d71cca5420ad03e16bf174e15dabe7f902da41	2008-01-02 12:15:48 -08:00
Gabe Black	2cb7d4f068	SPARC: Fix a bug where the TLB would match against the wrong entries. --HG-- extra : convert_revision : 631b3b6a1416121b54bd9717ca1cdccdd5b8a1eb	2008-01-01 18:20:08 -05:00
Ali Saidi	45ea1549c9	Checkpointing: Fix a bug in the simulation script when restoring without standard switch and change some ifs to work with the default port since every port is now connected to something. --HG-- extra : convert_revision : 72507cf13e58465291b0dce6322e853bee5a2b89	2007-12-18 01:52:57 -05:00
Ali Saidi	71909a50de	CPU: Update where the simple cpus read their cpu id from the thread context to init() to make sure they read the right value. This fixes a bug with multi-processor full-system configurations. --HG-- extra : convert_revision : 4f2801967a271b43817d88e147c2f80c4480b2c3	2007-12-16 03:48:13 -05:00
Gabe Black	27cc351688	X86: Please excuse my dear Aunt Sally. (precedence bug) --HG-- extra : convert_revision : 9ad4f31e7a962c3177896bcbfb93e2e54720d117	2007-12-03 14:32:56 -08:00
Gabe Black	73caca57a8	X86: Make sure the memory index is calculated using the address size for bit test instructions. --HG-- extra : convert_revision : 9634675857dae53b5e79e49267c864a0265afde1	2007-12-02 01:46:38 -08:00
Gabe Black	b5d4018382	X86: Fix a copy/paste mistake where the bit test instructions were using an immediate where they should use a register. --HG-- extra : convert_revision : b0ee80e4c7fdb58a1eb85b3bcc82a0cdaa93330a	2007-12-02 01:46:29 -08:00
Gabe Black	62ad1d2872	X86: Make the page not present panic more descriptive. --HG-- extra : convert_revision : 9360e47adb61e164ac218f2ea231eaa60bf3229d	2007-12-02 01:46:14 -08:00
Gabe Black	82e705d713	X86: Start setting up the real mode data structure. --HG-- extra : convert_revision : ba6d4939d4d58da5586655c83f1617f47dc7e359	2007-12-02 00:04:31 -08:00
Gabe Black	5de71e39d8	X86: Make the 0xA0-0xA3 versions of mov use the right sized immediates. --HG-- extra : convert_revision : a702403de29772618abb5bd5c5555279d91bdd59	2007-12-02 00:02:51 -08:00
Gabe Black	4c37f828f1	X86: Add in a missing "break". --HG-- extra : convert_revision : 2e48d8b0292bc3b78e4caa27dec20113d40e7d74	2007-12-01 23:11:23 -08:00
Gabe Black	9805916cec	X86: Actually do something for the MiscRegFile clear function. --HG-- extra : convert_revision : 36f8abaa9d09700d8ba9e09b4a10fa4dce580f36	2007-12-01 23:10:42 -08:00
Gabe Black	42ae409746	X86: Move startup code to the system object to initialize a Linux system. --HG-- extra : convert_revision : a4796c79f41aa8b8f38bf2f628bee8f1b3af64be	2007-12-01 23:09:56 -08:00
Gabe Black	e7fc5c42f3	X86: Add a missing microcode file to the sconscript. --HG-- extra : convert_revision : 6da8a67e07bada169abf7f10aded8a90d4e63eae	2007-12-01 23:07:41 -08:00
Gabe Black	67fee01026	X86: Fix a copy paste error in the bts microcode. --HG-- extra : convert_revision : c4ac007d35ac13211f9816f1104c84f2b447ddba	2007-12-01 23:06:52 -08:00
Gabe Black	988c6f227a	X86: Implement mov from control register. --HG-- extra : convert_revision : c8280f0686a3ae6d5c405327540ad15a3a5531f9	2007-12-01 23:06:03 -08:00
Gabe Black	fe833dd2c3	X86: First crack at far returns. This is grossly approximate. --HG-- extra : convert_revision : 23da0338af1f7663ae5ddf2289fb45dd32f37c42	2007-12-01 23:05:01 -08:00
Gabe Black	dc6f960171	X86: Reorganize segmentation and implement segment selector movs. --HG-- extra : convert_revision : 553c3ffeda1f5312cf02493f602e7d4ba2fe66e8	2007-12-01 23:03:39 -08:00
Gabe Black	a548067b01	X86: Make the "fault" microop predicated. --HG-- extra : convert_revision : ded34133afcd6af1f55b8991b82bad45258069d3	2007-12-01 23:01:56 -08:00
Gabe Black	557bc80647	X86: Implement the LIDT instruction. --HG-- extra : convert_revision : 380515e985318311632e00b13000585afb052e3b	2007-12-01 23:01:31 -08:00
Gabe Black	62c79ca637	X86: Implement the lgdt instruction. --HG-- extra : convert_revision : d1698a82df3c57cc9bbf8d5d190f271bfc7cb2e4	2007-12-01 23:01:17 -08:00
Gabe Black	4e3ff42762	X86: Implement wrbase and wrlimit for loading pseudo descriptors. --HG-- extra : convert_revision : fe03c4aed95ef12773e80cdb3d9cff68a2b20f02	2007-12-01 23:00:58 -08:00
Gabe Black	bfc62d1a70	X86: Separate the effective seg base and the "hidden" seg base. --HG-- extra : convert_revision : 5fcb8d94dbab7a7d6fe797277a5856903c885ad4	2007-12-01 23:00:15 -08:00
Gabe Black	7433032b39	SPARC: Fixes for invalidateAll and demapAll in the SPARC TLBs. --HG-- extra : convert_revision : 8de6c60b0e3e725eac11047a9d9888097dd359ff	2007-11-30 16:49:27 -08:00
Gabe Black	38e804f7cd	SPARC: Fix 32 bit register window flushing endian conversion. --HG-- extra : convert_revision : be91d6fecb44a85e983343704a098b456948af8a	2007-11-29 20:20:18 -08:00
Gabe Black	fa5e3b47c8	SPARC: Fix the initial stack to match what the Linux kernel does. --HG-- extra : convert_revision : a4451710d8463e52227fd8f760ab737ea8f404b5	2007-11-29 00:00:26 -08:00
Gabe Black	16e99e4677	SPARC: Combine the 64 and 32 bit process initialization code. Alignment is done as it was for 32 bit processes. --HG-- extra : convert_revision : 9368ad40dcc7911f8fc7ec1468c6a28aa92d196f	2007-11-29 00:00:02 -08:00
Ali Saidi	a84d9716d6	merge, no manual changes --HG-- extra : convert_revision : 6d6b744bbdfb09e7c3092368870a4f372241f9e8	2007-11-29 00:23:14 -05:00
Rick Strong	376c7285ee	Serialization: Fix serialization of file descriptors. Make sure open file descriptors are reopened and the file pointer is in the same place as when the checkpoint occured. Signed-off by: Ali Saidi --HG-- extra : convert_revision : d9d2cd388c9c02f60e1269d6845891c35f94fc47	2007-11-29 00:22:46 -05:00
Gabe Black	8a020d40d3	Make ports that aren't connected to anything fail more gracefully. --HG-- extra : convert_revision : 3803b28fb2fdfd729f01f1a44df2ae02ef83a2fc	2007-11-28 14:39:19 -08:00
Gabe Black	ab598eadbf	imported patch pagewalker.patch --HG-- extra : convert_revision : 8ddde313f2249e1346fa51372a156f0d2ddc3b8f	2007-11-21 00:04:15 -08:00
Gabe Black	ce26c3ccec	Get rid of a file that should have never been committed. --HG-- extra : convert_revision : c0e678ce0ce0301bb3afff8bef4fcab7aef3c6fe	2007-11-20 22:51:03 -08:00
Gabe Black	e35c4f2f08	Merge with head. --HG-- extra : convert_revision : c4215e516c6d82ad466db898ffeefa0233ca110e	2007-11-20 15:38:54 -08:00
Gabe Black	a12d5975cc	Simple CPU fix simple mistake in translateDataWriteAddr. --HG-- extra : convert_revision : 6a6a7d05f62d9d9868be0707e4dc186a5f7ecf7d	2007-11-20 15:37:56 -08:00
Ali Saidi	ac50694d1a	Serialization: Serialize SPARC PTEs last so their nameOut() calls don't interfere with other serialization in the TLB. --HG-- extra : convert_revision : 8a8478a200cd3c65b2ac98944d1278454811d38f	2007-11-19 22:47:08 -05:00
Ali Saidi	8026ecbb8e	Memory: Cache the physical memory start and size so we don't need a dynamic cast on every access. --HG-- extra : convert_revision : d6c3e93718991e7b68248242c80d8e6ac637ac51	2007-11-19 18:23:43 -05:00
Steve Reinhardt	785eb13190	Make EXTRAS work for relative directories. Also print a little feedback when processing EXTRAS. --HG-- extra : convert_revision : 9cb324b0d5bc60a3c98af6495f16415b529e4af2	2007-11-16 20:10:33 -08:00
Steve Reinhardt	7d83cf35e1	Tweak check for writable block fill. --HG-- extra : convert_revision : c04281bcfc4cd23c7613aeccb21dc74452bcc951	2007-11-16 20:10:33 -08:00
Steve Reinhardt	f03a62008a	Fix bug on exclusive response to ReadReq with pending WriteReq. --HG-- extra : convert_revision : 5429cd7ca84cf6348813a4607fa16f76aa5df7e0	2007-11-16 20:10:32 -08:00
Korey Sewell	5d23f86e98	add back in clobbered MIPS fix for g++ 4.2 --HG-- extra : convert_revision : 80ad1cc32c6e59925526abd274132e4f9e35f0c1	2007-11-17 00:02:56 -05:00
Korey Sewell	f2fea63c65	go back and fix up MIPS copyright headers --HG-- extra : convert_revision : 886e762e13b7a05d6d8a14bde6c2a3567c32a4d1	2007-11-16 21:32:22 -05:00
Korey Sewell	52e6aa6284	move initCPU, processInterrupts declaration to core_specific file. --HG-- extra : convert_revision : 9bc88380f05f86c68117280f555c77eb4c627d7b	2007-11-16 21:31:37 -05:00
Korey Sewell	92724490c9	Gabe's 32-bit X86 fix merge --HG-- extra : convert_revision : 6f79c5c785c93d6caef2ec26961b652cd51e30fe	2007-11-16 19:16:01 -05:00
Gabe Black	7ffd88a54b	X86: Fix 32 bit compilation. --HG-- extra : convert_revision : d16d68731a8480080ec6b8da3ebda8567e115a30	2007-11-16 14:18:47 -08:00
Korey Sewell	923c385b97	remove unnecessary namespace --HG-- extra : convert_revision : 8936fe2246ca659a6dfe0835f66aa8232ed427de	2007-11-15 20:52:59 -05:00
Korey Sewell	d09ab2bd22	add thread id to misc. reg functions --HG-- extra : convert_revision : 35d073d1279947d943a0290832e09a5268dd0b76	2007-11-15 20:35:49 -05:00
Korey Sewell	7c076479e4	add MicroPC functions back to thread context --HG-- extra : convert_revision : a9cfd2829c4aec191f5f9ec6ce7b5d1dccc92af1	2007-11-15 20:35:31 -05:00
Korey Sewell	cf9dc4b151	add microPC stuff back in. got deleted on changeset propragation somehow. --HG-- extra : convert_revision : 5e89484b2ef21457ffba35ef959df999a28c5676	2007-11-15 19:48:53 -05:00
Korey Sewell	8f8e7fe08e	put the flattenIndex stuff back in O3 AND put fatal() back in faults --HG-- extra : convert_revision : 16fb8d7f3fbc5f8f1fc3ed34427c3d90a3125ad0	2007-11-15 16:38:09 -05:00
Korey Sewell	3110b157e6	fix MIPS headers --HG-- extra : convert_revision : 2870a146a1be0e8c80878090f39c0eaa15d2eb13	2007-11-15 14:21:01 -05:00
Korey Sewell	641ee83e40	add core specific parameter to BaseCPU params --HG-- extra : convert_revision : 15c5995e3acf23a45c712891fd06ef273584f7e8	2007-11-15 14:18:56 -05:00
Korey Sewell	7ba65aecaa	Add CoreSpecific type to all archs --HG-- extra : convert_revision : 659786bf6489ab6151e47fbf1f4c0a723262fce2	2007-11-15 14:17:21 -05:00
Korey Sewell	789153dff6	Get MIPS simple regression working. Take out unecessary functions "setShadowSet", "CacheOp" --HG-- extra : convert_revision : a9ae8a7e62c27c2db16fd3cfa7a7f0bf5f0bf8ea	2007-11-15 03:10:41 -05:00
Korey Sewell	375ddf8d25	branch merge --HG-- extra : convert_revision : 1c56f3c6f2c50d642d2de5ddde83a55234455cec	2007-11-15 00:14:20 -05:00
Ali Saidi	7c8e4ca3a3	Checkpointing: Name SE page table entries better so that there isn't a problem if multiple workloads are being run at once. --HG-- extra : convert_revision : 3bac9bd7fd93fcadf764e2991c5b029f2c745c08	2007-11-14 23:42:08 -05:00
Korey Sewell	2820a448e2	comment and spacing --HG-- extra : convert_revision : b3acde37bc11919700c257eae58ea9e0f66c9786	2007-11-14 15:33:43 -05:00
Korey Sewell	5f7879a935	Get MIPS_SE actually working again by actually by fixing TLB stuff and running hello world --HG-- extra : convert_revision : 0944e7661934baddca1f1a895af0b75be2d96b10	2007-11-14 06:24:47 -05:00
Korey Sewell	bfdd2f379b	remove unnecessary debug messages I added --HG-- extra : convert_revision : 5c23218fd1b899fa7fe42701f7cb2f6033f7a583	2007-11-14 06:18:58 -05:00
Korey Sewell	2692590049	Add in files from merge-bare-iron, get them compiling in FS and SE mode --HG-- extra : convert_revision : d4e19afda897bc3797868b40469ce2ec7ec7d251	2007-11-13 16:58:16 -05:00
Gabe Black	5772e3cada	X86: Make microcode use presegmentation RIPs and the rest of m5 use post segmentation RIPS. --HG-- extra : convert_revision : d8cda7c8b9a2afb8a9d601b6d61529a96c5f87fe	2007-11-13 01:31:43 -08:00
Gabe Black	1048b548fa	X86: Separate out the page table walker into it's own cc and hh. --HG-- extra : convert_revision : cbc3af01ca3dc911a59224a574007c5c0bcf6042	2007-11-12 18:06:57 -08:00
Gabe Black	6095dceb0c	Params: Fix check for cycles in the configuration and clarify the comments/error message. --HG-- extra : convert_revision : 8f35dde408fae874bcba1a248d32a22222d98c35	2007-11-12 18:06:02 -08:00
Gabe Black	917ae9ec66	X86: Fix a stupid typo where WRMSR and RDMSR were switched, and add a debug statement. --HG-- extra : convert_revision : f1eb17291f4c01f3c0fa8f99650bc1edf09d21de	2007-11-12 14:39:14 -08:00
Gabe Black	4950798268	X86: Implement tlb invalidation and make it happen some of the times it should. --HG-- extra : convert_revision : 376516d33cd539fa526c834ef2b2c33069af3040	2007-11-12 14:39:07 -08:00
Gabe Black	f1f5dd79bf	X86: Implement the wrcr microop which writes a control register, and some control register work. --HG-- extra : convert_revision : 3e9daef9cdd0665c033420e5b4f981649e9908ab	2007-11-12 14:38:59 -08:00
Gabe Black	4d4d2883f9	X86: Implement some bit testing instructions. --HG-- extra : convert_revision : 54585e276e44322be9c56af0b2eabfe8d4b3e430	2007-11-12 14:38:53 -08:00
Gabe Black	f9ddb894dd	X86: Change the meaning of the sext and zext width operand, and make sext set zext if the sign bit is 0. --HG-- extra : convert_revision : 08bd7b4ff183038c016612d04ac73b20a255d141	2007-11-12 14:38:45 -08:00
Gabe Black	6d4ba8de34	X86: Flesh out the opcode groups for two byte opcodes. --HG-- extra : convert_revision : 4d51befd6dae4035c0eb685d33e1f5e38467c766	2007-11-12 14:38:38 -08:00
Gabe Black	fce45baf17	X86: Work on the page table walker, TLB, and related faults. --HG-- extra : convert_revision : 9edde958b7e571c07072785f18f9109f73b8059f	2007-11-12 14:38:31 -08:00
Gabe Black	f17f3d20be	X86: Implement a page table walker. --HG-- extra : convert_revision : 36bab5750100318faa9ba7178dc2e38590053aec	2007-11-12 14:38:24 -08:00
Gabe Black	7a39457d7f	X86: Make the micropc available through the thread context objects. This is necssary for fault handlers that branch to non-zero micro PCs. --HG-- extra : convert_revision : c1cb4863d779a9f4a508d0b450e64fb7a985f264	2007-11-12 14:38:17 -08:00
Gabe Black	53cb6cbcc1	X86: Implement the startupCPU function. --HG-- extra : convert_revision : d2331a0e0bd14863e82004508558f657c5b900a2	2007-11-12 14:38:10 -08:00
Gabe Black	d89d80a5d0	X86: Make some of the bits of CR0 do what they're supposed to. --HG-- extra : convert_revision : 13e79ef1ef09bd842d5e075e31f98ab2a4357901	2007-11-12 14:38:02 -08:00
Gabe Black	aaa30714b3	X86: Various fixes to indexing segmentation related registers --HG-- extra : convert_revision : 3d45da3a3fb38327582cfdfb72cfc4ce1b1d31af	2007-11-12 14:37:54 -08:00
Gabe Black	ada071db53	SPARC: Force %g1 to be zero on process startup even though it normally already should be. --HG-- extra : convert_revision : 9feb63109e8c955b49c7e96acad1ad7c29a4349f	2007-11-11 17:23:22 -08:00
Gabe Black	6cfe4176f5	Alpha: Fix a long standing bug where all code ran as PAL code in FS. --HG-- extra : convert_revision : 654a2376a601ddf91665ca627403518911b32532	2007-11-08 23:50:10 -08:00
Gabe Black	7c0076d5f3	Make non Apple compilation work again. Ali may have to refix this. --HG-- extra : convert_revision : 0f9455643eec14034314908ee26a6d693c54a864	2007-11-08 23:42:44 -08:00
Gabe Black	46505821ec	ISA parser: Make the isa parser generate MaxInstSrcRegs and MaxInstDestRegs. --HG-- extra : convert_revision : 8c35891945c6b4ebc320f0c88a7a0449f3c4b4d5	2007-11-08 18:51:50 -08:00
Ali Saidi	0673029689	Compiling: Fix for 64bit compile on Darwin/OSX 10.5. --HG-- extra : convert_revision : 1f23f7a3952f55cca8293fb43ae15db42005aeac	2007-11-08 16:11:09 -05:00
Ali Saidi	422ab8bec0	TimingSimpleCPU: Add some DPRINTFs when the cpu suspends and resumes. --HG-- extra : convert_revision : a305cf9dcaca5ed3b97499a5e24c511f4416125a	2007-11-08 10:46:41 -05:00
Ali Saidi	cf1c25dbcc	AtomicSimpleCPU: Refactor resume() code to have a cleaner control path. --HG-- extra : convert_revision : f27bb96850e7fb0252fb1f47c3d0860705c32884	2007-11-08 10:46:41 -05:00
Ali Saidi	f4222610ea	Python: Allow a range to be a python tuple/list. --HG-- extra : convert_revision : 81cf805055e2f4d62e56a02ac82a0b230251f40b	2007-11-08 10:46:41 -05:00
Ali Saidi	11b931df6a	Interrupts: Inline some code and remove duplication. --HG-- extra : convert_revision : 0631c601f281bdd2a12ff0d0ae94576780115c2a	2007-11-08 10:46:41 -05:00
Ali Saidi	e41197a3f8	CPU: Add function to explictly compare thread contexts after copying. --HG-- extra : convert_revision : 9b7af59a11202a91409aad7c427b7749cd1d2f12	2007-11-08 10:46:41 -05:00
Gabe Black	17e83e7f83	SPARC: Make 64 bit SPARC process initialization check checkpointRestored too. --HG-- extra : convert_revision : 8d48f705983f31db5947c6c4ae9f0df57f413d68	2007-11-07 15:03:49 -08:00
Gabe Black	19292d3f06	O3: Remove unneeded variable. --HG-- extra : convert_revision : 4624ccd3f08818f4632881d6aca6d1cc343bbdcf	2007-11-06 12:51:08 -08:00
Ali Saidi	d1fb5ad91e	TraceFlags: Fix off-by-one error with number of traceflags. --HG-- extra : convert_revision : 668299fc0a9083be858fe2f6e8fde512ddac9e32	2007-11-04 19:06:45 -05:00
Ali Saidi	c8123cef1b	Cache: Fix for OS X 10.5 compiling. --HG-- extra : convert_revision : ba3c33ed524367280eefc096177d767168ac2cf6	2007-11-04 18:57:36 -05:00
Ali Saidi	710f3ca3e1	SE: fix stat64 syscall on os x --HG-- extra : convert_revision : 40b62ef73d8e408cdd35b22147860f33533db57f	2007-11-02 02:11:15 -04:00
Ali Saidi	333ac6cc32	DRAM: Make latency parameters be Param.Latency instead of ints. --HG-- extra : convert_revision : 553b86cc4653da089d7aa0045a3f3bdcabf6c4d8	2007-11-01 17:30:50 -04:00
Steve Reinhardt	4b49bd47f4	String constant const-ness changes to placate g++ 4.2. Also some bug fixes in MIPS ISA uncovered by g++ warnings (Python string compares don't work in C++!). --HG-- extra : convert_revision : b347cc0108f23890e9b73b3ee96059f0cea96cf6	2007-10-31 18:04:22 -07:00
Ali Saidi	71b033f4dc	no manual changes --HG-- extra : convert_revision : bfc34f3adaabcc8011bf9b22bd614ee8ebcbfd01	2007-10-31 17:53:13 -04:00
Ali Saidi	980266b0a6	Traceflags: Old traceflags.py file is no longer needed. --HG-- extra : convert_revision : 1e88c2d9a0e2a64344d8b4d1a4474dae82473a6d	2007-10-31 17:52:56 -04:00
Steve Reinhardt	90f42bf3ad	Merge in bus DPRINTF changes. --HG-- extra : convert_revision : 3bbd7c0745b31bb2a628b604ab1627cd9c61643c	2007-10-31 00:39:16 -07:00
Ali Saidi	538fae951b	Traceflags: Add SCons function to created a traceflag instead of having one file with them all. --HG-- extra : convert_revision : 427f6bd8f050861ace3bc0d354a1afa5fc8319e6	2007-10-31 01:21:54 -04:00
Ali Saidi	8ce31ea471	Linux Support: Finally update vptr for new memory system. --HG-- extra : convert_revision : 8b4927431189abc12201d13428a31b746cdb7dee	2007-10-31 01:21:54 -04:00
Ali Saidi	7597f87430	Base: Rework the way M5 provides and creates random numbers. --HG-- extra : convert_revision : 10ec3484647b3acb8e821f8520f97d535e41e861	2007-10-31 01:21:54 -04:00
Vilas Sridharan	04d1cfe31c	Add constant stat. Signed Off: Ali Saidi <saidi@eecs.umich.edu> --HG-- extra : convert_revision : 3da9e507117d0279e212d151d78c312fd9cf0b5c	2007-10-30 22:21:05 -04:00
Gabe Black	503fb8ebed	X86: Compile fixes for 32 bit/debug/opt. --HG-- extra : convert_revision : 591fffb316830fca5792666c8df12abd4e7c551b	2007-10-30 16:34:00 -04:00
Gabe Black	fddfa71658	TLB: Fix serialization issues with the tlb entries and make the page table store the process, not the system. --HG-- extra : convert_revision : 2421af11f62f60fb48faeee6bddadac2987df0e8	2007-10-25 19:04:44 -07:00
Ali Saidi	0711f4f17a	SE: Fix page table and system serialization, don't reinit process if this is a checkpoint restore. --HG-- extra : convert_revision : 03dcf3c088e57b7abab60efe700d947117888306	2007-10-25 20:13:35 -04:00
Gabe Black	b0e3aab5df	X86: Fix X86_FS compilation. --HG-- extra : convert_revision : 5f014337e33a9e1ebe4df4063335315539fff69e	2007-10-23 17:40:40 -07:00
Gabe Black	7d396b1bf6	X86: Use the cda microop where appropriate. The ENTER instruction still needs these. --HG-- extra : convert_revision : c5a1a6d66c454f252d3b798c38a6798e7dd486f0	2007-10-22 14:39:40 -07:00
Gabe Black	421aea980f	X86: Implement the cda microop which checks if an address is legal to write to. --HG-- extra : convert_revision : afe20649180dd59ad0702b98f7293be6c9226359	2007-10-22 14:30:56 -07:00
Gabe Black	93da9eb7f6	CPU: Add functions to the "ExecContext"s that translate a given address. --HG-- extra : convert_revision : 7d898c6b6b13094fd05326eaa0b095a3ab132397	2007-10-22 14:30:45 -07:00
Gabe Black	43cb78004b	X86: Start using the stupd microop, and update statistics accordingly. --HG-- extra : convert_revision : 4aa9daa4e19acfb3e6840ce5d83cf199e30c2f19	2007-10-21 18:45:46 -07:00
Gabe Black	4d15e4cf7b	X86: Implement the stupd microop ("store with update", not "stupid") and use it in ENTER. --HG-- extra : convert_revision : 9151f701162d31ef26298497467c42b7b0ed85d5	2007-10-21 18:44:50 -07:00
Gabe Black	d8494325f0	X86: Implement the PUSHF, POPF, SAHF, and LAHF instructions. --HG-- extra : convert_revision : 37c63b1133022fa3432888592f8c84785fb95091	2007-10-19 15:21:16 -07:00
Gabe Black	35a8bc56cd	X86: Impelement the HLT instruction and fix the "halt" microop. --HG-- extra : convert_revision : 932e5bb5bf3644f8468dba92177fb87cc54b891a	2007-10-19 15:11:15 -07:00
Gabe Black	f69a463b4b	X86: Implement a "halt" microop. --HG-- extra : convert_revision : 53a846a157e4dce42343b81901df1207738f62cd	2007-10-19 15:10:23 -07:00
Gabe Black	7f37322532	X86: Implement the ENTER instruction. This could probably be optimized by cleaning up the indexing in the main loop. --HG-- extra : convert_revision : ad2d560f2a6f36176b22b8510c58cd6fe5a2c9c2	2007-10-19 15:09:37 -07:00
Gabe Black	63f4281d9d	Merge with head. --HG-- extra : convert_revision : 7a1c612e7f64fc6b35749547d744e919e034e66f	2007-10-18 22:44:33 -07:00
Gabe Black	9243666c39	X86: Replace "group10" placeholder with the corresponding instructions in the decoder. --HG-- extra : convert_revision : ffa8f7c4f8d1e381eefd29247ebd705863d385ad	2007-10-18 22:43:32 -07:00
Gabe Black	5c32422162	X86: Implement the string IO instructions, ins and outs. --HG-- extra : convert_revision : b021e70390d289b22a8e693cd8a99d6e7bd7d2b4	2007-10-18 22:42:53 -07:00
Gabe Black	f0dce3bfce	X86: Implement the undocumented SALC instruction which sets AL to 0xFF if CF=1 and 0x00 otherwise. --HG-- extra : convert_revision : 845d43c544e296d7595f54054906055a9f21ad9f	2007-10-18 22:42:17 -07:00
Gabe Black	46bd1c99a9	X86: Implement the XLAT instruction. --HG-- extra : convert_revision : 22d7d9e79e722293b4dc1e66d8610301dc04c5fa	2007-10-18 22:41:18 -07:00
Gabe Black	c526b00b35	X86: Implement the BOUND instruction. --HG-- extra : convert_revision : 7bcfa5b4a47d342bee267cc593a1bd4b4f31abe0	2007-10-18 22:40:48 -07:00
Gabe Black	33dbd8a766	X86: Make the "fault" microop predicated. --HG-- extra : convert_revision : 48dae1f3c680636833c137fe6b95b37ae84e188c	2007-10-18 22:40:18 -07:00
Gabe Black	70542c8e61	X86: Make "Inst" the default format instead of WarnUnimpl for one byte opcodes. --HG-- extra : convert_revision : 591e67fc21f5b72977c5876e39f488494fda77c2	2007-10-18 22:39:39 -07:00
Gabe Black	dc2e887f23	X86: Implement the in/out instructions. These will still need support from the TLB and memory system. --HG-- extra : convert_revision : a9503248ea9efca7e5247e4f2830967f428b8215	2007-10-18 22:39:00 -07:00
Gabe Black	2bbc058c6c	X86: Implement the LOOP instructions. --HG-- extra : convert_revision : 3ccd0565c83b6d9c9b63f9f7ac2b67839a2c714f	2007-10-18 22:38:17 -07:00
Gabe Black	418b30602b	X86: Attach the CMC instruction to the decoder. --HG-- extra : convert_revision : 909661062017c7640c343e80431eaf365e8fcf53	2007-10-18 22:37:44 -07:00
Gabe Black	674b6436b0	X86: Implemented the jrcx instruction. --HG-- extra : convert_revision : d738015ff33449e55d8f1624c8467c1bba193e16	2007-10-18 22:37:08 -07:00
Gabe Black	0ffb317ff9	X86: Make wrip sign extend its second operand. --HG-- extra : convert_revision : 2531af8b442ea5aaefccd7a7999c7720489edc36	2007-10-18 22:36:36 -07:00
Ali Saidi	8351660273	CPU: Use the ThreadContext cpu id instead of the params cpu id in all cases. --HG-- extra : convert_revision : 6d025764682181b1f67df3b1d8d1d59099136df7	2007-10-18 13:15:08 -04:00
Gabe Black	54466a31c3	Make the process objects use the Params structs in their constructors, and use a limit to check if access are on the stack. --HG-- extra : convert_revision : af40a7acf424c4c4f62d0d76db1001a714ae0474	2007-10-16 18:04:01 -07:00
Gabe Black	9660a0a552	Merge with head --HG-- extra : convert_revision : 490f9909469751a6cdaf6669e4cd4589ce3a4093	2007-10-12 20:10:57 -07:00
Gabe Black	ac27bc7878	Loader: Identify sections based on virtual addresses, and set the LoadAddrMask correctly for x86. --HG-- extra : convert_revision : efa6cf42f7e69074c645dfcac335a3edf0941389	2007-10-12 20:10:10 -07:00
Gabe Black	0d6383b69e	X86: Added some new versions of MOV and a new argument type tag. --HG-- extra : convert_revision : e21b2062d68baa983c7c631b3e1fe3149de56427	2007-10-12 20:08:12 -07:00
Gabe Black	d82d3bbda5	X86: Implemented LODS. --HG-- extra : convert_revision : 4bd8f15bbc25f5dce16ea0504ad6dd21805fa56a	2007-10-12 20:07:28 -07:00
Gabe Black	9498e536c0	X86: Implement MSR reads and writes and the wrsmr and rdmsr instructions. There are no priviledge checks, so these instructions will all work in all modes. --HG-- extra : convert_revision : ff893eb569313d8aecbfffb47bcbd1c2d65cd393	2007-10-12 16:37:55 -07:00
Gabe Black	a76f734d0b	X86: Get rid of BasicOperate format which wasn't used and referred to SparcStaticInst --HG-- extra : convert_revision : 5d2eac9a4b3f0fe5e3c3554d91acf8fee368c9dc	2007-10-09 17:21:04 -07:00
Gabe Black	8ecea59092	X86: Get rid of stray Sparc DPRINTF --HG-- extra : convert_revision : d98b2d95448cab4e689d01ceedaa6ad46f9ffc09	2007-10-09 17:20:23 -07:00
Gabe Black	f6e5b92d63	ELF Loader: Use physical addresses instead of virtual ones. This works in SE mode because the virtual and physical addresses specified for segments are the same. In Alpha, the LoadAddrMask is still necessary because the virtual and physical addresses are the same and apparently rely on the super page mechanism. All of the regressions pass. --HG-- extra : convert_revision : 45e49dec5002d64e541bc466c61a0f304af29ea5	2007-10-09 13:12:04 -07:00
Gabe Black	8858b0b667	X86: Make x86 initialize more state. --HG-- extra : convert_revision : a55866efd339ae795da4072c070918bf419b07fa	2007-10-07 18:20:51 -07:00
Gabe Black	a19c212757	X86: Work on the x86 tlb. --HG-- extra : convert_revision : a08a5cb049a6030ba9fd56a89383d56026238dbf	2007-10-07 18:18:39 -07:00
Gabe Black	cd36c69a4d	X86: Make faults maintain an error code which gets pushed on the stack. --HG-- extra : convert_revision : 7576f8cfaec9ddfb65e6ba7a6f64a5f453a42069	2007-10-07 18:17:52 -07:00
Gabe Black	efbff349a9	X86: Significantly filled out misc regs. --HG-- extra : convert_revision : 4c53be6568134d65e57f5411df986fd9a89e82c9	2007-10-07 18:16:00 -07:00
Gabe Black	999328f5ad	X86: Make sure there are fewer spurious differences between instructions for caching purposes. --HG-- extra : convert_revision : 7e6be1c42f28f92d9e8b47169e683827bb3f4aaf	2007-10-07 18:14:48 -07:00
Gabe Black	d53552355b	BitUnion: Fix some types in the bitunion classes. --HG-- extra : convert_revision : 1c003f9fc9ef3a57c9199d692d172e747581f383	2007-10-07 18:12:10 -07:00
Gabe Black	63a6d7376b	X86: Make initCPU and startupCPU do something basic. --HG-- extra : convert_revision : 1a04f4402f4f31e4e5cd482c7983d853fe117df5	2007-10-07 18:10:42 -07:00
Gabe Black	304e4c932a	X86: Make the Interrupts class complain less. --HG-- extra : convert_revision : 81d9544e85c90139704ffe4a117983df4bfa3bcd	2007-10-07 18:08:17 -07:00
Gabe Black	847a18ad48	X86: Adjust the config scripts for x86 fs. --HG-- extra : convert_revision : 36ed22b50066f54be0e51c3419babc07dd218e10	2007-10-07 17:52:36 -07:00
Gabe Black	e540c37282	X86: Make an x86 system object. --HG-- extra : convert_revision : 590a4c29cb9b943a2d8c3a97c5fdfbabb658ac45	2007-10-07 17:48:36 -07:00
Gabe Black	8fe672551e	X86: Make an x86 platform object. --HG-- extra : convert_revision : 7d64d3e78960f3bb937579f5d10937bed5f197be	2007-10-07 17:48:06 -07:00
Gabe Black	22196f8885	X86: X86 FS compile fix. --HG-- extra : convert_revision : bedd4cbab570d4ae84af9e8ead8f61db5c3c01dc	2007-10-07 17:46:56 -07:00
Gabe Black	bd5a88ba43	Merge with head. --HG-- extra : convert_revision : aa1969b60044f8ed88e689bdd25eeded2b1105ec	2007-10-04 12:35:35 -07:00
Gabe Black	e1516aefbb	X86: Fix the PageShift constant in isa_traits.hh (I thought I alread did this?) --HG-- extra : convert_revision : bdc51a66e4fdf4b0a51b5c774ca7372a00a57269	2007-10-04 12:34:29 -07:00
Gabe Black	2848ef6696	SPARC: Make software trap 3 flush the register windows like the ABI specifies. --HG-- extra : convert_revision : 8ff43617b56dcca5783d6cc490f87140fc20a36d	2007-10-04 12:24:16 -07:00
Gabe Black	50e2d20cb8	Merge with head. --HG-- extra : convert_revision : 1aa0e4569a7c10e6a395c2c951ac29275b5bcf59	2007-10-02 23:03:38 -07:00
Gabe Black	c2d60abf52	X86: Distinguish between the rep and repe prefixes. STOS and MOVS only accept the rep prefix which always loops until rcx becomes 0. The other string instructions accept repe (same encoding as rep) and repne which also check the condition code flags each iteration. --HG-- extra : convert_revision : 544149f640302070810fb53e53bfeb0e87160ffc	2007-10-02 23:02:18 -07:00
Gabe Black	504f90f763	X86: Start implementing the x86 tlb which will handle segmentation permission and limit checks and paging. --HG-- extra : convert_revision : 6072f7d9eecbaa066d39d6da7f0180ea4a2615af	2007-10-02 23:00:37 -07:00
Gabe Black	f4a932a6b3	X86: Fix places where movfp was used incorrectly. --HG-- extra : convert_revision : a6b5688eaa53d2f6675df1be193726641e558d37	2007-10-02 22:58:48 -07:00
Gabe Black	06d2d54b57	X86: Fix the movfp microop. --HG-- extra : convert_revision : 23829782a2802a97a05e4dfdb5dd38fbe4165a90	2007-10-02 22:58:04 -07:00
Gabe Black	3e644b48bb	X86: Fix x87 floating point stack register indexing. --HG-- extra : convert_revision : b515ec20cbfc50b38aa7da6cf4d465acf9054c08	2007-10-02 22:57:33 -07:00
Gabe Black	a56c651980	Predecoder: Clear out predecoder state on an ITLB fault. --HG-- extra : convert_revision : 68f8ff778dbd28ade5070edf5a7d662e7bf0045a	2007-10-02 22:21:38 -07:00
Gabe Black	4049c9f76a	X86: Put ldst into the microcode (the earlier changeset didn't really). Also clean things up as much as possible so that faulting won't break an instruction. More microops which verify addresses are needed. --HG-- extra : convert_revision : 7c6050cb4798d287fe7d3cc4bb8c20dfa40ad2be	2007-10-02 22:19:53 -07:00
Gabe Black	7c521db9de	X86: Implement the ldst microop and put it in existing microcode where appropriate. --HG-- extra : convert_revision : f08bd725d07a501bb7a0ce91590b5d37db99c6f3	2007-10-02 22:08:09 -07:00
Gabe Black	683d6d46f6	X86: Fix up the microcode for the FST and FSTP instructions. --HG-- extra : convert_revision : ad68633e9b7eab425593acb20cf242bf98c2b642	2007-10-02 22:06:59 -07:00
Gabe Black	b831f7409b	X86: Get rid of a hack for ruflag which is no longer necessary. --HG-- extra : convert_revision : 1bb60c9ddb483aead2af0201bbda938cc6d3f7cb	2007-10-02 22:05:50 -07:00
Gabe Black	efb309525a	X86: Allow logic instructions to set ECF as well as CF. --HG-- extra : convert_revision : 6ac20f069c86c23a8d443a7127afd6015166c00d	2007-10-02 22:05:10 -07:00
Gabe Black	65c247f21f	X86: Add classes for the actual x86 faults. --HG-- extra : convert_revision : bc060a01b5415551b335ca68ccbf126333ae20b0	2007-10-02 22:04:20 -07:00
Gabe Black	7d78f1b41c	X86: Hook in another version of the XCHG instruction. --HG-- extra : convert_revision : 7b6f9cd2f59443622f6963dfee454175322c0ef5	2007-10-02 22:03:38 -07:00
Gabe Black	66a08f7ba4	X86: Implement MOVS --HG-- extra : convert_revision : 29147e1b86f7c54ce9b5ff68001725802c665fc0	2007-10-02 22:02:58 -07:00
Gabe Black	fea7165b55	X86: Implement STOS. --HG-- extra : convert_revision : 95f3bf185f07fe644d6ab96bbb6e598e406b92f4	2007-10-02 22:02:30 -07:00
Gabe Black	7571e8346d	CPU: Make the cpuid parameter get set in SE mode as well. --HG-- extra : convert_revision : bc47206acb683ebaaa31f57af79b4b8db64e4d31	2007-10-02 18:33:57 -07:00
Gabe Black	8ca7feb726	Remote GDB: Turn on remote gdb in SE mode. --HG-- extra : convert_revision : e17eb629071edd0dbcb09dd6a6a2220d2c83d33f	2007-10-02 18:26:27 -07:00
Gabe Black	988cdb49f2	CPU: Make the cpus check the pc event queues in SE mode. --HG-- extra : convert_revision : 9dc4ea136c3c3f87a73d55e91bc4aae4eba70464	2007-10-02 18:25:37 -07:00
Gabe Black	48041fdc53	SPARC,Remote GDB: Flesh out the acc function for SE mode. --HG-- extra : convert_revision : eada066ab64701b5c53e7351dfffbdc0e0d4f344	2007-10-02 18:25:10 -07:00
Gabe Black	1c83418b14	SPARC,Remote GDB: Fix an accounting bug in the remote gdb stuff. --HG-- extra : convert_revision : f6f0986211c442ac94da315e344a8f54d4d58c8a	2007-10-02 18:24:24 -07:00
Gabe Black	5db7125317	Remote GDB: Get rid of an unwanted delete in SE. --HG-- extra : convert_revision : 7531ba87893a8ebff3863adb846b382d07a1d18d	2007-10-02 18:23:11 -07:00
Gabe Black	3eeda8008d	CPU: Make sure the system parameter gets set in the cpu builders. Other parameters need to be fixed as well. --HG-- extra : convert_revision : 0401970a79855ee0a96eb29305346ce07b5c98ea	2007-10-02 18:22:36 -07:00
Ali Saidi	0acf891c32	CPU: fix sparc_fs booting with SimpleTimingCPU. --HG-- extra : convert_revision : 3d95f6daa7f0e8e376d1a880f64c056619263885	2007-10-01 02:55:27 -04:00
Ali Saidi	d2a4f595d6	Update stats for quiesced cycles --HG-- extra : convert_revision : 703ba58f156c9f2677b020f05d36bc1e3ae0b9e5	2007-09-28 13:22:14 -04:00
Ali Saidi	d325f49b70	Rename cycles() function to ticks() --HG-- extra : convert_revision : 790eddb793d4f5ba35813d001037bd8601bd76a5	2007-09-28 13:21:52 -04:00
Ali Saidi	887cd6a273	Update statistics to use cycles properly instead of ticks --HG-- extra : convert_revision : 62911280b631ef24720f9ce701d1c19a9b8a9784	2007-09-28 13:21:30 -04:00
Gabe Black	58c448ced5	Condition Codes: Fix the findParity function. --HG-- extra : convert_revision : 37520ed12f55f6b8d9daedca9947eaa2eb8d7cc7	2007-09-25 20:26:10 -07:00
Gabe Black	2dd65dc254	Merge with head. --HG-- extra : convert_revision : f331b9cbd82086d63d4f35e18f9e08466c016225	2007-09-25 20:11:41 -07:00
Gabe Black	25a9b6ea5e	SPARC: Remove parameter that was only ever set to one value. --HG-- extra : convert_revision : 3c22e576d95bdc7566bbce9b92cf2a6ff153a66f	2007-09-25 20:11:03 -07:00
Gabe Black	e735001d54	SPARC: Remove some redundant code from some of the fp instructions. --HG-- extra : convert_revision : 68b0341ae7a367b84c44081f9a3d6d0bc6631649	2007-09-25 20:10:04 -07:00
Gabe Black	306b5c6b5b	SPARC: Clean up of privileged instructions. --HG-- extra : convert_revision : 1fb055a7d186a3e9dff46f1c1b46bad6bcd00562	2007-09-25 20:09:25 -07:00
Gabe Black	b896ad584b	SPARC: Long overdue cleanup of the condition code handlers. --HG-- extra : convert_revision : ddc53a622a8f908fa48788f3b570f33fcfc25fff	2007-09-25 20:08:34 -07:00
Gabe Black	25b4874664	Condition Codes: Fix type error. --HG-- extra : convert_revision : 99f6c232cc421c6f741a8a11c029285e599eb183	2007-09-25 20:07:06 -07:00
Gabe Black	8d53fea210	SPARC: Clean up the branch instructions a bit. --HG-- extra : convert_revision : 93d5cc68e4a327ee0492eeed7f3b56e98d2d83bb	2007-09-25 20:05:11 -07:00
Gabe Black	9ef0f6a7f1	Loader: Load all segments of an elf, rather than just the "text" and "data". --HG-- extra : convert_revision : b28bb9ac5cde72878e948d64f629de6e4b42c2e8	2007-09-25 20:03:51 -07:00
Gabe Black	85d46ce470	Loader: Only complain about TLS sections if you're using Alpha. --HG-- extra : convert_revision : 125d19ad3fa1847752e455fa248ca3b2a55a2067	2007-09-25 20:02:30 -07:00
Gabe Black	032a30f345	SPARC: Fix a stupid mistake which was breaking the SPARC regressions. --HG-- extra : convert_revision : 34a11df0d467ea249211dd3aba86bc8d2aea45de	2007-09-25 20:00:46 -07:00
Gabe Black	b3c6f32543	X86: Fix for uninitialized variables in stacktrace code. --HG-- extra : convert_revision : d19a03d8c14eb93a99f2c1838a9caa1286804c81	2007-09-25 14:44:12 -07:00
Gabe Black	418ddf43e6	X86: Get X86_FS to compile. --HG-- extra : convert_revision : fb973bcf13648876d5691231845dd47a2be50f01	2007-09-24 17:39:56 -07:00
Gabe Black	dd277e0d8f	SPARC: Fix linking error from new flattenFloatIndex function. --HG-- extra : convert_revision : 5260f33336e3a9d5e3592b784458e243157f17e3	2007-09-19 19:08:42 -07:00
Gabe Black	3cd95a2748	X86: Implement the fld, fst, and fstp instructions. --HG-- extra : convert_revision : 7dd274bdc3c34839c17d9012a745d7c95dfcfdd8	2007-09-19 18:28:34 -07:00
Gabe Black	a75b6f5106	X86: Move the fp microops to their own file with their own base classes in C++ and python. --HG-- extra : convert_revision : 9cd223f2005adb36fea2bb56fa39793a58ec958c	2007-09-19 18:27:55 -07:00
Gabe Black	f3f3747431	X86: Put in the foundation for x87 stack based fp registers. --HG-- extra : convert_revision : 940f92efd4a9dc59106e991cc6d9836861ab69de	2007-09-19 18:26:42 -07:00
Gabe Black	a54ae9f92b	X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode. --HG-- rename : src/arch/x86/isa/insts/sse/__init__.py => src/arch/x86/isa/insts/simd128/__init__.py extra : convert_revision : efb4405aebaa4a04f33572e7d078ceca45872d9c	2007-09-19 18:25:17 -07:00
Gabe Black	a1912df360	X86: Enable the rename system call. --HG-- extra : convert_revision : bc4a3b5b5ce8e17f632e65ce89df91e2b50e1274	2007-09-19 18:24:11 -07:00
Gabe Black	bdc0261eb5	X86: Enable the unlink system call. --HG-- extra : convert_revision : 4230a13fdb652a87271f8d2ac9ead96cd2af07a5	2007-09-19 18:23:35 -07:00
Steve Reinhardt	76c4c5fabc	mem: clean up bus/cache DPRINTFs a bit Not so much noise on failed sends, and more complete info when grepping a trace using an address. --HG-- extra : convert_revision : 05a8261c9452072ca08b906200c6322b33e2b9f1	2007-09-16 16:46:38 -07:00
Gabe Black	4a4aa59632	Merge with head. --HG-- extra : convert_revision : 22aafb1cead3f584e64c188dc8eb45e271f4e7e9	2007-09-13 16:36:25 -07:00
Gabe Black	bbc8a40857	X86: Fix how ECF is computed in genFlags, and get rid of some duplicate code. --HG-- extra : convert_revision : f86330a5a9fea782ee63aaa18ca964fb6f9cef0b	2007-09-13 16:35:41 -07:00
Gabe Black	534c6a800a	X86: Make the shift and rotate instructions set the carry flag(s) and overflow flags like they're supposed to. --HG-- extra : convert_revision : c0523a5bbf53375ce979ca7d98a95e465be66fbe	2007-09-13 16:35:20 -07:00
Gabe Black	f7b6230d99	X86: Total overhaul of the division instructions and microops. --HG-- extra : convert_revision : 303ea45f69f7805361ad877fe6bb43fbc3dfd7a6	2007-09-13 16:34:46 -07:00
Ali Saidi	e282d9601c	Syscall Emulation: Add stat64 syscall. Patch submitted by: Jonas Diemer [diemer (a) ida.ing.tu-bs.de] --HG-- extra : convert_revision : 07638c05bb3f79aacce49457bbb8c17d0a3a7238	2007-09-13 12:30:12 -04:00
Ali Saidi	5f187e592e	Devices: More fixes to Intel NIC Model. --HG-- extra : convert_revision : 14306d3cd79bbef7decdf2fd370ed7e7f2b10a93	2007-09-12 15:24:23 -04:00
Ali Saidi	19fbdcd30b	Loader: Error if a TLS section is found in the binary. --HG-- extra : convert_revision : d763c0382f3cbcc9786510f5a8e521ec9d55eff1	2007-09-11 00:01:24 -04:00
Gabe Black	0f57b407a3	X86: Make the isa parser run if any of the microcode files change. --HG-- extra : convert_revision : 7f6d07de7e0d728a9333fb46c953dbe6cb04e600	2007-09-10 16:49:07 -07:00
Gabe Black	87408d5ad2	Fix for leaving EXTRAS blank Apparently env['EXTRAS'] will return an empty string if not set. split will then split it into an empty string, and normalize will turn "" into ".". --HG-- extra : convert_revision : f79efebb129fdd65161fcf4d4582c2a8541aeacd	2007-09-10 16:42:41 -07:00
Gabe Black	8f724a8b96	Normalize the path pathed in through EXTRAS so it won't break with a trailing slash. --HG-- extra : convert_revision : c14e2c6d97b5bcb491b91eeb4e7dc04d1cc35475	2007-09-10 12:48:06 -07:00
Gabe Black	22a57562cd	Remove redundant endian.hh and use byteswap.hh in its place. --HG-- extra : convert_revision : 5be1a5ba20d69d696d3974df147c2f219414c0b2	2007-09-10 11:02:50 -07:00
Gabe Black	8e7bca8b36	X86: Move a comment to be next to the code it describes. --HG-- extra : convert_revision : c384391175babb7cfdd3885ae9d9f1a9405ea44f	2007-09-10 11:01:52 -07:00
Gabe Black	3e65e1d0e0	Merge with head. --HG-- extra : convert_revision : 4fc5f595b23f72c0825d62f21efab46ed1db835b	2007-09-06 16:32:03 -07:00
Gabe Black	e4c0171356	X86: Rework the multiplication microops so that they work like they would in the patent. --HG-- extra : convert_revision : 6fcf5dee440288d8bf92f6c5c2f97ef019975536	2007-09-06 16:27:28 -07:00
Gabe Black	7f079149f1	X86: Make signed multiplication do something different from unsigned. --HG-- extra : convert_revision : 333c4a3464d708d4d8cea88931259ab96c2f75ed	2007-09-06 16:25:29 -07:00
Gabe Black	5052e2cb10	X86: Make signed versions of partial register values available to microops. --HG-- extra : convert_revision : c820d1250f505911a341ced42d4f73796ea77f87	2007-09-06 16:22:08 -07:00
Gabe Black	832ef7412b	X86: Correct how the hi portion of a product is computed. --HG-- extra : convert_revision : 1f503e1cae0374e62e6254e8073e903adc29d067	2007-09-06 16:20:12 -07:00
Gabe Black	389abade01	X86: Add a square root microop and the SSE sqrt instruction. --HG-- extra : convert_revision : ddc6e7e95111189d43f75bf84cd3d82433d982b3	2007-09-06 16:18:34 -07:00
Gabe Black	4478487c37	X86: Add SSE comparison instructions and microops and move some FP microops to be with the other ones. --HG-- extra : convert_revision : ee0b5acde08d12c51a5282efb58d1ac72e0779af	2007-09-06 16:09:28 -07:00
Ali Saidi	bf7c01d43d	Bus: Fix drain code; old method could return 1 in atomic mode and never call de->process(). --HG-- extra : convert_revision : 35990e5eaf93f7a95a0ec72e9f92034a042def3e	2007-09-05 17:12:41 -04:00
Gabe Black	57da059415	Merge with head. --HG-- extra : convert_revision : 19bea7995285eeb7e277d3064f427429ade2bcb8	2007-09-04 23:46:08 -07:00
Gabe Black	fea46ee6e3	X86: Implement an SSE xor microop and instruction. --HG-- extra : convert_revision : 949737d0f5d6fe4aa77cc4680d0c88caab3e8174	2007-09-04 23:44:37 -07:00
Gabe Black	6c689a3b4b	X86: Make the movfp microop use FloatRegBits instead of FloatRegs. This fixes a problem where interpreting arbitrary bits as floating point would change what the value was. These values are legitimate because the fp registers could be used to move around arbitrary data. --HG-- extra : convert_revision : f1d7159ba137702b5722cc7c1b64ed7dd06c21de	2007-09-04 23:42:55 -07:00
Gabe Black	26ba7cc3b2	X86: Add tracing to the floating point register file. --HG-- extra : convert_revision : f452d9179b929b980cf9e2d1e3de0431c51c5f4a	2007-09-04 23:40:47 -07:00
Gabe Black	26044dca33	X86/StateTrace: Make m5 and statetrace track mmx and xmm registers, and actually compare xmm. --HG-- extra : convert_revision : 02c6641200edb133c9bc11f1fdf3c1a0b1c87e77	2007-09-04 23:39:57 -07:00
Gabe Black	760240176a	X86: Hook in the fp arithmetic instructions. Stale python made it work before. --HG-- extra : convert_revision : af27f26ae810ebaae13faa572c5b4eb074620d91	2007-09-04 23:38:34 -07:00
Gabe Black	d2fc4ee625	X86: Implement some SSE fp microops and instructions. --HG-- extra : convert_revision : 7e0595ef542fbfb701bfac7e9ac4648349a92b26	2007-09-04 23:33:50 -07:00
Gabe Black	8e3b199cb8	X86: Add some SSE floating point/integer conversion microops. --HG-- extra : convert_revision : 2a1aa16709db940f5f40bbd84ca082f26b03b9c5	2007-09-04 23:32:18 -07:00
Gabe Black	af4c04c426	X86: Add floating point micro registers. --HG-- extra : convert_revision : 442a5f8b9216638e4e6898f89eacb8695719e20f	2007-09-04 23:31:40 -07:00
Gabe Black	310912cf2c	X86: Fix a typo in the microassembly for the cqo instruction. --HG-- extra : convert_revision : ddf739e591e4414ade37b806a88f3c11292627e2	2007-09-04 23:23:51 -07:00
Gabe Black	aaee21afdb	X86: Implement idiv and propogate the mul corner case fix. --HG-- extra : convert_revision : 348aa081067728afa14dc5b609fc7e26dbc5fad5	2007-09-04 23:23:13 -07:00
Gabe Black	b0b4038ee9	X86: Fix a corner case where mul would overwrite an original register value it still needed. --HG-- extra : convert_revision : 86ee0e2bf716d52c34ee731727d6366935f103ed	2007-09-04 23:22:08 -07:00
Gabe Black	e1e7605213	X86: Add in a file with floating point indexing which -should- have been in an earlier changeset. --HG-- extra : convert_revision : bf05f81df5e5b1de1ecd8ab7a6ef751922418987	2007-09-04 23:21:41 -07:00
Ali Saidi	276a382557	Serialization: Fix unserialization of object pointers --HG-- extra : convert_revision : a5aed880b2fc05841067e8597a58a9484e30b84a	2007-09-04 13:12:58 -04:00
Ali Saidi	021421d663	Config: Remove some ini file code that no longer works --HG-- extra : convert_revision : cb01dc0abeabc97b03d7af10959d92ceb62ea936	2007-09-04 13:12:58 -04:00
Gabe Black	9da070ce8a	X86: Major rework of how regop microops are generated. The new implementation uses metaclass, and gives a lot more precise control with a lot less verbosity. The flags/no flags reg/imm variants are all handled by the same python class now which supplies a constructor to the right C++ class based on context. --HG-- extra : convert_revision : 712e3ec6de7a5a038da083f79635fd7a687d56e5	2007-08-31 22:28:07 -07:00
Gabe Black	9277545ba6	Microassembler: Pass the actual mnemonic used to the macroop add_micro function --HG-- extra : convert_revision : acaee747ab30747d602c1f4ac5f0c2b2573a2a9b	2007-08-31 22:26:02 -07:00
Gabe Black	941675690c	X86: Get x86 to compile again after the simobject constructor change. --HG-- extra : convert_revision : 17a3e16e849bee88892223f0c993b19c15daa554	2007-08-31 13:02:58 -07:00
Miles Kaufmann	eddf6f1637	python: Write configuration file without reassigning sys.stdout. Using print >>ini_file syntax instead of reassigning sys.stdout allows the python debugger to be used. --HG-- extra : convert_revision : 63fc268f2e80f338ad1a7abe54b9e979e2239609	2007-08-30 15:16:59 -04:00
Miles Kaufmann	e4eea9ee04	Fix miscellaneous small typos. --HG-- extra : convert_revision : bfc0ac8e1c8a5d01d9fa5203184bbf99c8361da3	2007-08-30 15:16:59 -04:00
Miles Kaufmann	cd890576bb	devices: Avoid using assert() to catch misconfiguration --HG-- extra : convert_revision : 2c6710e01a4402793a2e0eafcc829df19d03dda3	2007-08-30 15:16:59 -04:00
Miles Kaufmann	54cc0053f0	params: Deprecate old-style constructors; update most SimObject constructors. SimObjects not yet updated: - Process and subclasses - BaseCPU and subclasses The SimObject(const std::string &name) constructor was removed. Subclasses that still rely on that behavior must call the parent initializer as : SimObject(makeParams(name)) --HG-- extra : convert_revision : d6faddde76e7c3361ebdbd0a7b372a40941c12ed	2007-08-30 15:16:59 -04:00
Miles Kaufmann	9cb49ab9e0	python: Eliminate the Python use of eval() and frame manipulation --HG-- extra : convert_revision : 04520bcfab510580a1c7fb341afbd2487287d1ab	2007-08-30 15:16:58 -04:00
Gabe Black	f67cd04673	X86: Fix the sra microop to get the sign bit from the right operand. --HG-- extra : convert_revision : 71e58dd6dd6918ee403f2e332c47e29acdace464	2007-08-29 20:39:41 -07:00
Gabe Black	c1a776de8a	X86: Implement the movaps instruction. --HG-- extra : convert_revision : 2aeb1c05205f8ea8f7484e8bacf3fbbc581defd2	2007-08-29 20:38:22 -07:00
Gabe Black	3da3190f07	X86: Implement the movsd instruction. --HG-- extra : convert_revision : a5a73e0ddd39144d2aeeb9cc6a299516752fd4c2	2007-08-29 20:37:44 -07:00
Gabe Black	f0b20ff970	X86: Implement the movlpd instruction. --HG-- extra : convert_revision : dddb20fe48c0ae9de7cd0ba1a1467ecb690056c1	2007-08-29 20:37:16 -07:00
Gabe Black	3b97b6e0e2	X86: Add an fp move microop. --HG-- extra : convert_revision : a9d6d3568cd2c6a65df91bf56ee1e43523f04630	2007-08-29 20:36:44 -07:00
Gabe Black	22830c0747	X86: Add load and store microops that use the fp registers. --HG-- extra : convert_revision : 153a055e888d8c47d59758a599dbd38f63008137	2007-08-29 20:36:12 -07:00
Gabe Black	34f3c9d196	X86: Add operands to handle floating point registers. --HG-- extra : convert_revision : 2e8289dbd3f5dda1221014d4ed0e9450f60de0cf	2007-08-29 20:35:30 -07:00
Gabe Black	bc3635a110	X86: Flesh out register indexing constants. --HG-- extra : convert_revision : 56eedc076bbb7962c3976599a15ed93c7cb154c0	2007-08-29 20:34:52 -07:00
Gabe Black	6204d00940	X86: Make the fp accessors not panic. --HG-- extra : convert_revision : c6d08863049a3f8755c53e1f49ce19ad6a2dedc7	2007-08-29 20:34:00 -07:00
Gabe Black	61b1c53a2a	X86: Make x86 syscall return just stuff the return value in eax. --HG-- extra : convert_revision : 800d8a2398d5750c03c642264577c9c772684266	2007-08-29 20:29:18 -07:00
Gabe Black	c593cfbdeb	X86: More two byte opcode decoding. I missed two groups in the last changeset. --HG-- extra : convert_revision : 1a2813b2e7d3e0e02c8f1474f372de5cf16e7d7b	2007-08-28 19:36:51 -07:00
Gabe Black	fbab5c9bd3	X86: Hook in an implementation for lseek. --HG-- extra : convert_revision : d2424e73fa8ce56248c4edbda9db2714c4b0a92e	2007-08-28 17:34:15 -07:00
Gabe Black	37f1ff95e0	X86: More fully decode two byte opcodes. This includes the most of the SSE stuff, but not some of the "groups" of instructions. --HG-- extra : convert_revision : 4725c34f3d73971ae1763611685c5877b6c51412	2007-08-28 17:18:13 -07:00
Gabe Black	a3367adaff	Address translation: De-templatize the GenericTLB class. --HG-- extra : convert_revision : b605a90a4a1071e39f49085a839fdcd175e09fdb	2007-08-28 14:30:50 -07:00
Gabe Black	13b1f7231c	Address Translation: Make the Generic TLB only compile in SE mode. --HG-- extra : convert_revision : 7eb9a78480174f754f51f75983ee5a1b31280bd3	2007-08-27 18:30:58 -07:00
Gabe Black	703d10705c	Alpha: Fixes to get alpha to compile again. --HG-- extra : convert_revision : 9541cf6dae1fb1a1c6025898692b2e04fcf55c6d	2007-08-27 18:30:02 -07:00
Gabe Black	8253ff2ba9	MIPS: Fixes to get mips to compile. --HG-- extra : convert_revision : 23561eda853a51046ae56c23a88466230c3e83f2	2007-08-27 18:29:15 -07:00
Gabe Black	25ad253643	SPARC: Fixes to get SPARC to compile again. --HG-- extra : convert_revision : dab20c49fec9c2d385ca59b9ab627c2d3dddfe76	2007-08-27 18:26:36 -07:00
Gabe Black	7227ab5f22	Merge with head --HG-- extra : convert_revision : cc73b9aaf73e9dacf52f3350fa591e67ca4ccee6	2007-08-26 21:45:40 -07:00
Gabe Black	8d1c7a83d7	X86: Make the Ruflag microop work correctly, and make the code a little clearer. --HG-- extra : convert_revision : c551f51cdda46df99370363ed2d70916db8413eb	2007-08-26 20:41:36 -07:00
Gabe Black	ac5ec1542e	X86: Return values for some cpuid functions that match what my development machine returns. --HG-- extra : convert_revision : e6619da11f43bbe025ceabd06387dd24e1cd883b	2007-08-26 20:40:42 -07:00
Gabe Black	8b738f7f12	X86: Make the microassembler accept lines which are just labels. The labels on these lines will be associated with whatever the next microop is. --HG-- extra : convert_revision : 80c260e48ec1c16e6325061608e37c95a0610cfa	2007-08-26 20:39:55 -07:00
Gabe Black	03880cf828	X86: Make cpuid actually consider the eax parameter and return different values. --HG-- extra : convert_revision : 527c1cacdd20ab162859bba7f9a6bed33afa2d4f	2007-08-26 20:38:42 -07:00
Gabe Black	9c99f5f825	X86: Fix the sign extension microop so it extends zeros correctly. --HG-- extra : convert_revision : 9d7ca286ba7709175fa75226320601acce4ced98	2007-08-26 20:37:41 -07:00
Gabe Black	506bf83595	X86: Implement cmps (string compare) --HG-- extra : convert_revision : 0d6b783b2246b8ad8d91e4c63e407307ee11c651	2007-08-26 20:36:46 -07:00
Gabe Black	00d9036c62	X86: Make shift instructions set some of the flags they're supposed to. The flag mechanism for microops needs to be fleshd out a little more to allow for custom flag calculation methods for certain microops. Shift is an example where the rules for calculating OF and CF are unique. --HG-- extra : convert_revision : 91981a00c1efd05db702fffa9cea51f912583013	2007-08-26 20:35:48 -07:00
Gabe Black	9b49a78cfd	Address translation: Make the page table more flexible. The page table now stores actual page table entries. It is still a templated class here, but this will be corrected in the near future. --HG-- extra : convert_revision : 804dcc6320414c2b3ab76a74a15295bd24e1d13d	2007-08-26 20:33:57 -07:00
Gabe Black	80d51650c8	O3 CPU: Remove alignment check from dynamic instruction read/write functions. --HG-- extra : convert_revision : e5d415b4bf79353ef3c9f4dc5af09ab4102c55fb	2007-08-26 20:31:30 -07:00
Gabe Black	fcd04f953c	X86: Remove x86 code that attempted to fix misaligned accesses. --HG-- extra : convert_revision : 42f68010e6498aceb7ed25da278093e99150e4df	2007-08-26 20:30:36 -07:00

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3548 commits