add core specific parameter to BaseCPU params
--HG-- extra : convert_revision : 15c5995e3acf23a45c712891fd06ef273584f7e8
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@ -189,76 +189,7 @@ class BaseCPU : public MemObject
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Tick progress_interval;
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BaseCPU *checker;
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#if THE_ISA == MIPS_ISA
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/* Note: It looks like it will be better to allow simulator users
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to specify the values of individual variables instead of requiring
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users to define the values of entire registers
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Especially since a lot of these variables can be created from other
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user parameters (cache descriptions)
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-jpp
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*/
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// MIPS CP0 State - First individual variables
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// Page numbers refer to revision 2.50 (July 2005) of the MIPS32 ARM, Volume III (PRA)
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unsigned CP0_IntCtl_IPTI; // Page 93, IP Timer Interrupt
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unsigned CP0_IntCtl_IPPCI; // Page 94, IP Performance Counter Interrupt
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unsigned CP0_SrsCtl_HSS; // Page 95, Highest Implemented Shadow Set
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unsigned CP0_PRId_CompanyOptions; // Page 105, Manufacture options
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unsigned CP0_PRId_CompanyID; // Page 105, Company ID - (0-255, 1=>MIPS)
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unsigned CP0_PRId_ProcessorID; // Page 105
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unsigned CP0_PRId_Revision; // Page 105
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unsigned CP0_EBase_CPUNum; // Page 106, CPU Number in a multiprocessor system
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unsigned CP0_Config_BE; // Page 108, Big/Little Endian mode
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unsigned CP0_Config_AT; //Page 109
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unsigned CP0_Config_AR; //Page 109
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unsigned CP0_Config_MT; //Page 109
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unsigned CP0_Config_VI; //Page 109
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unsigned CP0_Config1_M; // Page 110
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unsigned CP0_Config1_MMU; // Page 110
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unsigned CP0_Config1_IS; // Page 110
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unsigned CP0_Config1_IL; // Page 111
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unsigned CP0_Config1_IA; // Page 111
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unsigned CP0_Config1_DS; // Page 111
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unsigned CP0_Config1_DL; // Page 112
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unsigned CP0_Config1_DA; // Page 112
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bool CP0_Config1_C2; // Page 112
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bool CP0_Config1_MD;// Page 112 - Technically not used in MIPS32
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bool CP0_Config1_PC;// Page 112
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bool CP0_Config1_WR;// Page 113
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bool CP0_Config1_CA;// Page 113
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bool CP0_Config1_EP;// Page 113
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bool CP0_Config1_FP;// Page 113
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bool CP0_Config2_M; // Page 114
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unsigned CP0_Config2_TU;// Page 114
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unsigned CP0_Config2_TS;// Page 114
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unsigned CP0_Config2_TL;// Page 115
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unsigned CP0_Config2_TA;// Page 115
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unsigned CP0_Config2_SU;// Page 115
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unsigned CP0_Config2_SS;// Page 115
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unsigned CP0_Config2_SL;// Page 116
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unsigned CP0_Config2_SA;// Page 116
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bool CP0_Config3_M; //// Page 117
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bool CP0_Config3_DSPP;// Page 117
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bool CP0_Config3_LPA;// Page 117
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bool CP0_Config3_VEIC;// Page 118
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bool CP0_Config3_VInt; // Page 118
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bool CP0_Config3_SP;// Page 118
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bool CP0_Config3_MT;// Page 119
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bool CP0_Config3_SM;// Page 119
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bool CP0_Config3_TL;// Page 119
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bool CP0_WatchHi_M; // Page 124
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bool CP0_PerfCtr_M; // Page 130
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bool CP0_PerfCtr_W; // Page 130
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// Then, whole registers
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unsigned CP0_PRId;
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unsigned CP0_Config;
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unsigned CP0_Config1;
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unsigned CP0_Config2;
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unsigned CP0_Config3;
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#endif
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TheISA::CoreSpecific coreParams; //ISA-Specific Params That Set Up State in Core
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Params();
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};
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