X86: Add classes for the actual x86 faults.
--HG-- extra : convert_revision : bc060a01b5415551b335ca68ccbf126333ae20b0
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Gabe Black
parent
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commit
65c247f21f
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@ -63,18 +63,91 @@
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namespace X86ISA
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{
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class X86Fault : public FaultBase
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// Base class for all x86 "faults" where faults is in the m5 sense
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class X86FaultBase : public FaultBase
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{
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protected:
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const char * name() const
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const char * faultName;
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const char * mnem;
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X86FaultBase(const char * _faultName, const char * _mnem) :
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faultName(_faultName), mnem(_mnem)
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{
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return "generic_x86_fault";
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}
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const char * name() const
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{
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return faultName;
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}
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virtual bool isBenign()
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{
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return true;
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}
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virtual const char * mnemonic() const
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{
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return mnem;
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}
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};
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// Base class for x86 faults which behave as if the underlying instruction
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// didn't happen.
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class X86Fault : public X86FaultBase
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{
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protected:
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X86Fault(const char * name, const char * mnem) :
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X86FaultBase(name, mnem)
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{}
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};
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// Base class for x86 traps which behave as if the underlying instruction
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// completed.
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class X86Trap : public X86FaultBase
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{
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protected:
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X86Trap(const char * name, const char * mnem) :
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X86FaultBase(name, mnem)
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{}
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#if FULL_SYSTEM
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void invoke(ThreadContext * tc)
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{
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panic("X86 faults are not implemented!");
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}
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#endif
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};
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// Base class for x86 aborts which seem to be catastrophic failures.
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class X86Abort : public X86FaultBase
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{
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protected:
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X86Abort(const char * name, const char * mnem) :
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X86FaultBase(name, mnem)
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{}
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#if FULL_SYSTEM
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void invoke(ThreadContext * tc)
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{
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panic("X86 faults are not implemented!");
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}
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#endif
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};
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// Base class for x86 interrupts.
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class X86Interrupt : public X86FaultBase
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{
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protected:
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X86Interrupt(const char * name, const char * mnem) :
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X86FaultBase(name, mnem)
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{}
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#if FULL_SYSTEM
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void invoke(ThreadContext * tc)
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{
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panic("X86 faults are not implemented!");
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}
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#endif
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};
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class UnimpInstFault : public FaultBase
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@ -95,6 +168,223 @@ namespace X86ISA
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{
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panic("Machine check fault not implemented in x86!\n");
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}
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// Below is a summary of the interrupt/exception information in the
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// architecture manuals.
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// Class | Type | vector | Cause | mnem
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//------------------------------------------------------------------------
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//Contrib Fault 0 Divide-by-Zero-Error #DE
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//Benign Either 1 Debug #DB
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//Benign Interrupt 2 Non-Maskable-Interrupt #NMI
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//Benign Trap 3 Breakpoint #BP
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//Benign Trap 4 Overflow #OF
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//Benign Fault 5 Bound-Range #BR
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//Benign Fault 6 Invalid-Opcode #UD
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//Benign Fault 7 Device-Not-Available #NM
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//Benign Abort 8 Double-Fault #DF
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// 9 Coprocessor-Segment-Overrun
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//Contrib Fault 10 Invalid-TSS #TS
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//Contrib Fault 11 Segment-Not-Present #NP
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//Contrib Fault 12 Stack #SS
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//Contrib Fault 13 General-Protection #GP
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//Either Fault 14 Page-Fault #PF
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// 15 Reserved
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//Benign Fault 16 x87 Floating-Point Exception Pending #MF
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//Benign Fault 17 Alignment-Check #AC
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//Benign Abort 18 Machine-Check #MC
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//Benign Fault 19 SIMD Floating-Point #XF
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// 20-29 Reserved
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//Contrib ? 30 Security Exception #SX
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// 31 Reserved
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//Benign Interrupt 0-255 External Interrupts #INTR
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//Benign Interrupt 0-255 Software Interrupts INTn
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class DivideByZero : public X86Fault
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{
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public:
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DivideByZero() :
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X86Fault("Divide-by-Zero-Error", "#DE")
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{}
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};
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class DebugException : public X86FaultBase
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{
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public:
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DebugException() :
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X86FaultBase("Debug", "#DB")
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{}
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};
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class NonMaskableInterrupt : public X86Interrupt
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{
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public:
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NonMaskableInterrupt() :
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X86Interrupt("Non-Maskable-Interrupt", "#NMI")
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{}
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};
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class Breakpoint : public X86Trap
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{
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public:
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Breakpoint() :
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X86Trap("Breakpoint", "#BP")
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{}
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};
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class OverflowTrap : public X86Trap
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{
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public:
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OverflowTrap() :
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X86Trap("Overflow", "#OF")
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{}
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};
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class BoundRange : public X86Fault
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{
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public:
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BoundRange() :
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X86Fault("Bound-Range", "#BR")
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{}
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};
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class InvalidOpcode : public X86Fault
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{
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public:
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InvalidOpcode() :
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X86Fault("Invalid-Opcode", "#UD")
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{}
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};
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class DeviceNotAvailable : public X86Fault
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{
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public:
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DeviceNotAvailable() :
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X86Fault("Device-Not-Available", "#NM")
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{}
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};
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class DoubleFault : public X86Abort
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{
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public:
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DoubleFault() :
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X86Abort("Double-Fault", "#DF")
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{}
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};
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class InvalidTSS : public X86Fault
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{
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public:
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InvalidTSS() :
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X86Fault("Invalid-TSS", "#TS")
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{}
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};
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class SegmentNotPresent : public X86Fault
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{
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public:
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SegmentNotPresent() :
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X86Fault("Segment-Not-Present", "#NP")
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{}
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};
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class StackFault : public X86Fault
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{
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public:
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StackFault() :
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X86Fault("Stack", "#SS")
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{}
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};
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class GeneralProtection : public X86Fault
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{
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public:
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GeneralProtection() :
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X86Fault("General-Protection", "#GP")
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{}
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};
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class PageFault : public X86Fault
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{
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public:
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PageFault() :
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X86Fault("Page-Fault", "#PF")
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{}
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};
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class X87FpExceptionPending : public X86Fault
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{
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public:
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X87FpExceptionPending() :
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X86Fault("x87 Floating-Point Exception Pending", "#MF")
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{}
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};
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class AlignmentCheck : X86Fault
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{
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public:
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AlignmentCheck() :
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X86Fault("Alignment-Check", "#AC")
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{}
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};
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class MachineCheck : X86Abort
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{
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public:
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MachineCheck() :
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X86Abort("Machine-Check", "#MC")
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{}
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};
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class SIMDFloatingPointFault : X86Fault
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{
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public:
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SIMDFloatingPointFault() :
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X86Fault("SIMD Floating-Point", "#XF")
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{}
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};
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class SecurityException : X86FaultBase
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{
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public:
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SecurityException() :
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X86FaultBase("Security Exception", "#SX")
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{}
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};
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class ExternalInterrupt : X86Interrupt
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{
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public:
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ExternalInterrupt() :
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X86Interrupt("External Interrupt", "#INTR")
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{}
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};
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class SoftwareInterrupt : X86Interrupt
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{
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public:
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SoftwareInterrupt() :
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X86Interrupt("Software Interrupt", "INTn")
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{}
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};
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// These faults aren't part of the ISA definition. They trigger filling
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// the tlb on a miss and are to take the place of a hardware table walker.
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class FakeITLBFault : public X86Fault
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{
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public:
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FakeITLBFault() :
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X86Fault("fake instruction tlb fault", "itlb")
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{}
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};
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class FakeDTLBFault : public X86Fault
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{
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public:
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FakeDTLBFault() :
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X86Fault("fake data tlb fault", "dtlb")
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{}
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};
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};
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#endif // __ARCH_X86_FAULTS_HH__
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@ -56,6 +56,6 @@
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microcode = '''
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def macroop UD2
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{
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fault "new X86Fault"
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fault "new InvalidOpcode()"
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};
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'''
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