sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity

Rename cycles() function to ticks()

Browse source 
--HG--
extra : convert_revision : 790eddb793d4f5ba35813d001037bd8601bd76a5
This commit is contained in:
Ali Saidi 2007-09-28 13:21:52 -04:00
parent 887cd6a273
commit d325f49b70
26 changed files with 54 additions and 54 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
src/arch/mips/regfile/misc_regfile.cc
View file

@ -304,7 +304,7 @@ MiscRegFile::scheduleCP0Update(int delay)
//schedule UPDATE
CP0Event *cp0_event = new CP0Event(this, cpu, UpdateCP0);
cp0_event->schedule(curTick + cpu->cycles(delay));
cp0_event->schedule(curTick + cpu->ticks(delay));
}
}
@ -364,9 +364,9 @@ void
MiscRegFile::CP0Event::scheduleEvent(int delay)
{
if (squashed())
reschedule(curTick + cpu->cycles(delay));
reschedule(curTick + cpu->ticks(delay));
else if (!scheduled())
schedule(curTick + cpu->cycles(delay));
schedule(curTick + cpu->ticks(delay));
}
void

4
src/arch/sparc/tlb.cc
View file

@ -1033,7 +1033,7 @@ doMmuReadError:
(uint32_t)asi, va);
}
pkt->makeAtomicResponse();
return tc->getCpuPtr()->cycles(1);
return tc->getCpuPtr()->ticks(1);
}
Tick
@ -1280,7 +1280,7 @@ doMmuWriteError:
(uint32_t)pkt->req->getAsi(), pkt->getAddr(), data);
}
pkt->makeAtomicResponse();
return tc->getCpuPtr()->cycles(1);
return tc->getCpuPtr()->ticks(1);
}
#endif

10
src/arch/sparc/ua2005.cc
View file

@ -85,7 +85,7 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
if (!(tick_cmpr & ~mask(63)) && time > 0) {
if (tickCompare->scheduled())
tickCompare->deschedule();
tickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
tickCompare->schedule(time * tc->getCpuPtr()->ticks(1));
}
panic("writing to TICK compare register %#X\n", val);
break;
@ -101,7 +101,7 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
if (!(stick_cmpr & ~mask(63)) && time > 0) {
if (sTickCompare->scheduled())
sTickCompare->deschedule();
sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1) + curTick);
sTickCompare->schedule(time * tc->getCpuPtr()->ticks(1) + curTick);
}
DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val);
break;
@ -171,7 +171,7 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
if (!(hstick_cmpr & ~mask(63)) && time > 0) {
if (hSTickCompare->scheduled())
hSTickCompare->deschedule();
hSTickCompare->schedule(curTick + time * tc->getCpuPtr()->cycles(1));
hSTickCompare->schedule(curTick + time * tc->getCpuPtr()->ticks(1));
}
DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val);
break;
@ -315,7 +315,7 @@ MiscRegFile::processSTickCompare(ThreadContext *tc)
setReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc);
}
} else
sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick);
sTickCompare->schedule(ticks * tc->getCpuPtr()->ticks(1) + curTick);
}
void
@ -341,6 +341,6 @@ MiscRegFile::processHSTickCompare(ThreadContext *tc)
}
// Need to do something to cause interrupt to happen here !!! @todo
} else
hSTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick);
hSTickCompare->schedule(ticks * tc->getCpuPtr()->ticks(1) + curTick);
}

4
src/arch/x86/tlb.cc
View file

@ -95,13 +95,13 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
Tick
DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
{
return tc->getCpuPtr()->cycles(1);
return tc->getCpuPtr()->ticks(1);
}
Tick
DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
{
return tc->getCpuPtr()->cycles(1);
return tc->getCpuPtr()->ticks(1);
}
#endif

4
src/cpu/base.cc
View file

@ -74,7 +74,7 @@ CPUProgressEvent::process()
{
Counter temp = cpu->totalInstructions();
#ifndef NDEBUG
double ipc = double(temp - lastNumInst) / (interval / cpu->cycles(1));
double ipc = double(temp - lastNumInst) / (interval / cpu->ticks(1));
DPRINTFN("%s progress event, instructions committed: %lli, IPC: %0.8d\n",
cpu->name(), temp - lastNumInst, ipc);
@ -223,7 +223,7 @@ BaseCPU::startup()
if (params->progress_interval) {
new CPUProgressEvent(&mainEventQueue,
cycles(params->progress_interval),
ticks(params->progress_interval),
this);
}
}

2
src/cpu/base.hh
View file

@ -82,7 +82,7 @@ class BaseCPU : public MemObject
public:
// Tick currentTick;
inline Tick frequency() const { return Clock::Frequency / clock; }
inline Tick cycles(int numCycles) const { return clock * numCycles; }
inline Tick ticks(int numCycles) const { return clock * numCycles; }
inline Tick curCycle() const { return curTick / clock; }
inline Tick tickToCycles(Tick val) const { return val / clock; }
// @todo remove me after debugging with legion done

2
src/cpu/memtest/memtest.cc
View file

@ -270,7 +270,7 @@ void
MemTest::tick()
{
if (!tickEvent.scheduled())
tickEvent.schedule(curTick + cycles(1));
tickEvent.schedule(curTick + ticks(1));
if (++noResponseCycles >= 500000) {
cerr << name() << ": deadlocked at cycle " << curTick << endl;

2
src/cpu/memtest/memtest.hh
View file

@ -55,7 +55,7 @@ class MemTest : public MemObject
// register statistics
virtual void regStats();
inline Tick cycles(int numCycles) const { return numCycles; }
inline Tick ticks(int numCycles) const { return numCycles; }
// main simulation loop (one cycle)
void tick();

2
src/cpu/o3/commit_impl.hh
View file

@ -325,7 +325,7 @@ DefaultCommit<Impl>::initStage()
cpu->activateStage(O3CPU::CommitIdx);
cpu->activityThisCycle();
trapLatency = cpu->cycles(trapLatency);
trapLatency = cpu->ticks(trapLatency);
}
template <class Impl>

6
src/cpu/o3/cpu.cc
View file

@ -464,7 +464,7 @@ FullO3CPU<Impl>::tick()
lastRunningCycle = curTick;
timesIdled++;
} else {
tickEvent.schedule(nextCycle(curTick + cycles(1)));
tickEvent.schedule(nextCycle(curTick + ticks(1)));
DPRINTF(O3CPU, "Scheduling next tick!\n");
}
}
@ -558,7 +558,7 @@ FullO3CPU<Impl>::activateContext(int tid, int delay)
// Needs to set each stage to running as well.
if (delay){
DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
"on cycle %d\n", tid, curTick + cycles(delay));
"on cycle %d\n", tid, curTick + ticks(delay));
scheduleActivateThreadEvent(tid, delay);
} else {
activateThread(tid);
@ -585,7 +585,7 @@ FullO3CPU<Impl>::deallocateContext(int tid, bool remove, int delay)
// Schedule removal of thread data from CPU
if (delay){
DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate "
"on cycle %d\n", tid, curTick + cycles(delay));
"on cycle %d\n", tid, curTick + ticks(delay));
scheduleDeallocateContextEvent(tid, remove, delay);
return false;
} else {

12
src/cpu/o3/cpu.hh
View file

@ -146,9 +146,9 @@ class FullO3CPU : public BaseO3CPU
void scheduleTickEvent(int delay)
{
if (tickEvent.squashed())
tickEvent.reschedule(nextCycle(curTick + cycles(delay)));
tickEvent.reschedule(nextCycle(curTick + ticks(delay)));
else if (!tickEvent.scheduled())
tickEvent.schedule(nextCycle(curTick + cycles(delay)));
tickEvent.schedule(nextCycle(curTick + ticks(delay)));
}
/** Unschedule tick event, regardless of its current state. */
@ -187,10 +187,10 @@ class FullO3CPU : public BaseO3CPU
// Schedule thread to activate, regardless of its current state.
if (activateThreadEvent[tid].squashed())
activateThreadEvent[tid].
reschedule(nextCycle(curTick + cycles(delay)));
reschedule(nextCycle(curTick + ticks(delay)));
else if (!activateThreadEvent[tid].scheduled())
activateThreadEvent[tid].
schedule(nextCycle(curTick + cycles(delay)));
schedule(nextCycle(curTick + ticks(delay)));
}
/** Unschedule actiavte thread event, regardless of its current state. */
@ -238,10 +238,10 @@ class FullO3CPU : public BaseO3CPU
// Schedule thread to activate, regardless of its current state.
if (deallocateContextEvent[tid].squashed())
deallocateContextEvent[tid].
reschedule(nextCycle(curTick + cycles(delay)));
reschedule(nextCycle(curTick + ticks(delay)));
else if (!deallocateContextEvent[tid].scheduled())
deallocateContextEvent[tid].
schedule(nextCycle(curTick + cycles(delay)));
schedule(nextCycle(curTick + ticks(delay)));
}
/** Unschedule thread deallocation in CPU */

2
src/cpu/o3/inst_queue_impl.hh
View file

@ -752,7 +752,7 @@ InstructionQueue<Impl>::scheduleReadyInsts()
FUCompletion *execution = new FUCompletion(issuing_inst,
idx, this);
execution->schedule(curTick + cpu->cycles(issue_latency - 1));
execution->schedule(curTick + cpu->ticks(issue_latency - 1));
// @todo: Enforce that issue_latency == 1 or op_latency
if (issue_latency > 1) {

4
src/cpu/ozone/cpu.hh
View file

@ -315,9 +315,9 @@ class OzoneCPU : public BaseCPU
void scheduleTickEvent(int delay)
{
if (tickEvent.squashed())
tickEvent.reschedule(curTick + cycles(delay));
tickEvent.reschedule(curTick + ticks(delay));
else if (!tickEvent.scheduled())
tickEvent.schedule(curTick + cycles(delay));
tickEvent.schedule(curTick + ticks(delay));
}
/// Unschedule tick event, regardless of its current state.

2
src/cpu/ozone/cpu_impl.hh
View file

@ -613,7 +613,7 @@ OzoneCPU<Impl>::tick()
comInstEventQueue[0]->serviceEvents(numInst);
if (!tickEvent.scheduled() && _status == Running)
tickEvent.schedule(curTick + cycles(1));
tickEvent.schedule(curTick + ticks(1));
}
template <class Impl>

2
src/cpu/ozone/lw_back_end_impl.hh
View file

@ -45,7 +45,7 @@ LWBackEnd<Impl>::generateTrapEvent(Tick latency)
TrapEvent *trap = new TrapEvent(this);
trap->schedule(curTick + cpu->cycles(latency));
trap->schedule(curTick + cpu->ticks(latency));
thread->trapPending = true;
}

16
src/cpu/simple/atomic.cc
View file

@ -254,7 +254,7 @@ AtomicSimpleCPU::activateContext(int thread_num, int delay)
notIdleFraction++;
//Make sure ticks are still on multiples of cycles
tickEvent.schedule(nextCycle(curTick + cycles(delay)));
tickEvent.schedule(nextCycle(curTick + ticks(delay)));
_status = Running;
}
@ -584,7 +584,7 @@ AtomicSimpleCPU::tick()
{
DPRINTF(SimpleCPU, "Tick\n");
Tick latency = cycles(1); // instruction takes one cycle by default
Tick latency = ticks(1); // instruction takes one cycle by default
for (int i = 0; i < width; ++i) {
numCycles++;
@ -642,14 +642,14 @@ AtomicSimpleCPU::tick()
if (simulate_stalls) {
Tick icache_stall =
icache_access ? icache_latency - cycles(1) : 0;
icache_access ? icache_latency - ticks(1) : 0;
Tick dcache_stall =
dcache_access ? dcache_latency - cycles(1) : 0;
Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1);
if (cycles(stall_cycles) < (icache_stall + dcache_stall))
latency += cycles(stall_cycles+1);
dcache_access ? dcache_latency - ticks(1) : 0;
Tick stall_cycles = (icache_stall + dcache_stall) / ticks(1);
if (ticks(stall_cycles) < (icache_stall + dcache_stall))
latency += ticks(stall_cycles+1);
else
latency += cycles(stall_cycles);
latency += ticks(stall_cycles);
}
}

2
src/cpu/simple/timing.cc
View file

@ -222,7 +222,7 @@ TimingSimpleCPU::activateContext(int thread_num, int delay)
_status = Running;
// kick things off by initiating the fetch of the next instruction
fetchEvent = new FetchEvent(this, nextCycle(curTick + cycles(delay)));
fetchEvent = new FetchEvent(this, nextCycle(curTick + ticks(delay)));
}

4
src/cpu/trace/trace_cpu.cc
View file

@ -110,10 +110,10 @@ TraceCPU::tick()
if (mainEventQueue.empty()) {
exitSimLoop("end of memory trace reached");
} else {
tickEvent.schedule(mainEventQueue.nextEventTime() + cycles(1));
tickEvent.schedule(mainEventQueue.nextEventTime() + ticks(1));
}
} else {
tickEvent.schedule(max(curTick + cycles(1), nextCycle));
tickEvent.schedule(max(curTick + ticks(1), nextCycle));
}
}

2
src/cpu/trace/trace_cpu.hh
View file

@ -107,7 +107,7 @@ class TraceCPU : public SimObject
MemInterface *dcache_interface,
MemTraceReader *data_trace);
inline Tick cycles(int numCycles) { return numCycles; }
inline Tick ticks(int numCycles) { return numCycles; }
/**
* Perform all the accesses for one cycle.

4
src/dev/i8254xGBe.cc
View file

@ -1104,7 +1104,7 @@ IGbE::restartClock()
{
if (!tickEvent.scheduled() && (rxTick || txTick || txFifoTick) && getState() ==
SimObject::Running)
tickEvent.schedule((curTick/cycles(1)) * cycles(1) + cycles(1));
tickEvent.schedule((curTick/ticks(1)) * ticks(1) + ticks(1));
}
unsigned int
@ -1400,7 +1400,7 @@ IGbE::tick()
if (rxTick || txTick || txFifoTick)
tickEvent.schedule(curTick + cycles(1));
tickEvent.schedule(curTick + ticks(1));
}
void

2
src/dev/i8254xGBe.hh
View file

@ -614,7 +614,7 @@ class IGbE : public EtherDevice
virtual EtherInt *getEthPort(const std::string &if_name, int idx);
Tick clock;
inline Tick cycles(int numCycles) const { return numCycles * clock; }
inline Tick ticks(int numCycles) const { return numCycles * clock; }
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);

6
src/dev/ns_gige.cc
View file

@ -1469,7 +1469,7 @@ NSGigE::rxKick()
}
// Go to the next state machine clock tick.
rxKickTick = curTick + cycles(1);
rxKickTick = curTick + ticks(1);
}
switch(rxDmaState) {
@ -1916,7 +1916,7 @@ NSGigE::txKick()
}
// Go to the next state machine clock tick.
txKickTick = curTick + cycles(1);
txKickTick = curTick + ticks(1);
}
switch(txDmaState) {
@ -2322,7 +2322,7 @@ NSGigE::transferDone()
DPRINTF(Ethernet, "transfer complete: data in txFifo...schedule xmit\n");
txEvent.reschedule(curTick + cycles(1), true);
txEvent.reschedule(curTick + ticks(1), true);
}
bool

2
src/dev/ns_gige.hh
View file

@ -199,7 +199,7 @@ class NSGigE : public EtherDevice
/* state machine cycle time */
Tick clock;
inline Tick cycles(int numCycles) const { return numCycles * clock; }
inline Tick ticks(int numCycles) const { return numCycles * clock; }
/* tx State Machine */
TxState txState;

2
src/dev/sinic.cc
View file

@ -1211,7 +1211,7 @@ Device::transferDone()
DPRINTF(Ethernet, "transfer complete: data in txFifo...schedule xmit\n");
txEvent.reschedule(curTick + cycles(1), true);
txEvent.reschedule(curTick + ticks(1), true);
}
bool

2
src/dev/sinic.hh
View file

@ -51,7 +51,7 @@ class Base : public PciDev
bool rxEnable;
bool txEnable;
Tick clock;
inline Tick cycles(int numCycles) const { return numCycles * clock; }
inline Tick ticks(int numCycles) const { return numCycles * clock; }
protected:
Tick intrDelay;

2
src/sim/pseudo_inst.cc
View file

@ -105,7 +105,7 @@ namespace PseudoInst
EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent();
Tick resume = curTick + tc->getCpuPtr()->cycles(cycles);
Tick resume = curTick + tc->getCpuPtr()->ticks(cycles);
quiesceEvent->reschedule(resume, true);