DRAM: Make latency parameters be Param.Latency instead of ints.
--HG-- extra : convert_revision : 553b86cc4653da089d7aa0045a3f3bdcabf6c4d8
This commit is contained in:
parent
4b49bd47f4
commit
333ac6cc32
1 changed files with 6 additions and 6 deletions
|
@ -46,12 +46,12 @@ class DRAMMemory(PhysicalMemory):
|
|||
mem_actpolicy = Param.String("open", "Open/Close policy")
|
||||
memctrladdr_type = Param.String("interleaved", "Mapping interleaved or direct")
|
||||
bus_width = Param.Int(16, "")
|
||||
act_lat = Param.Int(2, "RAS to CAS delay")
|
||||
cas_lat = Param.Int(1, "CAS delay")
|
||||
war_lat = Param.Int(2, "write after read delay")
|
||||
pre_lat = Param.Int(2, "precharge delay")
|
||||
dpl_lat = Param.Int(2, "data in to precharge delay")
|
||||
trc_lat = Param.Int(6, "row cycle delay")
|
||||
act_lat = Param.Latency("2ns", "RAS to CAS delay")
|
||||
cas_lat = Param.Latency("1ns", "CAS delay")
|
||||
war_lat = Param.Latency("2ns", "write after read delay")
|
||||
pre_lat = Param.Latency("2ns", "precharge delay")
|
||||
dpl_lat = Param.Latency("2ns", "data in to precharge delay")
|
||||
trc_lat = Param.Latency("6ns", "row cycle delay")
|
||||
num_banks = Param.Int(4, "Number of Banks")
|
||||
num_cpus = Param.Int(4, "Number of CPUs connected to DRAM")
|
||||
|
||||
|
|
Loading…
Reference in a new issue