X86: Major rework of how regop microops are generated.
The new implementation uses metaclass, and gives a lot more precise control with a lot less verbosity. The flags/no flags reg/imm variants are all handled by the same python class now which supplies a constructor to the right C++ class based on context. --HG-- extra : convert_revision : 712e3ec6de7a5a038da083f79635fd7a687d56e5
This commit is contained in:
Gabe Black
parent
9277545ba6
commit
9da070ce8a
3 changed files with 283 additions and 317 deletions
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@ -153,7 +153,8 @@ def template MacroConstructor {{
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let {{
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from micro_asm import Combinational_Macroop, Rom_Macroop
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class X86Macroop(Combinational_Macroop):
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def add_microop(self, microop):
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def add_microop(self, mnemonic, microop):
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microop.mnemonic = mnemonic
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microop.micropc = len(self.microops)
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self.microops.append(microop)
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def setAdjustEnv(self, val):
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@ -69,6 +69,7 @@ let {{
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let {{
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class X86Microop(object):
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def __init__(self, name):
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self.name = name
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@ -88,7 +89,8 @@ let {{
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return text
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def getAllocator(self, mnemonic, *microFlags):
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return 'new %s(machInst, %s)' % (self.className, mnemonic, self.microFlagsText(microFlags))
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return 'new %s(machInst, %s)' % \
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(self.className, mnemonic, self.microFlagsText(microFlags))
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}};
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//////////////////////////////////////////////////////////////////////////
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@ -228,313 +228,235 @@ def template MicroRegOpImmConstructor {{
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}};
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let {{
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class X86MicroMeta(type):
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def __new__(mcls, name, bases, dict):
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abstract = False
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if "abstract" in dict:
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abstract = dict['abstract']
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del dict['abstract']
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cls = type.__new__(mcls, name, bases, dict)
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if not abstract:
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allClasses[name] = cls
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return cls
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class XXX86Microop(object):
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__metaclass__ = X86MicroMeta
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abstract = True
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class RegOp(X86Microop):
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abstract = True
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def __init__(self, dest, src1, src2, flags, dataSize):
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self.dest = dest
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self.src1 = src1
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self.src2 = src2
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self.flags = flags
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self.dataSize = dataSize
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if flags is None:
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self.ext = 0
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else:
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if not isinstance(flags, (list, tuple)):
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raise Exception, "flags must be a list or tuple of flags"
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self.ext = " | ".join(flags)
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self.className += "Flags"
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def getAllocator(self, *microFlags):
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allocator = '''new %(class_name)s(machInst, mnemonic
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%(flags)s, %(src1)s, %(src2)s, %(dest)s,
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%(dataSize)s, %(ext)s)''' % {
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"class_name" : self.className,
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"flags" : self.microFlagsText(microFlags),
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"src1" : self.src1, "src2" : self.src2,
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"dest" : self.dest,
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"dataSize" : self.dataSize,
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"ext" : self.ext}
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return allocator
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class RegOpImm(X86Microop):
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abstract = True
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def __init__(self, dest, src1, imm8, flags, dataSize):
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self.dest = dest
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self.src1 = src1
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self.imm8 = imm8
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self.flags = flags
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self.dataSize = dataSize
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if flags is None:
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self.ext = 0
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else:
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if not isinstance(flags, (list, tuple)):
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raise Exception, "flags must be a list or tuple of flags"
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self.ext = " | ".join(flags)
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self.className += "Flags"
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def getAllocator(self, *microFlags):
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allocator = '''new %(class_name)s(machInst, mnemonic
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%(flags)s, %(src1)s, %(imm8)s, %(dest)s,
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%(dataSize)s, %(ext)s)''' % {
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"class_name" : self.className,
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"flags" : self.microFlagsText(microFlags),
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"src1" : self.src1, "imm8" : self.imm8,
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"dest" : self.dest,
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"dataSize" : self.dataSize,
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"ext" : self.ext}
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return allocator
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}};
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let {{
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# Make these empty strings so that concatenating onto
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# them will always work.
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header_output = ""
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decoder_output = ""
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exec_output = ""
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# A function which builds the C++ classes that implement the microops
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def setUpMicroRegOp(name, Name, base, code, flagCode = "", condCheck = "true", elseCode = ";", imm=False):
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global header_output
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global decoder_output
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global exec_output
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global microopClasses
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immTemplates = (
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MicroRegOpImmDeclare,
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MicroRegOpImmConstructor,
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MicroRegOpImmExecute)
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iop = InstObjParams(name, Name, base,
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{"code" : code,
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"flag_code" : flagCode,
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"cond_check" : condCheck,
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"else_code" : elseCode})
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if imm:
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header_output += MicroRegOpImmDeclare.subst(iop)
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decoder_output += MicroRegOpImmConstructor.subst(iop)
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exec_output += MicroRegOpImmExecute.subst(iop)
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else:
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header_output += MicroRegOpDeclare.subst(iop)
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decoder_output += MicroRegOpConstructor.subst(iop)
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exec_output += MicroRegOpExecute.subst(iop)
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regTemplates = (
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MicroRegOpDeclare,
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MicroRegOpConstructor,
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MicroRegOpExecute)
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class RegOpMeta(type):
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def buildCppClasses(self, name, Name, suffix, \
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code, flag_code, cond_check, else_code):
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# Globals to stick the output in
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global header_output
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global decoder_output
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global exec_output
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# Stick all the code together so it can be searched at once
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allCode = "|".join((code, flag_code, cond_check, else_code))
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# If op2 is used anywhere, make register and immediate versions
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# of this code.
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matcher = re.compile("op2(?P<typeQual>\\.\\w+)?")
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if matcher.search(allCode):
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self.buildCppClasses(name, Name, suffix,
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matcher.sub("psrc2", code),
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matcher.sub("psrc2", flag_code),
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matcher.sub("psrc2", cond_check),
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matcher.sub("psrc2", else_code))
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self.buildCppClasses(name + "i", Name, suffix + "Imm",
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matcher.sub("imm8", code),
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matcher.sub("imm8", flag_code),
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matcher.sub("imm8", cond_check),
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matcher.sub("imm8", else_code))
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return
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# If there's something optional to do with flags, generate
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# a version without it and fix up this version to use it.
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if flag_code is not "" or cond_check is not "true":
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self.buildCppClasses(name, Name, suffix,
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code, "", "true", else_code)
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suffix = "Flags" + suffix
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# If psrc1 or psrc2 is used, we need to actually insert code to
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# compute it.
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matcher = re.compile("(?<!\w)psrc1(?!\w)")
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if matcher.search(allCode):
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code = "IntReg psrc1 = pick(SrcReg1, 0, dataSize);" + code
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matcher = re.compile("(?<!\w)psrc2(?!\w)")
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if matcher.search(allCode):
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code = "IntReg psrc2 = pick(SrcReg2, 1, dataSize);" + code
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base = "X86ISA::RegOp"
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# If imm8 shows up in the code, use the immediate templates, if
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# not, hopefully the register ones will be correct.
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templates = regTemplates
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matcher = re.compile("(?<!\w)imm8(?!\w)")
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if matcher.search(allCode):
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base += "Imm"
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templates = immTemplates
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# Get everything ready for the substitution
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iop = InstObjParams(name, Name + suffix, base,
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{"code" : code,
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"flag_code" : flag_code,
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"cond_check" : cond_check,
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"else_code" : else_code})
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# Generate the actual code (finally!)
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header_output += templates[0].subst(iop)
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decoder_output += templates[1].subst(iop)
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exec_output += templates[2].subst(iop)
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checkCCFlagBits = "checkCondition(ccFlagBits)"
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genCCFlagBits = \
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"ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, op2);"
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genCCFlagBitsSub = \
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"ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2, true);"
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genCCFlagBitsLogic = '''
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//Don't have genFlags handle the OF or CF bits
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uint64_t mask = CFBit | OFBit;
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ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1, op2);
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//If a logic microop wants to set these, it wants to set them to 0.
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ccFlagBits &= ~(CFBit & ext);
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ccFlagBits &= ~(OFBit & ext);
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'''
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def __new__(mcls, Name, bases, dict):
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abstract = False
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name = Name.lower()
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if "abstract" in dict:
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abstract = dict['abstract']
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del dict['abstract']
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regPick = '''
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IntReg psrc1 = pick(SrcReg1, 0, dataSize);
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IntReg psrc2 = pick(SrcReg2, 1, dataSize);
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'''
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immPick = '''
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IntReg psrc1 = pick(SrcReg1, 0, dataSize);
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'''
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cls = super(RegOpMeta, mcls).__new__(mcls, Name, bases, dict)
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if not abstract:
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cls.className = Name
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cls.base_mnemonic = name
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code = cls.code
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flag_code = cls.flag_code
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cond_check = cls.cond_check
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else_code = cls.else_code
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# Set up the C++ classes
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mcls.buildCppClasses(cls, name, Name, "",
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code, flag_code, cond_check, else_code)
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# Hook into the microassembler dict
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global microopClasses
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microopClasses[name] = cls
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allCode = "|".join((code, flag_code, cond_check, else_code))
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# If op2 is used anywhere, make register and immediate versions
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# of this code.
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matcher = re.compile("op2(?P<typeQual>\\.\\w+)?")
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if matcher.search(allCode):
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microopClasses[name + 'i'] = cls
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return cls
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# This creates a python representations of a microop which are a cross
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# product of reg/immediate and flag/no flag versions.
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def defineMicroRegOp(mnemonic, code, flagCode=genCCFlagBits, \
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cc=False, doImm=True, elseCode=";"):
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Name = mnemonic
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name = mnemonic.lower()
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class RegOp(X86Microop):
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__metaclass__ = RegOpMeta
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# This class itself doesn't act as a microop
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abstract = True
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# Find op2 in each of the instruction definitions. Create two versions
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# of the code, one with an integer operand, and one with an immediate
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# operand.
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matcher = re.compile("op2(?P<typeQual>\\.\\w+)?")
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regCode = regPick + matcher.sub("psrc2", code)
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immCode = immPick + matcher.sub("imm8", code)
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# Default template parameter values
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flag_code = ""
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cond_check = "true"
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else_code = ";"
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if not cc:
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condCode = "true"
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else:
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flagCode = ""
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condCode = checkCCFlagBits
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def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"):
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self.dest = dest
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self.src1 = src1
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self.op2 = op2
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self.flags = flags
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self.dataSize = dataSize
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if flags is None:
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self.ext = 0
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else:
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if not isinstance(flags, (list, tuple)):
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raise Exception, "flags must be a list or tuple of flags"
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self.ext = " | ".join(flags)
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self.className += "Flags"
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regFlagCode = matcher.sub("psrc2", flagCode)
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immFlagCode = matcher.sub("imm8", flagCode)
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def getAllocator(self, *microFlags):
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className = self.className
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if self.mnemonic == self.base_mnemonic + 'i':
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className += "Imm"
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allocator = '''new %(class_name)s(machInst, mnemonic
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%(flags)s, %(src1)s, %(op2)s, %(dest)s,
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%(dataSize)s, %(ext)s)''' % {
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"class_name" : className,
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"flags" : self.microFlagsText(microFlags),
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"src1" : self.src1, "op2" : self.op2,
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"dest" : self.dest,
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"dataSize" : self.dataSize,
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"ext" : self.ext}
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return allocator
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class RegOpChild(RegOp):
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mnemonic = name
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className = Name
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def __init__(self, dest, src1, src2, \
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flags=None, dataSize="env.dataSize"):
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super(RegOpChild, self).__init__(dest, src1, src2, \
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flags, dataSize)
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class LogicRegOp(RegOp):
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abstract = True
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flag_code = '''
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//Don't have genFlags handle the OF or CF bits
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uint64_t mask = CFBit | OFBit;
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ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1, op2);
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//If a logic microop wants to set these, it wants to set them to 0.
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ccFlagBits &= ~(CFBit & ext);
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ccFlagBits &= ~(OFBit & ext);
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'''
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microopClasses[name] = RegOpChild
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class FlagRegOp(RegOp):
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abstract = True
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flag_code = \
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"ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, op2);"
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setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode);
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setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp",
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regCode, flagCode=regFlagCode,
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condCheck=condCode, elseCode=elseCode);
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class SubRegOp(RegOp):
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abstract = True
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flag_code = \
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"ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2, true);"
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if doImm:
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class RegOpChildImm(RegOpImm):
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mnemonic = name + 'i'
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className = Name + 'Imm'
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def __init__(self, dest, src1, src2, \
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flags=None, dataSize="env.dataSize"):
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super(RegOpChildImm, self).__init__(dest, src1, src2, \
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flags, dataSize)
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class CondRegOp(RegOp):
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abstract = True
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cond_check = "checkCondition(ccFlagBits)"
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microopClasses[name + 'i'] = RegOpChildImm
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class Add(FlagRegOp):
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code = 'DestReg = merge(DestReg, psrc1 + op2, dataSize);'
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setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", \
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immCode, imm=True);
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setUpMicroRegOp(name + "i", Name + "ImmFlags", "X86ISA::RegOpImm",
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immCode, flagCode=immFlagCode,
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condCheck=condCode, elseCode=elseCode, imm=True);
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class Or(LogicRegOp):
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code = 'DestReg = merge(DestReg, psrc1 | op2, dataSize);'
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# This has it's own function because Wr ops have implicit destinations
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def defineMicroRegOpWr(mnemonic, code, elseCode=";"):
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Name = mnemonic
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name = mnemonic.lower()
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# Find op2 in each of the instruction definitions. Create two versions
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# of the code, one with an integer operand, and one with an immediate
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# operand.
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matcher = re.compile("op2(?P<typeQual>\\.\\w+)?")
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regCode = regPick + matcher.sub("psrc2", code)
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immCode = immPick + matcher.sub("imm8", code)
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class RegOpChild(RegOp):
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mnemonic = name
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className = Name
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def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"):
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super(RegOpChild, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize)
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microopClasses[name] = RegOpChild
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setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode);
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setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode,
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condCheck = checkCCFlagBits, elseCode = elseCode);
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class RegOpChildImm(RegOpImm):
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mnemonic = name + 'i'
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className = Name + 'Imm'
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def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"):
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super(RegOpChildImm, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize)
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microopClasses[name + 'i'] = RegOpChildImm
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setUpMicroRegOp(name + 'i', Name + "Imm", "X86ISA::RegOpImm", \
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immCode, imm=True);
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setUpMicroRegOp(name + 'i', Name + "ImmFlags", "X86ISA::RegOpImm", \
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immCode, condCheck = checkCCFlagBits, elseCode = elseCode, \
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imm=True);
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# This has it's own function because Rd ops don't always have two parameters
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def defineMicroRegOpRd(mnemonic, code):
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Name = mnemonic
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name = mnemonic.lower()
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class RegOpChild(RegOp):
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className = Name
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mnemonic = name
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def __init__(self, dest, src1 = "NUM_INTREGS", dataSize="env.dataSize"):
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super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS", None, dataSize)
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microopClasses[name] = RegOpChild
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setUpMicroRegOp(name, Name, "X86ISA::RegOp", code);
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def defineMicroRegOpImm(mnemonic, code, flagCode=""):
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Name = mnemonic
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name = mnemonic.lower()
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code = immPick + code
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class RegOpChild(RegOpImm):
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className = Name
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mnemonic = name
|
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def __init__(self, dest, src1, src2, \
|
||||
flags=None, dataSize="env.dataSize"):
|
||||
super(RegOpChild, self).__init__(dest, \
|
||||
src1, src2, flags, dataSize)
|
||||
|
||||
microopClasses[name] = RegOpChild
|
||||
|
||||
setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code, imm=True);
|
||||
setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOpImm", \
|
||||
code, flagCode=flagCode, imm=True);
|
||||
|
||||
def defineMicroRegOpRdImm(mnemonic, code, flagCode=""):
|
||||
Name = mnemonic
|
||||
name = mnemonic.lower()
|
||||
code = immPick + code
|
||||
|
||||
class RegOpChildRdImm(RegOpImm):
|
||||
className = Name
|
||||
mnemonic = name
|
||||
def __init__(self, dest, imm, flags=None, \
|
||||
dataSize="env.dataSize"):
|
||||
super(RegOpChildRdImm, self).__init__(dest, \
|
||||
"NUM_INTREGS", imm, flags, dataSize)
|
||||
|
||||
microopClasses[name] = RegOpChildRdImm
|
||||
|
||||
setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code, imm=True);
|
||||
setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOpImm", \
|
||||
code, flagCode=flagCode, imm=True);
|
||||
|
||||
defineMicroRegOp('Add', 'DestReg = merge(DestReg, psrc1 + op2, dataSize)')
|
||||
defineMicroRegOp('Or', 'DestReg = merge(DestReg, psrc1 | op2, dataSize);',
|
||||
flagCode = genCCFlagBitsLogic)
|
||||
defineMicroRegOp('Adc', '''
|
||||
class Adc(FlagRegOp):
|
||||
code = '''
|
||||
CCFlagBits flags = ccFlagBits;
|
||||
DestReg = merge(DestReg, psrc1 + op2 + flags.CF, dataSize);
|
||||
''')
|
||||
defineMicroRegOp('Sbb', '''
|
||||
'''
|
||||
|
||||
class Sbb(SubRegOp):
|
||||
code = '''
|
||||
CCFlagBits flags = ccFlagBits;
|
||||
DestReg = merge(DestReg, psrc1 - op2 - flags.CF, dataSize);
|
||||
''', flagCode = genCCFlagBitsSub)
|
||||
defineMicroRegOp('And', \
|
||||
'DestReg = merge(DestReg, psrc1 & op2, dataSize)', \
|
||||
flagCode = genCCFlagBitsLogic)
|
||||
defineMicroRegOp('Sub', \
|
||||
'DestReg = merge(DestReg, psrc1 - op2, dataSize)', \
|
||||
flagCode = genCCFlagBitsSub)
|
||||
defineMicroRegOp('Xor', \
|
||||
'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)', \
|
||||
flagCode = genCCFlagBitsLogic)
|
||||
defineMicroRegOp('Mul1s', '''
|
||||
'''
|
||||
|
||||
class And(LogicRegOp):
|
||||
code = 'DestReg = merge(DestReg, psrc1 & op2, dataSize)'
|
||||
|
||||
class Sub(SubRegOp):
|
||||
code = 'DestReg = merge(DestReg, psrc1 - op2, dataSize)'
|
||||
|
||||
class Xor(LogicRegOp):
|
||||
code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)'
|
||||
|
||||
class Mul1s(FlagRegOp):
|
||||
code = '''
|
||||
int signPos = (dataSize * 8) / 2 - 1;
|
||||
IntReg srcVal1 = psrc1 | (-bits(psrc1, signPos) << signPos);
|
||||
IntReg srcVal2 = op2 | (-bits(psrc1, signPos) << signPos);
|
||||
DestReg = merge(DestReg, srcVal1 * srcVal2, dataSize)
|
||||
''')
|
||||
defineMicroRegOp('Mul1u', '''
|
||||
'''
|
||||
|
||||
class Mul1u(FlagRegOp):
|
||||
code = '''
|
||||
int halfSize = (dataSize * 8) / 2;
|
||||
IntReg srcVal1 = psrc1 & mask(halfSize);
|
||||
IntReg srcVal2 = op2 & mask(halfSize);
|
||||
DestReg = merge(DestReg, srcVal1 * srcVal2, dataSize)
|
||||
''')
|
||||
defineMicroRegOp('Mulel', \
|
||||
'DestReg = merge(DestReg, psrc1 * op2, dataSize)')
|
||||
defineMicroRegOp('Muleh', '''
|
||||
'''
|
||||
|
||||
class Mulel(FlagRegOp):
|
||||
code = 'DestReg = merge(DestReg, psrc1 * op2, dataSize)'
|
||||
|
||||
class Muleh(FlagRegOp):
|
||||
code = '''
|
||||
int halfSize = (dataSize * 8) / 2;
|
||||
uint64_t psrc1_h = psrc1 >> halfSize;
|
||||
uint64_t psrc1_l = psrc1 & mask(halfSize);
|
||||
|
|
@ -545,46 +467,51 @@ let {{
|
|||
((psrc1_h * psrc2_l) >> halfSize) +
|
||||
psrc1_h * psrc2_h;
|
||||
DestReg = merge(DestReg, result, dataSize);
|
||||
''')
|
||||
defineMicroRegOp('Div1', '''
|
||||
'''
|
||||
|
||||
class Div1(FlagRegOp):
|
||||
code = '''
|
||||
int halfSize = (dataSize * 8) / 2;
|
||||
IntReg quotient = (psrc1 / op2) & mask(halfSize);
|
||||
IntReg remainder = (psrc1 % op2) & mask(halfSize);
|
||||
IntReg result = quotient | (remainder << halfSize);
|
||||
DestReg = merge(DestReg, result, dataSize);
|
||||
''')
|
||||
defineMicroRegOp('Divq', '''
|
||||
DestReg = merge(DestReg, psrc1 / op2, dataSize);
|
||||
''')
|
||||
defineMicroRegOp('Divr', '''
|
||||
DestReg = merge(DestReg, psrc1 % op2, dataSize);
|
||||
''')
|
||||
'''
|
||||
|
||||
#
|
||||
# HACK HACK HACK HACK - Put psrc1 in here but make it inert to shut up gcc.
|
||||
#
|
||||
defineMicroRegOp('Mov',
|
||||
'DestReg = merge(SrcReg1, psrc1 * 0 + op2, dataSize)',
|
||||
elseCode='DestReg=DestReg;', cc=True)
|
||||
class Divq(FlagRegOp):
|
||||
code = 'DestReg = merge(DestReg, psrc1 / op2, dataSize);'
|
||||
|
||||
defineMicroRegOp('Movfp',
|
||||
'FpDestReg = FpSrcReg2 + psrc1 * 0 + psrc2 * 0',
|
||||
elseCode='FpDestReg=FpDestReg;', cc=True, doImm=False)
|
||||
class Divr(FlagRegOp):
|
||||
code = 'DestReg = merge(DestReg, psrc1 % op2, dataSize);'
|
||||
|
||||
class Mov(CondRegOp):
|
||||
code = 'DestReg = merge(SrcReg1, op2, dataSize)'
|
||||
else_code = 'DestReg=DestReg;'
|
||||
|
||||
class Movfp(CondRegOp):
|
||||
code = 'FpDestReg = FpSrcReg2'
|
||||
else_code = 'FpDestReg = FpDestReg;'
|
||||
|
||||
# Shift instructions
|
||||
defineMicroRegOp('Sll', '''
|
||||
|
||||
class Sll(FlagRegOp):
|
||||
code = '''
|
||||
uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
|
||||
DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize);
|
||||
''')
|
||||
defineMicroRegOp('Srl', '''
|
||||
'''
|
||||
|
||||
class Srl(FlagRegOp):
|
||||
code = '''
|
||||
uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
|
||||
// Because what happens to the bits shift -in- on a right shift
|
||||
// is not defined in the C/C++ standard, we have to mask them out
|
||||
// to be sure they're zero.
|
||||
uint64_t logicalMask = mask(dataSize * 8 - shiftAmt);
|
||||
DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize);
|
||||
''')
|
||||
defineMicroRegOp('Sra', '''
|
||||
'''
|
||||
|
||||
class Sra(FlagRegOp):
|
||||
code = '''
|
||||
uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
|
||||
// Because what happens to the bits shift -in- on a right shift
|
||||
// is not defined in the C/C++ standard, we have to sign extend
|
||||
|
|
@ -592,8 +519,10 @@ let {{
|
|||
uint64_t arithMask =
|
||||
-bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt);
|
||||
DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize);
|
||||
''')
|
||||
defineMicroRegOp('Ror', '''
|
||||
'''
|
||||
|
||||
class Ror(FlagRegOp):
|
||||
code = '''
|
||||
uint8_t shiftAmt =
|
||||
(op2 & ((dataSize == 8) ? mask(6) : mask(5)));
|
||||
if(shiftAmt)
|
||||
|
|
@ -604,8 +533,10 @@ let {{
|
|||
}
|
||||
else
|
||||
DestReg = DestReg;
|
||||
''')
|
||||
defineMicroRegOp('Rcr', '''
|
||||
'''
|
||||
|
||||
class Rcr(FlagRegOp):
|
||||
code = '''
|
||||
uint8_t shiftAmt =
|
||||
(op2 & ((dataSize == 8) ? mask(6) : mask(5)));
|
||||
if(shiftAmt)
|
||||
|
|
@ -619,8 +550,10 @@ let {{
|
|||
}
|
||||
else
|
||||
DestReg = DestReg;
|
||||
''')
|
||||
defineMicroRegOp('Rol', '''
|
||||
'''
|
||||
|
||||
class Rol(FlagRegOp):
|
||||
code = '''
|
||||
uint8_t shiftAmt =
|
||||
(op2 & ((dataSize == 8) ? mask(6) : mask(5)));
|
||||
if(shiftAmt)
|
||||
|
|
@ -632,8 +565,10 @@ let {{
|
|||
}
|
||||
else
|
||||
DestReg = DestReg;
|
||||
''')
|
||||
defineMicroRegOp('Rcl', '''
|
||||
'''
|
||||
|
||||
class Rcl(FlagRegOp):
|
||||
code = '''
|
||||
uint8_t shiftAmt =
|
||||
(op2 & ((dataSize == 8) ? mask(6) : mask(5)));
|
||||
if(shiftAmt)
|
||||
|
|
@ -649,28 +584,56 @@ let {{
|
|||
}
|
||||
else
|
||||
DestReg = DestReg;
|
||||
''')
|
||||
'''
|
||||
|
||||
defineMicroRegOpWr('Wrip', 'RIP = psrc1 + op2', elseCode="RIP = RIP;")
|
||||
defineMicroRegOpWr('Br', 'nuIP = psrc1 + op2;', elseCode='nuIP = nuIP;')
|
||||
defineMicroRegOpWr('Wruflags', 'ccFlagBits = psrc1 ^ op2')
|
||||
class WrRegOp(RegOp):
|
||||
abstract = True
|
||||
def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"):
|
||||
super(WrRegOp, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize)
|
||||
|
||||
defineMicroRegOpRd('Rdip', 'DestReg = RIP')
|
||||
defineMicroRegOpRd('Ruflags', 'DestReg = ccFlagBits')
|
||||
defineMicroRegOpRdImm('Ruflag', '''
|
||||
class Wrip(WrRegOp, CondRegOp):
|
||||
code = 'RIP = psrc1 + op2'
|
||||
else_code="RIP = RIP;"
|
||||
|
||||
class Br(WrRegOp, CondRegOp):
|
||||
code = 'nuIP = psrc1 + op2;'
|
||||
else_code='nuIP = nuIP;'
|
||||
|
||||
class Wruflags(WrRegOp):
|
||||
code = 'ccFlagBits = psrc1 ^ op2'
|
||||
|
||||
class RdRegOp(RegOp):
|
||||
abstract = True
|
||||
def __init__(self, dest, src1 = "NUM_INTREGS", dataSize="env.dataSize"):
|
||||
super(RdRegOp, self).__init__(dest, src1, "NUM_INTREGS", None, dataSize)
|
||||
|
||||
class Rdip(RdRegOp):
|
||||
code = 'DestReg = RIP'
|
||||
|
||||
class Ruflags(RdRegOp):
|
||||
code = 'DestReg = ccFlagBits'
|
||||
|
||||
class Ruflag(RegOp):
|
||||
code = '''
|
||||
int flag = bits(ccFlagBits, imm8 + 0*psrc1);
|
||||
DestReg = merge(DestReg, flag, dataSize);
|
||||
ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
|
||||
(ccFlagBits & ~EZFBit);
|
||||
''')
|
||||
'''
|
||||
def __init__(self, dest, imm, flags=None, \
|
||||
dataSize="env.dataSize"):
|
||||
super(Ruflag, self).__init__(dest, \
|
||||
"NUM_INTREGS", imm, flags, dataSize)
|
||||
|
||||
defineMicroRegOpImm('Sext', '''
|
||||
class Sext(RegOp):
|
||||
code = '''
|
||||
IntReg val = psrc1;
|
||||
int sign_bit = bits(val, imm8-1, imm8-1);
|
||||
uint64_t maskVal = mask(imm8);
|
||||
val = sign_bit ? (val | ~maskVal) : (val & maskVal);
|
||||
DestReg = merge(DestReg, val, dataSize);
|
||||
''')
|
||||
'''
|
||||
|
||||
defineMicroRegOpImm('Zext', 'DestReg = bits(psrc1, imm8-1, 0);')
|
||||
class Zext(RegOp):
|
||||
code = 'DestReg = bits(psrc1, imm8-1, 0);'
|
||||
}};
|
||||
|
|
|
|||
Loading…
Reference in a new issue