X86: Significantly filled out misc regs.
--HG-- extra : convert_revision : 4c53be6568134d65e57f5411df986fd9a89e82c9
This commit is contained in:
Gabe Black
parent
999328f5ad
commit
efbff349a9
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@ -69,11 +69,11 @@ namespace X86ISA
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case ConditionTests::True:
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return true;
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case ConditionTests::ECF:
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return ccflags.ECF;
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return ccflags.ecf;
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case ConditionTests::EZF:
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return ccflags.EZF;
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return ccflags.ezf;
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case ConditionTests::SZnZF:
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return !(!ccflags.EZF & ccflags.ZF);
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return !(!ccflags.ezf & ccflags.zf);
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case ConditionTests::MSTRZ:
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panic("This condition is not implemented!");
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case ConditionTests::STRZ:
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@ -81,32 +81,32 @@ namespace X86ISA
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case ConditionTests::MSTRC:
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panic("This condition is not implemented!");
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case ConditionTests::STRZnEZF:
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return !ccflags.EZF & ccflags.ZF;
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return !ccflags.ezf & ccflags.zf;
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//And no interrupts or debug traps are waiting
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case ConditionTests::OF:
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return ccflags.OF;
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return ccflags.of;
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case ConditionTests::CF:
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return ccflags.CF;
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return ccflags.cf;
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case ConditionTests::ZF:
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return ccflags.ZF;
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return ccflags.zf;
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case ConditionTests::CvZF:
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return ccflags.CF | ccflags.ZF;
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return ccflags.cf | ccflags.zf;
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case ConditionTests::SF:
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return ccflags.SF;
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return ccflags.sf;
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case ConditionTests::PF:
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return ccflags.PF;
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return ccflags.pf;
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case ConditionTests::SxOF:
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return ccflags.SF ^ ccflags.OF;
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return ccflags.sf ^ ccflags.of;
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case ConditionTests::SxOvZF:
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return ccflags.SF ^ ccflags.OF | ccflags.ZF;
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return ccflags.sf ^ ccflags.of | ccflags.zf;
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case ConditionTests::False:
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return false;
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case ConditionTests::NotECF:
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return !ccflags.ECF;
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return !ccflags.ecf;
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case ConditionTests::NotEZF:
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return !ccflags.EZF;
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return !ccflags.ezf;
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case ConditionTests::NotSZnZF:
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return !ccflags.EZF & ccflags.ZF;
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return !ccflags.ezf & ccflags.zf;
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case ConditionTests::NotMSTRZ:
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panic("This condition is not implemented!");
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case ConditionTests::NotSTRZ:
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@ -114,24 +114,24 @@ namespace X86ISA
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case ConditionTests::NotMSTRC:
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panic("This condition is not implemented!");
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case ConditionTests::STRnZnEZF:
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return !ccflags.EZF & !ccflags.ZF;
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return !ccflags.ezf & !ccflags.zf;
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//And no interrupts or debug traps are waiting
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case ConditionTests::NotOF:
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return !ccflags.OF;
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return !ccflags.of;
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case ConditionTests::NotCF:
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return !ccflags.CF;
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return !ccflags.cf;
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case ConditionTests::NotZF:
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return !ccflags.ZF;
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return !ccflags.zf;
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case ConditionTests::NotCvZF:
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return !(ccflags.CF | ccflags.ZF);
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return !(ccflags.cf | ccflags.zf);
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case ConditionTests::NotSF:
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return !ccflags.SF;
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return !ccflags.sf;
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case ConditionTests::NotPF:
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return !ccflags.PF;
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return !ccflags.pf;
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case ConditionTests::NotSxOF:
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return !(ccflags.SF ^ ccflags.OF);
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return !(ccflags.sf ^ ccflags.of);
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case ConditionTests::NotSxOvZF:
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return !(ccflags.SF ^ ccflags.OF | ccflags.ZF);
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return !(ccflags.sf ^ ccflags.of | ccflags.zf);
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}
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panic("Unknown condition: %d\n", condition);
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return true;
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@ -482,13 +482,13 @@ let {{
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class Adc(FlagRegOp):
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code = '''
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CCFlagBits flags = ccFlagBits;
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DestReg = merge(DestReg, psrc1 + op2 + flags.CF, dataSize);
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DestReg = merge(DestReg, psrc1 + op2 + flags.cf, dataSize);
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'''
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class Sbb(SubRegOp):
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code = '''
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CCFlagBits flags = ccFlagBits;
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DestReg = merge(DestReg, psrc1 - op2 - flags.CF, dataSize);
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DestReg = merge(DestReg, psrc1 - op2 - flags.cf, dataSize);
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'''
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class And(LogicRegOp):
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@ -733,7 +733,7 @@ let {{
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if(shiftAmt)
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{
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CCFlagBits flags = ccFlagBits;
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uint64_t top = flags.CF << (dataSize * 8 - shiftAmt);
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uint64_t top = flags.cf << (dataSize * 8 - shiftAmt);
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if(shiftAmt > 1)
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top |= psrc1 << (dataSize * 8 - shiftAmt - 1);
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uint64_t bottom = bits(psrc1, dataSize * 8, shiftAmt);
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@ -804,7 +804,7 @@ let {{
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{
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CCFlagBits flags = ccFlagBits;
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uint64_t top = psrc1 << shiftAmt;
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uint64_t bottom = flags.CF << (shiftAmt - 1);
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uint64_t bottom = flags.cf << (shiftAmt - 1);
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if(shiftAmt > 1)
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bottom |=
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bits(psrc1, dataSize * 8 - 1,
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@ -117,9 +117,139 @@ namespace X86ISA
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// Flags register
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MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs,
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/*
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* Model Specific Registers
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*/
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// Time stamp counter
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MISCREG_TSC,
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MISCREG_MTRRCAP,
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MISCREG_SYSENTER_CS,
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MISCREG_SYSENTER_ESP,
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MISCREG_SYSENTER_EIP,
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MISCREG_MCG_CAP,
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MISCREG_MCG_STATUS,
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MISCREG_MCG_CTL,
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MISCREG_DEBUG_CTL_MSR,
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MISCREG_LAST_BRANCH_FROM_IP,
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MISCREG_LAST_BRANCH_TO_IP,
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MISCREG_LAST_EXCEPTION_FROM_IP,
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MISCREG_LAST_EXCEPTION_TO_IP,
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MISCREG_MTRR_PHYS_BASE_BASE,
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MISCREG_MTRR_PHYS_BASE_0 = MISCREG_MTRR_PHYS_BASE_BASE,
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MISCREG_MTRR_PHYS_BASE_1,
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MISCREG_MTRR_PHYS_BASE_2,
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MISCREG_MTRR_PHYS_BASE_3,
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MISCREG_MTRR_PHYS_BASE_4,
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MISCREG_MTRR_PHYS_BASE_5,
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MISCREG_MTRR_PHYS_BASE_6,
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MISCREG_MTRR_PHYS_BASE_7,
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MISCREG_MTRR_PHYS_MASK_BASE,
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MISCREG_MTRR_PHYS_MASK_0 = MISCREG_MTRR_PHYS_MASK_BASE,
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MISCREG_MTRR_PHYS_MASK_1,
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MISCREG_MTRR_PHYS_MASK_2,
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MISCREG_MTRR_PHYS_MASK_3,
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MISCREG_MTRR_PHYS_MASK_4,
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MISCREG_MTRR_PHYS_MASK_5,
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MISCREG_MTRR_PHYS_MASK_6,
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MISCREG_MTRR_PHYS_MASK_7,
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MISCREG_MTRR_FIX_64K_00000,
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MISCREG_MTRR_FIX_16K_80000,
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MISCREG_MTRR_FIX_16K_A0000,
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MISCREG_MTRR_FIX_4K_C0000,
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MISCREG_MTRR_FIX_4k_C8000,
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MISCREG_MTRR_FIX_4K_D0000,
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MISCREG_MTRR_FIX_4K_D8000,
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MISCREG_MTRR_FIX_4K_E0000,
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MISCREG_MTRR_FIX_4K_E8000,
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MISCREG_MTRR_FIX_4K_F0000,
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MISCREG_MTRR_FIX_4K_F8000,
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MISCREG_PAT,
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MISCREG_DEF_TYPE,
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MISCREG_MC_CTL_BASE,
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MISCREG_MC0_CTL = MISCREG_MC_CTL_BASE,
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MISCREG_MC1_CTL,
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MISCREG_MC2_CTL,
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MISCREG_MC3_CTL,
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MISCREG_MC4_CTL,
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MISCREG_MC_STATUS_BASE,
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MISCREG_MC0_STATUS = MISCREG_MC_STATUS_BASE,
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MISCREG_MC1_STATUS,
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MISCREG_MC2_STATUS,
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MISCREG_MC3_STATUS,
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MISCREG_MC4_STATUS,
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MISCREG_MC_ADDR_BASE,
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MISCREG_MC0_ADDR = MISCREG_MC_ADDR_BASE,
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MISCREG_MC1_ADDR,
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MISCREG_MC2_ADDR,
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MISCREG_MC3_ADDR,
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MISCREG_MC4_ADDR,
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MISCREG_MC_MISC_BASE,
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MISCREG_MC0_MISC = MISCREG_MC_MISC_BASE,
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MISCREG_MC1_MISC,
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MISCREG_MC2_MISC,
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MISCREG_MC3_MISC,
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MISCREG_MC4_MISC,
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// Extended feature enable register
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MISCREG_EFER,
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MISCREG_STAR,
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MISCREG_LSTAR,
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MISCREG_CSTAR,
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MISCREG_SF_MASK,
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MISCREG_KERNEL_GS_BASE,
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MISCREG_TSC_AUX,
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MISCREG_PERF_EVT_SEL_BASE,
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MISCREG_PERF_EVT_SEL0 = MISCREG_PERF_EVT_SEL_BASE,
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MISCREG_PERF_EVT_SEL1,
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MISCREG_PERF_EVT_SEL2,
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MISCREG_PERF_EVT_SEL3,
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MISCREG_PERF_EVT_CTR_BASE,
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MISCREG_PERF_EVT_CTR0 = MISCREG_PERF_EVT_CTR_BASE,
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MISCREG_PERF_EVT_CTR1,
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MISCREG_PERF_EVT_CTR2,
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MISCREG_PERF_EVT_CTR3,
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MISCREG_SYSCFG,
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MISCREG_IORR_BASE_BASE,
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MISCREG_IORR_BASE0 = MISCREG_IORR_BASE_BASE,
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MISCREG_IORR_BASE1,
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MISCREG_IORR_MASK_BASE,
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MISCREG_IORR_MASK0 = MISCREG_IORR_MASK_BASE,
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MISCREG_IORR_MASK1,
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MISCREG_TOP_MEM,
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MISCREG_TOP_MEM2,
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MISCREG_VM_CR,
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MISCREG_IGNNE,
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MISCREG_SMM_CTL,
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MISCREG_VM_HSAVE_PA,
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/*
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* Segment registers
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*/
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// Segment selectors
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MISCREG_SEG_SEL_BASE,
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MISCREG_ES = MISCREG_SEG_SEL_BASE,
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@ -200,6 +330,66 @@ namespace X86ISA
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return (MiscRegIndex)(MISCREG_DR_BASE + index);
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}
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static inline MiscRegIndex
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MISCREG_MTRR_PHYS_BASE(int index)
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{
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return (MiscRegIndex)(MISCREG_MTRR_PHYS_BASE_BASE + index);
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}
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static inline MiscRegIndex
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MISCREG_MTRR_PHYS_MASK(int index)
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{
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return (MiscRegIndex)(MISCREG_MTRR_PHYS_MASK_BASE + index);
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}
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static inline MiscRegIndex
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MISCREG_MC_CTL(int index)
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{
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return (MiscRegIndex)(MISCREG_MC_CTL_BASE + index);
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}
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static inline MiscRegIndex
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MISCREG_MC_STATUS(int index)
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{
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return (MiscRegIndex)(MISCREG_MC_STATUS_BASE + index);
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}
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static inline MiscRegIndex
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MISCREG_MC_ADDR(int index)
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{
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return (MiscRegIndex)(MISCREG_MC_ADDR_BASE + index);
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}
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static inline MiscRegIndex
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MISCREG_MC_MISC(int index)
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{
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return (MiscRegIndex)(MISCREG_MC_MISC_BASE + index);
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}
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static inline MiscRegIndex
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MISCREG_PERF_EVT_SEL(int index)
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{
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return (MiscRegIndex)(MISCREG_PERF_EVT_SEL_BASE + index);
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}
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static inline MiscRegIndex
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MISCREG_PERF_EVT_CTR(int index)
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{
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return (MiscRegIndex)(MISCREG_PERF_EVT_CTR_BASE + index);
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}
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static inline MiscRegIndex
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MISCREG_IORR_BASE(int index)
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{
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return (MiscRegIndex)(MISCREG_IORR_BASE_BASE + index);
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}
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static inline MiscRegIndex
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MISCREG_IORR_MASK(int index)
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{
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return (MiscRegIndex)(MISCREG_IORR_MASK_BASE + index);
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}
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static inline MiscRegIndex
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MISCREG_SEG_SEL(int index)
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{
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@ -253,54 +443,54 @@ namespace X86ISA
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* plus two flags, EZF and ECF, which are only visible to microcode.
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*/
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BitUnion64(CCFlagBits)
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Bitfield<11> OF;
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Bitfield<7> SF;
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Bitfield<6> ZF;
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Bitfield<5> EZF;
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Bitfield<4> AF;
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Bitfield<3> ECF;
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Bitfield<2> PF;
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Bitfield<0> CF;
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Bitfield<11> of;
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Bitfield<7> sf;
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Bitfield<6> zf;
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Bitfield<5> ezf;
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Bitfield<4> af;
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Bitfield<3> ecf;
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Bitfield<2> pf;
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Bitfield<0> cf;
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EndBitUnion(CCFlagBits)
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/**
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* RFLAGS
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*/
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BitUnion64(RFLAGS)
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Bitfield<21> ID; // ID Flag
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Bitfield<20> VIP; // Virtual Interrupt Pending
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Bitfield<19> VIF; // Virtual Interrupt Flag
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Bitfield<18> AC; // Alignment Check
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Bitfield<17> VM; // Virtual-8086 Mode
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Bitfield<16> RF; // Resume Flag
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Bitfield<14> NT; // Nested Task
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Bitfield<13, 12> IOPL; // I/O Privilege Level
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Bitfield<11> OF; // Overflow Flag
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Bitfield<10> DF; // Direction Flag
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Bitfield<9> IF; // Interrupt Flag
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Bitfield<8> TF; // Trap Flag
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Bitfield<7> SF; // Sign Flag
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Bitfield<6> ZF; // Zero Flag
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Bitfield<4> AF; // Auxiliary Flag
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Bitfield<2> PF; // Parity Flag
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Bitfield<0> CF; // Carry Flag
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Bitfield<21> id; // ID Flag
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Bitfield<20> vip; // Virtual Interrupt Pending
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Bitfield<19> vif; // Virtual Interrupt Flag
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Bitfield<18> ac; // Alignment Check
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Bitfield<17> vm; // Virtual-8086 Mode
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Bitfield<16> rf; // Resume Flag
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Bitfield<14> nt; // Nested Task
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Bitfield<13, 12> iopl; // I/O Privilege Level
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Bitfield<11> of; // Overflow Flag
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Bitfield<10> df; // Direction Flag
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Bitfield<9> intf; // Interrupt Flag
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Bitfield<8> tf; // Trap Flag
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Bitfield<7> sf; // Sign Flag
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Bitfield<6> zf; // Zero Flag
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Bitfield<4> af; // Auxiliary Flag
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Bitfield<2> pf; // Parity Flag
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Bitfield<0> cf; // Carry Flag
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EndBitUnion(RFLAGS)
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/**
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* Control registers
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*/
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BitUnion64(CR0)
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Bitfield<31> PG; // Paging
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Bitfield<30> CD; // Cache Disable
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Bitfield<29> NW; // Not Writethrough
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Bitfield<18> AM; // Alignment Mask
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Bitfield<16> WP; // Write Protect
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Bitfield<5> NE; // Numeric Error
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Bitfield<4> ET; // Extension Type
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Bitfield<3> TS; // Task Switched
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Bitfield<2> EM; // Emulation
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Bitfield<1> MP; // Monitor Coprocessor
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Bitfield<0> PE; // Protection Enabled
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Bitfield<31> pg; // Paging
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Bitfield<30> cd; // Cache Disable
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Bitfield<29> nw; // Not Writethrough
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Bitfield<18> am; // Alignment Mask
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Bitfield<16> wp; // Write Protect
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Bitfield<5> ne; // Numeric Error
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Bitfield<4> et; // Extension Type
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Bitfield<3> ts; // Task Switched
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Bitfield<2> em; // Emulation
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Bitfield<1> mp; // Monitor Coprocessor
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Bitfield<0> pe; // Protection Enabled
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EndBitUnion(CR0)
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// Page Fault Virtual Address
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@ -309,42 +499,217 @@ namespace X86ISA
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EndBitUnion(CR2)
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BitUnion64(CR3)
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Bitfield<51, 12> longPDTB; // Long Mode Page-Directory-Table
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Bitfield<51, 12> longPdtb; // Long Mode Page-Directory-Table
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// Base Address
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Bitfield<31, 12> PDTB; // Non-PAE Addressing Page-Directory-Table
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Bitfield<31, 12> pdtb; // Non-PAE Addressing Page-Directory-Table
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// Base Address
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Bitfield<31, 5> PAEPDTB; // PAE Addressing Page-Directory-Table
|
||||
Bitfield<31, 5> paePdtb; // PAE Addressing Page-Directory-Table
|
||||
// Base Address
|
||||
Bitfield<4> PCD; // Page-Level Cache Disable
|
||||
Bitfield<3> PWT; // Page-Level Writethrough
|
||||
Bitfield<4> pcd; // Page-Level Cache Disable
|
||||
Bitfield<3> pwt; // Page-Level Writethrough
|
||||
EndBitUnion(CR3)
|
||||
|
||||
BitUnion64(CR4)
|
||||
Bitfield<10> OSXMMEXCPT; // Operating System Unmasked
|
||||
Bitfield<10> osxmmexcpt; // Operating System Unmasked
|
||||
// Exception Support
|
||||
Bitfield<9> OSFXSR; // Operating System FXSave/FSRSTOR Support
|
||||
Bitfield<8> PCE; // Performance-Monitoring Counter Enable
|
||||
Bitfield<7> PGE; // Page-Global Enable
|
||||
Bitfield<6> MCE; // Machine Check Enable
|
||||
Bitfield<5> PAE; // Physical-Address Extension
|
||||
Bitfield<4> PSE; // Page Size Extensions
|
||||
Bitfield<3> DE; // Debugging Extensions
|
||||
Bitfield<2> TSD; // Time Stamp Disable
|
||||
Bitfield<1> PVI; // Protected-Mode Virtual Interrupts
|
||||
Bitfield<0> VME; // Virtual-8086 Mode Extensions
|
||||
Bitfield<9> osfxsr; // Operating System FXSave/FSRSTOR Support
|
||||
Bitfield<8> pce; // Performance-Monitoring Counter Enable
|
||||
Bitfield<7> pge; // Page-Global Enable
|
||||
Bitfield<6> mce; // Machine Check Enable
|
||||
Bitfield<5> pae; // Physical-Address Extension
|
||||
Bitfield<4> pse; // Page Size Extensions
|
||||
Bitfield<3> de; // Debugging Extensions
|
||||
Bitfield<2> tsd; // Time Stamp Disable
|
||||
Bitfield<1> pvi; // Protected-Mode Virtual Interrupts
|
||||
Bitfield<0> vme; // Virtual-8086 Mode Extensions
|
||||
EndBitUnion(CR4)
|
||||
|
||||
BitUnion64(CR8)
|
||||
Bitfield<3, 0> TPR; // Task Priority Register
|
||||
EndBitUnion(CR4)
|
||||
Bitfield<3, 0> tpr; // Task Priority Register
|
||||
EndBitUnion(CR8)
|
||||
|
||||
// MTRR capabilities
|
||||
BitUnion64(MTRRcap)
|
||||
Bitfield<7, 0> vcnt; // Variable-Range Register Count
|
||||
Bitfield<8> fix; // Fixed-Range Registers
|
||||
Bitfield<10> wc; // Write-Combining
|
||||
EndBitUnion(MTRRcap)
|
||||
|
||||
/**
|
||||
* SYSENTER configuration registers
|
||||
*/
|
||||
BitUnion64(SysenterCS)
|
||||
Bitfield<15, 0> targetCS;
|
||||
EndBitUnion(SysenterCS)
|
||||
|
||||
BitUnion64(SysenterESP)
|
||||
Bitfield<31, 0> targetESP;
|
||||
EndBitUnion(SysenterESP)
|
||||
|
||||
BitUnion64(SysenterEIP)
|
||||
Bitfield<31, 0> targetEIP;
|
||||
EndBitUnion(SysenterEIP)
|
||||
|
||||
/**
|
||||
* Global machine check registers
|
||||
*/
|
||||
BitUnion64(McgCap)
|
||||
Bitfield<7, 0> count; // Number of error reporting register banks
|
||||
Bitfield<8> MCGCP; // MCG_CTL register present.
|
||||
EndBitUnion(McgCap)
|
||||
|
||||
BitUnion64(McgStatus)
|
||||
Bitfield<0> ripv; // Restart-IP valid
|
||||
Bitfield<1> eipv; // Error-IP valid
|
||||
Bitfield<2> mcip; // Machine check in-progress
|
||||
EndBitUnion(McgStatus)
|
||||
|
||||
BitUnion64(DebugCtlMsr)
|
||||
Bitfield<0> lbr; // Last-branch record
|
||||
Bitfield<1> btf; // Branch single step
|
||||
Bitfield<2> pb0; // Performance monitoring pin control 0
|
||||
Bitfield<3> pb1; // Performance monitoring pin control 1
|
||||
Bitfield<4> pb2; // Performance monitoring pin control 2
|
||||
Bitfield<5> pb3; // Performance monitoring pin control 3
|
||||
/*uint64_t pb(int index)
|
||||
{
|
||||
return bits(__data, index + 2);
|
||||
}*/
|
||||
EndBitUnion(DebugCtlMsr)
|
||||
|
||||
BitUnion64(MtrrPhysBase)
|
||||
Bitfield<7, 0> type; // Default memory type
|
||||
Bitfield<51, 12> physbase; // Range physical base address
|
||||
EndBitUnion(MtrrPhysBase)
|
||||
|
||||
BitUnion64(MtrrPhysMask)
|
||||
Bitfield<11> valid; // MTRR pair enable
|
||||
Bitfield<51, 12> physmask; // Range physical mask
|
||||
EndBitUnion(MtrrPhysMask)
|
||||
|
||||
BitUnion64(MtrrFixed)
|
||||
/*uint64_t type(int index)
|
||||
{
|
||||
return bits(__data, index * 8 + 7, index * 8);
|
||||
}*/
|
||||
EndBitUnion(MtrrFixed)
|
||||
|
||||
BitUnion64(Pat)
|
||||
/*uint64_t pa(int index)
|
||||
{
|
||||
return bits(__data, index * 8 + 2, index * 8);
|
||||
}*/
|
||||
EndBitUnion(Pat)
|
||||
|
||||
BitUnion64(MtrrDefType)
|
||||
Bitfield<7, 0> type; // Default type
|
||||
Bitfield<10> fe; // Fixed range enable
|
||||
Bitfield<11> e; // MTRR enable
|
||||
EndBitUnion(MtrrDefType)
|
||||
|
||||
/**
|
||||
* Machine check
|
||||
*/
|
||||
BitUnion64(McStatus)
|
||||
Bitfield<15,0> mcaErrorCode;
|
||||
Bitfield<31,16> modelSpecificCode;
|
||||
Bitfield<56,32> otherInfo;
|
||||
Bitfield<57> pcc; // Processor-context corrupt
|
||||
Bitfield<58> addrv; // Error-address register valid
|
||||
Bitfield<59> miscv; // Miscellaneous-error register valid
|
||||
Bitfield<60> en; // Error condition enabled
|
||||
Bitfield<61> uc; // Uncorrected error
|
||||
Bitfield<62> over; // Status register overflow
|
||||
Bitfield<63> val; // Valid
|
||||
EndBitUnion(McStatus)
|
||||
|
||||
BitUnion64(McCtl)
|
||||
/*uint64_t en(int index)
|
||||
{
|
||||
return bits(__data, index);
|
||||
}*/
|
||||
EndBitUnion(McCtl)
|
||||
|
||||
// Extended feature enable register
|
||||
BitUnion64(Efer)
|
||||
Bitfield<0> sce; // System call extensions
|
||||
Bitfield<8> lme; // Long mode enable
|
||||
Bitfield<10> lma; // Long mode active
|
||||
Bitfield<11> nxe; // No-execute enable
|
||||
Bitfield<12> svme; // Secure virtual machine enable
|
||||
Bitfield<14> ffxsr; // Fast fxsave/fxrstor
|
||||
EndBitUnion(Efer)
|
||||
|
||||
BitUnion64(Star)
|
||||
Bitfield<31,0> targetEip;
|
||||
Bitfield<47,32> syscallCsAndSs;
|
||||
Bitfield<63,48> sysretCsAndSs;
|
||||
EndBitUnion(Star)
|
||||
|
||||
BitUnion64(SfMask)
|
||||
Bitfield<31,0> mask;
|
||||
EndBitUnion(SfMask)
|
||||
|
||||
BitUnion64(PerfEvtSel)
|
||||
Bitfield<7,0> eventMask;
|
||||
Bitfield<15,8> unitMask;
|
||||
Bitfield<16> usr; // User mode
|
||||
Bitfield<17> os; // Operating-system mode
|
||||
Bitfield<18> e; // Edge detect
|
||||
Bitfield<19> pc; // Pin control
|
||||
Bitfield<20> intEn; // Interrupt enable
|
||||
Bitfield<22> en; // Counter enable
|
||||
Bitfield<23> inv; // Invert mask
|
||||
Bitfield<31,24> counterMask;
|
||||
EndBitUnion(PerfEvtSel)
|
||||
|
||||
BitUnion32(Syscfg)
|
||||
Bitfield<18> mfde; // MtrrFixDramEn
|
||||
Bitfield<19> mfdm; // MtrrFixDramModEn
|
||||
Bitfield<20> mvdm; // MtrrVarDramEn
|
||||
Bitfield<21> tom2; // MtrrTom2En
|
||||
EndBitUnion(Syscfg)
|
||||
|
||||
BitUnion64(IorrBase)
|
||||
Bitfield<3> wr; // WrMem Enable
|
||||
Bitfield<4> rd; // RdMem Enable
|
||||
Bitfield<51,12> physbase; // Range physical base address
|
||||
EndBitUnion(IorrBase)
|
||||
|
||||
BitUnion64(IorrMask)
|
||||
Bitfield<11> v; // I/O register pair enable (valid)
|
||||
Bitfield<51,12> physmask; // Range physical mask
|
||||
EndBitUnion(IorrMask)
|
||||
|
||||
BitUnion64(Tom)
|
||||
Bitfield<51,23> physAddr; // Top of memory physical address
|
||||
EndBitUnion(Tom)
|
||||
|
||||
BitUnion64(VmCrMsr)
|
||||
Bitfield<0> dpd;
|
||||
Bitfield<1> rInit;
|
||||
Bitfield<2> disA20M;
|
||||
EndBitUnion(VmCrMsr)
|
||||
|
||||
BitUnion64(IgnneMsr)
|
||||
Bitfield<0> ignne;
|
||||
EndBitUnion(IgnneMsr)
|
||||
|
||||
BitUnion64(SmmCtlMsr)
|
||||
Bitfield<0> dismiss;
|
||||
Bitfield<1> enter;
|
||||
Bitfield<2> smiCycle;
|
||||
Bitfield<3> exit;
|
||||
Bitfield<4> rsmCycle;
|
||||
EndBitUnion(SmmCtlMsr)
|
||||
|
||||
/**
|
||||
* Segment Selector
|
||||
*/
|
||||
BitUnion64(SegSelector)
|
||||
Bitfield<15, 3> SI; // Selector Index
|
||||
Bitfield<2> TI; // Table Indicator
|
||||
Bitfield<1, 0> RPL; // Requestor Privilege Level
|
||||
Bitfield<15, 3> si; // Selector Index
|
||||
Bitfield<2> ti; // Table Indicator
|
||||
Bitfield<1, 0> rpl; // Requestor Privilege Level
|
||||
EndBitUnion(SegSelector)
|
||||
|
||||
/**
|
||||
|
|
@ -354,39 +719,48 @@ namespace X86ISA
|
|||
BitUnion64(SegDescriptor)
|
||||
Bitfield<63, 56> baseHigh;
|
||||
Bitfield<39, 16> baseLow;
|
||||
Bitfield<55> G; // Granularity
|
||||
Bitfield<54> D; // Default Operand Size
|
||||
Bitfield<54> B; // Default Operand Size
|
||||
Bitfield<53> L; // Long Attribute Bit
|
||||
Bitfield<52> AVL; // Available To Software
|
||||
Bitfield<55> g; // Granularity
|
||||
Bitfield<54> d; // Default Operand Size
|
||||
Bitfield<54> b; // Default Operand Size
|
||||
Bitfield<53> l; // Long Attribute Bit
|
||||
Bitfield<52> avl; // Available To Software
|
||||
Bitfield<51, 48> limitHigh;
|
||||
Bitfield<15, 0> limitLow;
|
||||
Bitfield<47> P; // Present
|
||||
Bitfield<46, 45> DPL; // Descriptor Privilege-Level
|
||||
Bitfield<44> S; // System
|
||||
Bitfield<47> p; // Present
|
||||
Bitfield<46, 45> dpl; // Descriptor Privilege-Level
|
||||
Bitfield<44> s; // System
|
||||
SubBitUnion(type, 43, 40)
|
||||
// Specifies whether this descriptor is for code or data.
|
||||
Bitfield<43> codeOrData;
|
||||
|
||||
// These bit fields are for code segments
|
||||
Bitfield<42> C; // Conforming
|
||||
Bitfield<41> R; // Readable
|
||||
Bitfield<42> c; // Conforming
|
||||
Bitfield<41> r; // Readable
|
||||
|
||||
// These bit fields are for data segments
|
||||
Bitfield<42> E; // Expand-Down
|
||||
Bitfield<41> W; // Writable
|
||||
Bitfield<42> e; // Expand-Down
|
||||
Bitfield<41> w; // Writable
|
||||
|
||||
// This is used for both code and data segments.
|
||||
Bitfield<40> A; // Accessed
|
||||
Bitfield<40> a; // Accessed
|
||||
EndSubBitUnion(type)
|
||||
EndBitUnion(SegDescriptor)
|
||||
|
||||
BitUnion64(SegAttr)
|
||||
Bitfield<0> writable;
|
||||
Bitfield<1> readable;
|
||||
Bitfield<2> expandDown;
|
||||
Bitfield<4, 3> dpl;
|
||||
Bitfield<5> defaultSize;
|
||||
Bitfield<6> longMode;
|
||||
EndBitUnion(SegAttr)
|
||||
|
||||
BitUnion64(GateDescriptor)
|
||||
Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset
|
||||
Bitfield<15, 0> offsetLow; // Target Code-Segment Offset
|
||||
Bitfield<31, 16> selector; // Target Code-Segment Selector
|
||||
Bitfield<47> P; // Present
|
||||
Bitfield<46, 45> DPL; // Descriptor Privilege-Level
|
||||
Bitfield<47> p; // Present
|
||||
Bitfield<46, 45> dpl; // Descriptor Privilege-Level
|
||||
Bitfield<43, 40> type;
|
||||
Bitfield<36, 32> count; // Parameter Count
|
||||
EndBitUnion(GateDescriptor)
|
||||
|
|
|
|||
|
|
@ -257,7 +257,7 @@ namespace X86ISA
|
|||
|
||||
typedef int RegContextVal;
|
||||
|
||||
typedef uint8_t RegIndex;
|
||||
typedef uint16_t RegIndex;
|
||||
};
|
||||
|
||||
#endif // __ARCH_X86_TYPES_HH__
|
||||
|
|
|
|||
Loading…
Reference in a new issue