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X86: Move a comment to be next to the code it describes.

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--HG--
extra : convert_revision : c384391175babb7cfdd3885ae9d9f1a9405ea44f
This commit is contained in:
Gabe Black 2007-09-10 11:01:52 -07:00
parent 3e65e1d0e0
commit 8e7bca8b36
1 changed files with 5 additions and 5 deletions
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10
src/arch/x86/isa/microops/regop.isa
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@ -460,6 +460,11 @@ let {{
class Xor(LogicRegOp):
code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)'
# Neither of these is quite correct because it assumes that right shifting
# a signed or unsigned value does sign or zero extension respectively.
# The C standard says that what happens on a right shift with a 1 in the
# MSB position is undefined. On x86 and under likely most compilers the
# "right thing" happens, but this isn't a guarantee.
class Mul1s(WrRegOp):
code = '''
ProdLow = psrc1 * op2;
@ -489,11 +494,6 @@ let {{
class Mulel(RdRegOp):
code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);'
# Neither of these is quite correct because it assumes that right shifting
# a signed or unsigned value does sign or zero extension respectively.
# The C standard says that what happens on a right shift with a 1 in the
# MSB position is undefined. On x86 and under likely most compilers the
# "right thing" happens, but this isn't a guarantee.
class Muleh(RdRegOp):
def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"):
if not src1: