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Author SHA1 Message Date
Gabe Black 23ba9c7b96 ARM: Fix vcvtr so that it uses the rounding mode in the FPSCR. 2010-06-02 12:58:15 -05:00
Gabe Black 1fda944716 ARM: Fix saturation of VCVT from fp to integer. 2010-06-02 12:58:15 -05:00
Gabe Black 347ab6c704 ARM: Compensate for ARM's underflow coming from -before- rounding, but x86's after. 2010-06-02 12:58:15 -05:00
Gabe Black fd82a47b96 ARM: Implement flush to zero for destinations as well. 2010-06-02 12:58:15 -05:00
Gabe Black 186273e5f3 ARM: Fix up nans to match ARM's expected behavior. 2010-06-02 12:58:15 -05:00
Gabe Black 98e2315f1c ARM: Set the value of the MVFR0 and MVFR1 registers. 2010-06-02 12:58:15 -05:00
Gabe Black 8466999aef ARM: Implement flush to zero mode for VFP, and clean up some corner cases. 2010-06-02 12:58:15 -05:00
Gabe Black efbceff96a ARM: Add barriers that make sure FP operations happen where they're supposed to. 2010-06-02 12:58:15 -05:00
Gabe Black 1b3b75ee68 ARM: Implement the version of VCVT float to int that rounds towards zero. 2010-06-02 12:58:15 -05:00
Gabe Black aa05e5401c ARM: Implement the floating/fixed point VCVT instructions. 2010-06-02 12:58:15 -05:00
Gabe Black 86a1093992 ARM: Add code to extract and record VFP exceptions. 2010-06-02 12:58:14 -05:00
Gabe Black e478df35f5 ARM: Implement the VFP version of VCMP. 2010-06-02 12:58:14 -05:00
Gabe Black c1f7bf7f0e ARM: Add support for VFP vector mode. 2010-06-02 12:58:14 -05:00
Gabe Black f245f4937b ARM: Introduce new VFP base classes that are optionally microops. 2010-06-02 12:58:14 -05:00
Gabe Black 41012d2418 ARM: Implement VCVT between double and single width FP. 2010-06-02 12:58:14 -05:00
Gabe Black a430f749ce ARM: Implement vcvt between int and fp. Ignore rounding. 2010-06-02 12:58:14 -05:00
Gabe Black a9d1de4769 ARM: Consolidate the VFP register index computation code. 2010-06-02 12:58:14 -05:00
Gabe Black 80fa3a7ccf ARM: Implement the VFP negated multiplies. 2010-06-02 12:58:14 -05:00
Gabe Black 3111a62169 ARM: Implement the VFP versions of VMLA and VMLS. 2010-06-02 12:58:14 -05:00
Gabe Black 90d70a22cb ARM: Implement the VFP version of vdiv and vsqrt. 2010-06-02 12:58:14 -05:00
Gabe Black cc665240a4 ARM: Implement the VFP version of vsub. 2010-06-02 12:58:14 -05:00
Gabe Black 44759669aa ARM: Implement the VFP version of vadd. 2010-06-02 12:58:14 -05:00
Gabe Black 9e32ff3491 ARM: Implement the VFP version of vabs. 2010-06-02 12:58:14 -05:00
Gabe Black cd0a6a1303 ARM: Implement the VFP version of vneg. 2010-06-02 12:58:14 -05:00
Gabe Black 65f5204325 ARM: Implement the VFP version of vmul. 2010-06-02 12:58:14 -05:00
Gabe Black 19e05d7e8d ARM: Move the VFP data operation decode into a function. 2010-06-02 12:58:14 -05:00
Gabe Black 527b735cfc ARM: Implement and update the DFSR and IFSR registers on faults. 2010-06-02 12:58:14 -05:00
Gabe Black 4491170df6 ARM: Make integer division by zero return a fault. 2010-06-02 12:58:13 -05:00
Gabe Black cd86e34187 ARM: Add in some missing SCTLR fields. 2010-06-02 12:58:13 -05:00
Gabe Black c5a8a1d673 ARM: Decode ARM unconditional MRC and MCR instructions. 2010-06-02 12:58:13 -05:00
Gabe Black 98fe7b0fbe ARM: Move the CP15 decode block into a function. 2010-06-02 12:58:13 -05:00
Gabe Black 5d9191a428 ARM: Decode the unconditional version of ARM fp instructions. 2010-06-02 12:58:13 -05:00
Gabe Black 81b7c3d264 ARM: Move the FP decode blocks into functions. 2010-06-02 12:58:13 -05:00
Gabe Black e21f93702a ARM: Warn/ignore when TLB maintenance operations are performed. 2010-06-02 12:58:13 -05:00
Gabe Black eac239b4d6 ARM: Handle accesses to TLBTR. 2010-06-02 12:58:13 -05:00
Gabe Black 9fb573d91e ARM: Handle accesses to the DACR. 2010-06-02 12:58:13 -05:00
Gabe Black 951b7edaba ARM: Handle accesses to TTBR0 and TTBR1. 2010-06-02 12:58:13 -05:00
Gabe Black b5cfa9361b ARM: Convert the CP15 registers from MPU to MMU. 2010-06-02 12:58:13 -05:00
Ali Saidi 556ea0ee57 ARM: Add some support for wfi/wfe/yield/etc 2010-06-02 12:58:13 -05:00
Ali Saidi 5e6d28996a ARM: Move PC mode bits around so they can be used for exectrace 2010-06-02 12:58:13 -05:00
Ali Saidi aec73ba6af ARM: Add a traceflag to print cpsr 2010-06-02 12:58:13 -05:00
Ali Saidi 65a5177b53 ARM: Undef instruction on invalid user CP15 access 2010-06-02 12:58:13 -05:00
Gabe Black 2e4ddbd234 ARM: Decode the VSTR instruction. 2010-06-02 12:58:12 -05:00
Gabe Black 6106bd18cd ARM: Implement the vstr instruction. 2010-06-02 12:58:12 -05:00
Ali Saidi f64c8bafd2 ARM: BXJ should be BX when there is no J support 2010-06-02 12:58:12 -05:00
Gabe Black 1fcd389fa3 ARM: Make sure macroops aren't interrupted midinstruction. 
Do this by setting the delayed commit flag for all but the last microop.
 2010-06-02 12:58:12 -05:00
Gabe Black 67766cbf17 ARM: Fix the implementation of the VFP ldm and stm macroops. 
There were four bugs in these instructions. First, the loaded value was being
stored into a floating point register as floating point, changing the value as
it was transfered. Second, the meaning of the "up" bit had been reversed.
Third, the statically sized microop array wasn't bit enough for all possible
inputs. It's now dynamically sized and should always be big enough. Fourth,
the offset was stored as an unsigned 8 bit value. Negative offsets would look
like moderately large positive offsets.
 2010-06-02 12:58:12 -05:00
Gabe Black ad9c5af945 ARM: Fix up thumb decoding of coproc instructions. 2010-06-02 12:58:12 -05:00
Gabe Black dea707704f ARM: Clean up some redundancy and fault behavior for unimplemented thumb MCR, MRC. 2010-06-02 12:58:12 -05:00
Gabe Black 943b77b9bb ARM: Decode the VLDR instruction. 2010-06-02 12:58:12 -05:00
Gabe Black 4f130683e0 ARM: Implement the VLDR instruction. 2010-06-02 12:58:12 -05:00
Gabe Black dbec303864 ARM: Decode all the various forms of vmov. 2010-06-02 12:58:12 -05:00
Gabe Black ff3996b24d ARM: Make VFP load/store and 64 bit move decode correspond with CP10 and CP11. 2010-06-02 12:58:12 -05:00
Gabe Black dd1aedc98b ARM: Implement the various versions of VMOV. 2010-06-02 12:58:12 -05:00
Gabe Black 1f059541d6 ARM: Add a new RegImmOp base class. 2010-06-02 12:58:12 -05:00
Gabe Black 6976b4890a ARM: Add a RegRegImmOp base class. 2010-06-02 12:58:12 -05:00
Gabe Black 186cfe3ae3 ARM: Widen the immediate fields in the misc instruction classes. 2010-06-02 12:58:12 -05:00
Gabe Black b87ebf382f ARM: Add a function to decode VFP modified immediate constants. 2010-06-02 12:58:12 -05:00
Gabe Black 7eb4d02dd9 ARM: Add a function to decode SIMD modified immediate constants. 2010-06-02 12:58:12 -05:00
Gabe Black abda50173c ARM: Add fp operands to operands.isa. 2010-06-02 12:58:12 -05:00
Gabe Black 6365d29c21 ARM: Decode the VMRS instruction. 2010-06-02 12:58:11 -05:00
Gabe Black fbf2ad5ae8 ARM: Update the set of FP related miscregs. 2010-06-02 12:58:11 -05:00
Gabe Black aade63a8fe ARM: Implement the VMRS instruction. 2010-06-02 12:58:11 -05:00
Gabe Black a8b56b452c ARM: Decode the VMSR instruction. 2010-06-02 12:58:11 -05:00
Gabe Black 06008c54eb ARM: Implement the VMSR instruction. 2010-06-02 12:58:11 -05:00
Gabe Black 0ff71c7c34 ARM: Decode 8, 16, and 32 bit transfers between core and extension (fp) registers. 2010-06-02 12:58:11 -05:00
Gabe Black c9c4dfc09d ARM: Ignore attempts to disable coprocessors that aren't implemented anyway. 2010-06-02 12:58:11 -05:00
Gabe Black c3bf29bbea ARM: Implement the udiv instruction. 2010-06-02 12:58:11 -05:00
Gabe Black f3e65c2de2 ARM: Implement the sdiv instruction. 2010-06-02 12:58:11 -05:00
Gabe Black 5943f0fc84 ARM: Ignore writing a bad mode to CPSR with MSR. 2010-06-02 12:58:11 -05:00
Gabe Black ba33db8fd6 ARM: Decode the CPS instruction. 2010-06-02 12:58:11 -05:00
Gabe Black 7861b084f6 ARM: Implement the CPS instruction. 2010-06-02 12:58:11 -05:00
Gabe Black eb1447302d ARM: Decode the SRS instruction. 2010-06-02 12:58:11 -05:00
Gabe Black bb6fea91da ARM: Implement the SRS instruction. 2010-06-02 12:58:11 -05:00
Gabe Black dbee6e0c54 ARM: Add a base class for SRS. 2010-06-02 12:58:11 -05:00
Gabe Black 239c9af90d ARM: Implement a badMode function that says whether a mode is legal. 2010-06-02 12:58:11 -05:00
Gabe Black a5ea52bb45 ARM: Allow flattening into any mode. 2010-06-02 12:58:11 -05:00
Gabe Black 698ee26c6b ARM: Decode TBB and TBH. 2010-06-02 12:58:11 -05:00
Gabe Black 6fa713a66c ARM: Decode the setend instruction. 2010-06-02 12:58:11 -05:00
Gabe Black 4683cd1655 ARM: Define the setend instruction. 2010-06-02 12:58:10 -05:00
Gabe Black fb23297914 ARM: Make a base class for instructions that use only an immediate. 2010-06-02 12:58:10 -05:00
Gabe Black 247acd93c4 ARM: Decode the arm version of ldrexd. 2010-06-02 12:58:10 -05:00
Gabe Black 3ad31f61c2 ARM: Decode the strex instructions. 2010-06-02 12:58:10 -05:00
Gabe Black 54ab07e636 ARM: Implement the strex instructions. 2010-06-02 12:58:10 -05:00
Gabe Black 524a8195e1 ARM: Set CPSR.E to SCTLR.EE on faults. 2010-06-02 12:58:10 -05:00
Gabe Black 683421e0c6 ARM: Warn about not implementing MPU translation, not panic about MMU. 
We'll start out with a stbu version of PMSA and switch over to VMSA for the
full implementation.
 2010-06-02 12:58:10 -05:00
Gabe Black 6fb5189c47 ARM: Ignore/warn on accesses to the DRBAR, DRACR, and DRSR registers. 2010-06-02 12:58:10 -05:00
Gabe Black 89b1dd5582 ARM: Allow access to the RGNR register. 2010-06-02 12:58:10 -05:00
Gabe Black c3381167c9 ARM: Make the MPUIR register report that 1 unified data region is supported. 2010-06-02 12:58:10 -05:00
Gabe Black 3aa8faf177 ARM: Ignore/warn on accesses to the BPIALLIS and BPIALL registers. 2010-06-02 12:58:10 -05:00
Gabe Black faf6c727f6 ARM: Respect the E bit of the CPSR when doing loads and stores. 2010-06-02 12:58:10 -05:00
Gabe Black b6cb6f1874 ARM: Zero the micropc when vectoring to a fault. 2010-06-02 12:58:10 -05:00
Gabe Black 1d5233958a ARM: Implement the V7 version of alignment checking. 2010-06-02 12:58:10 -05:00
Gabe Black 7b397925af ARM: Decode the RFE instruction. 2010-06-02 12:58:10 -05:00
Gabe Black a2cb503ba6 ARM: Implement the RFE instruction. 2010-06-02 12:58:10 -05:00
Gabe Black ec4cd00b11 ARM: Add a base class for the RFE instruction. 2010-06-02 12:58:10 -05:00
Gabe Black 1ada9d4880 ARM: Make sure some undefined thumb32 instructions fault. 2010-06-02 12:58:10 -05:00
Gabe Black 3caa75d53a ARM: Squash the low order bits of the PC when performing a regular branch. 2010-06-02 12:58:10 -05:00
Gabe Black 36eeee0133 ARM: When changing the CPSR and branching, make sure the branch is second. 2010-06-02 12:58:09 -05:00
Gabe Black 68f2908a70 ARM: Ignore/warn when CSSELR or CCSIDR are accessed. 
These registers provide information about the caches. Since we can't provide
that information, these will be harmlessly inert.
 2010-06-02 12:58:09 -05:00
Gabe Black 741b243260 ARM: Ignore/warn access to the bpimva registers. 2010-06-02 12:58:09 -05:00
Gabe Black 8a7f60194e ARM: Ignore/warn on accesses to the dccmvac register. 2010-06-02 12:58:09 -05:00
Gabe Black 89133b15da ARM: Decode the enterx and leavex instructions. 2010-06-02 12:58:09 -05:00
Gabe Black 6a4ea7cca9 ARM: Implement the enterx and leavex instructions. 
These enter and leave thumbEE mode. Currently thumbEE mode behaves exactly the
same as Thumb mode, but at least this will make it -look- like we're enter and
leaving it. The actual behavioral changes will be implemented in future
changes.
 2010-06-02 12:58:09 -05:00
Gabe Black eb0823c4f2 ARM: Fix the implementation of BX to work in thumbEE mode. 2010-06-02 12:58:09 -05:00
Gabe Black bb0d390105 ARM: When an instruction is intentionally undefined, fault on it. 2010-06-02 12:58:09 -05:00
Gabe Black 61a5e71be7 ARM: Decode the thumb version of the ldrd and strd instructions. 2010-06-02 12:58:09 -05:00
Gabe Black 9d4a1bf2ba ARM: Explicitly keep track of the second destination for double loads/stores. 2010-06-02 12:58:09 -05:00
Gabe Black 28023f6f3d ARM: Decode the thumb32 load byte/memory hint instructions. 2010-06-02 12:58:09 -05:00
Gabe Black 7a9dcdf99f ARM: Decode the load halfword, memory hints instructions for 32 bit Thumb. 2010-06-02 12:58:09 -05:00
Gabe Black a483d44d9f ARM: Ignore/warn on accesses to icimvau. 2010-06-02 12:58:09 -05:00
Gabe Black 630f309a77 ARM: Ignore/warn on iciallu. 2010-06-02 12:58:09 -05:00
Gabe Black d618121670 ARM: Ignore/warn on ICIALLUIS. 2010-06-02 12:58:09 -05:00
Gabe Black e658b6fed4 ARM: Add support for the clidr register. 
This register will always report 0 caches as implemented. It's not clear how
to find out how many there really are when dealing with an arbitrary
hierarchy.
 2010-06-02 12:58:09 -05:00
Gabe Black 896c7617c4 ARM: Decode the unimplemented data barrier CP15 accesses. 
These are CP15DSB (Data Synchronization Barrier), and CP15DMB (Data Memory
Barrier).
 2010-06-02 12:58:09 -05:00
Gabe Black af6b1667e9 ARM: Implement a stub of CPACR. 
This register controls access to the coprocessors. This doesn't actually
implement it, it allows writes which don't turn anything off. In other words,
it allows the simulated program to ask for what it already has.
 2010-06-02 12:58:09 -05:00
Gabe Black 660270746b ARM: Actually write the value of sctlr in ISA.clear(). 2010-06-02 12:58:08 -05:00
Gabe Black 6c9ab5d898 ARM: Replace the ARM decode of CP15 MCR and MRC instructions. 2010-06-02 12:58:08 -05:00
Gabe Black 35f0c01fea ARM: Decode the unimplemented cp15 instruction barrier. 2010-06-02 12:58:08 -05:00
Gabe Black 7932b86298 ARM: Ignore accesses to DCCIMVAC. 2010-06-02 12:58:08 -05:00
Gabe Black 6ae4d34a12 ARM: Allow accesses to the software thread id registers. 2010-06-02 12:58:08 -05:00
Gabe Black 54850e4d23 ARM: Allow accesses to the contextidr register. 2010-06-02 12:58:08 -05:00
Gabe Black 221e0ac523 ARM: Warn about and ignore accesses to DCCISW. 
This register is supposed to "Clean and invalidate data or unified cache line
by set/way." Since there isn't a good way to do that, we'll just ignore these
and warn about it.
 2010-06-02 12:58:08 -05:00
Gabe Black 8c1be04af6 ARM: Decode the thumb versions of the mcr and mrc instructions. 2010-06-02 12:58:08 -05:00
Gabe Black 625a43e7c7 ARM: Implement the mrc and mcr instructions. 2010-06-02 12:58:08 -05:00
Gabe Black 6c1b10043f ARM: Rename the RevOp base class to something more generic. 2010-06-02 12:58:08 -05:00
Gabe Black f9d1bba22a ARM: Add a version of the Dest and Op1 operands for accessing the MiscRegs. 2010-06-02 12:58:08 -05:00
Gabe Black 6aa229386d ARM: Implement a function to decode CP15 registers to MiscReg indices. 2010-06-02 12:58:08 -05:00
Gabe Black 7ff24c8777 ARM: Decode the bfi and bfc instructions. 2010-06-02 12:58:08 -05:00
Gabe Black a37b6b6bce ARM: Implement the bfc and bfi instructions. 2010-06-02 12:58:08 -05:00
Gabe Black 5a63887617 ARM: Decode the ubfx and sbfx instructions. 2010-06-02 12:58:08 -05:00
Gabe Black 2e717558e2 ARM: Decode miscellaneous arm mode media instructions. 2010-06-02 12:58:08 -05:00
Gabe Black 09cc401848 ARM: Implement the ubfx and sbfx instructions. 2010-06-02 12:58:08 -05:00
Gabe Black b1158e4938 ARM: Add a register, immediate, immediate to register base for [su]bfx. 2010-06-02 12:58:08 -05:00
Gabe Black 504ac6518b ARM: Decode the clz instruction. 2010-06-02 12:58:08 -05:00
Gabe Black 2c94bf7f30 ARM: Implement the clz instruction. 2010-06-02 12:58:08 -05:00
Gabe Black 00320a53ab ARM: Decode the rbit instruction. 2010-06-02 12:58:07 -05:00
Gabe Black 5cc1bb6842 ARM: Implement the rbit instruction. 2010-06-02 12:58:07 -05:00
Gabe Black 566b2ff20c ARM: Decode the nop instruction. 2010-06-02 12:58:07 -05:00
Gabe Black b9cfe9a3db ARM: Implement nop. 2010-06-02 12:58:07 -05:00
Gabe Black a2d8dcebba ARM: Decode the ldrex instruction. 2010-06-02 12:58:07 -05:00
Gabe Black 952253483b ARM: Rearrange the load/store double/exclusive, table branch thumb decoding. 2010-06-02 12:58:07 -05:00
Gabe Black f7f75ad053 ARM: Implement the ldrex instruction. 2010-06-02 12:58:07 -05:00
Gabe Black 00baeb742d ARM: Decode the usad8 and usada8 instructions. 2010-06-02 12:58:07 -05:00
Gabe Black 8f566e5ee3 ARM: Implement the usad8 and usada8 instructions. 2010-06-02 12:58:07 -05:00
Gabe Black c643b1c274 ARM: Add a base class to support usada8. 2010-06-02 12:58:07 -05:00
Gabe Black 64ade8316e ARM: Decode the sel instruction. 2010-06-02 12:58:07 -05:00
Gabe Black 7fa6835a0c ARM: Implement the sel instruction. 2010-06-02 12:58:07 -05:00
Gabe Black 498f9d925e ARM: Add a base class for the sel instruction. 2010-06-02 12:58:07 -05:00
Gabe Black f581fd3f89 ARM: Decode pkh instructions. 2010-06-02 12:58:07 -05:00
Gabe Black 9ffc5e2ae6 ARM: Implement the pkh instruction. 2010-06-02 12:58:07 -05:00
Gabe Black c4d09747a5 ARM: Decode the sign/zero extend instructions. 2010-06-02 12:58:07 -05:00
Gabe Black 69365876d8 ARM: Implement zero/sign extend instructions. 2010-06-02 12:58:07 -05:00
Gabe Black 554fb3774e ARM: Add a base class for extend and add instructions. 2010-06-02 12:58:07 -05:00
Gabe Black cb2e3b0ace ARM: Generalize the saturation instruction bases for use in other instructions. 2010-06-02 12:58:07 -05:00
Gabe Black a1208aa66d ARM: Decode the 8/16 bit signed/unsigned add/subtract half instructions. 2010-06-02 12:58:07 -05:00
Gabe Black cabf766a06 ARM: Implement the 8/16 bit signed/unsigned add/subtract half instructions. 2010-06-02 12:58:06 -05:00
Gabe Black 82614b6f3a ARM: Fix signed most significant multiply instructions. 2010-06-02 12:58:06 -05:00
Gabe Black 3cff58602a ARM: Fix multiply overflow flag setting. 2010-06-02 12:58:06 -05:00
Gabe Black 90c2284714 ARM: Decode the saturation instructions. 2010-06-02 12:58:06 -05:00
Gabe Black 61b8e33225 ARM: Implement the saturation instructions. 2010-06-02 12:58:06 -05:00
Gabe Black c96f03a250 ARM: Implement base classes for the saturation instructions. 2010-06-02 12:58:06 -05:00
Gabe Black 0aff168f1a ARM: Decode the signed add/subtract and subtract/add instructions. 2010-06-02 12:58:06 -05:00
Gabe Black 8ba812f1fb ARM: Implement signed add/subtract and subtract/add. 2010-06-02 12:58:06 -05:00
Gabe Black a895514d35 ARM: Decode the unsigned 8 and 16 bit add and subtract instructions. 2010-06-02 12:58:06 -05:00
Gabe Black 3f12eb02ab ARM: Implement the unsigned 8 bit and 16 bit vector adds and subtracts. 2010-06-02 12:58:06 -05:00
Gabe Black 29acf9516c ARM: Decode the unsigned saturating instructions. 2010-06-02 12:58:06 -05:00
Gabe Black be888e67e7 ARM: Implement the unsigned saturating instructions. 2010-06-02 12:58:06 -05:00
Gabe Black 5495ebd68d ARM: Decode the ssub instructions. 2010-06-02 12:58:06 -05:00
Gabe Black fd6e9f304e ARM: Implement the ssub instructions. 2010-06-02 12:58:06 -05:00
Gabe Black bcf0454864 ARM: Decode the SADD8 and SADD16 instructions. 2010-06-02 12:58:06 -05:00
Gabe Black 87975aa691 ARM: Implement the SADD8 and SADD16 instructions. 2010-06-02 12:58:06 -05:00
Gabe Black d70c31437a ARM: Support instructions that set the GE bits when they write the condition codes. 2010-06-02 12:58:06 -05:00
Gabe Black e32aaefe8c ARM: Decode 32 bit thumb data processing register instructions. 2010-06-02 12:58:06 -05:00
Gabe Black f19b605aed ARM: Decode the 16 bit thumb versions of the REV* instructions. 2010-06-02 12:58:06 -05:00
Gabe Black 15356af288 ARM: Decode the ARM version of the REV* instructions. 2010-06-02 12:58:05 -05:00
Gabe Black 59c726b6f4 ARM: Pull decoding of ARM pack, unpack, saturate and reverse instructions into a format. 2010-06-02 12:58:05 -05:00
Gabe Black aa8493d7d1 ARM: Implement the REV* instructions. 2010-06-02 12:58:05 -05:00
Gabe Black c981a4de2b ARM: Add base classes suitable for the REV* instructions. 2010-06-02 12:58:05 -05:00
Gabe Black 57443a2144 ARM: Make LDM that loads the PC perform an interworking branch. 2010-06-02 12:58:05 -05:00
Gabe Black 1344fc2668 ARM: Decode the swp and swpb instructions. 2010-06-02 12:58:05 -05:00
Gabe Black e157b1f52a ARM: Implement the swp and swpb instructions. 2010-06-02 12:58:05 -05:00
Gabe Black 1884ed65bd ARM: Decode MRS and MSR for thumb. 2010-06-02 12:58:05 -05:00
Gabe Black ff3b21bc2b ARM: Replace the versions of MRS and MSR in the ARM decoder with the new ones. 2010-06-02 12:58:05 -05:00
Gabe Black f0811eb208 ARM: Define versions of MSR and MRS outside the decoder. 2010-06-02 12:58:05 -05:00
Gabe Black f61bb9adb9 ARM: Hook up the push/pop versions of stm/ldm in thumb. 2010-06-02 12:58:05 -05:00
Gabe Black a76ab8e040 ARM: Hook SVC into the thumb decoder. 2010-06-02 12:58:05 -05:00
Gabe Black cbdebf852e ARM: Implement SVC (was SWI) outside of the decoder. 2010-06-02 12:58:05 -05:00
Gabe Black 34032f97d6 ARM: Trigger system calls from the SupervisorCall invoke method. 
This simplifies the decoder slightly, and makes the system call mechanism
very slightly more realistic.
 2010-06-02 12:58:05 -05:00
Gabe Black 52460938cb ARM: Fix multiply operations. 
These fixes were provided by Ali and fix the saturation condition code and
various multiply instructions.
 2010-06-02 12:58:05 -05:00
Gabe Black 4fb6fcd82d ARM: Decode the scalar saturating add/subtract instructions. 2010-06-02 12:58:05 -05:00
Gabe Black 30dd622622 ARM: Decode the parallel add and subtract instructions. 2010-06-02 12:58:05 -05:00
Gabe Black 62e8487d57 ARM: Implement signed saturating add and/or subtract instructions. 2010-06-02 12:58:05 -05:00
Gabe Black a1253ec644 ARM: Implemented prefetch instructions/decoding (pli, pld, pldw). 2010-06-02 12:58:05 -05:00
Gabe Black 61b00d3224 ARM: Decode unconditional ARM instructions. 2010-06-02 12:58:04 -05:00
Gabe Black b6e2f5d33f ARM: Make sure ldm exception return writes back its base in the right mode. 
This change moves the writeback of load multiple instructions to the beginning
of the macroop. That way, the MicroLdrRetUop that changes the mode will
necessarily happen later, ensuring the writeback happens in the original mode.
The actual value in the base register if it also shows up in the register list
is undefined, so it's fine if it gets clobbered by one of the loads. For
stores where the base register is the lowest numbered in the register list,
the original value should be written back. That means stores can't write back
at the beginning, but the mode changing problem doesn't affect them so they
can continue to write back at the end.
 2010-06-02 12:58:04 -05:00
Gabe Black 89060f1fd8 ARM: Rework how unrecognized/unimplemented instructions are handled. 
Instead of panic immediately when these instructions are executed, an
UndefinedInstruction fault is returned. In FS mode (not currently
implemented), this is the fault that should, to my knowledge, be triggered in
these situations and should be handled using the normal architected
mechanisms. In SE mode, the fault causes a panic when it's invoked that gives
the same information as the instruction did. When/if support for speculative
execution of ARM is supported, this will allow a mispeculated and unrecognized
and/or unimplemented instruction from causing a panic. Only once the
instruction is going to be committed will the fault be invoked, triggering the
panic.
 2010-06-02 12:58:04 -05:00
Gabe Black aa45fafb2e ARM: Add support for "SUBS PC, LR and related instructions". 2010-06-02 12:58:04 -05:00
Gabe Black 2419903dc0 ARM: Make ldrs into the PC and ldm exception return do interworking branches. 2010-06-02 12:58:04 -05:00
Gabe Black 28227440a7 ARM: Align the PC when using it as the base for a load. 2010-06-02 12:58:04 -05:00
Gabe Black d63f748b53 ARM: Implement ADR as separate from ADD. 2010-06-02 12:58:04 -05:00
Gabe Black e92dc21fde ARM: Add support for interworking branch ALU instructions. 2010-06-02 12:58:04 -05:00
Gabe Black 11c3361be4 ARM: Fix when the flag bits are updated for thumb. 2010-06-02 12:58:04 -05:00
Gabe Black 14d25fbad0 ARM: Don't rely on undefined behavior to get arithmetic right shift. 
Shifting to the right of a signed value when the MSB is one is technically
undefined behavior, even though in my experience it's done the "right thing"
and sign extended the value. This replaces the arithmetic right shift code in
ARM that uses that coincidence with some code that relies on bit math.
 2010-06-02 12:58:04 -05:00
Gabe Black 05d880f7a1 ARM: Restrict the shift amount from a register to 8 bits. 
The shift amount when taken from a register is supposed to be truncated to an
8 bit value.
 2010-06-02 12:58:04 -05:00
Gabe Black 9ebaf8ecd5 ARM: Define the VFP load/store multiple instructions. 2010-06-02 12:58:04 -05:00
Gabe Black 3f83094af2 ARM: Decode the VFP load/store multiple instructions. 2010-06-02 12:58:04 -05:00
Gabe Black 647edea970 ARM: Fix the constant describing the number of floating point registers. 2010-06-02 12:58:04 -05:00
Gabe Black 2f3102f1ef ARM: Add templates for VFP load/store multiple instructions. 2010-06-02 12:58:04 -05:00
Gabe Black 739f23c64c ARM: Add base classes for VFP load/store multiple. 2010-06-02 12:58:04 -05:00
Gabe Black cb631d87c3 ARM: Add floating point load/store microops. 2010-06-02 12:58:04 -05:00
Gabe Black 3a11412c99 ARM: Add an fp version of one of the microop indexed registers. 2010-06-02 12:58:04 -05:00
Gabe Black d5aee75efe ARM: Move the mmap region to where Linux actually has it. 2010-06-02 12:58:04 -05:00
Gabe Black a8eb9d521c ARM: Eliminate the unused rhi and rlo operands. 2010-06-02 12:58:03 -05:00
Gabe Black b02c7f1bcd ARM: Move the macro mem constructor out of the isa desc. 
This code doesn't use the parser at all, and moving it out reduces the
conceptual complexity of that code.
 2010-06-02 12:58:03 -05:00
Gabe Black 7b62e9ad71 ARM: Make macroops panic if executed directly. 
The macroop should never be executed, only it's microops will.
 2010-06-02 12:58:03 -05:00
Ali Saidi 8fadf2691d ARM: GCC < 4.3 has some issues with attribute no return on some functions. Fix so it works for older gccs. 2010-06-02 12:58:03 -05:00
Gabe Black f18040a205 ARM: Split out the "basic" templates and format. 
--HG--
rename : src/arch/arm/isa/formats/basic.isa => src/arch/arm/isa/templates/basic.isa
 2010-06-02 12:58:03 -05:00
Gabe Black c175f1b993 ARM: Remove unnecessary cruft from includes.isa. 2010-06-02 12:58:03 -05:00
Gabe Black e29ec7d2ed ARM: Move the inst2string function out of the isa_desc. 
Delete the now empty formats/util.isa.
 2010-06-02 12:58:03 -05:00
Gabe Black ae135228fc ARM: Get rid of the unused ArmGenericCodeSubs. 2010-06-02 12:58:03 -05:00
Gabe Black 8c012e9571 ARM: Make the predecoder print out the ExtMachInst it gathered when traced. 2010-06-02 12:58:03 -05:00
Gabe Black 458bd025d4 ARM: Remove special naming for the new version of multiply. 2010-06-02 12:58:03 -05:00
Gabe Black 2196f75a25 ARM: Hook the new multiply instructions into all the decoders. 2010-06-02 12:58:03 -05:00
Gabe Black 33da368e99 ARM: Implement all integer multiply instructions. 2010-06-02 12:58:03 -05:00
Gabe Black 50229be27f ARM: Add templates for multiply instructions. 2010-06-02 12:58:03 -05:00
Gabe Black 3430b34cff ARM: Add base classes for multiply instructions. 2010-06-02 12:58:03 -05:00
Gabe Black c7d2f43641 ARM: Decode plain binary immediate thumb data processing instructions. 2010-06-02 12:58:03 -05:00
Gabe Black dcf218155d ARM: Define a new "movt" data processing instruction. 2010-06-02 12:58:03 -05:00
Gabe Black b615ed1470 ARM: Hook the new branch instructions into the 32 bit thumb decoder. 2010-06-02 12:58:03 -05:00
Gabe Black 274badd201 ARM: Hook the new branch instructions into the 16 bit thumb decoder. 2010-06-02 12:58:03 -05:00
Gabe Black b6b2f8891a ARM: Eliminate the old style branch instructions. 2010-06-02 12:58:03 -05:00
Gabe Black d082705b01 ARM: Hook the new branch instructions into the ARM decoder. 2010-06-02 12:58:02 -05:00
Gabe Black 9869343636 ARM: Implement branch instructions external to the decoder. 2010-06-02 12:58:02 -05:00
Gabe Black a6c1c8debb ARM: Add new templates for branch instructions. 2010-06-02 12:58:02 -05:00
Gabe Black ef3972eaae ARM: Implement new base classes for branches. 2010-06-02 12:58:02 -05:00
Gabe Black 769f3406fe ARM: Replace the interworking branch base class with a special operand. 2010-06-02 12:58:02 -05:00
Gabe Black b6e7029dd5 ARM: Fix PC operand handling. 2010-06-02 12:58:02 -05:00
Gabe Black 7eb3ea2798 ARM: Remove the special naming from the new version of data processing instructions. 2010-06-02 12:58:02 -05:00
Gabe Black 4f08b52af2 ARM: Get rid of unnecessary flag calculating functions. 2010-06-02 12:58:02 -05:00
Gabe Black bf903ec9a1 ARM: Get rid of the unused Jump format. 2010-06-02 12:58:02 -05:00
Gabe Black 36ca0658a4 ARM: Get rid of obsoleted predicated inst formats, etc. 2010-06-02 12:58:02 -05:00
Gabe Black 7939b48265 ARM: Implement disassembly for the new data processing classes. 2010-06-02 12:58:02 -05:00
Gabe Black b66e3aec43 ARM: Hook the external data processing instructions into the Thumb decoder. 2010-06-02 12:58:02 -05:00
Gabe Black beb759912b ARM: Move the modified_imm function from all ARM instructions to just data processing ones. 2010-06-02 12:58:02 -05:00
Gabe Black 8136cb3605 ARM: Hook the new external data processing instructions to the ARM decoder. 2010-06-02 12:58:02 -05:00
Gabe Black bf45d44cbe ARM: Implement data processing instructions external to the decoder. 2010-06-02 12:58:02 -05:00
Gabe Black c02f9cdddf ARM: Add new base classes for data processing instructions. 2010-06-02 12:58:02 -05:00
Gabe Black 1e7b317a98 ARM: Hook up 32 bit thumb load/store multiple. 2010-06-02 12:58:02 -05:00
Gabe Black 64d6b6ebfd ARM: Hook up 16 bit thumb load/store multiple. 2010-06-02 12:58:02 -05:00
Gabe Black 51bde086d5 ARM: Reimplement load/store multiple external to the decoder. 
--HG--
rename : src/arch/arm/isa/formats/macromem.isa => src/arch/arm/isa/insts/macromem.isa
rename : src/arch/arm/isa/formats/macromem.isa => src/arch/arm/isa/templates/macromem.isa
 2010-06-02 12:58:02 -05:00
Gabe Black 93a3714816 ARM: Move the templates for predicated instructions into a separate file. 
This allows the templates to all be available at the same time before any of
the formats, etc. This breaks an artificial circular dependence.

--HG--
rename : src/arch/arm/isa/formats/pred.isa => src/arch/arm/isa/templates/pred.isa
 2010-06-02 12:58:01 -05:00
Gabe Black 04300e33d4 ARM: Remove the special naming for the new memory instructions. 
These are the only memory instructions now.
 2010-06-02 12:58:01 -05:00
Gabe Black deb6e8f805 ARM: Eliminate the old memory formats which are no longer used. 2010-06-02 12:58:01 -05:00
Gabe Black 1905024766 ARM: Eliminate decoding for the very deprecated FPA instructions. 2010-06-02 12:58:01 -05:00
Gabe Black 55465844dc ARM: Make the addressing mode 3 loads/stores use the externally defined instructions. 2010-06-02 12:58:01 -05:00
Gabe Black 36b6ca2ce3 ARM: Pull double memory instructions out of the decoder. 2010-06-02 12:58:01 -05:00
Gabe Black 79b288f7b5 ARM: Force the condition code for 16 bit thumb instructions to be unconditional. 
Before, because 16 bit thumb instructions didn't set the upper 16 bits of the
ExtMachInst, that field would be interpretted as "equals".
 2010-06-02 12:58:01 -05:00
Gabe Black a86491fbf2 ARM: Decode 16 bit thumb PC relative memory instructions. 2010-06-02 12:58:01 -05:00
Gabe Black dc8af1b211 ARM: Decode 16 bit thumb immediate addressed memory instructions. 2010-06-02 12:58:01 -05:00
Gabe Black 4bbd73649d ARM: Decode 16 bit thumb register addressed memory instructions. 2010-06-02 12:58:01 -05:00
Gabe Black 462cf6f49b ARM: Make single stores decode to the new external store instructions. 2010-06-02 12:58:01 -05:00
Gabe Black 3b0f3b1ee2 ARM: Add a .w to the disassembly of 32 bit thumb instructions. 
This isn't technically correct since the .w should only be added if there are
32 and 16 bit encodings, but always having it always is better than never
having it.
 2010-06-02 12:58:01 -05:00
Gabe Black fde3c8f41d ARM: Make 32 bit thumb use the new, external load instructions. 2010-06-02 12:58:01 -05:00
Gabe Black 3b93015304 ARM: Define the store instructions from outside the decoder. 
--HG--
rename : src/arch/arm/isa/insts/ldr.isa => src/arch/arm/isa/insts/str.isa
 2010-06-02 12:58:01 -05:00
Gabe Black 81fdced83f ARM: Define the load instructions from outside the decoder. 2010-06-02 12:58:01 -05:00
Gabe Black 321d3a6e8c ARM: Implement a new set of base classes for non macro memory instructions. 2010-06-02 12:58:01 -05:00
Gabe Black 8933857af7 ARM: Create a "decoder" directory for the files implementing the decoder. 
--HG--
rename : src/arch/arm/isa/armdecode.isa => src/arch/arm/isa/decoder/arm.isa
rename : src/arch/arm/isa/decoder.isa => src/arch/arm/isa/decoder/decoder.isa
rename : src/arch/arm/isa/thumbdecode.isa => src/arch/arm/isa/decoder/thumb.isa
rename : src/arch/arm/isa/vfpdecode.isa => src/arch/arm/isa/decoder/vfp.isa
 2010-06-02 12:58:01 -05:00
Gabe Black 4ebd44dc4f ARM: Flesh out the 32 bit thumb store single instructions. 2010-06-02 12:58:01 -05:00
Gabe Black 386424ccb5 ARM: Implement the 32 bit thumb load word instructions. 2010-06-02 12:58:01 -05:00
Gabe Black 292b8a3c91 ARM: Add an operand for accessing the current PC. 2010-06-02 12:58:00 -05:00
Gabe Black 003346077f ARM: Flesh out 32 bit thumb load word decoding. 2010-06-02 12:58:00 -05:00
Gabe Black 0d4c4cacab ARM: Implement some 32 bit thumb data processing immediate instructions. 2010-06-02 12:58:00 -05:00
Gabe Black bd8812cf99 ARM: Replace the "never" condition with the "unconditional" condition. 2010-06-02 12:58:00 -05:00
Gabe Black af91d27271 ARM: Add a base class for 32 bit thumb data processing immediate instructions. 2010-06-02 12:58:00 -05:00
Gabe Black bfe1a194dd ARM: Add a function to decode 32 bit thumb immediate values. 2010-06-02 12:58:00 -05:00
Gabe Black 0116655674 ARM: Expand the decoding for 32 bit thumb data processing immediate instructions. 2010-06-02 12:58:00 -05:00
Gabe Black cef2e8ecee ARM: Stub out the 32 bit Thumb portion of the decoder. 2010-06-02 12:58:00 -05:00
Gabe Black 659f8d021f ARM: Add bitfields for 32 bit thumb. 2010-06-02 12:58:00 -05:00
Gabe Black bc6ae010c9 ARM: Decode VFP instructions. 2010-06-02 12:58:00 -05:00
Gabe Black 7b8525287d ARM: Stub out the 16 bit thumb decoder. 2010-06-02 12:58:00 -05:00
Gabe Black aaa619ea23 ARM: Add thumb bitfields to the ExtMachInst and the isa definition. 2010-06-02 12:58:00 -05:00
Gabe Black a1838f2c79 ARM: Make the decoder handle thumb instructions separately. 
--HG--
rename : src/arch/arm/isa/decoder.isa => src/arch/arm/isa/armdecode.isa
rename : src/arch/arm/isa/decoder.isa => src/arch/arm/isa/thumbdecode.isa
 2010-06-02 12:58:00 -05:00
Gabe Black 0dffd8ce79 ARM: Add a thumb bit bitfield. 2010-06-02 12:58:00 -05:00
Gabe Black 96be7e16c1 ARM: Make the predecoder handle Thumb instructions. 2010-06-02 12:58:00 -05:00
Gabe Black f49cdb4f5d ARM: Make sure ExtMachInst is used consistently instead of regular MachInst. 2010-06-02 12:58:00 -05:00
Gabe Black 330d9d4dbc ARM: Add a bitfield for setting the regular, inst bits of an ExtMachInst. 2010-06-02 12:58:00 -05:00
Gabe Black a59d219989 ARM: Add a bit to the ExtMachInst to select thumb mode. 2010-06-02 12:58:00 -05:00
Gabe Black 4ddeceba96 ARM: Allow ARM processes to start in Thumb mode. 2010-06-02 12:58:00 -05:00
Gabe Black ebb273bb7b ARM: Add a new base class for instructions that can do an interworking branch. 2010-06-02 12:57:59 -05:00
Gabe Black 9ef82c0bc4 ARM: Track the current ISA mode using the PC. 2010-06-02 12:57:59 -05:00
Gabe Black 1c0d9806e5 ARM: Fix custom writer/reader code for non indexed operands. 2010-06-02 12:57:59 -05:00
Gabe Black 4b87bc887a ARM: Remove IsControl from operands that don't imply control transfers. 
Also remove IsInteger from CondCodes.
 2010-06-02 12:57:59 -05:00
Nathan Binkert bb589d463b x86: put back code that I accidentally deleted 2010-05-25 20:15:44 -07:00
Nathan Binkert 13d64906c2 copyright: Change HP copyright on x86 code to be more friendly 2010-05-23 22:44:15 -07:00
Gabe Black c5c559b6ab SPARC: Implement the version of movcc that uses the fp condition codes. 2010-05-14 14:22:51 -07:00
Gabe Black c4497dbf03 X86: Make the cvti2f microop sign extend its integer source correctly. 
The code was using the wrong bit as the sign bit. Other similar bits of code
seem to be correct.
 2010-05-12 00:51:35 -07:00
Gabe Black cc76842f83 X86: Actual change that fixes div. How did that happen? 2010-05-12 00:49:12 -07:00
Gabe Black 2ee7a89209 X86: Update the base aux vector X86 processes install. 2010-05-03 00:44:08 -07:00
Gabe Black 7524fdda6a X86: Sometimes CPUID depends on ecx, so pass that in. 2010-05-02 00:40:17 -07:00
Gabe Black 51a3d65e25 X86: Finally fix a division corner case. 
When doing an unsigned 64 bit division with a divisor that has its most
significant bit set, the division code would spill a bit off of the end of a
uint64_t trying to shift the dividend into position. This change adds code
that handles that case specially by purposefully letting it spill and then
going ahead assuming there was a 65th one bit.
 2010-05-02 00:39:29 -07:00
Nathan Binkert e99828b06a tick: rename Clock namespace to SimClock 2010-04-15 16:24:12 -07:00
Steve Reinhardt 4d77ea7a57 cpu: fix exec tracing memory corruption bug 
Accessing traceData (to call setAddress() and/or setData())
after initiating a timing translation was causing crashes,
since a failed translation could delete the traceData
object before returning.

It turns out that there was never a need to access traceData
after initiating the translation, as the traced data was
always available earlier; this ordering was merely
historical.  Furthermore, traceData->setAddress() and
traceData->setData() were being called both from the CPU
model and the ISA definition, often redundantly.

This patch standardizes all setAddress and setData calls
for memory instructions to be in the CPU models and not
in the ISA definition.  It also moves those calls above
the translation calls to eliminate the crashes.
 2010-03-23 08:50:57 -07:00
Nathan Binkert 1068ca85d0 scons: import ply to work around scons sys.path weirdness 2010-03-10 15:39:34 -08:00
Nathan Binkert f0b4259e98 cpu_models: get rid of cpu_models.py and move the stuff into SCons 2010-02-26 18:14:48 -08:00
Nathan Binkert ac106767c8 isa_parser: Make SCons import the isa_parser 
this is instead of forking a new interpreter
 2010-02-26 18:14:48 -08:00
Nathan Binkert 629e8df196 isa_parser: move the operand map stuff into the ISAParser class. 2010-02-26 18:14:48 -08:00
Nathan Binkert 4db57edade isa_parser: move more support functions into the ISAParser class 2010-02-26 18:14:48 -08:00
Nathan Binkert 5ad139375e isa_parser: move more stuff into the ISAParser class 2010-02-26 18:14:48 -08:00
Nathan Binkert 4ef6e129d6 isa_parser: move the formatMap and exportContext into the ISAParser class 2010-02-26 18:14:48 -08:00
Nathan Binkert 4e105f6fe1 isa_parser: Make stack objects class members instead of globals 2010-02-26 18:14:48 -08:00
Nathan Binkert b4178b1ae7 isa_parser: add a debug variable that changes how errors are reported. 
This allows us to get tracebacks in certain cases where they're more
useful than our error message.
 2010-02-26 18:14:48 -08:00
Nathan Binkert 40a05f04fb isa_parser: Use an exception to flag error 
This allows the error to propagate more easily
 2010-02-26 18:14:48 -08:00
Nathan Binkert f82a92925c isa_parser: Move more stuff into the ISAParser class 2010-02-26 18:14:48 -08:00
Nathan Binkert f7a627338c isa_parser: move code around to prepare for putting more stuff in the class 2010-02-26 18:14:48 -08:00
Nathan Binkert eb4ce01056 isa_parser: simple fixes, formatting and style 2010-02-26 18:14:48 -08:00
Timothy M. Jones 29e8bcead5 O3PCU: Split loads and stores that cross cache line boundaries. 
When each load or store is sent to the LSQ, we check whether it will cross a
cache line boundary and, if so, split it in two. This creates two TLB
translations and two memory requests. Care has to be taken if the first
packet of a split load is sent but the second blocks the cache. Similarly,
for a store, if the first packet cannot be sent, we must store the second
one somewhere to retry later.

This modifies the LSQSenderState class to record both packets in a split
load or store.

Finally, a new const variable, HasUnalignedMemAcc, is added to each ISA
to indicate whether unaligned memory accesses are allowed. This is used
throughout the changed code so that compiler can optimise away code dealing
with split requests for ISAs that don't need them.
 2010-02-12 19:53:20 +00:00
Timothy M. Jones dd60902152 Power ISA: Add an alignment fault to Power ISA and check alignment in TLB. 2010-02-12 19:53:19 +00:00
Nathan Binkert 8a3fbbd8d9 compile: compile on 32 bit hardware 2009-11-05 17:21:26 -08:00
Nathan Binkert 52ccfde2cd isa_parser: allow negative integer literals 2009-11-05 17:21:25 -08:00
Lisa Hsu d6da172517 util: do checkpoint aggregation more cleanly, fix last changeset. 
1) Move alpha-specific code out of page_table.cc:serialize().
2) Begin serializing M5_pid and unserializing it, but adding an function to do optional paramIn so that old checkpoints don't need to be fixed up.
3) Fix up alpha startup code so that the unserialized M5_pid value is properly written to DTB_IPR_ASN.
4) Fix the memory unserialize that I forgot somehow in the last changeset.
5) Add in an agg_se.py to handle aggregated checkpoints. --bench foo-bar plus positional arguments foo bar are the only changes in usage from se.py.
Note this aggregation stuff has only been tested for Alpha and nothing else, though it should take a very minimal amount of work to get it to work with another ISA.
 2010-01-19 22:03:44 -08:00
Matt DeVuyst 18dc80e07b MIPS: Beef up process initialization. 2009-12-31 15:30:51 -05:00
Gabe Black ecaa7070e6 MIPS: Implement the SE mode version of rdhwr. 2009-12-31 15:30:51 -05:00
Gabe Black c70f3c93af MIPS: Fix decoding of the rdhwr instruction. 2009-12-31 15:30:51 -05:00
Gabe Black 134937b594 MIPS: Implement the set_thread_area system call. 2009-12-31 15:30:50 -05:00
Gabe Black d3ed32b989 MIPS: Create an artificial control register to hold the thread pointer. 
In Linux, the set_thread_area system call stores the address of the thread
local storage area into a field of the current thread_info structure. Later,
to access that value, the program uses the rdhwr instruction to read a
"hardware register" with index 29. The 64 bit MIPS manual, volume II, says
that index 29 is reserved for a future ABI extension and should cause a
"Reserved Instruction Exception". In Linux (and potentially other ISAs) that
exception is trapped and emulated to return the value stored by
set_thread_area as if that were actually stored by a physical register.

The tp_value address (as named in the Linux kernel) is ironically stored as a
control register so that it goes with a particular ThreadContext. Syscall
emulation will use that to emulate storing to the OS's thread info structure,
and rdhwr will emulate faulting and returning that value from software by
returning the value itself, as if it was in hardware. In other words, we fake
faking the register in SE mode. In an FS mode implementation it should
work as specified in the manual.
 2009-12-31 15:30:50 -05:00
Gabe Black cc07dcf026 MIPS: Extract CPU pointer from the thread context in scheduleCP0 setMiscReg. 
The MIPS ISA object expects to be constructed with a CPU pointer it uses to
look at other thread contexts and allow them to be manipulated with control
registers. Unfortunately, that differs from all the other ISA classes and
would complicate their implementation.

This change makes the event constructor use a CPU pointer pulled out of the
thread context passed to setMiscReg instead.
 2009-12-31 15:30:50 -05:00
Gabe Black 1261f1d8db MIPS: Add missing syscall slots. 
These are all after the existing ones, suggesting they were added after the
original list was created.
 2009-12-21 14:59:40 -08:00
Soumyaroop Roy 1bd0f772f1 Alpha: Implement MVI and remaining BWX instructions. 2009-12-20 15:03:23 -06:00
Gabe Black c7ca1d3c8a X86: Add a common named flag for signed media operations. 2009-12-19 01:48:31 -08:00
Gabe Black 2554511533 X86: Create a common flag with a name to indicate high multiplies. 2009-12-19 01:48:07 -08:00
Gabe Black e474079ddc X86: Create a common flag with a name to indicate scalar media instructions. 2009-12-19 01:47:30 -08:00
Ali Saidi 422f0d9f10 ARM: Begin implementing CP15 2009-11-17 18:02:09 -06:00
Ali Saidi 0916c376a9 ARM: Differentiate between LDM exception return and LDM user regs. 2009-11-17 18:02:08 -06:00
Ali Saidi 1470dae8e9 ARM: Boilerplate full-system code. 
--HG--
rename : src/arch/sparc/interrupts.hh => src/arch/arm/interrupts.hh
rename : src/arch/sparc/kernel_stats.hh => src/arch/arm/kernel_stats.hh
rename : src/arch/sparc/stacktrace.cc => src/arch/arm/stacktrace.cc
rename : src/arch/sparc/system.cc => src/arch/arm/system.cc
rename : src/arch/sparc/system.hh => src/arch/arm/system.hh
rename : src/dev/sparc/T1000.py => src/dev/arm/Versatile.py
rename : src/dev/sparc/t1000.cc => src/dev/arm/versatile.cc
rename : src/dev/sparc/t1000.hh => src/dev/arm/versatile.hh
 2009-11-17 18:02:08 -06:00
Ali Saidi 171e7f7b24 imported patch isa_fixes2.diff 2009-11-16 11:37:03 -06:00
Gabe Black 9127ee5ac8 ARM: Make the exception return form of ldm restore CPSR. 2009-11-15 00:23:14 -08:00
Gabe Black 903fb8c73d ARM: Create a new type of load uop that restores spsr into cpsr. 2009-11-15 00:15:42 -08:00
Gabe Black b41725f723 ARM: Check in the actual change from the last commit. 
The last commit was somehow empty. This was what was supposed to go in it.
 2009-11-14 21:03:10 -08:00
Gabe Black c4042985d7 ARM: Fix up the implmentation of the msr instruction. 2009-11-14 19:22:30 -08:00
Gabe Black e2ab64543b ARM: Define a mask to differentiate purely CPSR bits from CondCodes bits. 2009-11-14 19:22:30 -08:00
Gabe Black 425ebf6bd7 ARM: Add a bitfield to indicate if an immediate should be used. 2009-11-14 19:22:30 -08:00
Gabe Black e543f16247 ARM: Write some functions to write to the CPSR and SPSR for instructions. 2009-11-14 19:22:30 -08:00
Gabe Black 812e390693 ARM: Fix up the implmentation of the mrs instruction. 2009-11-14 19:22:29 -08:00
Gabe Black 1df0025e28 ARM: More accurately describe the effects of using the control operands. 2009-11-14 19:22:29 -08:00
Gabe Black 50b9149c75 ARM: Hook up the moded versions of the SPSR. 
These registers can be accessed directly, or through MISCREG_SPSR which will
act as whichever SPSR is appropriate for the current mode.
 2009-11-14 19:22:29 -08:00
Ali Saidi 48bc573f5f ARM: Move around decoder to properly decode CP15 2009-11-14 11:25:00 -06:00
Vince Weaver 8f6744c19c X86: add ULL to 1's being shifted in 64-bit values 
Some of the micro-ops weren't casting 1 to ULL before shifting,
which can cause problems.  On the perl makerand input this
caused some values to be negative that shouldn't have been.

The casts are done as ULL(1) instead of 1ULL to match others
in the m5 code base.
 2009-11-11 17:49:09 -05:00
Gabe Black 5524af83ef ARM: Fix some bugs in the ISA desc and fill out some instructions. 2009-11-10 23:44:05 -08:00
Gabe Black 850eb54a7c Merge with the head. 2009-11-10 21:12:53 -08:00