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Author SHA1 Message Date
Daniel Sanchez
ab5e4a22b3 ruby: Removed System name clash by renaming ruby's System to RubySystem 2009-05-11 10:38:44 -07:00
Nathan Binkert
84a18e7fdc ruby: rename config.include to config.hh and clean up the macro stuff. 
I did the macro cleanup because I was worried that the SCons scanner
would get confused.  This code will hopefully go away soon anyway.

--HG--
rename : src/mem/ruby/config/config.include => src/mem/ruby/config/config.hh
 2009-05-11 10:38:44 -07:00
Nathan Binkert
b05da09cd6 ruby: strip out some unused defines 2009-05-11 10:38:44 -07:00
Nathan Binkert
2f30950143 ruby: Import ruby and slicc from GEMS 
We eventually plan to replace the m5 cache hierarchy with the GEMS
hierarchy, but for now we will make both live alongside eachother.
 2009-05-11 10:38:43 -07:00
Korey Sewell
c70241810d cpus: fix cpu progress event 
this was double scheduling itself (once in constructor and once in cpu code). also add support for stopping / starting
progress events through repeatEvent flag and also changing the interval of the progress event as well
 2009-05-05 02:51:31 -04:00
Nathan Binkert
dc35d2f125 scons: re-work the *Source functions to take more information. 
Start by turning all of the *Source functions into classes
so we can do more calculations and more easily collect the data we need.
Add parameters to the new classes for indicating what sorts of flags the
objects should be compiled with so we can allow certain files to be compiled
without Werror for example.
 2009-05-04 16:58:24 -07:00
Gabe Black
7146eb79f1 X86: Precompute the default and alternate address and operand size and the stack size. 2009-04-26 16:49:24 -07:00
Gabe Black
b6bfe8af26 X86: Split out the internal memory space from the regular translate() and precompute mode. 2009-04-26 16:48:44 -07:00
Gabe Black
4ee34dfb4e X86: Centralize updates to the handy M5 reg. 2009-04-26 16:47:48 -07:00
Gabe Black
06b3e3c303 X86: Implement lowest priority interrupts more correctly. 
Lowest priority interrupts are now delivered based on a rotating offset into
the list of potential recipients. There could be parasitic cases were a
processor gets picked on and ends up at that rotating offset all the time, but
it's much more likely that the group will stay consistent and the pain will be
distributed evenly.
 2009-04-26 02:09:54 -07:00
Gabe Black
2f34a7eaeb X86: Tell the function that sends int messages who to send to instead of figuring it out itself. 2009-04-26 02:09:27 -07:00
Gabe Black
88ab4bb257 X86: Make the local APICs register themselves with the IO APIC. 
This is a hack so that the IO APIC can figure out information about the local
APICs. The local APICs still have no way to find out about each other.
Ideally, when the local APICs update state that's relevant to somebody else,
they'd send an update to everyone. Without being able to do a broadcast, that
would still require knowing who else there is to notify. Other broadcasts are
implemented using assumptions that may not always be true.
 2009-04-26 02:09:13 -07:00
Gabe Black
c5e2cf841d X86: Record the initial APIC ID which identifies an APIC in M5. 
The ID as exposed to software can be changed. Tracking those changes in M5
would be cumbersome, especially since there's no guarantee the IDs will remain
unique.
 2009-04-26 02:06:21 -07:00
Gabe Black
8d84f81e70 X86, Config: Make makeX86System consider the number of CPUs, and clean up interrupt assignment. 2009-04-26 02:04:32 -07:00
Gabe Black
9d0fa27d09 SPARC: Tighten up the clone system call and SPARCs copyRegs. 2009-04-24 23:11:21 -07:00
Steve Reinhardt
7c056e44e5 request: reorganize flags to group related flags together. 2009-04-23 06:44:32 -07:00
Gabe Black
ee7055c289 X86: Put the StoreCheck flag with the others, and don't collide with other flags. 2009-04-23 01:43:00 -07:00
Nathan Binkert
b4816037ba stats: expose statistics to python 2009-04-22 13:38:01 -07:00
Nathan Binkert
aa9b4e6a68 stats: Move flags into info.hh and use base/flags.hh to manage the flags 2009-04-22 13:38:01 -07:00
Nathan Binkert
8c3eb1a192 stats: Shuffle around info stuff so it can be accessed separately 2009-04-22 13:38:00 -07:00
Nathan Binkert
4d9f25b75c stats: Rename the info classes to hopefully make things a bit clearer 
FooInfoBase became FooInfo
FooInfo became FooInfoProxy
 2009-04-22 13:38:00 -07:00
Nathan Binkert
ca3d82b38a stats: remove simplescalar compatibility for printing 2009-04-22 10:25:14 -07:00
Nathan Binkert
61a68371be stats: fix initialization bug in distribution text output 2009-04-22 06:44:29 -07:00
Steve Reinhardt
e7fa4f2f8e i8254xGBe: major style overhaul. 
Moved DescCache template functions from .hh to .cc file.
Also fixed lots of line-wrapping problems, and some irregular indentation.
 2009-04-22 01:58:53 -04:00
Steve Reinhardt
6629d9b2bc mem: use single BadAddr responder per system. 
Previously there was one per bus, which caused some coherence problems
when more than one decided to respond.  Now there is just one on
the main memory bus.  The default bus responder on all other buses
is now the downstream cache's cpu_side port.  Caches no longer need
to do address range filtering; instead, we just have a simple flag
to prevent snoops from propagating to the I/O bus.
 2008-07-16 11:10:33 -07:00
Nathan Binkert
4d001e43da Automated merge with ssh://m5sim.org//repo/m5 2009-04-21 16:04:55 -07:00
Nathan Binkert
fcc142463d pseudo: only include kernel stats if FULL_SYSTEM. 2009-04-21 15:40:26 -07:00
Nathan Binkert
43c7698f49 arm: include missing file for arm 2009-04-21 15:40:26 -07:00
Nathan Binkert
50f1570352 arm: Unify the ARM tlb. We forgot about this when we did the rest. 
This code compiles, but there are no tests still
 2009-04-21 15:40:25 -07:00
Steve Reinhardt
03b3925e58 syscall_emul: style fixes (mostly wrapping overly long lines) 2009-04-21 08:17:36 -07:00
Steve Reinhardt
52b6764f31 syscall: Resolve conflicts between m5threads and Gabe's recent SE changes. 2009-04-21 08:17:36 -07:00
Daniel Sanchez
b0e9654f86 Commit m5threads package. 
This patch adds limited multithreading support in syscall-emulation
mode, by using the clone system call.  The clone system call works
for Alpha, SPARC and x86, and multithreaded applications run
correctly in Alpha and SPARC.
 2009-04-21 08:17:36 -07:00
Nathan Binkert
b0489d18ed SCons: Export export_vars so SConsopts files can add to them 2009-04-21 08:17:36 -07:00
Steve Reinhardt
97b6947eb7 Minor tweaks for future Ruby compatibility. 2009-04-21 08:17:36 -07:00
Steve Reinhardt
eb3b6935d3 request: add PREFETCH flag. 2009-04-21 08:17:10 -07:00
Steve Reinhardt
3083268d60 request: rename INST_READ to INST_FETCH. 2009-04-20 18:54:02 -07:00
Steve Reinhardt
7f8ea68a30 request: split public and private flags into separate fields. 
This frees up needed space for more public flags.  Also:
- remove unused Request accessor methods
- make Packet use public Request accessors, so it need not be a friend
 2009-04-20 18:40:00 -07:00
Gabe Black
9e9a34fed1 Mem: Fill out the comment that describes the LOCKED request flag. 2009-04-19 22:00:24 -07:00
Gabe Black
bd6f2bb538 Mem: Change isLlsc to isLLSC. 2009-04-19 21:44:15 -07:00
Gabe Black
089b384086 X86: Fix the functions that manipulate large bit arrays in the local APIC. 2009-04-19 13:47:15 -07:00
Gabe Black
eee74ba427 X86: Fix up a copyright. 2009-04-19 13:17:35 -07:00
Gabe Black
6910baa015 X86: Fix how the TLB handles the storecheck flag. 2009-04-19 04:57:51 -07:00
Gabe Black
0a6ff60caa X86: Recognize and handle the lock legacy prefix. 2009-04-19 04:57:28 -07:00
Gabe Black
61edc9ba66 X86: Implement a locking version of XADD. 2009-04-19 04:56:49 -07:00
Gabe Black
209cfc89fd X86: Implement a locking version of BTC. 2009-04-19 04:56:45 -07:00
Gabe Black
e475cf85f0 X86: Implement a locking version of BTR. 2009-04-19 04:56:43 -07:00
Gabe Black
43f58927d6 X86: Implement a locking version of CMPXCHG. 2009-04-19 04:56:40 -07:00
Gabe Black
b493906eb9 X86: Implement a locking version of BTS. 2009-04-19 04:56:36 -07:00
Gabe Black
985d959ea6 X86: Implement a locking version of DEC. 2009-04-19 04:56:34 -07:00
Gabe Black
4f2d4f466a X86: Implement a locking version of INC. 2009-04-19 04:56:31 -07:00
Gabe Black
2394f73f90 X86: Implement a locking version of NEG. 2009-04-19 04:56:28 -07:00
Gabe Black
9b9b7a412c X86: Implement a locking version of NOT. 2009-04-19 04:56:25 -07:00
Gabe Black
b8f81c62a2 X86: Implement a locking version of XCHG. 2009-04-19 04:56:22 -07:00
Gabe Black
750f5a0a67 X86: Implement a locking version of XOR. 2009-04-19 04:56:20 -07:00
Gabe Black
cfb289ebeb X86: Implement a locking version of SUB. 2009-04-19 04:56:16 -07:00
Gabe Black
789b3191b9 X86: Implement a locking version of AND. 2009-04-19 04:56:14 -07:00
Gabe Black
e742cad6f4 X86: Implement a locking version of SBB. 2009-04-19 04:56:11 -07:00
Gabe Black
193265c6e5 X86: Implement a locking version of ADC. 2009-04-19 04:56:08 -07:00
Gabe Black
2f607b882c X86: Implement a locking version of OR. 2009-04-19 04:56:06 -07:00
Gabe Black
a7f79c9049 X86: Implement a locking version of ADD. 2009-04-19 04:56:02 -07:00
Gabe Black
d90456a486 X86: Implement the stul microop. 
This microop does a store and unlocks the requested address. The RISC86
microop ISA doesn't seem to have an equivalent to this, so I'm guessing that
the store following an ldstl is automatically unlocking. We don't do it this
way for performance reasons since the behavior is the same.
 2009-04-19 04:55:58 -07:00
Gabe Black
d2554ff030 X86: Implement the ldstl microop. 
This microop does a load, checks that a store would succeed, and locks the
requested address.
 2009-04-19 04:55:43 -07:00
Gabe Black
1a8a765a5c CPUs: Make the atomic CPU support locked memory accesses. 2009-04-19 04:50:07 -07:00
Gabe Black
742c3f045e Memory: Add a LOCKED flag back in for x86 style locking. 2009-04-19 04:39:25 -07:00
Gabe Black
3e5f487663 Memory: Rename LOCKED for load locked store conditional to LLSC. 2009-04-19 04:25:01 -07:00
Gabe Black
ca85981478 SE mode: Make keeping track of the number of syscalls less hacky. 2009-04-19 04:15:32 -07:00
Gabe Black
e174239bd8 X86: Mask the PIC at startup to avoid a glitch which causes an NMI. 2009-04-19 04:15:06 -07:00
Gabe Black
5f164ba720 X86: Actually handle 16 bit mode modrm. 2009-04-19 04:14:31 -07:00
Gabe Black
93cccf7d19 X86: Make the TEST instruction set all the flags it's supposed to. 2009-04-19 04:14:16 -07:00
Gabe Black
f82c123242 X86: Implement broadcast IPIs. 2009-04-19 04:14:01 -07:00
Gabe Black
829e424353 X86: Fix the ordering of the vendor string reported by CPUID. 2009-04-19 04:13:45 -07:00
Gabe Black
8b2ac20753 X86: Keep track of what the initial count value was in the LAPIC timer. 2009-04-19 03:56:57 -07:00
Gabe Black
18b3863127 X86: Only recognize the first startup IPI after INIT or reset. 2009-04-19 03:56:36 -07:00
Gabe Black
4d32cd10ce X86: Use recvResponse to implement the idle bit in the Local APIC ICR. 2009-04-19 03:56:24 -07:00
Gabe Black
bdda224d41 X86: Add a function which gets called when an interrupt message has been delivered. 2009-04-19 03:54:11 -07:00
Gabe Black
3031af21c7 X86: Fix the flags for interrupt response messages. 2009-04-19 03:53:29 -07:00
Gabe Black
3eed59768c X86: Explicitly use the right width in a few places that need a 64 bit value. 2009-04-19 03:47:59 -07:00
Gabe Black
8761057c78 X86: Keep track of the pioAddr for the local APIC. 2009-04-19 03:47:12 -07:00
Gabe Black
038225a6ca X86: Implement far jmp. 2009-04-19 03:42:41 -07:00
Gabe Black
3b1b21cb15 X86: Some segment selectors can be used when "NULL". 2009-04-19 03:41:10 -07:00
Gabe Black
a0cc081997 X86: Fix a bug in the chks microop where it ignored that it found a fault. 2009-04-19 03:40:08 -07:00
Gabe Black
f2ff5b9249 X86: Make the interrupt entering microcode record the value to use, not actually use it. 2009-04-19 03:36:57 -07:00
Gabe Black
35eea4191b X86: LEA calculates an address before segmentation. 2009-04-19 03:24:51 -07:00
Gabe Black
bdd55ec8b6 X86: Implement the save machine status word instruction (SMSW). 2009-04-19 03:22:38 -07:00
Gabe Black
d86cd1d2a0 X86: Implement the load machine status word instruction (LMSW). 2009-04-19 03:17:14 -07:00
Gabe Black
eba640c963 X86: Only use %eax to select a function and look like we support sse2. 2009-04-19 03:11:24 -07:00
Gabe Black
27e54982b4 X86: Fix the mov to segment selector in real mode instruction microcode. 2009-04-19 03:08:40 -07:00
Gabe Black
633c96bd85 X86: The startup IPI delivery mode is not reserved. 2009-04-19 03:01:46 -07:00
Gabe Black
08f021aad0 X86: Implement the STARTUP IPI. 2009-04-19 02:56:03 -07:00
Gabe Black
d277feb925 X86: Implement the INIT IPI. 2009-04-19 02:53:00 -07:00
Gabe Black
a340b214cf X86: Fix the halt microop. 2009-04-19 02:51:09 -07:00
Gabe Black
641513fe08 X86: Start implementing the interrupt command register in the local APIC. 2009-04-19 02:43:22 -07:00
Gabe Black
9549694ecd X86: Make code that sends an interrupt from the IO APIC available for IPIs. 2009-04-19 02:42:19 -07:00
Gabe Black
d10195b1a4 CPU: If the simple CPU is already idle, just return from suspendContext, don't assert. 2009-04-19 02:23:29 -07:00
Gabe Black
05b5861419 X86: Condense the startupCPU code. 2009-04-19 02:20:57 -07:00
Gabe Black
f668340f2c X86: Set the local APIC ID to something meaningful. 2009-04-19 02:16:49 -07:00
Gabe Black
79a3a6aecb X86: Don't pretend to be an AMD CPU any more. We're not good enough at it. 2009-04-19 02:06:51 -07:00
Korey Sewell
d8a34a9745 mips-tlb-fix: check for alignment faults.\nMIPS was never updated to use TLBS correcty in SE mode. The error was forwarding translations directly to pageTable. The TLB should check for alignment faults at bare minimum here but in the long run we should be using TLBs in SE mode for MIPS. 2009-04-18 10:42:29 -04:00
Korey Sewell
e501e1af54 mips-syscall: mark with correct flag. \nMIPS was using wrong serialization flag on syscall instructions allowing O3 to handle SE mode syscalls incorrectly and speculate on instructions after a syscall 2009-04-18 10:42:29 -04:00
Korey Sewell
5c1742b822 o3-delay-slot-bpred: fix decode stage handling of uncdtl. branches.\n decode stage was not setting the predicted PC correctly or passing that information back to fetch correctly 2009-04-18 10:42:29 -04:00
Korey Sewell
cc9e834e93 mips-shadowsets: fix calcuations. \n Remove Shadowsets from Int & Arch. Reg Calculations 2009-04-18 10:42:28 -04:00
Steve Reinhardt
14808ecac9 o3, inorder: fix FS bug due to initializing ThreadState to Halted. 
For some reason o3 FS init() only called initCPU if the thread state
was Suspended, which was no longer the case.  There's no apparent
reason to check, so I whacked the test completely rather than
changing the check to Halted.
The inorder init() was also updated to be symmetric, though the
previous code was just a fancy no-op.
 2009-04-17 16:54:58 -07:00
Steve Reinhardt
b146131d18 o3: handle fetch with no active threads correctly. 
This situation can arise now on the first fetch cycle after
the last active thread is halted.  It seems easy enough to
deal with when it happens rather than trying to avoid it.
 2009-04-15 23:12:00 -07:00
Steve Reinhardt
bb974d5a47 o3: fix {read,set}ArchFloatReg* functions. 
Register indices were not being calculated properly.
 2009-04-15 23:10:43 -07:00
Steve Reinhardt
7617dcf736 ThreadState: initialize status to Halted in constructor. 
This provides a common initial status for all threads independent
of CPU model (unlike the prior situation where CPUs initialized
threads to inconsistent states).
This mostly matters for SE mode; in FS mode, ISA-specific startupCPU()
methods generally handle boot-time initialization of thread contexts
(since the right thing to do is ISA-dependent).
 2009-04-15 13:18:24 -07:00
Steve Reinhardt
8882dc1283 Get rid of the Unallocated thread context state. 
Basically merge it in with Halted.
Also had to get rid of a few other functions that
called ThreadContext::deallocate(), including:
 - InOrderCPU's setThreadRescheduleCondition.
 - ThreadContext::exit().  This function was there to avoid terminating
   simulation when one thread out of a multi-thread workload exits, but we
   need to find a better (non-cpu-centric) way.
 2009-04-15 13:13:47 -07:00
Gabe Black
5c79191603 X86: Fix minor bug in the page table walker from TLB shuffling. 2009-04-13 04:14:15 -07:00
Nathan Binkert
c87c9950df stats: disallow duplicate statistic names. 2009-04-08 22:22:50 -07:00
Nathan Binkert
18a30524d6 alpha: get rid of all turbolaser remnants 2009-04-08 22:22:49 -07:00
Nathan Binkert
e0de2c3443 tlb: More fixing of unified TLB 2009-04-08 22:21:27 -07:00
Gabe Black
7b5a96f06b tlb: Don't separate the TLB classes into an instruction TLB and a data TLB 2009-04-08 22:21:27 -07:00
Gabe Black
d080581db1 Merge ARM into the head. ARM will compile but may not actually work. 2009-04-06 10:19:36 -07:00
Stephen Hines
7a7c4c5fca arm: add ARM support to M5 2009-04-05 18:53:15 -07:00
Ali Saidi
639cb0a42d CPA: Fix a typo that managed to sneak in. 2009-03-25 20:06:54 -04:00
Nathan Binkert
4eea8acaf2 stats: fix compiler error 2009-03-16 15:16:58 -07:00
Steve Reinhardt
758bfe4eb5 cache: set dirty bit on swaps (oops!) 2009-03-11 23:05:26 -07:00
Steve Reinhardt
61ff48a1f8 cpu: fix minor endian issue with trace output 
(no functional change)
 2009-03-11 23:05:24 -07:00
Steve Reinhardt
a94c68228a prefetch: don't panic on requests w/o contextID (e.g., writebacks). 2009-03-10 17:37:15 -07:00
Nathan Binkert
ac64586a99 build: fix compiler warnings in g++ 3.4 2009-03-07 21:34:50 -08:00
Steve Reinhardt
4f1855484c Fix up regression execution to better handle tests that end abnormally. 
E.g., mark aborts due to assertion failures as failed tests,
but those that get killed by the user as needing to be rerun, etc.
 2009-03-07 16:58:51 -08:00
Nathan Binkert
ac7bda0212 stats: fix duplicate statistics names. 
This generally requires providing a more meaningful name() function for a
class.
 2009-03-07 14:30:54 -08:00
Nathan Binkert
fcaf1b74b0 stats: cleanup text output stuff and fix mysql output 2009-03-07 14:30:53 -08:00
Nathan Binkert
66a85b54e2 build: fix errors for compilers other than g++ 4.3 2009-03-07 14:30:52 -08:00
Nathan Binkert
6f787e3d36 stats: create an enable phase, and a prepare phase. 
Enable more or less takes the place of check, but also allows stats to
do some other configuration.  Prepare moves all of the code that readies
a stat for dumping into a separate function in preparation for supporting
serialization of certain pieces of statistics data.
While we're at it, clean up the visitor code and some of the python code.
 2009-03-05 19:09:53 -08:00
Nathan Binkert
9f45fbaaa6 stats: clean up how templates are used on the data side. 
This basically works by taking advantage of the curiously recurring template
pattern in an intelligent way so as to reduce the number of lines of code
and hopefully make things a little bit clearer.
 2009-03-05 19:09:53 -08:00
Nathan Binkert
cc95b57390 stats: Fix all stats usages to deal with template fixes 2009-03-05 19:09:53 -08:00
Nathan Binkert
c7e82f965f stats: remove the template wart left over from the ancient binning stuff 2009-03-05 19:09:53 -08:00
Nathan Binkert
244c2a517a stats: stick the distribution's fancy parameter into the parameters structure. 2009-03-05 19:09:53 -08:00
Nathan Binkert
e19fd1d521 stats: Add a wrapper class for the information side of things. 
This provides an easy way to provide the callbacks into the data side
of things from the info side of things.  Rename Wrap to DataWrap so it
is more easily distinguishable from InfoWrap
 2009-03-05 19:09:53 -08:00
Nathan Binkert
c7bd1ec261 stats: better naming of template parameters for the wrapper stuff 
Parent and Child are bad names.  Derived and Base are better.
 2009-03-05 19:09:53 -08:00
Nathan Binkert
2dd5a5b3dc stats: get rid of meaningless uses of virtual 2009-03-05 19:09:53 -08:00
Nathan Binkert
ec209953e7 stats: miscellaneous cleanup 2009-03-05 19:09:53 -08:00
Nathan Binkert
a767819d56 serialize: Allow floats and doubles to be serialized 2009-03-05 19:09:53 -08:00
Steve Reinhardt
e3d6e8882e Get rid of 'using namespace' declarations in headers. 2009-03-05 17:15:31 -08:00
Korey Sewell
9e1dc7f205 InOrderCPU: Clean up Constructors to initialize variables correctly (i.e. in a way for the compiler to play *nice*) 2009-03-04 22:37:45 -05:00
Korey Sewell
7c8d544216 Give each resource in InOrder it's own TraceFlag instead of just standard 'Resource' flag 2009-03-04 13:17:09 -05:00
Korey Sewell
30cd2d21fa Remove unused functions/comments cluttering up the code. 2009-03-04 13:17:08 -05:00
Korey Sewell
f69b018571 make handling of interstage buffers (i.e. StageQueues) more consistent: (1)number from 0-n, not 1-n+1, (2) always check nextStageValid before a stageNum+1 and prevStageValid for a stageNum-1 reference (3) add skidSize() to get StageQueue size for all threads 2009-03-04 13:17:07 -05:00
Korey Sewell
f98e9161a8 InOrder didnt have all it's params set to a default value, which is now required for M5 objects; Also, a # of values need to be reset to 0 (or the appropriate value) before we assume they are OK for use. 2009-03-04 13:17:05 -05:00
Korey Sewell
846f953c2b Give TimeBuffer an ID that can be set. Necessary because InOrder uses generic stages so w/o an ID there is no way to differentiate buffers when debugging 2009-03-04 13:16:49 -05:00
Korey Sewell
e4aa4ca40c use numCycles instead of simTicks to determine CPI stat in InOrder 2009-03-04 13:16:48 -05:00
Steve Reinhardt
9ee8e685a4 O3: Make numThreads error message more helpful. 2009-03-04 09:25:53 -05:00
Steve Reinhardt
307905095c Fix Num_Syscall_Descs check bug in non-x86 ISAs. 
(See cset d35d2b28df38 for x86 fix.)
 2009-02-28 20:14:22 -05:00
Nathan Binkert
4523741c1c quell gcc 4.3 warning 2009-02-27 17:29:58 -08:00
Gabe Black
b69a9ad45a X86: Install the exit system call. 2009-02-27 09:26:41 -08:00
Gabe Black
9265b3d598 X86: Install the 32 bit write system call. 2009-02-27 09:26:32 -08:00
Gabe Black
b36f28472d X86: Implement shrd. 2009-02-27 09:26:26 -08:00
Gabe Black
2fe87e62ba X86: Add a structure to allow mapping between the host and guest fstat formats. 2009-02-27 09:26:17 -08:00
Gabe Black
27b751ec46 X86: Don't treat the REX prefixes as prefixes in 32 bit modes. These are inc/dec instructions. 2009-02-27 09:26:09 -08:00
Gabe Black
aa51c01d69 X86: Set address size to 64 bits when generating addresses internally. 2009-02-27 09:26:01 -08:00
Gabe Black
db3c51d3a0 X86: Add a vsyscall page for 32 bit processes to use. 2009-02-27 09:25:51 -08:00
Gabe Black
c3d7d7ed0e X86: Implement sysenter as a system call interface. 2009-02-27 09:25:43 -08:00
Gabe Black
5c1cc99d48 X86: Add a 32 bit mmap2 system call. 2009-02-27 09:25:33 -08:00
Gabe Black
04dbed79f8 X86: Install a 32 bit fstat64 system call. 2009-02-27 09:25:26 -08:00
Gabe Black
8a1eb7e8be X86: Take address size into account when computing an effective address. 2009-02-27 09:25:16 -08:00
Gabe Black
1d18eb9043 X86: Make instructions that use intseg preserve all 8 bytes of their addresses. 2009-02-27 09:25:02 -08:00
Gabe Black
79bc1b3740 X86: Fix a decoder bug and add in some missing instructions. 2009-02-27 09:24:10 -08:00
Gabe Black
3dfa564e70 X86: Respect segment override prefixes even when there's no ModRM byte. 2009-02-27 09:23:58 -08:00
Gabe Black
9dfa3f7f73 X86: Fix segment limit checks. 2009-02-27 09:23:50 -08:00
Gabe Black
9491debaa6 X86: Implement the 32 bit set_thread_area system call. 2009-02-27 09:23:42 -08:00
Gabe Black
1786f20058 X86: Set an initial value for the LDT selector. 2009-02-27 09:23:27 -08:00
Gabe Black
e23d688d8f X86: Set up a space for a GDT in SE so we can set up TLS or LDT segments. 2009-02-27 09:23:17 -08:00
Gabe Black
281ef8111a X86: Compute shift instruction flags correctly. 2009-02-27 09:23:00 -08:00
Gabe Black
14fc06640e X86: Install some 32 bit system calls. 2009-02-27 09:22:50 -08:00
Gabe Black
6ca53f8675 X86: Handle 32 bit system call arguments. 2009-02-27 09:22:30 -08:00
Gabe Black
9a000c5173 Processes: Make getting and setting system call arguments part of a process object. 2009-02-27 09:22:14 -08:00
Gabe Black
60aab03e85 X86: Implement the int system call interface in the decoder. 2009-02-27 09:21:58 -08:00
Gabe Black
05de9f4e2c X86: Distinguish the width of values on the stack between 32 and 64 bit processes. 2009-02-27 09:21:36 -08:00
Gabe Black
932f6440a1 X86: Add a class to support 32 bit x86 linux process. 2009-02-27 09:21:14 -08:00
Ali Saidi
bebbc9dc89 CPA: Add annotations to IGbE and CopyEngine device models. 2009-02-26 19:29:17 -05:00
Ali Saidi
d447ccb2c6 CPA: Add code to automatically record function symbols as CPU executes. 2009-02-26 19:29:17 -05:00
Ali Saidi
6fd4bc34a1 CPA: Add new object for gathering critical path annotations. 2009-02-26 19:29:17 -05:00
Ali Saidi
894925f135 Trace: fix the --trace-start option 2009-02-26 19:29:16 -05:00
Gabe Black
4a64493158 Devices: Make the RTC device reflect the use of BCD in its status registers. 2009-02-25 10:22:49 -08:00
Gabe Black
7400769768 X86: Implement IST stack switching. 2009-02-25 10:22:43 -08:00
Gabe Black
5c546e3504 CPU: Only look up the nearest symbol in the kernel if you're actually in kernel code. 2009-02-25 10:22:36 -08:00
Gabe Black
437b02884d ISA: Get rid of the get*RegName functions. 2009-02-25 10:22:31 -08:00
Gabe Black
3b01535ec1 SPARC: Get rid of the state keeping track of register frames. 2009-02-25 10:22:25 -08:00
Gabe Black
4633677145 ISA: Set up common trace flags for tracing registers. 2009-02-25 10:22:17 -08:00
Gabe Black
44d5351071 ISA: Get rid of FlattenIntIndex function. 2009-02-25 10:22:09 -08:00
Gabe Black
c1c61d52a0 SPARC: Get rid of flattenIndex in the int register file. 2009-02-25 10:21:59 -08:00
Gabe Black
ce2e50a64c ISA: Use the "Stack" traceflag for DPRINTFs about the initial stack frame. 2009-02-25 10:21:52 -08:00
Gabe Black
9d5b6e377f SPARC: Get rid of the setGlobals function. 2009-02-25 10:21:46 -08:00
Gabe Black
f41ce6b5e9 SPARC: Get rid of the setCWP function. 2009-02-25 10:21:40 -08:00
Gabe Black
88ee7d4c32 SPARC: Add a traceflag for register windows. 2009-02-25 10:21:33 -08:00
Gabe Black
7aa875f4f3 X86: Implement the lldt instruction. 2009-02-25 10:21:27 -08:00
Gabe Black
bda7077c64 X86: Add segmentation checks for ldt related descriptors and selectors. 2009-02-25 10:21:21 -08:00
Gabe Black
e08d60389d X86: Make the TSS type check actually return a fault if it fails. 2009-02-25 10:21:14 -08:00
Gabe Black
68300cfb8c X86: Make rdcr use merge and the mov to control register instructions use the right operand size. 2009-02-25 10:21:08 -08:00
Gabe Black
9842f1ca9d X86: Implement CLTS. 2009-02-25 10:21:02 -08:00
Gabe Black
b035c917a5 X86: Make the segment register reading microops use merge. 2009-02-25 10:20:47 -08:00
Gabe Black
28efb3c6e3 X86: Implement the mov to debug register intructions. 2009-02-25 10:20:42 -08:00
Gabe Black
c39ed53d05 X86: Rename oszForPseudoDesc maxOsz to reflect its more general use. 2009-02-25 10:20:30 -08:00
Gabe Black
3ca2451d81 X86: Add code to interpret debug register values. 2009-02-25 10:20:25 -08:00
Gabe Black
1e70401c08 X86: Fix a few bugs with the segment register instructions in real mode. 
Fix a few instances where the register form of zext was used where zexti was
intended. Also get rid of the 64 bit only rip relative addressed version since
64 bit and real mode are mutually exclusive.
 2009-02-25 10:20:19 -08:00
Gabe Black
8813168b5a X86: Do a merge for the zero extension microop. 2009-02-25 10:20:10 -08:00
Gabe Black
28a35a6adb X86: Add microops for reading/writing debug registers. 2009-02-25 10:20:01 -08:00
Gabe Black
11fbed02ea X86: Add classes that break out the bits of the DR6 and DR7 registers. 2009-02-25 10:19:54 -08:00
Gabe Black
cb4141f6e6 X86: Check src1 for illegal values since that's the index we actually use. 2009-02-25 10:19:47 -08:00
Gabe Black
d48214a656 X86: Implement the fence instructions. These are not microcoded. 2009-02-25 10:19:41 -08:00
Gabe Black
9940e21fa9 CPU: Add a flag to identify a read barrier to the static inst class. 2009-02-25 10:19:33 -08:00
Gabe Black
06ff83e1b9 X86: Implement a basic prefetch instruction. 2009-02-25 10:19:22 -08:00
Gabe Black
5f0428ef9f X86: Use the right portion of a register for stores. 2009-02-25 10:19:14 -08:00
Gabe Black
c849ef58c0 X86: Actually check page protections. 2009-02-25 10:18:58 -08:00
Gabe Black
f35a37ca9e X86: Update CS later so stack accesses have the right permission checks. 2009-02-25 10:18:51 -08:00
Gabe Black
da61c4b3ee CPU: Don't fetch when executing a macroop. 
If the CPL changes mid macroop, the end of the instruction might not be
priveleged enough to execute the beginning.
 2009-02-25 10:18:36 -08:00
Gabe Black
ba69184630 X86: Use atCPL0 for accesses that are part of CPU machinery. 2009-02-25 10:18:29 -08:00
Gabe Black
dc53ca89f6 X86: Add a flag to force memory accesses to happen at CPL 0. 2009-02-25 10:18:22 -08:00
Gabe Black
897c374892 X86: Move where CS is set so CPL checks work out. 2009-02-25 10:18:16 -08:00
Gabe Black
710b43dfbd X86: Implement inUserMode for x86. 2009-02-25 10:18:06 -08:00
Gabe Black
1cedc748d4 X86: Add a trace flag for tracing faults. 2009-02-25 10:17:59 -08:00
Gabe Black
eec3f49a57 X86: Implement the sysret instruction in long mode. 2009-02-25 10:17:54 -08:00
Gabe Black
6325245e3e X86: Implement the longmode versions of the syscall instruction. 2009-02-25 10:17:49 -08:00
Gabe Black
dadc30b0a4 X86: Make the microcode assembler recognize r8-r15. 2009-02-25 10:17:43 -08:00
Gabe Black
fcad6e3b13 X86: Add a wrattr microop. 2009-02-25 10:17:38 -08:00
Gabe Black
e4ede69b2f X86: Add a trace flag for the page table walker. 2009-02-25 10:17:27 -08:00
Gabe Black
99aa121fca X86: Make exceptions handle stack switching. 2009-02-25 10:17:19 -08:00
Gabe Black
aa7bc1be74 X86: Implement the LTR instruction. 2009-02-25 10:17:14 -08:00
Gabe Black
08f3a126d5 X86: Fix segment limit checking. 2009-02-25 10:17:08 -08:00
Gabe Black
2f31643db5 X86: Add a check to chks to verify a task state segment descriptor. 2009-02-25 10:17:02 -08:00
Gabe Black
7b1cb74ac3 X86: Add a check to chks which raises #GP(selector) if selector is NULL or not in the GDT. 2009-02-25 10:16:54 -08:00
Gabe Black
82288e7c3e X86: Add makeAtomicResponse to the read/write functions of x86 devices. 2009-02-25 10:16:43 -08:00
Gabe Black
7462cb0842 X86: Fix the timing mode of the page table walker. 2009-02-25 10:16:34 -08:00
Gabe Black
40fdba2454 X86: Make the X86 TLB take advantage of delayed translations, and get rid of the fake TLB miss faults. 2009-02-25 10:16:21 -08:00
Gabe Black
6ed47e9464 CPU: Implement translateTiming which defers to translateAtomic, and convert the timing simple CPU to use it. 2009-02-25 10:16:15 -08:00
Gabe Black
15940d06b5 SPARC: Adjust a few instructions to not write registers in initiateAcc. 2009-02-25 10:16:04 -08:00
Gabe Black
1b336a8fe7 X86: Make the stupd microop not update registers in initiateAcc. 2009-02-25 10:15:56 -08:00
Gabe Black
5605079b1f ISA: Replace the translate functions in the TLBs with translateAtomic. 2009-02-25 10:15:44 -08:00
Gabe Black
a1aba01a02 CPU: Get rid of translate... functions from various interface classes. 2009-02-25 10:15:34 -08:00
Nathan Binkert
f3090e5b70 stats: reorganize how parameters are stored and accessed. 2009-02-23 12:22:19 -08:00
Nathan Binkert
aaf98aaa32 stats: move the limits stuff into the types.hh file 2009-02-23 12:22:18 -08:00
Nathan Binkert
80d5f34da6 stats: get rid of the convoluted 'database' code. 
Just use the stuff directly and things ought to be more clear
 2009-02-23 12:22:17 -08:00
Nathan Binkert
fb74987c52 stats: Try to make the names of things more intuitive. 
Basically, this means renaming several things called data to info, which
is information about the statistics.  Things that are named data now are
actual data stored for the statistic.
 2009-02-23 12:22:15 -08:00
Nathan Binkert
bcb7e70178 stats: clean up the statistics unittest 2009-02-23 12:04:52 -08:00
Nathan Binkert
d940a2b741 stats: fix text printout for distributions 2009-02-23 12:04:50 -08:00
Nathan Binkert
f69ea20fc6 stats: cleanup static stats to make startup work. 
This is mainly to allow the unit test to run without requiring the standard
M5 stats from being initialized (e.g. sim_seconds, sim_ticks, host_seconds)
 2009-02-23 12:03:06 -08:00
Nathan Binkert
3fa9812e1d debug: Move debug_break into src/base 2009-02-23 11:48:40 -08:00
Gabe Black
e8c1c3e72e X86: Pass whether an access was a read/write/fetch so faults can behave accordingly. 2009-02-23 00:20:34 -08:00
Korey Sewell
6c5afe6346 Remove unnecessary building of FreeList/RenameMap in InOrder. Clean-up comments and O3 extensions InOrder Thread Context 2009-02-20 11:02:48 -05:00
Nathan Binkert
c41c9cf3a6 events: Make trace events happen at the right priority. 
Also, while we're at it, remember that priorities are in the Event class
and add a disable method to disable tracing.
 2009-02-18 10:00:15 -08:00
Steve Reinhardt
6cfff91d43 Make etherdump timestamps zero-based. 
We previously used the actual wall time for the base timestamps,
making etherdumps non-deterministic.  This fixes that problem and
gets rid of the "malformed packet" at the front that we needed to
provide the right base timestamp to wireshark/tcpdump.
 2009-02-17 19:24:46 -08:00
Lisa Hsu
5d029ff11e sycalls: implement mremap() and add DATA flag for getrlimit(). mremap has been tested on Alpha, compiles for the rest but not tested. I don't see why it wouldn't work though. 2009-02-16 17:47:39 -05:00
Steve Reinhardt
89a7fb0393 Fixes to get prefetching working again. 
Apparently we broke it with the cache rewrite and never noticed.
Thanks to Bao Yungang <baoyungang@gmail.com> for a significant part
of these changes (and for inspiring me to work on the rest).
Some other overdue cleanup on the prefetch code too.
 2009-02-16 08:56:40 -08:00
Gabe Black
6923282fb5 X86: Make the loader recognize 32 bit x86 processes. 2009-02-15 23:43:39 -08:00
Nathan Binkert
e0f425bb94 traceflags: fix --trace-help 2009-02-15 20:39:12 -08:00
Nathan Binkert
f255957b90 style 2009-02-10 22:19:27 -08:00
Korey Sewell
cf4a00ca41 Configs: Add support for the InOrder CPU model 2009-02-10 15:49:29 -08:00
Korey Sewell
973d8b8b13 InOrder: Import new inorder CPU model from MIPS. 
This model currently only works in MIPS_SE mode, so it will take some effort
to clean it up and make it generally useful. Hopefully people are willing to
help make that happen!
 2009-02-10 15:49:29 -08:00
Korey Sewell
36d9065f5f syscall: Expose ioctl for MIPS 2009-02-10 15:49:29 -08:00
Korey Sewell
34a5cd8870 ExeTrace: Allow subclasses of the tracer to define their own prefix to dump 2009-02-10 15:49:29 -08:00
Korey Sewell
2d0a66cbc1 CPU: Prepare CPU models for the new in-order CPU model. 
Some new functions and forward declarations are necessary to make things work
 2009-02-10 15:49:29 -08:00
Nathan Binkert
20c5ec6e1c copyright: This file need not have had the more restrictive copyright. 2009-02-09 20:10:15 -08:00
Nathan Binkert
dd6ea8797f scons: Require SCons version 0.98.1 
This allows me to clean things up so we are up to date with respect to
deprecated features.  There are many features scheduled for permanent failure
in scons 2.0 and 0.98.1 provides the most compatability for that.  It
also paves the way for some nice new features that I will add soon
 2009-02-09 20:10:14 -08:00
Nathan Binkert
9e268ae63f scons: Don't build the intermediate static library unless explicitly requested. 
This means that similar to libm5_fast.so, you need to explicitly build
build/ALPHA_SE/libm5_fast.a if you want it.
 2009-02-09 20:10:12 -08:00
Nathan Binkert
e1798d063e Quell g++ 4.3 warning about operator ambiguity 2009-02-06 20:55:50 -08:00
Nathan Binkert
64eb0dc9cd some new files are missing copyright notices 2009-02-04 16:26:15 -08:00
Gabe Black
73f579a804 X86: Add some missing default arguments. 2009-02-01 22:40:51 -08:00
Gabe Black
5a4eed5d34 X86: All x86 fault classes now attempt to do something useful. 2009-02-01 17:09:08 -08:00
Gabe Black
923a14dde7 X86: Make the fault classes handle error codes better. 2009-02-01 17:08:32 -08:00
Gabe Black
2f8cec849d X86: Make the long mode interrupt/exception microcode handle an error code. 2009-02-01 17:07:43 -08:00
Gabe Black
9b4d1e0f9a X86: Distinguish between hardware and software interrupts/exceptions 2009-02-01 17:07:18 -08:00
Gabe Black
041402a949 X86: Fix the upper bound on some ranges that were setting up the micro code assembler. 2009-02-01 17:06:25 -08:00
Gabe Black
6b53b8387e X86: Make the chks microop check for the right int descriptor type. 2009-02-01 17:05:37 -08:00
Gabe Black
c0cd58812e X86: Touch up the interrupt entering microcode. 2009-02-01 17:04:21 -08:00
Gabe Black
03a00735c2 X86: Keep track of the vector for all exceptions/faults. 2009-02-01 17:03:11 -08:00
Gabe Black
7b58511470 CPU: Don't always reset the micro pc on faults. Let the faults handle it. 2009-02-01 00:30:54 -08:00
Gabe Black
6b60a29706 X86: Fix the time keeping of the Local APIC timer. 2009-02-01 00:30:11 -08:00
Gabe Black
ca6e0d75c8 X86: Fix the microcode for the LODS instruction. 2009-02-01 00:28:28 -08:00
Gabe Black
57be1dfe48 X86: Implement pciToDma. 2009-02-01 00:27:15 -08:00
Gabe Black
70cd5bfce5 X86: Configure the first PCI interrupt. 2009-02-01 00:26:10 -08:00
Gabe Black
f1b43b39a7 X86: Hook up the IDE controller interrupt line. 2009-02-01 00:25:15 -08:00
Gabe Black
d432bd13b2 X86: Fix some incorrect register widths. 2009-02-01 00:18:13 -08:00
Gabe Black
f3b8371dfc X86: Add extended Intel MP entries correctly. 2009-02-01 00:15:38 -08:00
Gabe Black
06cdbe5ea7 X86: Compute PCI config addresses correctly. 2009-02-01 00:11:49 -08:00
Gabe Black
483c3e96b7 X86: Calculate flags based on the actual result. 2009-02-01 00:08:16 -08:00
Gabe Black
7720968949 X86: Make sure the predecoder is cleared out for interrupts. 2009-02-01 00:04:34 -08:00
Gabe Black
3ecc38cb8b Devices: Add support for legacy fixed IO locations in BARs. 2009-02-01 00:02:21 -08:00
Gabe Black
bb7ad80bbe X86: Plug in an IDE controller. 2009-02-01 00:00:03 -08:00
Gabe Black
c2c5740b98 X86: Refactor and clean up the keyboard controller. 2009-01-31 23:59:25 -08:00
Gabe Black
7cf276bed3 X86: Add a keyboard controller device. 2009-01-31 23:59:01 -08:00
Gabe Black
0287f19ede X86: Set up the console interrupt and add some DPRINTFs. 2009-01-31 23:56:46 -08:00
Gabe Black
e1c412cec6 X86: Configure the IO APIC more. 2009-01-31 23:44:05 -08:00
Gabe Black
6a3f255a84 X86: Rework interrupt pins to allow one to many connections. 2009-01-31 23:33:54 -08:00
Gabe Black
64b663c607 X86: Initialize the value behind port 61 so unused bits are consistent. 2009-01-31 23:26:43 -08:00
Gabe Black
953e4bba59 X86: Set/correct some default values for x86 parameters. 2009-02-01 16:59:34 -08:00
Ali Saidi
be5d350afc SCons: Fix how we get Mercurial revision information since internals keep changing. 2009-01-30 20:04:57 -05:00
Ali Saidi
e7293dd24e Errors: Use the correct panic/warn/fatal/info message in some places. 2009-01-30 20:04:17 -05:00
Ali Saidi
f4291aac25 Errors: Print a URL with a hash of the format string to find more information about an error. 2009-01-30 20:04:15 -05:00
Ali Saidi
35a85a4e86 Config: Cause a fatal() when a parameter without a default value isn't set(FS #315). 2009-01-30 19:08:13 -05:00
Nathan Binkert
0b228fc1ab Fix typo 2009-01-29 22:27:11 -08:00
Gabe Black
56e182a6a9 X86: Add a dummy minimal DMA controller that doesn't do anything. 2009-01-25 20:35:00 -08:00
Gabe Black
151bc018dd X86: Add a device to back the non-existant floppy drive controller. 2009-01-25 20:34:17 -08:00
Gabe Black
dbe28da1be X86: Add fake devices for non-existant serial ports. 2009-01-25 20:33:52 -08:00
Gabe Black
52defeb4e7 X86: Implement the xadd instruction. 2009-01-25 20:33:27 -08:00
Gabe Black
3c5988b86c X86: Implement the bswap instruction. 2009-01-25 20:32:43 -08:00
Gabe Black
919c3e7fb6 Dev: Make the RTC device ignore writes to a read only bit. 2009-01-25 20:32:26 -08:00
Gabe Black
0449fb2b7a X86: Fix a bug in the iret microcode. 2009-01-25 20:31:17 -08:00
Gabe Black
389fbfdab1 X86: Make the interrupt object wake up the CPU when something becomes pending. 2009-01-25 20:30:51 -08:00
Gabe Black
d9794784ba CPU: Add a setCPU function to the interrupt objects. 2009-01-25 20:29:03 -08:00
Gabe Black
3f9e2350a1 Devices: Make the destructor virtual on the CopyEnginChannel object. 
This fixes a compile warning which becomes an error.
 2009-01-25 20:26:53 -08:00
Nathan Binkert
64ed39f61b pseudo inst: Add new wake cpu instruction for sending a message to wake a cpu. 
It's instantaneous and so it's somewhat bogus, but it's a first step.
 2009-01-24 07:27:22 -08:00
Nathan Binkert
f0fb3ac060 cpu: provide a wakeup mechanism that can be used to pull CPUs out of sleep. 
Make interrupts use the new wakeup method, and pull all of the interrupt
stuff into the cpu base class so that only the wakeup code needs to be updated.
I tried to make wakeup, wakeCPU, and the various other mechanisms for waking
and sleeping a little more sane, but I couldn't understand why the statistics
were changing the way they were.  Maybe we'll try again some day.
 2009-01-24 07:27:21 -08:00
Ali Saidi
56d5212ba7 Trace: Add DPRINTFS macro that takes parameter to call name() for trace printing. 2009-01-23 17:19:48 -05:00
Ali Saidi
37ffe52ca4 IGbE: Fix two e1000 driver bugs that I missed before. 2009-01-23 17:19:47 -05:00
Nathan Binkert
10fc45da27 o3cpu: give a name to the activity recorder for better tracing 2009-01-21 14:56:18 -08:00
Nathan Binkert
dbac448b08 thread_context: move getSystemPtr so SE mode can get to it. 
There was really no reason that it should be FS only.
 2009-01-19 20:36:49 -08:00
Nathan Binkert
81b8c0c79a python: add fatal() function to the m5 package and use it 2009-01-19 14:43:09 -08:00
Nathan Binkert
da14789c32 python: Try to isolate the stuff that's in the m5.internal package a bit more. 2009-01-19 09:59:15 -08:00
Nathan Binkert
c9d3113015 tracing: Add help strings for some of the trace flags 2009-01-19 09:59:14 -08:00
Nathan Binkert
0876c822dd tracing: panic() if people try to use tracing, but TRACING_ON is not set. 
Also clean things up so that help strings can more easily be added.
Move the help function into trace.py
 2009-01-19 09:59:13 -08:00
Nathan Binkert
f15f252d4e python: Rework how things are imported 2009-01-19 09:59:13 -08:00
Nathan Binkert
51d780fa4d scons: Don't add all objects to the library twice 2009-01-19 09:03:41 -08:00
Ali Saidi
b4227bd7f6 Fix issue 326: glibc non-deterministic because it reads /proc 2009-01-17 18:56:46 -05:00
Ali Saidi
140b4b891e CopyEngine: Implement a I/OAT-like copy engine. 2009-01-17 18:55:09 -05:00
Nathan Binkert
8153790d00 SCons: centralize the Dir() workaround for newer versions of scons. 
Scons bug id: 2006 M5 Bug id: 308
 2009-01-13 14:17:50 -08:00
Richard Strong
81180a3bf0 This fix addresses an ill formed if statement that fails 
to compile. The fix was the simple addition of another set
of parenthesis to ensure the correct condition resolution.
 2009-01-11 22:45:03 -08:00
Steve Reinhardt
c370a9cb98 FastAlloc: track allocation tick in debug mode, 
minor enhancements to debug output
 2009-01-08 14:13:33 -08:00
Gabe Black
b23633ad1b X86: Hook in the M5 pseudo insts. 2009-01-06 23:55:46 -08:00
Gabe Black
115b1a7ed3 X86: Autogenerate macroop generateDisassemble function. 2009-01-06 22:55:27 -08:00
Gabe Black
8cab1805f9 X86: Move the function that prints memory args into the inst base class. 2009-01-06 22:46:28 -08:00
Gabe Black
9e24d8c599 X86: Move the macroop class out of the isa description into C++. 2009-01-06 22:44:59 -08:00
Gabe Black
7b7a72158a X86: Change indentation on microop disassembly. 2009-01-06 22:40:41 -08:00
Gabe Black
b0ab5c894d Tracing: Make tracing aware of macro and micro ops. 2009-01-06 22:34:18 -08:00
Ali Saidi
2adc60795b IGbE: Implement header splitting with large MTU 2009-01-06 10:36:57 -05:00
Ali Saidi
11ac0c7acf INET: Add functions to header types to get offset in packet and start of payload; add function to split packet at last known header 2009-01-06 10:36:56 -05:00
Ali Saidi
9f89d43b65 IGbE: Remove is8257 variable 2009-01-06 10:36:55 -05:00
Steve Reinhardt
1704ba2273 Make Alpha pseudo-insts available from SE mode. 2008-12-17 09:51:18 -08:00
Gabe Black
02cd18f536 SPARC: Truncate syscall args and return values appropriately. 2008-12-16 23:06:37 -08:00
Gabe Black
f0d1a20971 PCI: Add some missing breaks to a couple case statements. 2008-12-15 00:47:01 -08:00
Author Name
13f7fdcf67 The ide_ctrl serialize and unserialize were broken. 
Multiple channels were saving their state under the
same name. This patch separates the saved state of
the primary and secondary channel.
 2008-12-14 23:29:49 -08:00
Richard Strong
dae531c049 IDE: Fix serialization for the IDE controller. 2008-12-09 10:34:08 -08:00
Nathan Binkert
d0c0c25ebc eventq: Add some debugging code to the eventq. 2008-12-08 07:17:48 -08:00
Nathan Binkert
19273164da output: Change default output directory and files and update tests. 
--HG--
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr => tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout => tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr => tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout => tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr => tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout => tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr => tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout => tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt => tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr => tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout => tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt => tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr => tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout => tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt => tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr => tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout => tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/stderr => tests/long/00.gzip/ref/x86/linux/simple-timing/simerr
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/stdout => tests/long/00.gzip/ref/x86/linux/simple-timing/simout
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/m5stats.txt => tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stderr => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stdout => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/m5stats.txt => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stderr => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stdout => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/m5stats.txt => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr => tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout => tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt => tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr => tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout => tests/long/10.mcf/ref/sparc/linux/simple-timing/simout
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt => tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/stderr => tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout => tests/long/10.mcf/ref/x86/linux/simple-atomic/simout
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/stderr => tests/long/10.mcf/ref/x86/linux/simple-timing/simerr
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/stdout => tests/long/10.mcf/ref/x86/linux/simple-timing/simout
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/m5stats.txt => tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
rename : tests/long/20.parser/ref/x86/linux/simple-atomic/stderr => tests/long/20.parser/ref/x86/linux/simple-atomic/simerr
rename : tests/long/20.parser/ref/x86/linux/simple-atomic/stdout => tests/long/20.parser/ref/x86/linux/simple-atomic/simout
rename : tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt
rename : tests/long/20.parser/ref/x86/linux/simple-timing/stderr => tests/long/20.parser/ref/x86/linux/simple-timing/simerr
rename : tests/long/20.parser/ref/x86/linux/simple-timing/stdout => tests/long/20.parser/ref/x86/linux/simple-timing/simout
rename : tests/long/20.parser/ref/x86/linux/simple-timing/m5stats.txt => tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
rename : tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr => tests/long/30.eon/ref/alpha/tru64/o3-timing/simerr
rename : tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout => tests/long/30.eon/ref/alpha/tru64/o3-timing/simout
rename : tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr => tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr
rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout => tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout
rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr => tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr
rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout => tests/long/30.eon/ref/alpha/tru64/simple-timing/simout
rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stderr => tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simerr
rename : tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stdout => tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout
rename : tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr => tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr
rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout => tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr => tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr
rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout => tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout
rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr => tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr
rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout => tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr => tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr
rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout => tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout
rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr => tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr
rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout => tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout
rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr => tests/long/50.vortex/ref/sparc/linux/simple-atomic/simerr
rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout => tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout
rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt => tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr => tests/long/50.vortex/ref/sparc/linux/simple-timing/simerr
rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout => tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt => tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr => tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simerr
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rename : tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr => tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr
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rename : tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr => tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr
rename : tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout => tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout
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rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/stderr => tests/long/60.bzip2/ref/x86/linux/simple-atomic/simerr
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rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
rename : tests/long/60.bzip2/ref/x86/linux/simple-timing/stderr => tests/long/60.bzip2/ref/x86/linux/simple-timing/simerr
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rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr => tests/long/70.twolf/ref/alpha/tru64/o3-timing/simerr
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rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr
rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout
rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr => tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr
rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout => tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout
rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr => tests/long/70.twolf/ref/sparc/linux/simple-atomic/simerr
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rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt => tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr => tests/long/70.twolf/ref/sparc/linux/simple-timing/simerr
rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout => tests/long/70.twolf/ref/sparc/linux/simple-timing/simout
rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt => tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt
rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/stderr => tests/long/70.twolf/ref/x86/linux/simple-atomic/simerr
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rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stderr => tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr
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rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr => tests/quick/00.hello/ref/alpha/linux/o3-timing/simerr
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rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/stderr => tests/quick/00.hello/ref/x86/linux/simple-atomic/simerr
rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout => tests/quick/00.hello/ref/x86/linux/simple-atomic/simout
rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt => tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/x86/linux/simple-timing/stderr => tests/quick/00.hello/ref/x86/linux/simple-timing/simerr
rename : tests/quick/00.hello/ref/x86/linux/simple-timing/stdout => tests/quick/00.hello/ref/x86/linux/simple-timing/simout
rename : tests/quick/00.hello/ref/x86/linux/simple-timing/m5stats.txt => tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr => tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr
rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout => tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt => tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr => tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr
rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout => tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout
rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt => tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt
rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr => tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr
rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout => tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout
rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt => tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr => tests/quick/02.insttest/ref/sparc/linux/simple-timing/simerr
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout => tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt => tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/stderr => tests/quick/20.eio-short/ref/alpha/eio/detailed/simerr
rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/stdout => tests/quick/20.eio-short/ref/alpha/eio/detailed/simout
rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/m5stats.txt => tests/quick/20.eio-short/ref/alpha/eio/detailed/stats.txt
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stderr => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stderr => tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stdout => tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/m5stats.txt => tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stderr => tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stdout => tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/m5stats.txt => tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/stderr => tests/quick/50.memtest/ref/alpha/linux/memtest/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/stdout => tests/quick/50.memtest/ref/alpha/linux/memtest/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt => tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
 2008-12-08 07:16:40 -08:00
Gabe Black
9192b7f1ef Devices: Clean up the IDE controller. 2008-12-07 12:59:48 -08:00
Lisa Hsu
993b7be4bb imported patch aux-fix.patch 2008-12-07 15:07:42 -05:00
Gabe Black
e4790bcbe2 X86: Add add_entry back in. 2008-12-06 14:48:59 -08:00
Nathan Binkert
489e3e7381 eventq: use the flags data structure 2008-12-06 14:18:18 -08:00
Nathan Binkert
cbbc4501c8 eventq: move virtual function definitiions to the .cc file. 2008-12-06 14:18:18 -08:00
Nathan Binkert
a0d322be40 traceflags: Make "All" a valid trace flag. 2008-12-06 14:18:18 -08:00
Nathan Binkert
e08c6be9fe SimObject: change naming of vectors so there are the same numbers of digits. 
i.e. we used to have Foo0, Foo1, ..., Foo10, Foo11, ..., Foo100
now we have Foo000, Foo001, ..., Foo010, Foo011, ..., Foo100
 2008-12-06 14:18:18 -08:00
Nathan Binkert
e141cb7441 flags: Change naming of functions to be clearer 2008-12-06 14:18:18 -08:00
Ali Saidi
dd788a23c9 IGbE: Add support for newer 8257x based Intel NICs 2008-12-05 13:58:22 -05:00
Ali Saidi
400e516261 IGbE: Add support for TCP segment offload 2008-12-05 13:58:21 -05:00
Ali Saidi
aab595a306 INet: Allow updating on id, len, seq, and flag field for TCP segment offload 2008-12-05 13:58:21 -05:00
Lisa Hsu
854aa60fdc Automated merge with ssh://m5sim.org//repo/m5 2008-12-05 12:11:46 -05:00
Lisa Hsu
f1430941cf This brings M5 closer to modernity - the kernel being advertised is newer so it won't die on binaries compiled with newer glibc's, and enables use of TLS-toolchain built binaries for ALPHA_SE by putting auxiliary vectors on the stack. There are some comments in the code to help. Finally, stats changes for ALPHA are from slight perturbations to the initial stack frame, all minimal diffs. 2008-12-05 12:09:29 -05:00
Lisa Hsu
e2c7618e50 This patch pulls out the auxiliary vector struct from individual ISA 
LiveProcesses to the base LiveProcess definition so anyone can use them.
 2008-12-04 18:03:35 -05:00
Nathan Binkert
74f10be526 cprintf: support a configurable width and precision ("*" in printf) 2008-12-03 04:57:54 -08:00
Steve Reinhardt
041ca19edc Assume files w/o obvious OS are Linux (with warning) 
instead of giving a fatal error.
 2008-11-20 19:08:46 -08:00
Steve Reinhardt
ce4c9a7c10 Sort trace flags before printing them. 2008-11-17 12:41:50 -08:00
Clint Smullen
3087be945d Output: Include gzstream package to allow automatically-gzipped output 
The gzstream package provides an ostream-interface for writing gzipped files.
The package comes from:
    http://www.cs.unc.edu/Research/compgeom/gzstream/
And is distributed under the LGPL license. Both the license and version
information has been preservered, though all other files in the package have
been purged. Minor modifications to the code have been made. The output module
detects when a filename ends in .gz and constructs an ogzstream object instead
of an ofstream object. This works for both the create(...) and find(...)
commands. Additionally, since gzstream objects needs to be closed to ensure
proper file termination, I have the output deconstructor deleting all ostream's
that it manages on behalf of find(...). At the moment, the only output file
that I know this functionality works for is stats, i.e. by specifying
"--stats-file=m5stats.txt.gz" on the command line.
 2008-11-15 23:42:11 -05:00
Steve Reinhardt
4514f565e3 syscalls: fix latent brk/obreak bug. 
Bogus calls to ChunkGenerator with negative size were triggering
a new assertion that was added there.
Also did a little renaming and cleanup in the process.
 2008-11-15 09:30:10 -08:00
Steve Reinhardt
640b415688 Cache: get rid of obsolete Tag methods. 
I think readData() and writeData() were used for Erik's compression
work, but that code is gone, these aren't called anymore, and they
don't even really do what their names imply.
 2008-11-14 14:14:35 -08:00
Nathan Binkert
5711282f87 Fix a bunch of bugs I introduced when I changed the flags stuff for packets. 
I did some of the flags and assertions wrong. Thanks to Brad Beckmann
for pointing this out.  I should have run the opt regressions instead
of the fast. I also screwed up some of the logical functions in the Flags
class.
 2008-11-14 04:55:30 -08:00
Gabe Black
7a4d75bae3 CPU: Refactor read/write in the simple timing CPU. 2008-11-13 23:30:37 -08:00
Nathan Binkert
4d64d7664c SCons: Allow top level directory of EXTRAS able to contain SConscripts. 
The current EXTRAS will fail if the top level directory pointed to by EXTRAS
has a SConscript file in it.  We allow this by including the directory name
of the EXTRA in the build directory which prevents a clash between
src/SConscript and extra/SConscript. Maintain compatibility with older uses
of EXTRAS by adding a -I for each top level extra directory.
 2008-11-10 11:51:18 -08:00
Nathan Binkert
eb5d9ba72b pseudo inst: Add rpns (read processor nanoseconds) instruction. 
This instruction basically returns the number of nanoseconds that the CPU
has been running.
 2008-11-10 11:51:18 -08:00
Nathan Binkert
c25d966b06 Clean up the SimpleTimingPort class a little bit. 
Move the constructor into the .cc file and get rid of the typedef for
SendEvent.
 2008-11-10 11:51:18 -08:00
Nathan Binkert
ea70a44c9f clean: Move some stuff from the hh file to the cc file. 2008-11-10 11:51:18 -08:00
Nathan Binkert
4e02e7c217 python: Fix the reference counting for python events placed on the eventq. 
We need to add a reference when an object is put on the C++ queue, and remove
a reference when the object is removed from the queue.  This was not happening
before and caused a memory problem.
 2008-11-10 11:51:18 -08:00
Clint Smullen
1adfe5c7f3 O3CPU: Make the instcount debugging stuff per-cpu. 
This is to prevent the assertion from firing if you have a large multicore.
Also make sure that it's not compiled in when NDEBUG is defined
 2008-11-10 11:51:18 -08:00
Nathan Binkert
9c49bc7b00 mem: update stuff for changes to Packet and Request 2008-11-10 11:51:17 -08:00
Nathan Binkert
3535d746ab style: clean up the Packet stuff 2008-11-10 11:51:17 -08:00
Nathan Binkert
2dd699ed3d flags: Provide an object for managing boolean flags for an object. 
In many cases it might be preferable to use bitset, but this object
allows the user more easily manipulate groups of flags because the
underlying type (e.g. uint64_t) is exposed.
 2008-11-10 11:51:17 -08:00
Nathan Binkert
194f0310d3 safe_cast: add a new cast function for casts that should always succeed. 
In DEBUG mode, this does a dynamic_cast and asserts that the result is
non null.  Otherwise, it just does a static_cast.  Again, this is only
intended for cases where the cast should always succeed and what's
desired is a debugging check to make sure.
 2008-11-10 11:51:17 -08:00
Steve Reinhardt
27e8f3c98a DmaDevice: fix minor type in error message. 2008-11-10 14:45:31 -08:00
Steve Reinhardt
63127cbf37 mem: Assert that requests have non-negative size. 
Would have saved me much debugging time if these
had been in there previously.
 2008-11-10 14:11:07 -08:00
Steve Reinhardt
42bd460d7f Cache: Refactor packet forwarding a bit. 
Makes adding write-through operations easier.
 2008-11-10 14:10:28 -08:00
Gabe Black
846cb450f9 CPU: Make unaligned accesses work in the timing simple CPU. 2008-11-09 21:56:28 -08:00
Gabe Black
8c15518f30 X86: Fix completeAcc get call. 2008-11-09 21:55:43 -08:00
Gabe Black
909380f3ee X86: Make the timing simple CPU handle variable length instructions. 2008-11-09 21:55:01 -08:00
Nathan Binkert
44839d6b71 Fix a few more places where the context stuff wasn't changed 2008-11-05 07:20:03 -08:00
Lisa Hsu
46b56bb7b6 Fix SPARC_FS compile 2008-11-05 16:19:17 -05:00
Lisa Hsu
07969dbbf1 Right now a single thread cpu 1 could get assigned context Id != 1, depending 
on the order in which it's registered with the system.  To make them match,
here is a little change.
 2008-11-05 15:30:49 -05:00
Lisa Hsu
c68032ddcb decouple eviction from insertion in the cache. 2008-11-04 11:35:58 -05:00
Lisa Hsu
4ab52cb986 Change the findBlock(addr, lat) to accessBlock, which I think has better connotations for what is really happening and how it should be used. 2008-11-04 11:35:57 -05:00
Lisa Hsu
dd99ff23c6 get rid of all instances of readTid() and getThreadNum(). Unify and eliminate 
redundancies with threadId() as their replacement.
 2008-11-04 11:35:42 -05:00
Lisa Hsu
d857faf073 Add in Context IDs to the simulator. From now on, cpuId is almost never used, 
the primary identifier for a hardware context should be contextId().  The
concept of threads within a CPU remains, in the form of threadId() because
sometimes you need to know which context within a cpu to manipulate.
 2008-11-02 21:57:07 -05:00
Lisa Hsu
67fda02dda Make it so that all thread contexts are registered with the System, even in 
SE.  Process still keeps track of the tc's it owns, but registration occurs
with the System, this eases the way for system-wide context Ids based on
registration.
 2008-11-02 21:57:06 -05:00
Lisa Hsu
c55a467a06 make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered 
across the subclasses. generally make it so that member data is _cpuId and
accessor functions are cpuId(). The ID val comes from the python (default -1 if
none provided), and if it is -1, the index of cpuList will be given. this has
passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard
switch.
 2008-11-02 21:56:57 -05:00
Clint Smullen
95af120e60 CPU: The API change to EventWrapper did not get propagated to the entirety of TimingSimpleCPU. 
The constructor no-longer schedules an event at construction and the implict conversion between int and bool was allowing the old code to compile without warning.

Signed-off By: Ali Saidi
 2008-10-27 18:18:04 -04:00
Clint Smullen
cfa32d8de7 Checkpointing: createCountedDrain function, it was only returning an Event, which does not expose a setCount method to Python. 
Signed-off By: Ali Saidi
 2008-10-27 19:46:01 -04:00
Lisa Hsu
8788d703f8 s/cpu_id/cpuId in o3 (to be consistent and match style), also fix some typos in 
comments.
 2008-10-23 16:49:17 -04:00
Lisa Hsu
546a6c0c1b probe function no longer used anywhere. 2008-10-23 16:49:13 -04:00
Lisa Hsu
7a28ab2d18 remove the totally obsolete split cache 2008-10-23 16:11:28 -04:00
Nathan Binkert
9836d81c2b style: Use the correct m5 style for things relating to interrupts. 2008-10-21 07:12:53 -07:00
Ali Saidi
b760b99f4d O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. Removing hwrei causes 
the instruction after the hwrei to be fetched before the ITB/DTB_CM register is updated in a call pal
call sys and thus the translation fails because the user is attempting to access a super page address.

Minimally, it seems as though some sort of fetch stall or refetch after a hwrei is required. I think
this works currently because the hwrei uses the exec context interface, and the o3 stalls when that occurs.

Additionally, these changes don't update the LOCK register and probably break ll/sc. Both o3 changes were
removed since a great deal of manual patching would be required to only remove the hwrei change.
 2008-10-20 16:22:59 -04:00
Lisa Hsu
4fac54f227 Automated merge with ssh://daystrom.m5sim.org//z/repo/m5 2008-10-19 22:50:53 -04:00
Nathan Binkert
9b8011e255 need to add packet_access.hh in order to get tempalte definition 2008-10-16 22:22:47 -07:00
Nathan Binkert
81f5da1e89 get rid of local variable that's only used in an assert so fast compiles 2008-10-16 22:22:17 -07:00
Lisa Hsu
101c2d9174 Automated merge with ssh://daystrom.m5sim.org//z/repo/m5 2008-10-16 14:16:26 -04:00
Lisa Hsu
90e40ca982 This function declaration isn't used anywhere. 
HG: user: Lisa Hsu <hsul@eecs.umich.edu> HG: branch default HG: changed
src/mem/cache/cache.hh
 2008-10-14 17:22:03 -04:00
Nathan Binkert
5b07448cf1 eventq: make python events actually work 2008-10-14 09:34:11 -07:00
Nathan Binkert
ff2eea1ba3 eventq: revert code for unserializing events. 
Since I never implemented a proper solution, put it back to something that
at least works for now.  Once I add more event queues, I'll have to really
fix this though
 2008-10-14 09:33:52 -07:00
Gabe Black
809f6cb6d1 CPU: Explain why some code is commented out. 2008-10-12 23:52:02 -07:00
Gabe Black
34ca72d16d Get rid of some commented out code. 2008-10-12 23:50:22 -07:00
Gabe Black
3c4567f2a6 X86: Set the delayed commit flag in x86 microops appropriately. 2008-10-12 23:29:10 -07:00
Gabe Black
33ebd04474 X86: Make the local APIC timer event generate an interrupt. 2008-10-12 23:28:49 -07:00
Gabe Black
bdc28d793d X86: Implement the EOI register in the local APIC. 2008-10-12 23:28:11 -07:00
Gabe Black
fd37688294 X86: Add some DPRINTFs to the local APIC. 2008-10-12 23:27:45 -07:00
Gabe Black
be6055e0f2 X86: Make auto eoi mode work in the I8259 PIC. 2008-10-12 23:27:08 -07:00
Gabe Black
fb5bb434a9 X86: Make non-specific EOI commands work. 2008-10-12 23:25:48 -07:00
Gabe Black
8e664f3959 X86: Make the I8259 PIC accept a specific EOI command. 2008-10-12 23:22:58 -07:00
Gabe Black
e3004c579f X86: Fix the segment setting code in IRET, and make it restore the flags. 2008-10-12 23:05:22 -07:00
Gabe Black
349a155b6e X86: Panic when an unimplemented fault is invoked, rather than spinning forever 2008-10-12 23:00:28 -07:00
Gabe Black
564eda827b X86: Implement the swapgs instruction. 2008-10-12 23:00:07 -07:00
Gabe Black
a2e0d539d8 X86: Add wrval/rdval microops for reading significant miscregs. 2008-10-12 22:55:55 -07:00
Gabe Black
9e8e2f9ec6 X86: Make the x86 interrupt fault kick off the interrupt microcode. 2008-10-12 22:42:10 -07:00
Gabe Black
4c19c56a77 X86: Implement entering an interrupt in microcode. 2008-10-12 22:42:03 -07:00
Gabe Black
f813a4be49 X86: Make sure register microops set fault rather than returning one. 2008-10-12 22:24:06 -07:00
Gabe Black
961b40cdb5 X86: Implement an wrdh microop which loads bases/offsets from 16 byte descriptors. 2008-10-12 22:16:53 -07:00
Gabe Black
989fa4fc0f X86: Make the MicroPC type 16 bit. 2008-10-12 20:48:24 -07:00
Gabe Black
6074b1abf2 X86: Implement local labels for the ROM that actually refer into the ROM. 2008-10-12 20:44:11 -07:00
Gabe Black
6b46e5204d X86: Implement the chks check of interrupt gate target code segments. 2008-10-12 20:38:22 -07:00
Gabe Black
30feb90c1c X86: Add a check type for interrupt gates. 2008-10-12 20:33:37 -07:00
Gabe Black
15f5bb3055 X86: Fix chks checking the submode for stack segments. 2008-10-12 20:29:52 -07:00
Gabe Black
9e1fe2050a X86: Let segment manipulation microops be conditional. 2008-10-12 20:25:06 -07:00
Gabe Black
e9158d763a X86: Let the microassembler know about the microcode only H segment. 2008-10-12 20:17:38 -07:00
Gabe Black
223fc41c07 X86: Fix the rdbase microop 2008-10-12 20:07:46 -07:00
Gabe Black
0756dbb37a X86: Don't fetch in the simple CPU if you're in the ROM. 2008-10-12 19:32:06 -07:00
Gabe Black
f245358343 Get rid of old RegContext code. 2008-10-12 17:57:46 -07:00
Gabe Black
cefb768131 X86: Create a handy way to access labels from the ROM in microcode. 2008-10-12 17:52:51 -07:00
Gabe Black
e5f8092467 X86: Make X86's microcode ROM actually do something. 2008-10-12 17:48:44 -07:00
Gabe Black
c9ea0b7349 CPU: Make the highest order bit in the micro pc determine if it's combinational or from the ROM. 2008-10-12 16:59:55 -07:00
Gabe Black
2736086d7c CPU: Create a microcode ROM object in the CPU which is defined by the ISA. 2008-10-12 15:59:21 -07:00
Gabe Black
6fd4eff68f X86: Create an eret microop which returns from ROM to combinational decoding. 2008-10-12 15:53:04 -07:00
Gabe Black
4aa18aa800 X86: Make Br never report itself as the last microop. 2008-10-12 15:43:35 -07:00
Gabe Black
77c0e1d110 X86: Create a SeqOp class of microops and make Br one of them. 2008-10-12 15:33:17 -07:00
Gabe Black
a76c4b8ca1 X86: Implement CPUID with a magical function instead of microcode. 2008-10-12 15:31:28 -07:00
Gabe Black
d0a43ce2b2 X86: Fix the ordering of special physical address ranges. 2008-10-12 14:01:06 -07:00
Gabe Black
3a1905157e X86: Create a mechanism for the IO APIC to access I8259 vectors. 2008-10-12 13:54:57 -07:00
Gabe Black
c35da8e495 X86: Actually use the extra vector bits we get from ICW2. 2008-10-12 13:51:48 -07:00
Gabe Black
ec9d3aad71 X86: Make the local APIC process interrupts and send them to the CPU. 2008-10-12 13:45:21 -07:00
Gabe Black
876f4845f2 X86: Make the local APIC handle interrupt messages from the IO APIC. 2008-10-12 13:44:24 -07:00
Gabe Black
4d5c7f7038 X86: Change the default value for the IO APIC redirection table. 2008-10-12 13:35:26 -07:00
Gabe Black
3420ad7644 X86: Make the bases for x86 fault class public. 2008-10-12 13:29:26 -07:00
Gabe Black
557bde43c3 X86: Make APICs communicate through the memory system. 2008-10-12 13:28:54 -07:00
Gabe Black
e459013182 Create a message port for sending messages as apposed to reading/writing a memory range. 2008-10-12 12:08:51 -07:00
Gabe Black
e0f137a87c X86: Add a LocalApic trace flag. 2008-10-12 12:07:25 -07:00
Gabe Black
42ebebf99a X86: Make the local APIC accessible through the memory system directly, and make the timer work. 2008-10-12 11:08:00 -07:00
Gabe Black
d9f9c967fb Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object. 2008-10-12 09:09:56 -07:00
Gabe Black
c4f1cc3b48 CPU: Eliminate the get_vec function. 2008-10-12 08:24:09 -07:00
Gabe Black
0c3848732e CPU: Add a getInterruptController function 2008-10-11 16:13:58 -07:00
Gabe Black
168e524b9b X86: Create an IO APIC device. 2008-10-11 16:08:14 -07:00
Gabe Black
a2599e4fc1 X86: Set up a mechanism for the I8254 timer to cause interrupts. 2008-10-11 15:15:34 -07:00
Gabe Black
526933e5d0 X86: Add an Intel MP table to the simulation. 2008-10-11 15:14:37 -07:00
Gabe Black
f621b7b81f CPU: Eliminate the simPalCheck funciton. 2008-10-11 12:17:24 -07:00
Gabe Black
da7209ec93 CPU: Eliminate the hwrei function. 2008-10-11 02:27:21 -07:00
Gabe Black
3af428606a X86: Rename the PC device to Pc. 
--HG--
rename : src/dev/x86/PC.py => src/dev/x86/Pc.py
 2008-10-11 02:23:40 -07:00
Gabe Black
826621eb17 X86: Bring the South Bridge device into dev/x86 and get rid of south_bridge directory. 
--HG--
rename : src/dev/x86/south_bridge/SouthBridge.py => src/dev/x86/SouthBridge.py
rename : src/dev/x86/south_bridge/south_bridge.cc => src/dev/x86/south_bridge.cc
rename : src/dev/x86/south_bridge/south_bridge.hh => src/dev/x86/south_bridge.hh
 2008-10-11 02:21:44 -07:00
Gabe Black
bc2217eefc X86: Change I8254 and PCSpeaker devices from subdevices to SimObjects and eliminate subdevices. 
--HG--
rename : src/dev/x86/south_bridge/i8254.cc => src/dev/x86/i8254.cc
rename : src/dev/x86/south_bridge/i8254.hh => src/dev/x86/i8254.hh
rename : src/dev/x86/south_bridge/speaker.cc => src/dev/x86/speaker.cc
rename : src/dev/x86/south_bridge/speaker.hh => src/dev/x86/speaker.hh
 2008-10-11 02:16:11 -07:00
Gabe Black
a6600fdd88 Devices: Make the Intel8254Timer device only use pointers to its counters. 2008-10-11 01:49:39 -07:00
Gabe Black
539563e04b X86: Make the CMOS and I8259 devices use IntDev and IntPin. 2008-10-11 01:45:25 -07:00
Gabe Black
119e127d71 X86: Create the IntDev and IntPin system. 
The IntDev class is a base for anything that supports IntPins. IntPins allow
devices to generically trigger interrupts on a particular pin of an IntDev
device without having to know what the device is or what pin they're attached
to.
 2008-10-11 01:37:04 -07:00
Gabe Black
8c532d6297 X86: Hook the CMOS device to the I8259 PICs. 2008-10-11 01:31:32 -07:00
Gabe Black
cf9afbba51 X86: Make the I8259 decipher the commands it's given, and add some of it's registers. 2008-10-11 01:28:35 -07:00
Gabe Black
2753c07dc5 X86: Change the I8259 from a subdevice into a real SimObject. 
--HG--
rename : src/dev/x86/south_bridge/i8259.cc => src/dev/x86/i8259.cc
rename : src/dev/x86/south_bridge/i8259.hh => src/dev/x86/i8259.hh
 2008-10-11 01:22:20 -07:00
Gabe Black
f22c7d48f3 X86: Change the CMOS from a sub-device to a real SimObject 
--HG--
rename : src/dev/x86/south_bridge/cmos.cc => src/dev/x86/cmos.cc
rename : src/dev/x86/south_bridge/cmos.hh => src/dev/x86/cmos.hh
 2008-10-11 01:13:11 -07:00
Gabe Black
8c5dfa4532 TLB: Make all tlbs derive from a common base class in both python and C++. 2008-10-10 23:47:42 -07:00
Gabe Black
3d1734ec29 X86: Create SimObjects in python and C++ to represent the ACPI system description tables. 2008-10-10 23:43:33 -07:00
Gabe Black
f85a7f00c0 X86: Make the time on the RTC configurable. 2008-10-10 23:42:31 -07:00
Gabe Black
b03c95d075 X86: Create SimObjects in python and C++ to represent the Intel MP tables. 2008-10-10 23:39:53 -07:00
Nathan Binkert
89f016aacb cprintf: properly deal with pointer types 2008-10-10 21:45:35 -07:00
Nathan Binkert
1f57193439 swig: Add in a %rename to allow the same name to appear in multiple namespaces. 2008-10-10 21:45:34 -07:00
Nathan Binkert
96936c6bf5 Rename the info function to inform to avoid likely name conflicts 2008-10-10 12:17:53 -07:00
Nathan Binkert
8ac63c48a4 automerge 2008-10-10 10:38:53 -07:00
Nathan Binkert
afb279b1bb output: Make panic/fatal/warn more flexible so we can add some new ones. 
The major thrust of this change is to limit the amount of code
duplication surrounding the code for these functions.  This code also
adds two new message types called info and hack.  Info is meant to be
less harsh than warn so people don't get confused and start thinking
that the simulator is broken.  Hack is a way for people to add runtime
messages indicating that the simulator just executed a code "hack"
that should probably be fixed.  The benefit of knowing about these
code hacks is that it will let people know what sorts of inaccuracies
or potential bugs might be entering their experiments.  Finally, I've
added some flags to turn on and off these message types so command
line options can change them.
 2008-10-10 10:18:28 -07:00
Nathan Binkert
b25e56b32a gdb: add a debugging function that enters the python interpreter. 2008-10-10 10:15:01 -07:00
Nathan Binkert
70dbe61ffc jobfile: Add support for dictionaries as jobfile options. 
If the same dictionary option is seen in several options, those
dictionaries are composed.  If you define the same dictionary key in
multiple options, the system flags an error.
Also, clean up the jobfile code so that it is more debuggable.
 2008-10-10 10:15:01 -07:00
Nathan Binkert
84364f36d0 python: Add a utility for nested attribute dicts. 
Change attrdict so that attributes that begin with an underscore don't
go into the dict.
 2008-10-10 10:15:00 -07:00
Nathan Binkert
5586b1539b misc: remove #include <cassert> from misc.hh since not everyone needs it. 2008-10-10 10:15:00 -07:00
Gabe Black
ec0fb05d64 X86: Turn SMBios structures into simobjects. 2008-10-10 03:50:51 -07:00
Gabe Black
9be6e08227 X86: Add a couple comments to the bios SConscript 2008-10-10 03:50:42 -07:00
Gabe Black
d897aa939f X86: Move the smbios objects into a folder for BIOS objects. 2008-10-10 03:50:18 -07:00
Gabe Black
57d663877e X86: Fix compilation with new eventq API. 2008-10-10 03:50:07 -07:00
Nathan Binkert
94b08bed07 SimObjects: Clean up handling of C++ namespaces. 
Make them easier to express by only having the cxx_type parameter which
has the full namespace name, and drop the cxx_namespace thing.
Add support for multiple levels of namespace.
 2008-10-09 22:19:39 -07:00
Nathan Binkert
4ecc5d53a3 range_map: Add a method to find which range a single value falls into. 2008-10-09 22:19:38 -07:00
Nathan Binkert
6ccf28c896 style: conform to M5 style. 2008-10-09 09:25:41 -07:00
Nathan Binkert
b556dc4119 mem: Add a method for setting the time on a packet. 2008-10-09 04:58:24 -07:00
Nathan Binkert
e06321091d eventq: convert all usage of events to use the new API. 
For now, there is still a single global event queue, but this is
necessary for making the steps towards a parallelized m5.
 2008-10-09 04:58:24 -07:00
Nathan Binkert
8291d9db0a eventq: Major API change for the Event and EventQueue structures. 
Since the early days of M5, an event needed to know which event queue
it was on, and that data was required at the time of construction of
the event object.  In the future parallelized M5, this sort of
requirement does not work well since the proper event queue will not
always be known at the time of construction of an event.  Now, events
are created, and the EventQueue itself has the schedule function,
e.g. eventq->schedule(event, when).  To simplify the syntax, I created
a class called EventManager which holds a pointer to an EventQueue and
provides the schedule interface that is a proxy for the EventQueue.
The intent is that objects that frequently schedule events can be
derived from EventManager and then they have the schedule interface.
SimObject and Port are examples of objects that will become
EventManagers.  The end result is that any SimObject can just call
schedule(event, when) and it will just call that SimObject's
eventq->schedule function.  Of course, some objects may have more than
one EventQueue, so this interface might not be perfect for those, but
they should be relatively few.
 2008-10-09 04:58:23 -07:00
Nathan Binkert
68c75c589b pdb: Try to make pdb work better. 
I've done a few things here.  First, I invoke the script a little bit
differently so that pdb doesn't get confused.  Second, I've stored the
actual filename in the module's __file__ so that pdb can find the
source file on your machine.
 2008-10-09 04:58:23 -07:00
Nathan Binkert
886c5f8fe5 SINIC: Commit old code from ASPLOS 2006 studies. 
NOTE: This code was written by Nathan Binkert in 2006 and is properly copyright
"The Regents of the University of Michigan"
 2008-10-09 04:58:23 -07:00
Nathan Binkert
eb89a23556 eventq: Don't use inline friend function when a static function will do. 
Another good reason to avoid this is that swig will try to wrap the friend,
but it won't try to wrap a private static function.
 2008-10-09 04:58:23 -07:00
Nathan Binkert
a589eb4053 SCons: add code to provide a libm5 shared library. 
Targets look like libm5_debug.so.  This target can be dynamically
linked into another C++ program and provide just about all of the M5
features.  Additionally, this library is a standalone module that can
be imported into python with an "import libm5_debug" type command
line.
 2008-10-09 04:58:23 -07:00
Nathan Binkert
0b83563a9c eventq: I'm sick of the warning about MaxTick being unused. 2008-10-09 04:58:23 -07:00
Nathan Binkert
7cc2a88038 stats: use properly signed types for looping and comparison 2008-10-09 04:58:23 -07:00
Nathan Binkert
a52dce6d62 style: Bring statistics code in line with the proper style. 2008-10-09 04:58:23 -07:00
Gabe Black
b66eb3b8d1 O3: Generaize the O3 IMPL class so it isn't split out by ISA. 
--HG--
rename : src/cpu/o3/sparc/cpu_builder.cc => src/cpu/o3/cpu_builder.cc
rename : src/cpu/o3/sparc/dyn_inst.cc => src/cpu/o3/dyn_inst.cc
rename : src/cpu/o3/sparc/impl.hh => src/cpu/o3/impl.hh
rename : src/cpu/o3/sparc/thread_context.cc => src/cpu/o3/thread_context.cc
 2008-10-09 00:10:02 -07:00
Gabe Black
f57c286d2c O3: Generaize the O3 dynamic instruction class so it isn't split out by ISA. 
--HG--
rename : src/cpu/o3/dyn_inst.hh => src/cpu/o3/dyn_inst_decl.hh
rename : src/cpu/o3/alpha/dyn_inst_impl.hh => src/cpu/o3/dyn_inst_impl.hh
 2008-10-09 00:09:26 -07:00
Gabe Black
e09c403d32 O3: Generalize the O3 CPU object so it isn't split out by ISA. 2008-10-09 00:08:50 -07:00
Gabe Black
975c9e3af8 Microcode: Fix a silent typo error in the microcode assembler. 2008-10-09 00:07:38 -07:00
Gabe Black
523531a40e Microcode: Fix a very old bug with parsing external labels in microcode. 2008-10-09 00:07:21 -07:00
Gabe Black
c5c6ad7ed6 CPU: Fix where setMicroPC was being called instead of setNextMicroPC. 2008-10-09 00:06:05 -07:00
Gabe Black
e1b306fa53 X86: Fix the debugging microops. The debug functions can't handle a string object format. 2008-10-09 00:05:39 -07:00
Gabe Black
569db520ad X86: Make far ret modify CS instead of some random selector. 2008-10-09 00:04:36 -07:00
Nathan Binkert
6b2bb53fd6 python: cleanup options parsing stuff so that it properly deals with defaults. 
While we're at it, make it possible to run main.py in a somewhat
standalone mode again so that we can test things without compiling.
 2008-10-06 09:31:51 -07:00
Korey Sewell
6c046a28dc fix shadow set bugs in MIPS code that caused out of bounds access... 
panic rdpgpr/wrpgpr instructions until a better impl.
of MIPS shadow sets is available.
 2008-10-06 02:07:04 -04:00
Nathan Binkert
b25755993b unittest: Add unit tests to the scons framework. 
Also fix the unit tests so they actually compile correctly.
 2008-10-02 11:27:01 -07:00
Nathan Binkert
52493b2720 unittest: Cleanup unit tests. Follow style. Garbage Collect. 
--HG--
rename : src/unittest/rangemaptest2.cc => src/unittest/rangemultimaptest.cc
 2008-10-02 11:26:59 -07:00
Nathan Binkert
67a2918abc stats: Fix small bug pointed out by unit testing. 2008-10-02 11:26:59 -07:00
Ali Saidi
0a1613abe1 Output: Verify output files are open after opening them. 2008-10-02 12:46:57 -04:00
Steve Reinhardt
7bf6a219db Make overriding port assignments in Python work, 
and print better error messages when it doesn't.
 2008-09-29 23:30:14 -07:00
Steve Reinhardt
45cba35fc1 Fix EVENTQ_DEBUG vs DEBUG_EVENTQ #define inconsistency. 2008-09-29 23:30:14 -07:00
Nathan Binkert
1e9c428522 alpha: Need to include cstring so that g++ 4.3 works. 2008-09-29 07:15:30 -07:00
Nathan Binkert
80d9be86e6 gcc: Add extra parens to quell warnings. 
Even though we're not incorrect about operator precedence, let's add
some parens in some particularly confusing places to placate GCC 4.3
so that we don't have to turn the warning off.  Agreed that this is a
bit of a pain for those users who get the order of operations correct,
but it is likely to prevent bugs in certain cases.
 2008-09-27 21:03:49 -07:00
Nathan Binkert
cf7ddd8e8a style: Make a style pass over the whole arch/alpha directory. 2008-09-27 21:03:48 -07:00
Nathan Binkert
82f5723c7a alpha: Clean up namespace usage. 2008-09-27 21:03:47 -07:00
Nathan Binkert
8ea5176b7f arch: TheISA shouldn't really ever be used in the arch directory. 
We should always refer to the specific ISA in that arch directory.
This is especially necessary if we're ever going to make it to the
point where we actually have heterogeneous systems.
 2008-09-27 21:03:46 -07:00
Nathan Binkert
0b30c345f1 alpha: Get rid fo the namespace called EV5. 
We're never going to do an alpha platform other than the one we've got.
 2008-09-27 21:03:45 -07:00
Nathan Binkert
819023b8e2 style 2008-09-27 07:25:04 -07:00
Nathan Binkert
83f3bff643 add a bit of style 2008-09-27 00:15:45 -07:00
Nathan Binkert
ca4baf3871 style: missed space after switch 2008-09-26 09:37:21 -07:00
Nathan Binkert
9838be2521 When nesting if statements, use braces to avoid ambiguous else clauses. 2008-09-26 08:18:57 -07:00
Nathan Binkert
abca171e24 Use logical operator instead of bitwise operator for correctness. 2008-09-26 08:18:56 -07:00
Nathan Binkert
6798aa14ed style: bring this file into M5 style, use the new pte translate function. 2008-09-26 08:18:55 -07:00
Nathan Binkert
a053055e17 scons: disable several gcc warnings for swig autogenerated wrapper code. 2008-09-26 08:18:54 -07:00
Nathan Binkert
0309c877f3 style: These files didn't even come close to following the M5 style guide. 2008-09-26 08:18:53 -07:00
Kevin Lim
b784903207 O3CPU: Fix thread writeback logic. 
Fix the logic in the LSQ that determines if there are any stores to
write back. In the commit stage, check for thread specific writebacks
instead of just any writeback.
 2008-09-26 07:44:07 -07:00
Kevin Lim
712a8ee700 O3CPU: Add a hack to ensure that nextPC is set correctly after syscalls. 
Just check CPU's nextPC before and after syscall and if it changes,
update this instruction's nextPC because the syscall must have changed
the nextPC.
 2008-09-26 07:44:06 -07:00
Nathan Binkert
70ec46de17 sparc: Fix style, create a helper function for translation. 
The translate function simplifies code and removes some compiler
warnings in gcc 3.4
 2008-09-23 20:38:02 -07:00
Nathan Binkert
38dd9687ce scons: Separate swig environment so we can have different flags. 
Swig code isn't quite perfect, so let's not turn on all of the warnings.
 2008-09-22 08:25:58 -07:00
Nathan Binkert
6efb930e19 gcc: Version 4.3 is pretty anal about shadowing types, placate it. 
In the future, it would be nice to put the O3CPU into its own
namespace so that we don't end up hardcoding pointers to the global
namespace.
 2008-09-22 08:25:57 -07:00
Nathan Binkert
f3f4b17c5b style 2008-09-22 08:21:47 -07:00
Nathan Binkert
4826610d86 We're using the static keyword improperly in some cases. 2008-09-19 09:42:54 -07:00
Nathan Binkert
ce3d8c2b03 atomicio: provide atomic read and write functions. 
These functions keep trying to read and write until all data has been
transferred, or an error occurrs.  In the case where an end of file
hasn't been reached, but all of the bytes have not been read/written,
try again.  On EINTR, try again.
 2008-09-19 09:42:31 -07:00
Nathan Binkert
af9c5e05f7 Use C++ limits where applicable for portability 2008-09-19 09:11:43 -07:00
Nathan Binkert
befae3c0b0 Use the proper version of C++ headers 2008-09-19 09:11:43 -07:00
Nathan Binkert
ea83cedcf6 Check the return value of I/O operations for failure 2008-09-19 09:11:42 -07:00
Nathan Binkert
f066db7fcd inifile: Whack preprocessor access. 
We haven't used the preprocessor feature of the inifile stuff in a
very long time, so let's get rid of it since it would otherwise take
effort to maintain.
 2008-09-19 09:11:40 -07:00
Ali Saidi
3a3e356f4e style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs 2008-09-10 14:26:15 -04:00
Nathan Binkert
09a8fb0b52 style: this file did not conform to style 2008-09-09 16:27:17 -07:00
Nathan Binkert
496d3f2789 style: This file hugely violated the M5 style. 
Remove a bunch of unused cruft from the interface while we're at it
 2008-09-08 18:03:52 -07:00
Gabe Black
30bc897613 X86: Fix the microcode for sign/zero extending moves that use high byte registers. 2008-09-03 00:52:54 -04:00
Clint Smullen
4aa017affc Device: Fix bug in DmaPort::recvRetry. The interface attempts to send the same packet again. 
It doesn't cause a problem currently, however with a different Memory Object it could cause
problems
 2008-08-26 02:37:26 -04:00
Ali Saidi
3d5fe0c372 IGbE: Patches I neglected to apply before pushing the previous igbe changeset 2008-08-24 15:27:49 -04:00
Gabe Black
3633a916c2 CPU: Get rid of two more duplicated CPU params. 2008-08-19 21:59:09 -07:00
Richard Strong
8d018aef0f Changed BaseCPU::ProfileEvent's interval member to be of type Tick. This was done to be consistent with its 
python type of a latency.  In addition, the multiple definitions of profile in the different cpu models caused
problems for intialization of the interval value. If a child class's profile value was defined, the parent
BaseCPU::ProfileEvent interval field would be initialized with a garbage value. The fix was to remove the
multiple redifitions of profile in the child CPU classes.
 2008-08-18 10:50:58 -07:00
Ali Saidi
6248e12704 Add the ability to specify a think time before descriptor fetch/writeback starts/ends as well as after read/write dmas 2008-08-13 17:41:58 -04:00
Ali Saidi
549c43b2d0 Add the ability for a DMA to tack on an extra delay after the DMA is actually finished. 2008-08-13 17:41:56 -04:00
Ali Saidi
05954e1ba7 More subtle fixes to how interrupts are supposed to work in the device. Fix postedInterrupts statistics. 2008-08-13 16:30:30 -04:00
Ali Saidi
91d968783e Return an UnimpFault for an ITB translation of an uncachable address. We don't support fetching from uncached addresses in Alpha and it means that a speculative fetch can clobber device registers. 2008-08-13 16:29:59 -04:00
Nathan Binkert
1b1a7e33e7 style 2008-08-11 14:47:49 -07:00
Nathan Binkert
9cf8ad3a17 params: Get rid of the remnants of the old style parameter configuration stuff. 2008-08-11 12:22:17 -07:00
Nathan Binkert
ee62a0fec8 params: Convert the CPU objects to use the auto generated param structs. 
A whole bunch of stuff has been converted to use the new params stuff, but
the CPU wasn't one of them.  While we're at it, make some things a bit
more stylish. Most of the work was done by Gabe, I just cleaned stuff up
a bit more at the end.
 2008-08-11 12:22:16 -07:00
Steve Reinhardt
3448a12208 Make time format in 'started' line same as 'compiled'. 
Also make -B output consistent with normal header, and
only include actual build options.
 2008-08-04 01:46:46 -04:00
Steve Reinhardt
58c63ea8b1 Get rid of outputStream... wasn't really being used 
(except for warn()) and new -r/-e options make it
not worth fixing.
 2008-08-04 01:45:12 -04:00
Steve Reinhardt
fe8aeff362 Add -r/-e options to redirect stdout/stderr. 
Better than using shell since it automatically uses -d directory
for output files (creating it as needed).
 2008-08-04 00:40:31 -04:00
Nathan Binkert
50ef39af82 sockets: Add a function to disable all listening sockets. 
When invoking several copies of m5 on the same machine at the same
time, there can be a race for TCP ports for the terminal connections
or remote gdb.  Expose a function to disable those ports, and have the
regression scripts disable them.  There are some SimObjects that have
no other function than to be used with ports (NativeTrace and
EtherTap), so they will panic if the ports are disabled.
 2008-08-03 18:19:55 -07:00
Nathan Binkert
ede89c2d54 libm5: Create a libm5 static library for embedding m5. 
This should allow m5 to be more easily embedded into other simulators.
The m5 binary adds a simple main function which then calls into the m5
libarary to start the simulation. In order to make this work
correctly, it was necessary embed python code directly into the
library instead of the zipfile hack.  This is because you can't just
append the zipfile to the end of a library the way you can a binary.
As a result, Python files that are part of the m5 simulator are now
compile, marshalled, compressed, and then inserted into the library's
data section with a certain symbol name.  Additionally, a new Importer
was needed to allow python to get at the embedded python code.

Small additional changes include:
- Get rid of the PYTHONHOME stuff since I don't think anyone ever used
it, and it just confuses things.  Easy enough to add back if I'm wrong.
- Create a few new functions that are key to initializing and running
the simulator: initSignals, initM5Python, m5Main.

The original code for creating libm5 was inspired by a patch Michael
Adler, though the code here was done by me.
 2008-08-03 18:19:54 -07:00
Nathan Binkert
678abbc364 syscall: Avoid a compiler warning which turns into a bug. 
Simply cast the result to an int and life is good.
 2008-08-03 18:19:53 -07:00
Steve Reinhardt
62c08a75ad Make default PhysicalMemory latency slightly more realistic. 
Also update stats to reflect change.
 2008-08-03 18:13:29 -04:00
Gabe Black
b179c3f4cd X86: Make hint nops consume their modrm byte. 2008-08-03 14:43:24 -07:00
Nathan Binkert
e98ccd309b kill unused code 2008-08-02 20:42:15 -07:00
Nathan Binkert
4b1e0d235d scons: Get rid of generate.py in the build system. 
I decided that separating some of the scons code into generate.py was
just a bad idea because it caused the dependency system to get all
messed up.  If separation is the right way to go in the future, we
should probably use the sconscript mechanism, not the mechanism that I
just removed.
 2008-07-31 08:01:38 -07:00
Michael Adler
f3a3ab7f2c syscall: Fix TTY emulation in fstat() user-mode simulation for fd 1 (stdout). 
The code didn't set S_IFCHR in the st_mode
 2008-07-24 16:31:33 -07:00
Michael Adler
5f42bfcd56 process: separate stderr from stdout 
- Add the option of redirecting stderr to a file. With the old
behaviour, stderr would follow stdout if stdout was to a file, but
stderr went to the host stderr if stdout went to the host stdout.  The
new default maintains stdout and stderr going to the host.  Now the
two can specify different files, but they will share a file descriptor
if the name of the files is the same.
- Add --output and --errout options to se.py to go with --input.
 2008-07-23 14:41:34 -07:00
Michael Adler
2cd04fd6da syscalls: Add a bunch of missing system calls. 
readlink, umask, truncate, ftruncate, mkdir, and getcwd.
 2008-07-23 14:41:33 -07:00
Michael Adler
8c4f18f6f5 RemoteGDB: add an m5 command line option for setting or disabling remote gdb. 2008-07-23 14:41:33 -07:00
Steve Reinhardt
aa2bb4f7b9 Get rid of useless m5_assert macro. 
Its only purpose was to print the cycle number but that already
happens in the SIGABRT handler.  No one used it anyway.
 2008-07-15 14:38:51 -04:00
Steve Reinhardt
8e7ddce284 Use ReadResp instead of LoadLockedResp for LoadLockedReq responses. 2008-07-15 14:38:51 -04:00
Steve Reinhardt
6262e0d909 Add missing newlines to Bus DPRINTFs. 2008-07-15 14:38:51 -04:00
Nathan Binkert
f9a597ddf3 m5ops: clean up the m5ops stuff. 
- insert warnings for deprecated m5ops
- reserve opcodes for Ali's stuff
- remove code for stuff that has been deprecated forever
- simplify m5op_alpha
 2008-07-11 08:52:50 -07:00
Nathan Binkert
88766f7c71 style: fix indentation and formatting of the pseudo insts. 2008-07-11 08:52:50 -07:00
Nathan Binkert
f90b08a5cc eventq: change the event datastructure back to LIFO. 
The status quo is preferred since it is less likely that people will
rely on LIFO than FIFO, and when we move to a parallelized M5, no
ordering between events of the same time/priority will be guaranteed.
 2008-07-11 08:48:50 -07:00
Nathan Binkert
10df68dd72 eventq: new eventq data structure. The new data structure is singly 
linked list sorted by time and priority.  For things of the same time
and priority, a second, circularly linked list maintains the data
structure.  Events of the same time and priority are now inserted in
FIFO order instead of LIFO order.  This dramatically improves the
performance of systems that schedule multiple events at the same time.

The FIFO order version is not preferred to LIFO (because it may cause
people to rely on it), but I'm going to commit it anyway and
immediately commit the preferred LIFO version on top.
 2008-07-11 08:38:31 -07:00
Nathan Binkert
93517dd90c eventq: Clean up the Event class so that it uses fewer bytes. This 
will hopefullly allow it to fit in a cache line.
 2008-07-10 21:35:42 -07:00
Ali Saidi
7a83c50a59 Fix cases where RADV interrupt timer is used and make ITR interrupt moderation not always delay if no interrupts have been posted for the ITR value. 2008-07-01 10:30:08 -04:00
Ali Saidi
a4a7a09e96 Remove delVirtPort() and make getVirtPort() only return cached version. 2008-07-01 10:25:07 -04:00
Ali Saidi
c5fbbf376a Change everything to use the cached virtPort rather than created their own each time. 
This appears to work, but I don't want to commit it until it gets tested a lot more.
I haven't deleted the functionality in this patch that will come later, but one question
is how to enforce encourage objects that call getVirtPort() to not cache the virtual port
since if the CPU changes out from under them it will be worse than useless. Perhaps a null
function like delVirtPort() is still useful in that case.
 2008-07-01 10:24:19 -04:00
Ali Saidi
50e3e50e1a Make the cached virtPort have a thread context so it can do everything that a newly created one can. 2008-07-01 10:24:16 -04:00
Ali Saidi
9bd0bfe559 After a checkpoint (and thus a stats reset), the not_idle_fraction/notIdleFraction statistic is really wrong. 
The notIdleFraction statistic isn't updated when the statistics reset, probably because the cpu Status information
was pulled into the atomic and timing cpus. This changeset pulls Status back into the BaseSimpleCPU object. Anyone
care to comment on the odd naming of the Status instance? It shouldn't just be status because that is confusing
with Port::Status, but _status seems a bit strage too.
 2008-07-01 10:24:09 -04:00
Steve Reinhardt
96bbccc36b Automated merge after backout. 2008-06-28 13:20:00 -04:00
Steve Reinhardt
caaac16803 Backed out changeset 94a7bb476fca: caused memory leak. 2008-06-28 13:19:38 -04:00
Ali Saidi
3205768ea5 Automated merge with http://repo.m5sim.org/m5-stable 2008-06-24 15:51:12 -04:00
Ali Saidi
57b5de6b9f Checkpoinging/SWIG: Undo part of changeset 5464 since it broke checkpointing. 2008-06-24 15:48:45 -04:00
Gabe Black
18c83be507 SimObject: Add in missing includes of <string> and fix minor style problem. 2008-06-21 14:23:58 -04:00
Steve Reinhardt
1434b86943 Make bus address conflict error more informative 2008-06-21 01:06:27 -04:00
Steve Reinhardt
6b45238316 Generate more useful error messages for unconnected ports. 
Force all non-default ports to provide a name and an
owner in the constructor.
 2008-06-21 01:04:43 -04:00
Nathan Binkert
c1584e4227 imported patch sim_object_params.diff 2008-06-18 12:07:15 -07:00
Nathan Binkert
67a33eed40 AtomicSimpleCPU: Separate data stalls from instruction stalls. 
Separate simulation of icache stalls and dat stalls.
 2008-06-18 10:15:21 -07:00
Nathan Binkert
1099a9838a Ethernet: share statistics between all ethernet devices and apply some 
of those statistics to the e1000 model.
 2008-06-17 22:22:44 -07:00
Nathan Binkert
87d03d00cd inet: initialization fixes. 
Make sure variables are properly initialized and also make sure that
truth testing works properly.
 2008-06-17 22:14:12 -07:00
Nathan Binkert
8042b8f4c7 PacketFifo: Get slack out of the EthPacketData structure. This allows 
a packet to exist in multiple FIFOs if desired.
 2008-06-17 21:34:27 -07:00
Nathan Binkert
163465ac08 ThreadState: Ensure that kernelStats is properly initialized 2008-06-17 21:11:20 -07:00
Nathan Binkert
9dc4e2952c rename MipsConsole to MipsBackdoor 
--HG--
rename : src/dev/mips/MipsConsole.py => src/dev/mips/MipsBackdoor.py
rename : src/dev/mips/console.cc => src/dev/mips/backdoor.cc
rename : src/dev/mips/console.hh => src/dev/mips/backdoor.hh
 2008-06-17 20:39:51 -07:00
Nathan Binkert
934523c3a0 rename AlphaConsole to AlphaBackdoor 
--HG--
rename : src/dev/alpha/AlphaConsole.py => src/dev/alpha/AlphaBackdoor.py
rename : src/dev/alpha/console.cc => src/dev/alpha/backdoor.cc
rename : src/dev/alpha/console.hh => src/dev/alpha/backdoor.hh
 2008-06-17 20:36:39 -07:00
Nathan Binkert
6ff4539901 Change the default output filename for the terminal so it's more obvious. 
--HG--
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal
 2008-06-17 20:30:37 -07:00
Nathan Binkert
00df9016fe Rename SimConsole to Terminal since it makes more sense 
--HG--
rename : src/dev/SimConsole.py => src/dev/Terminal.py
rename : src/dev/simconsole.cc => src/dev/terminal.cc
rename : src/dev/simconsole.hh => src/dev/terminal.hh
 2008-06-17 20:29:06 -07:00
Nathan Binkert
fa8f91fdc0 physmem: Add a null option to physical memory so it doesn't store data. 2008-06-15 21:39:29 -07:00
Nathan Binkert
e3c267a3db port: Clean up default port setup and port switchover code. 2008-06-15 21:34:32 -07:00
Nathan Binkert
b429b1759d params: Prevent people from setting attributes on vector params. 2008-06-15 21:26:33 -07:00
Nathan Binkert
6dedc645f7 add compile flags to m5 2008-06-15 20:56:35 -07:00
Nathan Binkert
b2036bfda8 Command line option to print out List of SimObjects and their parameters 2008-06-14 21:51:08 -07:00
Nathan Binkert
bbeb8082a5 main: add .m5/options.py processing. This file is processed before 
arguments are parsed so that they can change the default options for
various config parameters.
 2008-06-14 21:16:00 -07:00
Nathan Binkert
fc48d1dcf5 Add .m5 configuration directory 2008-06-14 21:15:59 -07:00
Nathan Binkert
779c31077c python: Separate the options parsing stuff. Remove options parsing stuff from 
main.py so things are a bit more obvious.
 2008-06-14 21:15:58 -07:00
Nathan Binkert
4afdc40d70 params: Fix the memory bandwidth parameter 2008-06-14 20:42:45 -07:00
Nathan Binkert
3d2e7797cc params: Fix floating point parameters 2008-06-14 20:39:31 -07:00
Nathan Binkert
f82d4e2364 python: Move various utility classes into a new m5.util package so 
they're all in the same place.  This also involves having just one
jobfile.py and moving it into the utils directory to avoid
duplication.  Lots of improvements to the utility as well.

--HG--
rename : src/python/m5/attrdict.py => src/python/m5/util/attrdict.py
rename : util/pbs/jobfile.py => src/python/m5/util/jobfile.py
rename : src/python/m5/util.py => src/python/m5/util/misc.py
rename : src/python/m5/multidict.py => src/python/m5/util/multidict.py
rename : util/stats/orderdict.py => src/python/m5/util/orderdict.py
 2008-06-14 20:19:49 -07:00
Nathan Binkert
fe325c7f43 MemReq: Add option to reset the time on a request. 2008-06-14 19:39:01 -07:00
Nathan Binkert
ce43e46576 Fix various SWIG warnings 2008-06-14 12:57:21 -07:00
Nathan Binkert
7a58b5a38a Add missing dependencies on .i files 2008-06-14 12:10:50 -07:00
Nathan Binkert
2d037682ff scons: proper fix for hg version stuff 2008-06-14 10:30:18 -07:00
Nathan Binkert
fe4fd9f414 scons: fix program_info.cc generation 2008-06-13 17:34:22 -07:00
Steve Reinhardt
dace77dc4a Automated merge with ssh://m5sim.org//repo/m5 2008-06-13 01:59:10 -04:00
Steve Reinhardt
caccbd1edc Get rid of bogus bus assertion. 
It runs out that if a MemObject turns around and does a send in its
receive callback, and there are other sends already scheduled, then
it could observe a state where it's not at the head of the list but
the bus's sendEvent is not scheduled (because we're still in the
middle of processing the prior sendEvent).
 2008-06-13 01:33:49 -04:00
Steve Reinhardt
024ec4c5c3 Get rid of bogus cache assertion. 
I was asserting that the only reason you would defer targets is if
a write came in while you had an outstanding read miss, but there's
another case where you could get a read access after you've snooped
an invalidation and buffered it because it applies to a prior
outstanding miss.
 2008-06-13 01:29:20 -04:00
Ali Saidi
907b28cc62 HG: Add compiled hg revision and date to the standard M5 output. 2008-06-13 01:09:04 -04:00
Gabe Black
2b4874449c Alpha: Get rid of an old include of a non-existant file. 2008-06-12 01:54:21 -04:00
Gabe Black
7be8e671f1 Params: Allow nested namespaces in cxx_namespace 2008-06-12 01:00:29 -04:00
Gabe Black
5b5875341c X86: Make the cpuid processor identifier return a real string. 2008-06-12 01:00:19 -04:00
Gabe Black
c625cf0ae1 X86: Make the code compile as 32 bit. 2008-06-12 01:00:05 -04:00
Gabe Black
23c04b8c66 Params: Remove an unnecessary include. 2008-06-12 00:59:58 -04:00
Gabe Black
bceaa257a3 X86: Make the e820 table manually or automatically configurable from python. 2008-06-12 00:58:36 -04:00
Gabe Black
4f4ff17578 X86: Make the disassembly for halt conform with the other microops. 2008-06-12 00:58:27 -04:00
Gabe Black
31d40ad7c2 X86: Implement and hook up STI and CLI instructions. 2008-06-12 00:58:19 -04:00
Gabe Black
da20c0ec54 X86: Make sure there's something to catch when the kernel messes with ports "behind" the pci config magic ports. 2008-06-12 00:58:13 -04:00
Gabe Black
1f5b992b58 X86: Make the platform object initialize channel 0 of the PIT. 2008-06-12 00:56:54 -04:00
Gabe Black
16e26fbf03 X86: Hook the speaker device to the pit device. 2008-06-12 00:56:17 -04:00
Gabe Black
da7f512067 Timer: Fill out the periodic modes a little. 2008-06-12 00:56:07 -04:00
Gabe Black
4f9a0402f6 Dev: Seperate the 8254 timer from tsunami and use it in that and the PC. 2008-06-12 00:54:48 -04:00
Gabe Black
0368ccdeda BitUnion: Take out namespace declaration so bitunions can be declared inside classes. 2008-06-12 00:54:32 -04:00
Gabe Black
81936ae2ed X86: Add an event for the apic timer timeout. It doesn't get used yet. 2008-06-12 00:54:19 -04:00
Gabe Black
6b8d0363ee X86: Rename the divide count register to divide configuration. 2008-06-12 00:54:12 -04:00
Gabe Black
b10742ee2b X86: Make the apic isr and irr work. 2008-06-12 00:54:05 -04:00
Gabe Black
69000baef3 X86: Make the apic task priority register work. 2008-06-12 00:54:01 -04:00
Gabe Black
e9c481ea4a X86: Make the logical destination and destination format work. 2008-06-12 00:53:50 -04:00
Gabe Black
ed23a4970b X86: Make the apic ID register work. 2008-06-12 00:53:43 -04:00
Gabe Black
8a6723e038 X86: Make the apic version register work. 2008-06-12 00:53:37 -04:00
Gabe Black
8d2416c6e9 X86: Implement a partial, sort of correct version of the protected mode variant of iret. 2008-06-12 00:53:01 -04:00
Gabe Black
66f54a6037 X86: Change how segment loading is performed. 2008-06-12 00:52:12 -04:00
Gabe Black
129831c116 X86: Make pushes and pops use the stack size instead of the data size. 2008-06-12 00:51:57 -04:00
Gabe Black
b05299253f X86: In non 64bit mode, throw a fault when a NULL segment is accessed. 2008-06-12 00:51:50 -04:00
Gabe Black
a8384311d5 X86: Take advantage of the new meta register. 2008-06-12 00:51:14 -04:00
Gabe Black
d4e7c7edd3 X86: Keep handy values like the operating mode in one register. 2008-06-12 00:50:25 -04:00
Gabe Black
fa7c81c6df X86: Change what the microop chks does. 
Instead of computing the segment descriptor address, this now checks if a
selector value/descriptor are legal for a particular purpose.
 2008-06-12 00:50:10 -04:00
Gabe Black
6bd9cf3594 X86: Add a microop to read a segments attribute register. 2008-06-12 00:50:05 -04:00
Gabe Black
e0c20386ac X86: Add microops and supporting code to manipulate the whole rflags register. 2008-06-12 00:49:50 -04:00
Gabe Black
2bb8933f78 X86: Add microops which panic, fatal, warn, and warn_once. 2008-06-12 00:49:25 -04:00
Gabe Black
bbc1f394ff X86: Truncate descriptors to 16 bits. 2008-06-12 00:49:16 -04:00
Gabe Black
6106b05b6e X86: Redo BSF. 2008-06-12 00:48:58 -04:00
Gabe Black
dfc2d44ea3 X86: Flesh out 3dnow instruction decoding a bit and grab the byte immediate. 2008-06-12 00:48:46 -04:00
Gabe Black
de6eeaaa27 X86: Make string instructions work when rcx=0. 2008-06-12 00:48:15 -04:00
Gabe Black
8688ef3fe5 X86: Have all 8 machine check registers since the kernel assumes they're there. 2008-06-12 00:48:02 -04:00
Gabe Black
a8e3001df8 X86: Bypass unaligned access support for register addressed MSRs. 2008-06-12 00:47:25 -04:00
Gabe Black
b3e55339f9 X86: Remove enforcement of APIC register access alignment. Panic if more than one register is accessed at a time. 2008-06-12 00:46:22 -04:00
Gabe Black
8e2991b529 X86: Fix the implementation of BSF. 2008-06-12 00:46:04 -04:00
Gabe Black
16e189fad2 X86: Bit scan forward/reverse were accidentally transposed. 2008-06-12 00:45:52 -04:00
Gabe Black
254cc07650 X86: Fix a byte register indexing issue in the sign extending move from memory microcode. 2008-06-12 00:45:22 -04:00