Nathan Binkert
25aac791de
SmartDict: Make SmartDict an attrdict
2010-02-28 19:28:09 -08:00
Nathan Binkert
ebdd004eb2
uart: use integer versions of time instead of messing around with floats
2010-02-28 19:28:09 -08:00
Nathan Binkert
f0b4259e98
cpu_models: get rid of cpu_models.py and move the stuff into SCons
2010-02-26 18:14:48 -08:00
Nathan Binkert
ac106767c8
isa_parser: Make SCons import the isa_parser
...
this is instead of forking a new interpreter
2010-02-26 18:14:48 -08:00
Nathan Binkert
629e8df196
isa_parser: move the operand map stuff into the ISAParser class.
2010-02-26 18:14:48 -08:00
Nathan Binkert
4db57edade
isa_parser: move more support functions into the ISAParser class
2010-02-26 18:14:48 -08:00
Nathan Binkert
5ad139375e
isa_parser: move more stuff into the ISAParser class
2010-02-26 18:14:48 -08:00
Nathan Binkert
4ef6e129d6
isa_parser: move the formatMap and exportContext into the ISAParser class
2010-02-26 18:14:48 -08:00
Nathan Binkert
4e105f6fe1
isa_parser: Make stack objects class members instead of globals
2010-02-26 18:14:48 -08:00
Nathan Binkert
b4178b1ae7
isa_parser: add a debug variable that changes how errors are reported.
...
This allows us to get tracebacks in certain cases where they're more
useful than our error message.
2010-02-26 18:14:48 -08:00
Nathan Binkert
40a05f04fb
isa_parser: Use an exception to flag error
...
This allows the error to propagate more easily
2010-02-26 18:14:48 -08:00
Nathan Binkert
f82a92925c
isa_parser: Move more stuff into the ISAParser class
2010-02-26 18:14:48 -08:00
Nathan Binkert
f7a627338c
isa_parser: move code around to prepare for putting more stuff in the class
2010-02-26 18:14:48 -08:00
Nathan Binkert
eb4ce01056
isa_parser: simple fixes, formatting and style
2010-02-26 18:14:48 -08:00
Nathan Binkert
a9f6c8edc3
events: Give EventWrapped a default name and description
2010-02-26 18:09:41 -08:00
Lisa Hsu
7f3cd9a9fd
cache stats: account for writebacks and/or device occupancy in the cache.
...
Plus, a minor bugfix that neglects to update blk->contextSrc in certain cases on a cache insert.
2010-02-24 13:46:55 -08:00
Lisa Hsu
1d3228481f
cache: Make caches sharing aware and add occupancy stats.
...
On the config end, if a shared L2 is created for the system, it is
parameterized to have n sharers as defined by option.num_cpus. In addition to
making the cache sharing aware so that discriminating tag policies can make use
of context_ids to make decisions, I added an occupancy AverageStat and an occ %
stat to each cache so that you could know which contexts are occupying how much
cache on average, both in terms of blocks and percentage. Note that since
devices have context_id -1, having an array of occ stats that correspond to
each context_id will break here, so in FS mode I add an extra bucket for device
blocks. This bucket is explicitly not added in SE mode in order to not only
avoid ugliness in the stats.txt file, but to avoid broken stats (some formulas
break when a bucket is 0).
2010-02-23 09:34:22 -08:00
Lisa Hsu
be4cf50c5a
stats: this makes some fixes to AverageStat and AverageVector.
...
Also, make Formulas work on AverageVector. First, Stat::Average (and thus
Stats::AverageVector) was broken when coming out of a checkpoint and on resets,
this fixes that. Formulas also didn't work with AverageVector, but added
support for that.
2010-02-23 09:33:18 -08:00
Lisa Hsu
2ad386f104
cache: pull CacheSet out of LRU so that other tags can use associative sets.
2010-02-23 09:33:09 -08:00
Timothy M. Jones
a5feaa6a69
BaseDynInst: Preserve the faults returned from read and write.
...
When implementing timing address translations instead of atomic, I
forgot to preserve the faults that are returned from the read and
write calls. This patch reinstates them.
2010-02-20 20:11:58 +00:00
Timothy M. Jones
29e8bcead5
O3PCU: Split loads and stores that cross cache line boundaries.
...
When each load or store is sent to the LSQ, we check whether it will cross a
cache line boundary and, if so, split it in two. This creates two TLB
translations and two memory requests. Care has to be taken if the first
packet of a split load is sent but the second blocks the cache. Similarly,
for a store, if the first packet cannot be sent, we must store the second
one somewhere to retry later.
This modifies the LSQSenderState class to record both packets in a split
load or store.
Finally, a new const variable, HasUnalignedMemAcc, is added to each ISA
to indicate whether unaligned memory accesses are allowed. This is used
throughout the changed code so that compiler can optimise away code dealing
with split requests for ISAs that don't need them.
2010-02-12 19:53:20 +00:00
Timothy M. Jones
7fe9f92cfc
BaseDynInst: Make the TLB translation timing instead of atomic.
...
This initiates a timing translation and passes the read or write on to the
processor before waiting for it to finish. Once the translation is finished,
the instruction's state is updated via the 'finish' function. A new
DataTranslation class is created to handle this.
The idea is taken from the implementation of timing translations in
TimingSimpleCPU by Gabe Black. This patch also separates out the timing
translations from this CPU and uses the new DataTranslation class.
2010-02-12 19:53:19 +00:00
Timothy M. Jones
dd60902152
Power ISA: Add an alignment fault to Power ISA and check alignment in TLB.
2010-02-12 19:53:19 +00:00
Brad Beckmann
64999b4343
ruby: fixed data block assignment fix
...
Fixed data block assignment to not delete if not internally allocated.
2010-02-10 16:40:54 -08:00
Brad Beckmann
714865e4a4
ruby: Initialize sender in MI_example-dir
2010-02-10 16:40:54 -08:00
Brad Beckmann
a407675106
ruby: Fixed slicc to initialize the m_is_blocking flag
2010-02-10 16:40:54 -08:00
Brad Beckmann
1d4c3ecdc3
ruby: Added FS support to the simple mesh topology
...
Added full-system support to the simple mesh toplogy by allowing dma contrllers
to be attached to router zero in the network.
2010-02-01 14:27:16 -08:00
Brad Beckmann
db2ecbb6b6
ruby: Set default protocol back to MI_example
2010-02-01 11:07:38 -08:00
Korey Sewell
c7f6e2661c
inorder: double delete inst bug
...
Make sure that instructions are dereferenced/deleted twice by marking they are
on the remove list
2010-01-31 18:30:59 -05:00
Korey Sewell
9357e353fc
inorder: inst count mgmt
2010-01-31 18:30:48 -05:00
Korey Sewell
be6724f7e7
inorder: implement split stores
2010-01-31 18:30:43 -05:00
Korey Sewell
6939482c49
inorder: implement split loads
2010-01-31 18:30:35 -05:00
Korey Sewell
ea8909925f
inorder: add activity stats
2010-01-31 18:30:24 -05:00
Korey Sewell
f3bc2df663
inorder: object cleanup in destructors
2010-01-31 18:30:08 -05:00
Korey Sewell
1a89e8f4cb
inorder: user per-thread dummy insts/reqs
2010-01-31 18:29:59 -05:00
Korey Sewell
002f1b8b7e
inorder: add execution unit stats
2010-01-31 18:29:49 -05:00
Korey Sewell
82c5a754e6
inorder: recvRetry bug fix
...
- on certain retry requests you can get an assertion failure
- fix by allowing the request to literally "Retry" itself
if it wasnt successful before, and then block any requests
through cache port while waiting for the cache to be
made available for access
2010-01-31 18:29:18 -05:00
Korey Sewell
349d86c0e4
inorder-stats: add prereq to basic stat
...
only show requests processed when the resource is actually in use
2010-01-31 18:29:06 -05:00
Korey Sewell
0b29c2d057
inorder: ctxt switch stats
...
- m5 line enforcement on use_def.cc,hh
2010-01-31 18:28:59 -05:00
Korey Sewell
ffa9ecb1fa
inorder: pipeline stage stats
...
add idle/run/utilization stats for each pipeline stage
2010-01-31 18:28:51 -05:00
Korey Sewell
4d749472e3
inorder: enforce stage bandwidth
...
each stage keeps track of insts_processed on a per_thread basis but we should
be keeping that on a total basis inorder to enforce stage width limits
2010-01-31 18:28:31 -05:00
Korey Sewell
b4e0ef7837
inorder: set thread status'
...
set Active/Suspended/Halted status for threads. useful for system when determining
if/when to exit simulation
2010-01-31 18:28:12 -05:00
Korey Sewell
5e0b8337ed
inorder: add/remove halt/deallocate context respectively
...
Halt is called from the exit() system call while
deallocate is unused. So to clear up things, just
use halt and remove deallocate.
2010-01-31 18:28:05 -05:00
Korey Sewell
069b38c0d5
inorder: track last branch committed
...
when threads are switching in/out the CPU, we need to keep
track of special cases like branches. Add appropriate
variables in ThreadState t track this and then use
these variables when updating pc after context switch
2010-01-31 18:27:58 -05:00
Korey Sewell
aacc5cb205
inorder: add updatePC event to resPool
...
this will be used for when a thread comes back from a cache miss, it needs to update the PCs
because the inst might of been a branch or delayslot in which the next PC isnt always
a straight addition
2010-01-31 18:27:49 -05:00
Korey Sewell
90d3b45a56
inorder: ready thread wakeup
...
allow a thread to wakeup and be activated after
it has been in suspended state and another
thread is switched out. Need to give
pipeline stages a "activateThread" function
so that can get to their suspended instruction
when the time is right.
2010-01-31 18:27:38 -05:00
Korey Sewell
3eb04b4ad7
inorder: add threadmodel flag
...
this prints out messages relative to what
threading model is being used (smt, switch-on-miss, single, etc.)
2010-01-31 18:27:25 -05:00
Korey Sewell
611a8642c2
inorder: mem. mgmt. update
...
update address List and address Map to take
into account multiple threads
2010-01-31 18:27:12 -05:00
Korey Sewell
4dbc2f1718
inorder: suspend in respool
...
give resources their own specific
activity to do for a "suspend" event
instead of defaulting to deactivating the thread for a
suspend thread event. This really matters
for the fetch sequence unit which wants to remove the
thread from fetching while other units want to
ignore a thread suspension. If you deactivate a thread
in a resource then you may lose some of the allotted
bandwidth that the thread is taking up...
2010-01-31 18:27:02 -05:00
Korey Sewell
4ea296e296
inorder: fetch thread bug
...
dont check total # of threads but instead all
active threads
2010-01-31 18:26:54 -05:00
Korey Sewell
96b493d315
inorder: ready/suspend status fns
...
update/add in the use of isThreadReady & isThreadSuspended
functions.Check in activateThread what list a thread is
on so it can be managed accordingly.
2010-01-31 18:26:47 -05:00
Korey Sewell
d9eaa2fe21
inorder-cleanup: remove unused thread functions
2010-01-31 18:26:40 -05:00
Korey Sewell
e1fcc64980
inorder: activate thread on cache miss
...
-Support ability to activate next ready thread after a cache miss
through the activateNextReadyContext/Thread() functions
-To support this a "readyList" of thread ids is added
-After a cache miss, thread will suspend and then call
activitynextreadythread
2010-01-31 18:26:32 -05:00
Korey Sewell
4a945aab19
inorder: add event priority offset
...
allow for events to schedule themselves later if desired. this is important
because of cases like where you need to activate a thread only after the previous
thread has been deactivated. The ordering there has to be enforced
2010-01-31 18:26:26 -05:00
Korey Sewell
eac5eac67a
inorder: squash on memory stall
...
add code to recognize memory stalls in resources and the pipeline as well
as squash a thread if there is a stall and we are in the switch on cache miss
model
2010-01-31 18:26:13 -05:00
Korey Sewell
d8e0935af2
inorder: add insts to cpu event
...
some events are going to need instruction data when they process, so just
include the instruction in the event construction
2010-01-31 18:26:03 -05:00
Korey Sewell
e8312ab6f7
inorder: switch out buffer
...
add buffer for instructions to switch out to in a pipeline stage
can't squash the instruction and remove the pipeline so we kind of need
to 'suspend' an instruction at the stage while the memory stall resolves
for the switch on cache miss model
2010-01-31 18:25:48 -05:00
Korey Sewell
a892af7b26
inorder: dont allow early loads
...
- loads were happening on same cycle as the address was generated which is slightly
unrealistic. Instead, force address generation to be on separate cycle from load
initiation
- also, mark the stages in a more traditional way (F-D-X-M-W)
2010-01-31 18:25:27 -05:00
Korey Sewell
0e96798fe0
configs/inorder: add options for switch-on-miss to inorder cpu
2010-01-31 18:25:13 -05:00
Korey Sewell
7b3b362ba5
inorder: init internal debug cpu counters
...
- cpuEventNum
- resReqCount
2010-01-31 17:18:15 -05:00
Brad Beckmann
ab2f864af2
m5: Regression Tester Update
...
This patch includes the necessary regression updates to test the new ruby
configuration system. The patch includes support for multiple ruby protocols
and adds the ruby random tester. The patch removes atomic mode test for
ruby since ruby does not support atomic mode acceses. These tests can be
added back in when ruby supports atomic mode for real.
--HG--
rename : tests/quick/50.memtest/test.py => tests/quick/60.rubytest/test.py
2010-01-29 20:29:40 -08:00
Brad Beckmann
ceae8383ff
ruby: Replaced gems_common debug statements
...
Replaced Ruby debug statements with M5 statements.
2010-01-29 20:29:34 -08:00
Brad Beckmann
143d8ea698
ruby: removed last level cache support
...
Removed the last level cache support and MOESI_hammer's dependency on it.
Replaces the LLC support with the more generic MachineType count.
2010-01-29 20:29:34 -08:00
Brad Beckmann
90aab239a1
ruby: Added a Scons option to prevent HTML file creation
2010-01-29 20:29:33 -08:00
Brad Beckmann
1feae85017
ruby: Removed static members in RubyPort including hitcallback
...
Removed static members in RubyPort and removed the ruby request unique id.
2010-01-29 20:29:33 -08:00
Brad Beckmann
a579d3e43c
ruby: Removed the old config interface
...
Removed the old config interface from RubySystem and libruby.
2010-01-29 20:29:33 -08:00
Brad Beckmann
e4218dd08f
ruby: Re-enabled orion power models
...
Removed the dummy power function implementations so that Orion can implement
them correctly. Since Orion lacks modular design, this patch simply enables
scons to compile it. There are no python configuration changes in this patch.
2010-01-29 20:29:33 -08:00
Brad Beckmann
8dd45674ae
ruby: Converted Garnet to M5 configuration
2010-01-29 20:29:32 -08:00
Steve Reinhardt
b544462505
Garnet: reorganize directory tree.
...
Rename the ruby/network/garnet-foo directories to garnet/foo.
Move the common NetworkHeader.hh file from garnet-fixed-pipeline
up to the common garnet directory.
Fix up include paths.
--HG--
rename : src/mem/ruby/network/garnet-fixed-pipeline/NetworkHeader.hh => src/mem/ruby/network/garnet/NetworkHeader.hh
rename : src/mem/ruby/network/garnet-fixed-pipeline/CreditLink_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/CreditLink_d.hh
rename : src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
rename : src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh
rename : src/mem/ruby/network/garnet-fixed-pipeline/InputUnit_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.cc
rename : src/mem/ruby/network/garnet-fixed-pipeline/InputUnit_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh
rename : src/mem/ruby/network/garnet-fixed-pipeline/NetworkInterface_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
rename : src/mem/ruby/network/garnet-fixed-pipeline/NetworkInterface_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.hh
rename : src/mem/ruby/network/garnet-fixed-pipeline/NetworkLink_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc
rename : src/mem/ruby/network/garnet-fixed-pipeline/NetworkLink_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh
rename : src/mem/ruby/network/garnet-fixed-pipeline/OutVcState_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/OutVcState_d.cc
rename : src/mem/ruby/network/garnet-fixed-pipeline/OutVcState_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/OutVcState_d.hh
rename : src/mem/ruby/network/garnet-fixed-pipeline/OutputUnit_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.cc
rename : src/mem/ruby/network/garnet-fixed-pipeline/OutputUnit_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh
rename : src/mem/ruby/network/garnet-fixed-pipeline/Router_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc
rename : src/mem/ruby/network/garnet-fixed-pipeline/Router_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh
rename : src/mem/ruby/network/garnet-fixed-pipeline/RoutingUnit_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/RoutingUnit_d.cc
rename : src/mem/ruby/network/garnet-fixed-pipeline/RoutingUnit_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/RoutingUnit_d.hh
rename : src/mem/ruby/network/garnet-fixed-pipeline/SConscript => src/mem/ruby/network/garnet/fixed-pipeline/SConscript
rename : src/mem/ruby/network/garnet-fixed-pipeline/SWallocator_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc
rename : src/mem/ruby/network/garnet-fixed-pipeline/SWallocator_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.hh
rename : src/mem/ruby/network/garnet-fixed-pipeline/Switch_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc
rename : src/mem/ruby/network/garnet-fixed-pipeline/Switch_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.hh
rename : src/mem/ruby/network/garnet-fixed-pipeline/VCallocator_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/VCallocator_d.cc
rename : src/mem/ruby/network/garnet-fixed-pipeline/VCallocator_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/VCallocator_d.hh
rename : src/mem/ruby/network/garnet-fixed-pipeline/VirtualChannel_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.cc
rename : src/mem/ruby/network/garnet-fixed-pipeline/VirtualChannel_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.hh
rename : src/mem/ruby/network/garnet-fixed-pipeline/flitBuffer_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.cc
rename : src/mem/ruby/network/garnet-fixed-pipeline/flitBuffer_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.hh
rename : src/mem/ruby/network/garnet-fixed-pipeline/flit_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/flit_d.cc
rename : src/mem/ruby/network/garnet-fixed-pipeline/flit_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/flit_d.hh
rename : src/mem/ruby/network/garnet-flexible-pipeline/FlexibleConsumer.hh => src/mem/ruby/network/garnet/flexible-pipeline/FlexibleConsumer.hh
rename : src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.cc => src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc
rename : src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.hh => src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh
rename : src/mem/ruby/network/garnet-flexible-pipeline/InVcState.cc => src/mem/ruby/network/garnet/flexible-pipeline/InVcState.cc
rename : src/mem/ruby/network/garnet-flexible-pipeline/InVcState.hh => src/mem/ruby/network/garnet/flexible-pipeline/InVcState.hh
rename : src/mem/ruby/network/garnet-flexible-pipeline/NetworkConfig.hh => src/mem/ruby/network/garnet/flexible-pipeline/NetworkConfig.hh
rename : src/mem/ruby/network/garnet-flexible-pipeline/NetworkInterface.cc => src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
rename : src/mem/ruby/network/garnet-flexible-pipeline/NetworkInterface.hh => src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.hh
rename : src/mem/ruby/network/garnet-flexible-pipeline/NetworkLink.cc => src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.cc
rename : src/mem/ruby/network/garnet-flexible-pipeline/NetworkLink.hh => src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.hh
rename : src/mem/ruby/network/garnet-flexible-pipeline/OutVcState.cc => src/mem/ruby/network/garnet/flexible-pipeline/OutVcState.cc
rename : src/mem/ruby/network/garnet-flexible-pipeline/OutVcState.hh => src/mem/ruby/network/garnet/flexible-pipeline/OutVcState.hh
rename : src/mem/ruby/network/garnet-flexible-pipeline/Router.cc => src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
rename : src/mem/ruby/network/garnet-flexible-pipeline/Router.hh => src/mem/ruby/network/garnet/flexible-pipeline/Router.hh
rename : src/mem/ruby/network/garnet-flexible-pipeline/SConscript => src/mem/ruby/network/garnet/flexible-pipeline/SConscript
rename : src/mem/ruby/network/garnet-flexible-pipeline/VCarbiter.cc => src/mem/ruby/network/garnet/flexible-pipeline/VCarbiter.cc
rename : src/mem/ruby/network/garnet-flexible-pipeline/VCarbiter.hh => src/mem/ruby/network/garnet/flexible-pipeline/VCarbiter.hh
rename : src/mem/ruby/network/garnet-flexible-pipeline/flit.cc => src/mem/ruby/network/garnet/flexible-pipeline/flit.cc
rename : src/mem/ruby/network/garnet-flexible-pipeline/flit.hh => src/mem/ruby/network/garnet/flexible-pipeline/flit.hh
rename : src/mem/ruby/network/garnet-flexible-pipeline/flitBuffer.cc => src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.cc
rename : src/mem/ruby/network/garnet-flexible-pipeline/flitBuffer.hh => src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.hh
rename : src/mem/ruby/network/garnet-flexible-pipeline/netconfig.defaults => src/mem/ruby/network/garnet/flexible-pipeline/netconfig.defaults
2010-01-29 20:29:30 -08:00
Brad Beckmann
6c867f8263
ruby: Added a mesh topology
2010-01-29 20:29:27 -08:00
Brad Beckmann
faa76fc248
ruby: MESI_CMP_directory updated to the new config system
2010-01-29 20:29:27 -08:00
Brad Beckmann
3e286d825d
ruby: Sorted the file includes to maintain consistency
2010-01-29 20:29:26 -08:00
Brad Beckmann
5fb1f5c72b
ruby: Renamed the MESI directory sm file
...
Renamed the MESI directory file to be consistent with all other protocols.
--HG--
rename : src/mem/protocol/MESI_CMP_directory-mem.sm => src/mem/protocol/MESI_CMP_directory-dir.sm
2010-01-29 20:29:26 -08:00
Brad Beckmann
79f354466e
ruby: Removed the GPL header in MESI_CMP_directory-msg
...
I'm not sure how this got past our initial ruby code import, but this obviously
needed to be removed.
2010-01-29 20:29:26 -08:00
Brad Beckmann
31fcf09a68
ruby: MOESI_CMP_directory updated to the new config system
2010-01-29 20:29:26 -08:00
Brad Beckmann
1c4405ad5e
ruby: Added atomic support to MOESI_CMP_token
2010-01-29 20:29:25 -08:00
Brad Beckmann
042d5b87a4
ruby: fixed memory fetch bug for persistent requests
2010-01-29 20:29:25 -08:00
Brad Beckmann
d77a9df3c1
ruby: MOESI_CMP_token updates to use the new config system
2010-01-29 20:29:25 -08:00
Brad Beckmann
d42152742b
ruby: Allows boolean and string defaults for StateMachine parameters
2010-01-29 20:29:24 -08:00
Brad Beckmann
b3d195153e
ruby: MI_example updates to use the new config system
2010-01-29 20:29:24 -08:00
Brad Beckmann
134cc3d48d
ruby: convert to M5 MemorySize
...
Converted both ruby caches and directory memory to use the M5 MemorySize python
type.
2010-01-29 20:29:23 -08:00
Brad Beckmann
3a835c7cbb
ruby: Added Cache and MemCntrl profiler calls
2010-01-29 20:29:23 -08:00
Brad Beckmann
47502163b7
ruby: added data print to ruby request
2010-01-29 20:29:23 -08:00
Brad Beckmann
66279fac3f
ruby: Added atomic support to MOESI_hammer
2010-01-29 20:29:23 -08:00
Brad Beckmann
45230a4f6b
ruby: added the GEMS ruby tester
2010-01-29 20:29:23 -08:00
Brad Beckmann
4eb3bfc31b
ruby: fixed MOESI_hammer data writebacks to the directory
2010-01-29 20:29:22 -08:00
Brad Beckmann
f88faa6c11
ruby: cleaned up ruby profilers
...
Cleaned up the ruby profilers by moving the memory controller profiling code
out of the main profiler object and into a separate object similar to the
current CacheProfiler. Both the CacheProfiler and MemCntrlProfiler are
specific to a particular Ruby object, CacheMemory and MemoryControl
respectively. Therefore, these profilers should not be SimObjects and
created by the python configuration system, but instead private objects. This
simplifies the creation of these profilers.
2010-01-29 20:29:22 -08:00
Brad Beckmann
cfe41d0a1b
ruby: Removed RubySystem::getNumberOfSequencers
...
removed the static function RubySystem::getNumberOfSequencers and replaced
it with a python config variable
2010-01-29 20:29:21 -08:00
Brad Beckmann
1907e39fd2
ruby: added ruby stats print
...
Moved the previous rubymem stats print feature to ruby System so that ruby
stats are printed on simulation exit.
2010-01-29 20:29:21 -08:00
Brad Beckmann
020716cab3
ruby: fixed Set.cc bug to allow zero sized sets
...
This is necessary for example when no dma sequencers are necessary in the
simulated system.
2010-01-29 20:29:21 -08:00
Brad Beckmann
ce2d13195b
ruby: FS support using the new configuration system
2010-01-29 20:29:21 -08:00
Brad Beckmann
dc758641c9
ruby: reorganized ruby python configuration
...
Reorganized ruby python configuration so that protocol and ruby memory system
configuration code can be shared by multiple front-end configuration files
(i.e. memory tester, full system, and hopefully the regression tester). This
code works for memory tester, but have not tested fs mode.
2010-01-29 20:29:20 -08:00
Brad Beckmann
e735ca7c77
ruby: Removed out_link_vec from Consumer
...
Removed the out_line_vec data structure from the Consumer. I'm not sure
what this did before, but currently it has no usefulness.
2010-01-29 20:29:20 -08:00
Brad Beckmann
0f6535dba1
ruby: Convered ruby tracing support usage of sequencer
...
Modified ruby's tracing support to no longer rely on the RubySystem map
to convert a sequencer string name to a sequencer pointer. As a
temporary solution, the code uses the sim_object find function.
Eventually, we should develop a better fix.
2010-01-29 20:29:20 -08:00
Brad Beckmann
2c9ca672df
ruby: Memory Controller Profiler with new config system
...
This patch includes a rather substantial change to the memory controller
profiler in order to work with the new configuration system. Most
noteably, the mem_cntrl_profiler no longer uses a string map, but instead
a vector. Eventually this support should be removed from the main
profiler and go into a separate object. Each memory controller should have
a pointer to that new mem_cntrl profile object.
2010-01-29 20:29:20 -08:00
Brad Beckmann
2a0555470c
ruby: Converted MOESI_hammer dma cntrl to new config system
2010-01-29 20:29:19 -08:00
Brad Beckmann
3b290a35ac
ruby: Added the cache profiler to the new config system
2010-01-29 20:29:19 -08:00
Brad Beckmann
4e5f4b5074
ruby: Converted the sequencer deadlock event to m5 eventq
2010-01-29 20:29:19 -08:00
Brad Beckmann
e15abd17f9
ruby: Wrapped ruby events into m5 events
...
Wrapped ruby events using the m5 event object. Removed the prio_heap
from ruby's event queue and instead schedule ruby events on the m5 event
queue.
2010-01-29 20:29:19 -08:00
Brad Beckmann
63a60cc81e
ruby: Removed the tech_nm variable from RubySystem
2010-01-29 20:29:19 -08:00
Brad Beckmann
12daaed84a
ruby: Added clock to ruby system
...
As a first step to migrate ruby to the M5 eventqueue, added a clock
variable to the ruby system.
2010-01-29 20:29:19 -08:00
Brad Beckmann
ed81489954
ruby: Ruby changes required to use the python config system
...
This patch includes the necessary changes to connect ruby objects using
the python configuration system. Mainly it consists of removing
unnecessary ruby object pointers and connecting the necessary object
pointers using the generated param objects. This patch includes the
slicc changes necessary to connect generated ruby objects together using
the python configuraiton system.
2010-01-29 20:29:19 -08:00
Brad Beckmann
42bebab779
ruby: connects sm queues to the network
2010-01-29 20:29:18 -08:00
Steve Reinhardt
a8ea70dac6
ruby: Calculate system total memory capacity in Python
...
rather than in RubySystem object.
2010-01-29 20:29:18 -08:00
Steve Reinhardt
0b54f1db8e
ruby: Add support for generating topologies in Python.
2010-01-29 20:29:17 -08:00
Steve Reinhardt
184cf4db5b
scons: ignore blank lines in .slicc files
2010-01-29 20:29:17 -08:00
Steve Reinhardt
c6f1d959be
ruby: Make SLICC-generated objects SimObjects.
...
Also add SLICC support for state-machine parameter defaults
(passed through to Python as SimObject Param defaults).
2010-01-29 20:29:17 -08:00
Steve Reinhardt
98c94cfe3c
ruby: Convert most Ruby objects to M5 SimObjects.
...
The necessary companion conversion of Ruby objects generated by SLICC
are converted to M5 SimObjects in the following patch, so this patch
alone does not compile.
Conversion of Garnet network models is also handled in a separate
patch; that code is temporarily disabled from compiling to allow
testing of interim code.
2010-01-29 20:29:17 -08:00
Steve Reinhardt
b43994ba45
ruby: get rid of obsolete, unused CustomTopology class.
2010-01-29 20:29:14 -08:00
Brad Beckmann
7f03dce012
ruby: fix out_port declaration
2010-01-29 20:29:14 -08:00
Brad Beckmann
43e4f59e4f
ruby: Added message type check to OutPortDeclAST.py
...
Though OutPort's message type is not used to generate code, this fix checks
that the programmer's intent is correct. Eventually, we may want to
remove the message type from the OutPort declaration statement.
2010-01-29 20:29:13 -08:00
Nathan Binkert
5b90934dd2
build: need to include cstdio
2010-01-23 14:02:03 -08:00
Nathan Binkert
8a3fbbd8d9
compile: compile on 32 bit hardware
2009-11-05 17:21:26 -08:00
Nathan Binkert
52ccfde2cd
isa_parser: allow negative integer literals
2009-11-05 17:21:25 -08:00
Derek Hower
589218168c
Automated merge with ssh://hg@m5sim.org/m5
2010-01-22 17:23:21 -06:00
Lisa Hsu
d6da172517
util: do checkpoint aggregation more cleanly, fix last changeset.
...
1) Move alpha-specific code out of page_table.cc:serialize().
2) Begin serializing M5_pid and unserializing it, but adding an function to do optional paramIn so that old checkpoints don't need to be fixed up.
3) Fix up alpha startup code so that the unserialized M5_pid value is properly written to DTB_IPR_ASN.
4) Fix the memory unserialize that I forgot somehow in the last changeset.
5) Add in an agg_se.py to handle aggregated checkpoints. --bench foo-bar plus positional arguments foo bar are the only changes in usage from se.py.
Note this aggregation stuff has only been tested for Alpha and nothing else, though it should take a very minimal amount of work to get it to work with another ISA.
2010-01-19 22:03:44 -08:00
Derek Hower
07ea0891f1
ruby: new atomics implementation
...
This patch changes the way that Ruby handles atomic RMW instructions. This implementation, unlike the prior one, is protocol independent. It works by locking an address from the sequencer immediately after the read portion of an RMW completes. When that address is locked, the coherence controller will only satisfy requests coming from one port (e.g., the mandatory queue) and will ignore all others. After the write portion completed, the line is unlocked. This should also work with multi-line atomics, as long as the blocks are always acquired in the same order.
2010-01-19 17:11:36 -06:00
Derek Hower
279f179bab
merge
2010-01-19 15:48:12 -06:00
Lisa Hsu
4a40ac71f8
util: make a generic checkpoint aggregator that can aggregate different cpts into one multi-programmed cpt. Make minor changes to serialization/unserialization to get it to work properly. Note that checkpoints were made with a comment at the beginning with // - this must be changed to ## to work properly with the python config parser in the aggregator.
2010-01-18 14:30:31 -08:00
Lisa Hsu
8b4e8690b7
cache: make tags->insertBlock() and tags->accessBlock() context aware so that the cache can make context-specific decisions within their various tag policy implementations.
2010-01-12 10:53:02 -08:00
Lisa Hsu
9f63548478
since totalInstructions() is impl'ed by all the cpus, make it an abstract base class.
2010-01-12 10:22:46 -08:00
Lisa Hsu
daebe18e89
faults: i think these fault invocations should be panic and not fatal. it definitely made implementing a trace cpu easier this way.
2010-01-12 10:17:19 -08:00
Matt DeVuyst
18dc80e07b
MIPS: Beef up process initialization.
2009-12-31 15:30:51 -05:00
Gabe Black
ecaa7070e6
MIPS: Implement the SE mode version of rdhwr.
2009-12-31 15:30:51 -05:00
Gabe Black
c70f3c93af
MIPS: Fix decoding of the rdhwr instruction.
2009-12-31 15:30:51 -05:00
Gabe Black
134937b594
MIPS: Implement the set_thread_area system call.
2009-12-31 15:30:50 -05:00
Gabe Black
d3ed32b989
MIPS: Create an artificial control register to hold the thread pointer.
...
In Linux, the set_thread_area system call stores the address of the thread
local storage area into a field of the current thread_info structure. Later,
to access that value, the program uses the rdhwr instruction to read a
"hardware register" with index 29. The 64 bit MIPS manual, volume II, says
that index 29 is reserved for a future ABI extension and should cause a
"Reserved Instruction Exception". In Linux (and potentially other ISAs) that
exception is trapped and emulated to return the value stored by
set_thread_area as if that were actually stored by a physical register.
The tp_value address (as named in the Linux kernel) is ironically stored as a
control register so that it goes with a particular ThreadContext. Syscall
emulation will use that to emulate storing to the OS's thread info structure,
and rdhwr will emulate faulting and returning that value from software by
returning the value itself, as if it was in hardware. In other words, we fake
faking the register in SE mode. In an FS mode implementation it should
work as specified in the manual.
2009-12-31 15:30:50 -05:00
Gabe Black
cc07dcf026
MIPS: Extract CPU pointer from the thread context in scheduleCP0 setMiscReg.
...
The MIPS ISA object expects to be constructed with a CPU pointer it uses to
look at other thread contexts and allow them to be manipulated with control
registers. Unfortunately, that differs from all the other ISA classes and
would complicate their implementation.
This change makes the event constructor use a CPU pointer pulled out of the
thread context passed to setMiscReg instead.
2009-12-31 15:30:50 -05:00
Gabe Black
1261f1d8db
MIPS: Add missing syscall slots.
...
These are all after the existing ones, suggesting they were added after the
original list was created.
2009-12-21 14:59:40 -08:00
Soumyaroop Roy
1bd0f772f1
Alpha: Implement MVI and remaining BWX instructions.
2009-12-20 15:03:23 -06:00
Gabe Black
3e1cda5080
X86: Add a latency that describes how long an interrupt takes to propagate through the IO APIC.
2009-12-19 01:50:06 -08:00
Gabe Black
c7ca1d3c8a
X86: Add a common named flag for signed media operations.
2009-12-19 01:48:31 -08:00
Gabe Black
2554511533
X86: Create a common flag with a name to indicate high multiplies.
2009-12-19 01:48:07 -08:00
Gabe Black
e474079ddc
X86: Create a common flag with a name to indicate scalar media instructions.
2009-12-19 01:47:30 -08:00
Derek Hower
5aa104e072
ruby: cleaned up ruby-lang configuration
2009-12-04 13:12:40 -06:00
Brad Beckmann
5d8a669539
Resurrection of the CMP token protocol to GEM5
2009-11-18 16:34:33 -08:00
Brad Beckmann
dcac2ec24c
ruby: removed the chip pointer from MessageBuffer
...
The Chip object no longer exists and thus is removed from the MessageBuffer
constructor.
2009-11-18 16:34:32 -08:00
Brad Beckmann
c9764b1ff1
ruby: added error message to isinstance check
...
Added error message when a symbol is not an instance of a particular expected
type.
2009-11-18 16:34:32 -08:00
Brad Beckmann
20f872ed2a
ruby: Added boolean to State Machine parameters
...
* * *
ruby: Removed primitive .hh includes
2009-11-18 16:34:32 -08:00
Brad Beckmann
8011e80725
ruby: The persistent table files from GEMS
...
These files are need by the MOESI_CMP_token protocol.
2009-11-18 16:34:32 -08:00
Brad Beckmann
cef3c56163
ruby: MOESI hammer support for DMA reads and writes
2009-11-18 16:34:32 -08:00
Brad Beckmann
dbb2c111cc
ruby: Added a memory controller feature to MOESI hammer
2009-11-18 16:34:32 -08:00
Brad Beckmann
bc12b8432d
ruby: Hammer ruby configuration support
2009-11-18 16:34:32 -08:00
Brad Beckmann
877be2009c
ruby: Changes necessary to get the hammer protocol to work in GEM5
2009-11-18 16:34:32 -08:00
Brad Beckmann
b0973035b4
ruby: added the original hammer protocols from old ruby
2009-11-18 16:34:31 -08:00
Brad Beckmann
2783a7b9ad
ruby: returns the number of LLC needed for broadcast
...
Added feature to CacheMemory to return the number of last level caches.
This count is need for broadcast protocols such as MOESI_hammer.
2009-11-18 16:34:31 -08:00
Brad Beckmann
7b8fcecf11
ruby: cache configuration fix to use bytes
...
Changed cache size to be in bytes instead of kb so that testers can use very
small caches and increase the chance of writeback races.
2009-11-18 16:34:31 -08:00
Brad Beckmann
99338a7460
ruby: fix CacheMemory destructor
2009-11-18 16:33:35 -08:00
Brad Beckmann
7ab484624f
ruby: split CacheMemory.hh into a .hh and a .cc
2009-11-18 16:33:35 -08:00
Brad Beckmann
8b0f970084
ruby: Added default names to message buffers
...
Added default names to message buffers created by the simple network.
2009-11-18 13:55:58 -08:00
Brad Beckmann
ed54ecf1c8
ruby: slicc method error fix
...
Added error message when a method call is not supported by an object.
2009-11-18 13:55:58 -08:00
Brad Beckmann
994169327a
ruby: slicc action error fix
...
Small fix to the State Machine error message when duplicate actions are defined.
2009-11-18 13:55:58 -08:00
Brad Beckmann
cc2db929cb
ruby: slicc state machine error fixes
...
Added error messages when:
- a state does not exist in a machine's list of known states.
- an event does not exist in a machine
- the actions of a certain machine have not been declared
2009-11-18 13:55:58 -08:00
Brad Beckmann
e84881b7a3
ruby: Removed unused action z_stall
2009-11-18 13:55:58 -08:00
Brad Beckmann
b5d2052fa0
m5: Fixed bug in atomic cpu destructor
2009-11-18 13:55:58 -08:00
Brad Beckmann
faf1d97f24
ruby: fixed dma mi example to work with multiple dma ports
2009-11-18 13:55:58 -08:00
Brad Beckmann
f54790977b
m5: removed master and slave deletions.
...
The unresolved destructor call caused a seg fault when called.
2009-11-18 13:55:58 -08:00
Brad Beckmann
4d731a522d
m5: fixed destructor to deschedule the tickEvent and event
2009-11-18 13:55:58 -08:00
Brad Beckmann
93f0069dd5
ruby: getPort function fix
...
Fixed RubyMemory::getPort function to not pass in a -1 for the idx parameter
2009-11-18 13:55:58 -08:00
Brad Beckmann
204d1776ca
ruby: Fixed Directory memory destructor
2009-11-18 13:55:58 -08:00
Brad Beckmann
6e1dc2546c
m5: Added isValidSrc and isValidDest calls to packet.hh
2009-11-18 13:55:58 -08:00
Brad Beckmann
90d6e2652f
ruby: included ruby config parameter ports per core
...
Slightly improved the major hack need to correctly assign the number of ports
per core. CPUs have two ports: icache + dcache. MemTester has one port.
2009-11-18 13:55:58 -08:00
Brad Beckmann
dce53610c3
ruby: Added error check for openning the ruby config file
2009-11-18 13:55:58 -08:00
Brad Beckmann
3cf24f9716
ruby: Support for merging ALPHA_FS and ruby
...
Connects M5 cpu and dma ports directly to ruby sequencers and dma
sequencers. Rubymem also includes a pio port so that pio requests
and be forwarded to a special pio bus connecting to device pio
ports.
2009-11-18 13:55:58 -08:00
Brad Beckmann
d7a4f665ed
ruby: Added more info to bridge error message
2009-11-18 13:55:57 -08:00
Brad Beckmann
17e14efa7e
ruby: Ruby 64-bit address output fixes.
2009-11-18 13:55:57 -08:00
Brad Beckmann
b7cc66af31
ruby: Ruby destruction fix.
2009-11-18 13:55:57 -08:00
Brad Beckmann
5492f71755
ruby: Ruby debug print fixes.
2009-11-18 13:55:57 -08:00
Derek Hower
9ef5e72917
ruby: added sequencer stats to track what requests are waiting on
2009-11-18 11:55:30 -06:00
Derek Hower
d11dd6ed2c
ruby: turned off randomization by default, turned on memory controller random arbitrate
2009-11-18 11:53:43 -06:00
Ali Saidi
422f0d9f10
ARM: Begin implementing CP15
2009-11-17 18:02:09 -06:00
Ali Saidi
0916c376a9
ARM: Differentiate between LDM exception return and LDM user regs.
2009-11-17 18:02:08 -06:00
Ali Saidi
1470dae8e9
ARM: Boilerplate full-system code.
...
--HG--
rename : src/arch/sparc/interrupts.hh => src/arch/arm/interrupts.hh
rename : src/arch/sparc/kernel_stats.hh => src/arch/arm/kernel_stats.hh
rename : src/arch/sparc/stacktrace.cc => src/arch/arm/stacktrace.cc
rename : src/arch/sparc/system.cc => src/arch/arm/system.cc
rename : src/arch/sparc/system.hh => src/arch/arm/system.hh
rename : src/dev/sparc/T1000.py => src/dev/arm/Versatile.py
rename : src/dev/sparc/t1000.cc => src/dev/arm/versatile.cc
rename : src/dev/sparc/t1000.hh => src/dev/arm/versatile.hh
2009-11-17 18:02:08 -06:00
Ali Saidi
171e7f7b24
imported patch isa_fixes2.diff
2009-11-16 11:37:03 -06:00
Gabe Black
9127ee5ac8
ARM: Make the exception return form of ldm restore CPSR.
2009-11-15 00:23:14 -08:00
Gabe Black
903fb8c73d
ARM: Create a new type of load uop that restores spsr into cpsr.
2009-11-15 00:15:42 -08:00
Gabe Black
b41725f723
ARM: Check in the actual change from the last commit.
...
The last commit was somehow empty. This was what was supposed to go in it.
2009-11-14 21:03:10 -08:00
Gabe Black
c4042985d7
ARM: Fix up the implmentation of the msr instruction.
2009-11-14 19:22:30 -08:00
Gabe Black
e2ab64543b
ARM: Define a mask to differentiate purely CPSR bits from CondCodes bits.
2009-11-14 19:22:30 -08:00
Gabe Black
425ebf6bd7
ARM: Add a bitfield to indicate if an immediate should be used.
2009-11-14 19:22:30 -08:00
Gabe Black
e543f16247
ARM: Write some functions to write to the CPSR and SPSR for instructions.
2009-11-14 19:22:30 -08:00
Gabe Black
812e390693
ARM: Fix up the implmentation of the mrs instruction.
2009-11-14 19:22:29 -08:00
Gabe Black
1df0025e28
ARM: More accurately describe the effects of using the control operands.
2009-11-14 19:22:29 -08:00
Gabe Black
50b9149c75
ARM: Hook up the moded versions of the SPSR.
...
These registers can be accessed directly, or through MISCREG_SPSR which will
act as whichever SPSR is appropriate for the current mode.
2009-11-14 19:22:29 -08:00
Ali Saidi
4e9ce1805e
SE: Fix SE mode OS X compilation.
2009-11-14 11:49:01 -06:00
Ali Saidi
48bc573f5f
ARM: Move around decoder to properly decode CP15
2009-11-14 11:25:00 -06:00
Derek Hower
2f5839832e
ruby: added -A option to TwoLevel_SplitL1UnifiedL2 to set the L1 cache size
2009-11-13 09:45:23 -06:00
Derek Hower
f7f475a6f4
ruby: gave ALIASED_REQUEST priority over BUFFER_FULL in sequencer
2009-11-13 09:44:51 -06:00
Derek Hower
2ee04d6587
ruby: reduce the memory usage of ruby by making memory vector page based
2009-11-13 09:43:39 -06:00
Derek Hower
ceb8fde914
ruby: cache memory bugfix
2009-11-13 09:42:47 -06:00
Vince Weaver
8f6744c19c
X86: add ULL to 1's being shifted in 64-bit values
...
Some of the micro-ops weren't casting 1 to ULL before shifting,
which can cause problems. On the perl makerand input this
caused some values to be negative that shouldn't have been.
The casts are done as ULL(1) instead of 1ULL to match others
in the m5 code base.
2009-11-11 17:49:09 -05:00
Gabe Black
5524af83ef
ARM: Fix some bugs in the ISA desc and fill out some instructions.
2009-11-10 23:44:05 -08:00
Gabe Black
850eb54a7c
Merge with the head.
2009-11-10 21:12:53 -08:00
Gabe Black
b8120f6c38
Mem: Eliminate the NO_FAULT request flag.
2009-11-10 21:10:18 -08:00
Gabe Black
2e28da5583
ARM: Implement fault classes.
...
Implement some fault classes using the curriously recurring template pattern,
similar to SPARCs.
2009-11-10 20:34:38 -08:00
Gabe Black
4779020e13
ARM: Fix the integer register indexes.
...
The PC indexes in the various register sets was defined in the section for
unaliased registers which was throwing off the indexing. This moves those
where they belong. Also, to make detecting accesses to the PC easier and
because it's in the same place in all modes, the intRegForceUser function
now passes it through as index 15.
2009-11-10 20:19:55 -08:00
Vince Weaver
53e27c0277
X86: Fix bugs in movd implementation.
...
Unfortunately my implementation of the movd instruction had two bugs.
In one case, when moving a 32-bit value into an xmm register, the
lower half of the xmm register was not zero extended.
The other case is that xmm was used instead of xmmlm as the source
for a register move. My test case didn't notice this at first
as it moved xmm0 to eax, which both have the same register
number.
2009-11-10 11:29:30 -05:00
Vince Weaver
e81cc233a6
X86: Remove double-cast in Cvtf2i micro-op
...
This double cast led to rounding errors which caused
some benchmarks to get the wrong values, most notably lucas
which failed spectacularly due to CVTTSD2SI returning an
off-by-one value. equake was also broken.
2009-11-10 11:18:23 -05:00
Vince Weaver
7da221ca82
syscall: missing initializer in getcwd call
...
This one case was missed during the update to stack-based arguments.
Without this fix, m5 will crash during a gwtcwd call, at least
with X86.
2009-11-09 10:02:55 -05:00
Gabe Black
bbbfdee2ed
X86: Don't panic on faults on prefetches in SE mode.
2009-11-08 22:49:58 -08:00
Gabe Black
44e912c6bd
X86: Explain what really didn't work with unmapped addresses in SE mode.
2009-11-08 22:49:57 -08:00
Gabe Black
53086dfefe
X86: Make x86 use PREFETCH instead of PF_EXCLUSIVE.
2009-11-08 22:49:57 -08:00
Nathan Binkert
b1a1f9aec8
automerge
2009-11-08 20:15:54 -08:00
Steve Reinhardt
374d337693
scons: deal with generated .py files properly
2009-11-08 17:35:49 -08:00
Gabe Black
8a4af3668d
ARM: Support forcing load/store multiple to use user registers.
2009-11-08 15:49:03 -08:00
Gabe Black
bb903b6514
ARM: Simplify the load/store multiple generation code.
...
Specifically, get rid of the big switch statement so more cases can be
handled. Enumerating all the possible settings doesn't scale well. Also do
some minor style clean up.
2009-11-08 15:16:59 -08:00
Nathan Binkert
708faa7677
compile: wrap 64bit numbers with ULL() so 32bit compiles work
...
In the isa_parser, we need to check case statements.
2009-11-08 13:31:59 -08:00
Gabe Black
48525f581c
ARM: Split the condition codes out of the CPSR.
...
This allows those bits to be renamed while allowing the other fields to
control the behavior of the processor.
2009-11-08 02:08:40 -08:00
Gabe Black
d188821d37
ARM: Add in more bits for the mon mode.
2009-11-08 02:01:02 -08:00
Gabe Black
3a3e846151
ARM: Get rid of NumInternalProcRegs.
...
That constant is a carry over from Alpha and doesn't do anything in ARM.
2009-11-08 02:00:55 -08:00
Gabe Black
78bd8fe44f
ARM: Add back in spots for Rhi and Rlo, and use a named constant for LR.
2009-11-08 01:59:20 -08:00
Gabe Black
f63c260d89
ARM: Get rid of the Raddr operand.
2009-11-08 01:57:34 -08:00
Gabe Black
43e9209c21
ARM: Initialize processes in user mode.
...
I accidentally left in a change to test using int registers in system mode.
This change reverts that.
2009-11-08 00:54:32 -08:00
Gabe Black
a2b76516c4
ARM: Implement the shadow registers using register flattening.
2009-11-08 00:07:49 -08:00
Gabe Black
4a454c4f47
ARM: Set up an intregs.hh for ARM.
...
Add constants for all the modes and registers, maps for aliasing, functions
that use the maps and range check, and use a named constant instead of a magic
number for the microcode register.
2009-11-08 00:07:35 -08:00
Gabe Black
18b21c1eca
ARM: Get rid of some unneeded register indexes.
2009-11-07 22:34:33 -08:00
Vince Weaver
5cf2e7ccf0
X86: Fix problem with movhps instruction
...
This problem is like the one fixed with movhpd a few weeks ago.
A +8 displacement is used to access memory when there should
be none.
This fix is needed for the perlbmk spec2k benchmark to run.
2009-11-04 13:22:15 -05:00
Steve Reinhardt
9098010e3f
slicc: tweak file enumeration for scons
...
Right now .cc and .hh files are handled separately, but then
they're just munged together at the end by scons, so it
doesn't buy us anything. Might as well munge from the start
since we'll eventually be adding generated Python files
to the list too.
2009-11-05 11:11:06 -08:00
Steve Reinhardt
058ccfc7fe
slicc: whack some of Nate's leftover debug code
2009-11-05 11:11:05 -08:00
Nathan Binkert
2c5fe6f95e
build: fix compile problems pointed out by gcc 4.4
2009-11-04 16:57:01 -08:00
Steve Reinhardt
fbfe92b5b8
o3: get rid of unused physmem pointer
2009-11-04 14:23:25 -08:00
Vince Weaver
a1042db290
X86: Enable x86_64 vsyscall support
...
64-bit vsyscall is different than 32-bit.
There are only two syscalls, time and gettimeofday.
On a real system, there is complicated code that implements these
without entering the kernel. That would be complicated to implement in m5.
Instead we just place code that calls the regular syscalls (this is how
tools such as valgrind handle this case).
This is needed for the perlbmk spec2k benchmark.
2009-11-04 00:47:12 -05:00
Vince Weaver
9b0a747dd4
X86: Hook up time syscall on X86
...
This has been tested and verified that it works.
2009-11-04 00:19:15 -05:00
Vince Weaver
a12557439b
X86: Add support for x86 psrldq and pslldq instructions
...
These are complicated instructions and the micro-code might be suboptimal.
This has been tested with some small sample programs (attached)
The psrldq instruction is needed by various spec2k programs.
2009-10-30 12:49:37 -04:00
Vince Weaver
5873ec2238
X86: Implement movd_Vo_Edp on X86
...
This patch implements the movd_Vo_Edp series of instructions.
It addresses various concerns by Gabe Black about which file the
instruction belonged in, as well as supporting REX prefixed
instructions properly.
This instruction is needed for some of the spec2k benchmarks, most
notably bzip2.
2009-10-30 15:52:33 -04:00
Vince Weaver
b2067840a6
X86: Implement the X86 sse2 haddpd instruction
...
This patch implements the haddpd instruction.
It fixes the problem in the previous version (pointed out by Gabe Black)
where an incorrect result would happen if you issue the instruction
with the same argument twice, i.e. "haddpd %xmm0,%xmm0"
This instruction is used by many spec2k benchmarks.
2009-10-30 14:19:06 -04:00
Vince Weaver
cf269025f9
X86: Hookup truncate/ftruncate syscalls on X86
...
This patch hooks up the truncate, ftruncate, truncate64 and ftruncate64
system calls on 32-bit and 64-bit X86.
These have been tested on both architectures.
ftruncate/ftruncate64 is needed for the f90 spec2k benchmarks.
2009-10-30 12:51:13 -04:00
Vince Weaver
9ad3acab5e
SysCalls: Implement truncate64 system call
...
This uses the new stack-based argument infrastructure.
Tested on x86 and x86_64.
2009-10-30 12:31:55 -04:00
Gabe Black
d6ff7929b3
Syscalls: Fix a warning turned error about an unused variable in m5.fast.
2009-10-31 13:20:22 -07:00
Gabe Black
3f722b991f
Syscalls: Make system calls access arguments like a stack, not an array.
...
When accessing arguments for a syscall, the position of an argument depends on
the policies of the ISA, how much space preceding arguments took up, and the
"alignment" of the index for this particular argument into the number of
possible storate locations. This change adjusts getSyscallArg to take its
index parameter by reference instead of value and to adjust it to point to the
possible location of the next argument on the stack, basically just after the
current one. This way, the rules for the new argument can be applied locally
without knowing about other arguments since those have already been taken into
account implicitly.
All system calls have also been changed to reflect the new interface. In a
number of cases this made the implementation clearer since it encourages
arguments to be collected in one place in order and then used as necessary
later, as opposed to scattering them throughout the function or using them in
place in long expressions. It also discourages using getSyscallArg over and
over to retrieve the same value when a temporary would do the job.
2009-10-30 00:44:55 -07:00
Nathan Binkert
25d9328689
license: Fix license on network model code
...
This mostly was a matter of changing the license owner to Princeton
which is as it should have been. The code was originally licensed
under the GPL but was relicensed as BSD by Li-Shiuan Peh on July 27,
2009. This relicensing was in an explicit e-mail to Nathan Binkert,
Brad Beckmann, Mark Hill, David Wood, and Steve Reinhardt.
2009-10-28 11:56:56 -07:00
Gabe Black
f9624e49f6
X86: Replace "DISPLACEMENT" with disp in movhpd.
2009-10-27 23:50:25 -07:00
Vince Weaver
87b97f28bd
Fix problem with the x86 sse movhpd instruction.
...
The movhpd instruction was writing to the wrong memory offset.
2009-10-27 14:11:06 -04:00
Vince Weaver
14691148cd
Implement X86 sse2 movdqu and movdqa instructions
...
The movdqa instruction should enforce 16-byte alignment.
This implementation does not do that.
These instructions are needed for most of x86_64 spec2k to run.
2009-10-21 13:40:43 -04:00
Vince Weaver
5b6f707a00
hook up stat syscall on 64-bit x86_SE
2009-10-20 16:48:00 -04:00
Derek Hower
22d9a53080
ruby: removed obsolete configuration files
2009-10-20 15:29:02 -05:00
Vince Weaver
2b473cb099
hook up stat64 syscall on 32-bit X86_SE
2009-10-20 14:44:51 -04:00
Vince Weaver
776f9405fa
Fix stat64 structure on 32-bit X86_SE
...
The st_size entry was in the wrong place
(see linux-2.6.29/arch/x86/include/asm/stat.h )
Also, the packed attribute is needed when compiling on a
64-bit machine, otherwise gcc adds extra padding that
break the layout of the structure.
2009-10-20 15:15:37 -04:00
Timothy M. Jones
835a55e7f3
POWER: Add support for the Power ISA
...
This adds support for the 32-bit, big endian Power ISA. This supports both
integer and floating point instructions based on the Power ISA Book I v2.06.
2009-10-27 09:24:39 -07:00
Brad Beckmann
0fdfc82bde
fixed error message generation bug in SLICC ast files
2009-10-26 17:06:32 -07:00
Timothy M. Jones
1b2d75d6d2
syscall: Addition of an ioctl command code for Power.
2009-10-24 10:53:59 -07:00
Timothy M. Jones
03da1e53c2
syscall: Zero out memory that already exists during the brk system call.
...
Glibc often assumes that memory it receives from the kernel after a brk
system call will contain only zeros. This is important during a calloc,
because it won't clear the new memory itself. In the simulator, if the
new page exists, it will be cleared using this patch, to mimic the kernel's
functionality.
2009-10-24 10:53:58 -07:00
Timothy M. Jones
cc21f862e2
syscall: Fix conversion of the stat64 buffer during system calls.
2009-10-24 10:53:58 -07:00
Timothy M. Jones
c32d919bc0
syscall: Implementation of the ftruncate64 system call.
2009-10-24 10:53:58 -07:00
Timothy M. Jones
7cdd5316ab
syscall: Implementation of the time system call.
2009-10-24 10:53:57 -07:00
Timothy M. Jones
6c60db8ce9
syscall: Implementation of the times system call
2009-10-24 10:53:57 -07:00
Vince Weaver
56154cff5e
Enable getuid and getgid related syscalls on X86_SE
...
I've tested these on x86 and they work as expected.
In theory for 32-bit x86 we should have some sort of special
handling for the legacy 16-bit uid/gid syscalls, but in practice
modern toolchains don't use the 16-bit versions, and m5 sets the uid
and gid values to be less than 16-bits anyway.
This fix is needed for the perl spec2k benchmarks to run.
2009-10-19 17:29:34 -04:00
Derek Hower
909bac6840
ruby: add parameter to config to set # of l2 banks
2009-10-16 16:31:16 -05:00
Vince Weaver
22dc2b5595
Ignore rt_sigaction() syscalls on x86 and x86_64
...
This is currently how alpha handles this syscall.
This is needed for the gcc spec2k benchmarks to run.
2009-10-16 13:54:20 -04:00
Gabe Black
010b13c937
ISA: Fix compilation.
2009-10-17 01:13:41 -07:00
Brad Beckmann
28204b2a96
fixed MC146818 checkpointing bug and added isa serialization calls to simple_thread
2009-10-15 15:15:24 -07:00
Vince Weaver
30a185dcd0
Hook up the munmap() syscall for 32-bit x86.
...
This is straightforward, as munmapFunc() doesn't do anything.
I've tested it with code running munmap() just in case.
2009-10-10 22:31:56 -07:00
Derek Hower
4505216282
merge
2009-10-07 15:48:26 -05:00
Steve Reinhardt
8a761c44af
bus: add assertion to catch illegal retry
...
on mem-inhibited transaction.
2009-10-03 18:07:39 -07:00
Gabe Black
44ceb80c2d
X86: Make successive anonymous mmaps move down in 32 bit SE mode Linux.
2009-10-02 01:32:58 -07:00
Gabe Black
86f3bec76d
SE mode: Make the direction anonymous mmaps move through memory configurable.
2009-10-02 01:32:00 -07:00
Korey Sewell
f09f84da6e
inorder-debug: print out workload
2009-10-01 09:35:06 -04:00
Lisa Hsu
1290a5f340
commit Soumyaroop's bug catch about max_insts_all_threads
2009-09-29 18:03:10 -04:00
Nathan Binkert
160bcf4442
python: Fix m5.defines so grabbing flags works correctly
2009-09-26 12:51:37 -07:00
Steve Reinhardt
4bec4702e9
O3: Add flag to control whether faulting instructions are traced.
...
When enabled, faulting instructions appear in the trace twice
(once when they fault and again when they're re-executed).
This flag is set by the Exec compound flag for backwards compatibility.
2009-09-26 10:50:50 -07:00
Steve Reinhardt
f679630788
Minor cleanup: Use the blockAlign() method where it applies in the cache.
2009-09-26 10:50:50 -07:00
Steve Reinhardt
72cfed4164
Force prefetches to check cache and MSHRs immediately prior to issue.
...
This prevents redundant prefetches from being issued, solving the
occasional 'needsExclusive && !blk->isWritable()' assertion failure
in cache_impl.hh that several people have run into.
Eliminates "prefetch_cache_check_push" flag, neither setting of
which really solved the problem.
2009-09-26 10:50:50 -07:00
Steve Reinhardt
f28ea7a6c9
O3: Mark fetch stage as active if it faults.
...
Otherwise if the rest of the pipeline is idle then
fault will never propagate to commit to be handled,
causing CPU to deadlock.
2009-09-26 10:50:50 -07:00
Derek Hower
d9a2450054
protocol: cleaned up MESI...got rid of unneccessary virtual networks
2009-09-25 17:51:51 -05:00
Derek Hower
83a9dc2939
ruby: more helpful config error message
2009-09-25 17:51:12 -05:00
Derek Hower
26990dc492
slicc: removed unused atomics code from StateMachine
2009-09-25 17:47:38 -05:00
Korey Sewell
25d1f2728a
inorder-debug: fix cpu tick debug message
2009-09-25 11:18:55 -04:00
Nathan Binkert
baca1f0566
isa_parser: Turn the ISA Parser into a subclass of Grammar.
...
This is to prepare for future cleanup where we allow SCons to create a
separate grammar class for each ISA
2009-09-23 18:28:29 -07:00
Nathan Binkert
bae6a4a4d9
ply grammar: Fixup Tokenizer class so you can get lexer arguments
2009-09-23 18:28:29 -07:00
Nathan Binkert
be0d74d6f6
ruby: Disable all debug output by default
2009-09-23 18:17:11 -07:00
Nathan Binkert
d9f39c8ce7
arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh
2009-09-23 08:34:21 -07:00
Nathan Binkert
2278363015
slicc: Pure python implementation of slicc.
...
This is simply a translation of the C++ slicc into python with very minimal
reorganization of the code. The output can be verified as nearly identical
by doing a "diff -wBur".
Slicc can easily be run manually by using util/slicc
2009-09-22 18:12:39 -07:00
Nathan Binkert
30d5d95b6a
params: small cleanup to param description internals
2009-09-22 15:24:16 -07:00
Nathan Binkert
e9288b2cd3
scons: add slicc and ply to sys.path and PYTHONPATH so everyone has access
2009-09-22 15:24:16 -07:00
Nathan Binkert
9a8cb7db7e
python: Move more code into m5.util allow SCons to use that code.
...
Get rid of misc.py and just stick misc things in __init__.py
Move utility functions out of SCons files and into m5.util
Move utility type stuff from m5/__init__.py to m5/util/__init__.py
Remove buildEnv from m5 and allow access only from m5.defines
Rename AddToPath to addToPath while we're moving it to m5.util
Rename read_command to readCommand while we're moving it
Rename compare_versions to compareVersions while we're moving it.
--HG--
rename : src/python/m5/convert.py => src/python/m5/util/convert.py
rename : src/python/m5/smartdict.py => src/python/m5/util/smartdict.py
2009-09-22 15:24:16 -07:00
Nathan Binkert
0d58d32ad5
multiattrdict: make multilevel nesting work properly
2009-09-22 15:24:16 -07:00
Nathan Binkert
eec67312b5
attrdict: add pickle support to attrdict
2009-09-22 15:24:16 -07:00
Nathan Binkert
aa78db4ada
code_formatter: use __builtin__ which is correct, not __builtins__
2009-09-22 15:24:16 -07:00
Polina Dudnik
4f463b3a26
Atomics bug fix
2009-09-21 13:04:52 -05:00
Polina Dudnik
114d8724dd
Functionality migrated to sequencer.
2009-09-17 17:39:52 -05:00
Korey Sewell
b7094ec38b
mips: fix command line arguments
...
arguments were not being saved correctly into M5 memory
2009-09-17 15:59:43 -04:00
Korey Sewell
6f7e196113
inorder-mdu: multiplier latency fix
...
mdu was workign incorrectly for 4+ latency due to incorrectly assuming
multiply was finished the next stage
2009-09-17 15:45:27 -04:00
Gabe Black
931405da2f
X86: Fix the expected size of the immediate offset in MOV_MI.
2009-09-17 02:56:06 -07:00
Gabe Black
c876a781a5
X86: Sign extend the immediate of wripi like the register version.
2009-09-16 19:29:51 -07:00
Gabe Black
7a0ef6c36f
X86: Make the imm8 member of immediate microops really 8 bits consistently.
2009-09-16 19:28:57 -07:00
Gabe Black
239f1dea31
X86: Fix checking the NT bit during an IRET.
2009-09-16 19:28:30 -07:00
Gabe Black
eec6bfaa9d
X86: Fix setting the busy bit in the task descriptor in LTR.
2009-09-16 19:28:01 -07:00
Soumyaroop Roy
83eebe0464
inorder-smt: remove hardcoded values
...
allows for the 2T hello world example to work in inorder model
2009-09-16 09:47:38 -04:00
Vince Weaver
9b8e61beb3
Syscalls: Implement sysinfo() syscall.
2009-09-15 22:36:47 -07:00
Derek Hower
31a3ef03cb
ruby: improve libruby_issue_request feedback
2009-09-15 21:37:40 -05:00
Derek Hower
144459032a
removed isReady from the library interface
2009-09-15 20:49:54 -05:00
Derek Hower
20da0f788c
ruby: added broadcast mechanism
2009-09-15 20:39:00 -05:00
Derek Hower
a06cfa199f
ruby: added unified assert script
2009-09-15 11:32:11 -05:00
Derek Hower
803cf3b434
ruby: made configuration parameters uniform
2009-09-15 09:47:11 -05:00
Vince Weaver
0f569b4d9d
SPARC: Make resTemp in udivcc wide enough to hold all the bits we need.
2009-09-15 05:48:20 -07:00
Vince Weaver
9900ac95b5
[mq]: x86syscalls.patch
2009-09-15 05:30:08 -07:00
Korey Sewell
badb2382a8
inorder-alpha-fs: edit inorder model to compile FS mode
2009-09-15 01:44:48 -04:00
Derek Hower
11f3f83068
ruby:removed unused code from CacheMemory
2009-09-14 17:52:46 -05:00
Derek Hower
18e328cb63
ruby: configuration updates
2009-09-14 17:11:02 -05:00
Derek Hower
62b06f4a70
ruby: removed stray printf
2009-09-14 17:09:26 -05:00
Derek Hower
75c2baa81c
merge
2009-09-11 16:23:17 -05:00
Derek Hower
6fc2a4cadc
ruby: cleaned up unified MESI/MOESI configuration
2009-09-11 16:22:59 -05:00
Polina Dudnik
c7f0cf9803
Added new MESI files
2009-09-11 16:19:31 -05:00
Derek Hower
bd770274b0
merge
2009-09-11 14:17:21 -05:00
Polina Dudnik
8cdd7265ce
Config adjustments for MESI
2009-09-11 11:07:22 -05:00
Polina Dudnik
fc9ebc60db
Somayeh's MESI protocol with Polina's bug fixes
2009-09-11 11:04:55 -05:00
Polina Dudnik
7ef3e3b2c2
MI data corruption bug fix
2009-09-11 10:59:35 -05:00
Polina Dudnik
353a69eae7
Object print bug fix
2009-09-11 10:59:08 -05:00
Polina Dudnik
2af2e590e1
MOESI data corruption bug fix
2009-09-11 10:58:37 -05:00
Derek Hower
1e40ee4ea0
Automated merge with ssh://hg@m5sim.org/m5
2009-09-10 22:02:13 -05:00
Derek Hower
0637fe0bfd
ruby: removed SMT-related Sequencer assert
2009-09-10 21:19:54 -05:00
Derek Hower
ef87b6dc82
ruby: made randomization true by default
2009-09-10 21:19:34 -05:00
Derek Hower
26acdd4f34
protocol: made MI_example work with unordered networks
2009-09-10 21:18:09 -05:00
Derek Hower
e6e3ccf5c0
ruby: made L2 request/response latency based on cache latency by default
2009-09-10 13:32:16 -05:00
Derek Hower
3bb2fcfc84
ruby: made Locked read/write atomic requests within ruby
2009-09-09 12:39:10 -05:00
Polina Dudnik
ca0e0c3683
SCons fix to always make MemTest object
2009-09-01 10:38:25 -05:00
Derek Hower
edd522b30a
Automated merge with ssh://hg@m5sim.org/m5
2009-09-01 09:36:53 -05:00
Derek Hower
849bad7ad7
ruby: fixed config assertion failure
2009-09-01 09:35:48 -05:00
Polina Dudnik
041a8cefc7
[mq]: MOESI_patch
2009-08-31 16:38:22 -05:00
Polina Dudnik
a02dbd61f9
Reset the atomics flags if RMW_Read is not followed by a RMW_Read or RMW_Write
2009-08-28 15:09:41 -05:00
Polina Dudnik
95da6dc84c
imported patch mi_patch
2009-08-28 15:04:55 -05:00
Derek Hower
15aa180570
merge
2009-08-25 10:37:21 -05:00
Derek Hower
6cd552483b
Automated merge with ssh://hg@m5sim.org/m5
2009-08-25 10:10:23 -05:00
Derek Hower
03bf748ac7
ruby: CacheMemory tag lookup uses a hash instead of a loop
2009-08-25 10:09:47 -05:00
Gabe Black
e251b42c59
Merge with head.
2009-08-23 14:19:14 -07:00
Gabe Black
d0d597004f
X86: Preserve the NO_ACCESS flag when giving CDA a specialized interface.
2009-08-23 14:16:58 -07:00
Gabe Black
ce63e50364
Atomic CPU: Respect the NO_ACCESS request flag.
2009-08-23 14:15:15 -07:00
Polina Dudnik
a4fc1bad94
[mq]: first_patch
2009-08-21 15:52:46 -05:00
Nathan Binkert
890be77362
X86: fix some simple compile issues
...
static should not be used for constants that are not inside a class definition.
2009-08-21 09:10:25 -07:00
Gabe Black
f6bb7ec4eb
RTC: Make calls to writeData update the RTCs internal representation of time.
2009-08-20 23:09:03 -07:00
Gabe Black
da3c3bfa98
X86: Make the real time clock actually keep track of time.
2009-08-20 00:42:43 -07:00
Gabe Black
e8c0ca5cd1
X86: Fix the decoding for and fill out FST and FSTP.
2009-08-20 00:42:14 -07:00
Gabe Black
843d064668
X86: Add microassembler symbols for floating point stack register operands.
2009-08-20 00:41:27 -07:00
Gabe Black
bc67396ada
X86: Don't insist on binary encoding for the RTC since we implement BCD.
2009-08-20 00:40:14 -07:00
Derek Hower
efc1dddbd8
ruby: added random seed option to config scripts
2009-08-18 16:24:09 -05:00
Gabe Black
ed088ed15e
X86: Decode the immediate byte opcode extension for 3dNow! instructions.
2009-08-18 00:52:47 -07:00
Gabe Black
fd45c04cad
X86: Decode three byte opcodes.
2009-08-18 00:52:45 -07:00
Gabe Black
a1ea10d7ba
Merge with head.
2009-08-17 22:39:10 -07:00
Gabe Black
8f49cd1123
X86: Move the simulated date in X86_FS forward to 2012.
2009-08-17 20:25:15 -07:00
Gabe Black
9df74ab401
X86: Double check the two byte portion of the decoder and fix bugs/clean up.
2009-08-17 20:25:15 -07:00
Gabe Black
92867cac95
X86: Implement MOVNTI.
2009-08-17 20:25:15 -07:00
Gabe Black
6415252a0f
X86: Initialize the MXCSR in SE mode.
2009-08-17 20:25:14 -07:00
Gabe Black
56d87cdc08
X86: Implement MOVQ2DQ.
2009-08-17 20:25:14 -07:00
Gabe Black
317a9ac6d1
X86: Implement MOVDQ2Q.
2009-08-17 20:25:14 -07:00
Gabe Black
1606663aa9
X86: Implement the media instructions that convert fp values to ints.
2009-08-17 20:25:14 -07:00
Gabe Black
e3ef432a55
X86: Implement a microop for converting fp values to ints.
2009-08-17 20:25:14 -07:00
Gabe Black
123ea3b229
X86: Implement the instructions that compare fp values and write a mask as a result.
2009-08-17 20:25:14 -07:00
Gabe Black
288f428632
X86: Implement a microop that compares fp values and writes a mask as a result.
2009-08-17 20:25:14 -07:00
Gabe Black
87ad677209
X86: Implement the instructions that compare fp values and write to rflags.
2009-08-17 20:25:14 -07:00
Gabe Black
2c9ee52c37
X86: Implement a microop that compares fp values and writes to rflags.
2009-08-17 20:25:14 -07:00
Gabe Black
7d4db7266e
X86: Implement MOVSS.
2009-08-17 20:25:14 -07:00
Gabe Black
179fd4e536
X86: Implement LDMXCSR.
2009-08-17 20:25:14 -07:00
Gabe Black
b315c3effc
X86: Implement STMXCSR.
2009-08-17 20:25:13 -07:00
Gabe Black
7fbd9e1296
X86: Implement the shuffle media instructions.
2009-08-17 20:25:13 -07:00
Gabe Black
1fed0161d9
X86: Implement a shuffle media microop.
2009-08-17 20:25:13 -07:00
Gabe Black
d9970f139a
X86: Implement the mask move instructions.
2009-08-17 20:22:56 -07:00
Gabe Black
75528a497c
X86: Implement a mask move microop.
2009-08-17 20:22:56 -07:00
Gabe Black
90dc1abd0b
X86: Implement the instructions that move sign bits.
2009-08-17 20:22:56 -07:00
Gabe Black
90786e43fc
X86: Implement a microop that moves sign bits.
2009-08-17 20:22:56 -07:00
Gabe Black
4c23e631f2
X86: Implement the insert/extract instructions.
2009-08-17 20:22:56 -07:00
Gabe Black
c0e850c77a
X86: Fix a bug in the decoder where the insert/extract instructions go.
2009-08-17 20:22:56 -07:00
Gabe Black
965e546df3
X86: Extend mov2int and mov2fp so they can support insert and extract instructions.
2009-08-17 20:22:56 -07:00
Gabe Black
2beab367d7
X86: Implement the media average instructions.
2009-08-17 20:15:16 -07:00
Gabe Black
f6b12bfa8d
X86: Implement a media average microop.
2009-08-17 20:15:16 -07:00
Gabe Black
45bae0c70f
X86: Implement the multiply and add instructions.
2009-08-17 20:15:16 -07:00
Gabe Black
200fed31de
X86: Let the integer multiply microop use every other possible source value.
2009-08-17 20:15:16 -07:00
Gabe Black
cf2fc2613d
X86: Implement the media shifts that operate on 64 bits or less at a time.
2009-08-17 20:15:16 -07:00
Gabe Black
c8a0cf5df7
X86: Implement the media shift microops. These don't handle full 128 bit wide shifts.
2009-08-17 20:15:16 -07:00
Gabe Black
dabbc7d9d3
X86: Implement the sum of absolute differences instructions.
2009-08-17 20:15:16 -07:00
Gabe Black
470dcef229
X86: Implement a "sum of absolute differences" microop.
2009-08-17 20:15:16 -07:00
Gabe Black
31d29ee3f8
X86: Implement the media integer subtract instructions.
2009-08-17 20:15:15 -07:00
Gabe Black
a4437f8f14
X86: Implement an integer media subtract microop.
2009-08-17 20:15:15 -07:00
Gabe Black
c40698e315
X86: Implement the integer media multiply instructions.
2009-08-17 20:15:15 -07:00
Gabe Black
3424de2861
X86: Implement a media integer multiply microop.
2009-08-17 20:15:15 -07:00
Gabe Black
c76459e5a7
X86: Make larger blocks of instructions use the Inst format by default.
2009-08-17 20:04:03 -07:00
Gabe Black
5d834c28eb
X86: Implement the integer media max instructions.
2009-08-17 20:04:03 -07:00
Gabe Black
c9a954c77a
X86: Implement an integer media max microop.
2009-08-17 20:04:03 -07:00
Gabe Black
be6267e895
X86: Implement the integer media min instructions.
2009-08-17 20:04:03 -07:00
Gabe Black
e2759fe69c
X86: Add a media integer min microop.
2009-08-17 20:04:02 -07:00
Gabe Black
e678df6263
X86: Implement the media integer addition instructions.
2009-08-17 20:04:02 -07:00
Gabe Black
c278760da0
X86: Implement an integer media addition microop with optional saturation.
2009-08-17 20:04:02 -07:00
Gabe Black
f5ac4f51d9
X86: Implement the instructions that convert between forms of floating point.
2009-08-17 20:04:02 -07:00
Gabe Black
83df309a7e
X86: Implement a media microop that converts between floating point data types.
2009-08-17 20:04:02 -07:00
Gabe Black
35b0983ca9
X86: Implement the instructions that compare fp values and write masks as the result.
2009-08-17 20:04:02 -07:00
Gabe Black
f122c93faa
X86: Implement a microop that compares fp values and writes a mask as its result.
2009-08-17 20:04:02 -07:00
Gabe Black
df1b3fdcfb
X86: Implement the MOVDDUP instruction.
2009-08-17 18:50:29 -07:00
Gabe Black
cf9634a43f
X86: Implement many of the media mov instructions.
2009-08-17 18:44:44 -07:00
Gabe Black
ae64377afe
X86: Implement the media instructions that convert integer values to floating point.
2009-08-17 18:41:27 -07:00
Gabe Black
8e97cd9c8f
X86: Implement a media microop for converting integer values to floating point.
2009-08-17 18:41:25 -07:00
Gabe Black
b34b507fd8
X86: Implement the floating point media instructions.
2009-08-17 18:40:40 -07:00
Gabe Black
af3a53726b
X86: Implement a floating point media divide microop.
2009-08-17 18:40:38 -07:00
Gabe Black
fcb5b2226c
X86: Implement the floating point media multiply instructions.
2009-08-17 18:38:53 -07:00
Gabe Black
94e771e283
X86: Implement a floating point media multiply microop.
2009-08-17 18:38:51 -07:00
Gabe Black
dd81a34829
X86: Implement the floating point media subtract instructions.
2009-08-17 18:36:20 -07:00
Gabe Black
9fee8b75aa
X86: Implement a media floating point subtract microop.
2009-08-17 18:36:18 -07:00
Gabe Black
49c2610c04
X86: Implement the floating point media add instructions.
2009-08-17 18:35:06 -07:00
Gabe Black
df163284fc
X86: Implement a floating point media add microop.
2009-08-17 18:35:04 -07:00
Gabe Black
449db8a370
X86: Implement the media sqrt instructions.
2009-08-17 18:34:19 -07:00
Gabe Black
6a923c1c79
X86: Implement a media square root microop.
2009-08-17 18:34:16 -07:00
Gabe Black
09eed9ff62
X86: Implement the media floating point max instructions.
2009-08-17 18:33:28 -07:00
Gabe Black
8d37ce8652
X86: Implement the floating point media max microop.
2009-08-17 18:33:25 -07:00
Gabe Black
34f528bd95
X86: Implement the media floating point min instructions.
2009-08-17 18:32:12 -07:00
Gabe Black
1d706c0434
X86: Implement a floating point media min microop.
2009-08-17 18:32:09 -07:00
Gabe Black
e20c8a4b05
X86: Implement the pack instructions.
2009-08-17 18:32:08 -07:00
Gabe Black
1273277d3b
X86: Create a pack media microop.
2009-08-17 18:27:54 -07:00
Gabe Black
e6b5192c26
X86: Rename sel to ext for media microops.
2009-08-17 18:27:44 -07:00
Gabe Black
80b4456fec
X86: Move the MMX version of MOVD into the simd64 directory.
2009-08-17 18:27:30 -07:00
Gabe Black
63403bd562
X86: Implement the remaining unpack instructions.
2009-08-17 18:27:19 -07:00
Gabe Black
7b18f8a062
X86: Implement PANDN, ANDNPS, and ANDNPD.
2009-08-17 18:25:00 -07:00
Gabe Black
458521f055
X86: Implement a multimedia andn microop.
2009-08-17 18:24:58 -07:00
Gabe Black
3633392ec4
X86: Implement PAND, ANDPS, and ANDPD.
2009-08-17 18:24:18 -07:00
Gabe Black
ab49a34a4e
X86: Implement a multimedia and microop.
2009-08-17 18:24:16 -07:00
Gabe Black
83a78072df
X86: Implement POR, ORPD and ORPS.
2009-08-17 18:23:33 -07:00
Gabe Black
25c6b016a6
X86: Implement a media or microop.
2009-08-17 18:23:30 -07:00
Gabe Black
f9346d25c8
X86: Implement PXOR.
2009-08-17 18:23:04 -07:00
Gabe Black
69f0bf743c
X86: (Re)implement XORPS and XORPD.
2009-08-17 18:22:37 -07:00
Gabe Black
982b3ad1f0
X86: Implement a media xor microop.
2009-08-17 18:22:33 -07:00
Gabe Black
f3fb444af4
X86: Implement PUNPCKLQDQ.
2009-08-17 18:21:46 -07:00
Gabe Black
cfaeb5eaf7
X86: Implement PUNPCKHQDQ.
2009-08-17 18:21:09 -07:00
Gabe Black
aabbb22cca
X86: Implement PUNPCKHDQ.
2009-08-17 18:20:50 -07:00
Gabe Black
535ba241f8
X86: Implement PUNPCKHWD.
2009-08-17 18:19:43 -07:00
Gabe Black
093b5b3274
X86: Implement PUNPCKHBW.
2009-08-17 18:19:19 -07:00
Gabe Black
3ae2f03927
X86: Implement PUNPCKLDQ.
2009-08-17 18:19:01 -07:00
Gabe Black
673b19f5d4
X86: Implement PUNPCKLWD.
2009-08-17 18:18:40 -07:00
Gabe Black
ae4ee21ecd
X86: Implement the versions of PUNPCKLBW that use XMM registers.
2009-08-17 18:18:19 -07:00
Gabe Black
24496060e5
X86: Implement the MOVQ instruction.
2009-08-17 18:17:29 -07:00
Gabe Black
f1bfa9d6e4
X86: Implement the lfpimm microop.
2009-08-17 18:17:26 -07:00
Gabe Black
fca7cb83f0
X86: Implement the versions of MOVD that have an MMX source.
2009-08-17 18:16:07 -07:00
Gabe Black
247ed2379d
X86: Implement the versions of PUNPCKLBW that use MMX registers.
2009-08-17 18:15:42 -07:00
Gabe Black
ecc62e750e
X86: Implement an unpack microop.
2009-08-17 18:15:39 -07:00
Gabe Black
6457fb7003
X86: Implement the versions of MOVD that have an MMX destination.
2009-08-17 18:15:24 -07:00
Gabe Black
191590bcc4
X86: Ignore the size part of XMM/MMX operands. The instructions know what they want.
2009-08-17 18:15:23 -07:00
Gabe Black
33cb4c2f09
X86: Use suffixes to differentiate XMM/MMX/GPR operands.
2009-08-17 18:15:21 -07:00
Gabe Black
3a4438a868
X86: Add microcode assembler symbols for mmx registers.
2009-08-17 18:15:19 -07:00
Gabe Black
2f1001e95c
X86: Set up a media microop framework and create mov2int and mov2fp microops.
2009-08-17 18:15:18 -07:00
Gabe Black
cec4e3b39e
X86: Create base classes for use with media/SIMD microops.
2009-08-17 18:15:16 -07:00
Gabe Black
0b68fbdbe1
X86: Turn the DIV and IDIV microcode into templates and generate all the variants.
2009-08-17 18:15:14 -07:00
Gabe Black
a9b2bf5119
X86: Remove some FIXMEs from IDIV that have been fixed.
2009-08-17 18:15:13 -07:00
Gabe Black
3f2f3bede8
X86: Turn the CMPXCHG8B microcode into a template and generate each variant.
2009-08-17 18:15:00 -07:00
Polina Dudnik
c438b2e431
Branch Merge
2009-08-17 11:33:32 -05:00
Gabe Black
a43ae579dd
Merge with head.
2009-08-17 00:21:57 -07:00
Gabe Black
32c8514b45
X86: Fix a bug introduced to IDIV in a recent attempt to fix another bug.
2009-08-17 00:20:03 -07:00
Nathan Binkert
a6b39c07d9
code_formatter: Add a python class for writing code generator templates
2009-08-16 13:40:03 -07:00
Nathan Binkert
2ecaa99025
ply: add a base class called Grammar that encapsulates a ply grammar
2009-08-16 13:40:01 -07:00
Nathan Binkert
2334e6fdd5
orderdict: Use DictMixin and add orderdict to m5.util
2009-08-16 13:40:00 -07:00
Nathan Binkert
06c7ecb207
python: Make it possible to import the parts of m5 that are pure python
2009-08-16 13:39:59 -07:00
Polina Dudnik
6654fe02da
Made servicing_atomic a counter and added started writes:
...
a function for setting the flag to indicate that
the rmw_writes started issuing
2009-08-15 12:45:11 -05:00
Polina Dudnik
a8e11cf3bb
Bug fix: indicate when writes started coming in
2009-08-14 17:57:54 -05:00
Polina Dudnik
ee3226d973
Merge with current branch
2009-08-14 15:30:25 -05:00
Polina Dudnik
0b0f47ec16
Added proc_id to CacheMsg for SMT.
...
Not yet necessary, but in case each of the threads
is allowed to initiate an atomic, will come in handy
2009-08-14 15:30:07 -05:00
Polina Dudnik
de25decf37
Multi-line RMW handling
2009-08-14 14:24:15 -05:00
Polina Dudnik
4b924fd16c
SMT atomics modifications:
...
don't allow enquing from other threads if servicing and atomic for a thread
2009-08-14 14:06:14 -05:00
Derek Hower
bcaf93d182
Automated merge with ssh://hg@m5sim.org/m5
2009-08-13 10:37:37 -05:00
Derek Hower
db40cb8f51
ruby: config bugfix
2009-08-13 10:37:09 -05:00
Tushar Krishna
35082a67b6
ruby/network data_msg_size bug fix with updated stats
2009-08-11 15:19:04 -07:00
Brad Beckmann
b89add1e3f
merged Tushar's bug fix with public repository changes
2009-08-11 12:22:41 -07:00
Derek Hower
1c3efb48ad
Automated merge with ssh://hg@m5sim.org/m5
2009-08-09 13:59:14 -05:00
Derek Hower
1a452d228b
protocol: added recycle actions to MOESI DMA events
2009-08-09 13:58:40 -05:00
Gabe Black
c5fae51774
X86: Implement the CMPXCHG8B/CMPXCHG16B instruction.
2009-08-09 01:01:41 -07:00
Gabe Black
bbf117b20e
X86: Don't clobber the original dividend when doing signed divide.
2009-08-09 01:01:18 -07:00
Gabe Black
3b07a5829d
X86: Decode byte sized singed divide as byte sized.
2009-08-09 01:00:47 -07:00
Gabe Black
6e97feb8a5
X86: Make not taken conditional moves leave the destination alone. Adjust CMOVcc.
...
The manuals from both AMD and Intel say that when writing to a 32 bit
destination in 64 bit mode, the upper 32 bits of the register are filled with
zeros. They also both say that the CMOV instructions leave their destination
alone when their condition fails. Unfortunately, it seems that CMOV will zero
extend its destination register whether or not it was supposed to actually do
a move on both platforms. This seems to be the only case where this happens,
but it would be hard to say for sure.
2009-08-08 17:23:19 -07:00
Tushar Krishna
b952eb19c1
bug fix for data_msg_size in network/Network.cc
2009-08-07 13:59:40 -07:00
Gabe Black
7c606e3835
X86: (Re)Implemented SHRD.
2009-08-07 10:13:33 -07:00
Gabe Black
4f5270f946
X86: Implement SHLD.
2009-08-07 10:13:24 -07:00
Gabe Black
3a55fc5cac
X86: Implement shift right/left double microops.
...
This is my best guess as far as what these should do. Other existing microops
use implicit registers, mul1s and mul1u for instance, so this should be ok.
The microop that loads the implicit DoubleBits register would fall into one
of the microop slots for moving to/from special registers.
2009-08-07 10:13:20 -07:00
Gabe Black
62a2e85c9a
X86: Make the qaud width bswap instruction handle the fact that 32 bit operations zero extend.
2009-08-07 10:12:58 -07:00
Gabe Black
0526f453aa
X86: Use the right field when using legacy prefixes to distinguish instructions.
2009-08-07 10:12:52 -07:00
Gabe Black
2daba26359
X86: Don't truncate the immediate parameter for the ENTER instruction.
2009-08-07 10:12:29 -07:00
Gabe Black
2e3446a410
X86: Adjust the various sizes used for the enter and leave instructions.
2009-08-06 21:44:42 -07:00
Gabe Black
c7b894a06f
X86: Make scas compare its operands in the right order.
2009-08-06 21:44:41 -07:00
Gabe Black
011c1865ad
X86: Fix a copy/paste error for cmovnp.
2009-08-06 21:44:40 -07:00
Derek Hower
cbc52ef6c5
fixed MOESI_CMP_directory bug
2009-08-06 03:41:28 -05:00
Derek Hower
f5e0c56da2
protocol: fixed MOESI_CMP_directory bug
2009-08-06 01:15:55 -05:00
Derek Hower
a1b5a6320f
ruby: better configuration assert message
2009-08-06 01:15:23 -05:00
Derek Hower
dff7c9eaa0
merge
2009-08-05 14:23:32 -05:00
Derek Hower
fbf7391bb0
ruby: configuration supports multiple runs in same session
...
These changes allow to run Ruby-gems multiple times from the same
ruby-lang script with different configurations
2009-08-05 14:20:32 -05:00
Derek Hower
1276df51e2
protocol: made MI_example dma mapping generic
2009-08-05 14:17:23 -05:00
Gabe Black
60d4a0f6d7
Merge with head.
2009-08-05 03:12:39 -07:00
Gabe Black
da2df2fc25
X86: Make conditional moves zero extend their 32 bit destinations always.
2009-08-05 03:07:55 -07:00
Gabe Black
b64d0bdeda
X86: Fix condition code setting for signed multiplies with negative results.
2009-08-05 03:07:01 -07:00
Gabe Black
2914a8eb16
X86: Make the check for negative operands for sign multiply more direct.
2009-08-05 03:06:37 -07:00
Gabe Black
e2e0ae576a
X86: Make sure immediate values are truncated properly.
...
Register values will be "picked" which will assure they don't have junk beyond
the part we're using. Immediate values don't go through a similar process, so
we should truncate them explicitly.
2009-08-05 03:06:01 -07:00
Gabe Black
ef3896d851
X86: Use the new forced folding mechanism for the SAHF and LAHF instructions.
2009-08-05 03:04:17 -07:00
Gabe Black
664d50b439
X86: Fix the indexing for ah in byte division instructions.
2009-08-05 03:03:41 -07:00
Gabe Black
abe8fb3844
X86: Fix the indexing for ah in byte multiply instructions.
2009-08-05 03:03:28 -07:00
Gabe Black
df1abc4412
X86: Let microops force folding an index into the high byte of a register.
2009-08-05 03:03:07 -07:00
Gabe Black
c4140d7d60
X86: Handle rotate left with carry instructions that go all the way around or more.
2009-08-05 03:02:28 -07:00
Gabe Black
3990445354
X86: Set the flags on rotate left with carry instructions.
2009-08-05 03:02:05 -07:00
Gabe Black
d265f7683e
X86: Handle rotate right with carry instructions that go all the way around or more.
2009-08-05 03:01:49 -07:00
Gabe Black
77dc6b33ee
X86: Fix the overflow bit for rotate right with carry.
2009-08-05 03:01:23 -07:00
Gabe Black
c8b1a4583e
X86: Fix the computation of the bottom part of rotate right with carry.
2009-08-05 03:01:07 -07:00
Gabe Black
bab4597fc5
X86: Fix the computation of the upper part of rotate right with carry.
2009-08-05 03:00:43 -07:00
Gabe Black
4e4adcaaa8
X86: Set the flags for rotate right with carry instructions.
2009-08-05 03:00:23 -07:00
Gabe Black
64d7948692
X86: Handle rotating right all the way around or more.
2009-08-05 03:00:03 -07:00
Gabe Black
88041f75c4
X86: Set the flags on a rotate right instruction.
2009-08-05 02:59:39 -07:00
Gabe Black
029d360db2
X86: Make shifts/rotations that write to 32 bits of a register zero extend.
2009-08-05 02:59:25 -07:00
Gabe Black
7f9a3af250
X86: Handle left rotations that go all the way around or more.
2009-08-05 02:58:54 -07:00
Gabe Black
99adfd9dae
X86: Actually set the flags on a rotate left instruction.
2009-08-05 02:58:20 -07:00
Gabe Black
c087b60af3
X86: Fix the sar carry flag.
2009-08-05 02:58:03 -07:00
Gabe Black
860f0f8350
X86: Fix sign extension when doing an arithmetic shift right by 0.
2009-08-05 02:57:47 -07:00
Gabe Black
a238959c34
X86: Fix the carry flag for shr.
2009-08-05 02:56:49 -07:00
Gabe Black
22a5f66820
X86: Fix the carry flag for shl.
2009-08-05 02:56:38 -07:00
Gabe Black
df2c862a07
X86: Fix how the parity flag is computed.
...
It's only for the lowest order byte, and I had the polarity wrong.
2009-08-05 02:56:12 -07:00
Derek Hower
7f012ef8da
ruby: made mapAddressToRange based off a bit count
2009-08-04 23:05:37 -05:00
Derek Hower
33b28fde7a
slicc: added MOESI_CMP_directory, DMA SequencerMsg, parameterized controllers
...
This changeset contains a lot of different changes that are too
mingled to separate. They are:
1. Added MOESI_CMP_directory
I made the changes necessary to bring back MOESI_CMP_directory,
including adding a DMA controller. I got rid of MOESI_CMP_directory_m
and made MOESI_CMP_directory use a memory controller. Added a new
configuration for two level protocols in general, and
MOESI_CMP_directory in particular.
2. DMA Sequencer uses a generic SequencerMsg
I will eventually make the cache Sequencer use this type as well. It
doesn't contain an offset field, just a physical address and a length.
MI_example has been updated to deal with this.
3. Parameterized Controllers
SLICC controllers can now take custom parameters to use for mapping,
latencies, etc. Currently, only int parameters are supported.
2009-08-04 12:52:52 -05:00
Derek Hower
c1e0bd1df4
slicc: generate html by default
2009-08-04 12:42:45 -05:00
Nathan Binkert
bd7af84d5e
slicc: better error messages when the python parser fails
2009-08-04 09:37:27 -07:00
Gabe Black
f5c21eaa1a
Merged with head.
2009-08-03 11:06:19 -07:00
Gabe Black
676dc6d292
X86: Fix segment override prefixes on instructions that use rbp/rsp and a displacement.
2009-08-03 11:01:40 -07:00
Derek Hower
ac15e42c17
Automated merge with ssh://hg@m5sim.org/m5
2009-08-03 11:39:08 -05:00
Gabe Black
38c2af17a5
X86: Set up the IDE device correctly, ie. with and using legacy ports.
2009-08-02 18:01:13 -07:00
Gabe Black
80aa771dbc
IDE: Configure the IDE control to reflect the initial value of the command register.
2009-08-02 18:01:09 -07:00
Gabe Black
aff57202b4
X86: Fix the high result of mul1s, and removed undefined shifts from the mult microops.
2009-08-02 08:39:29 -07:00
Steve Reinhardt
a13a706a20
Fix setting of INST_FETCH flag for O3 CPU.
...
It's still broken in inorder.
Also enhance DPRINTFs in cache and physical memory so we
can see more easily whether it's getting set or not.
2009-08-01 22:50:14 -07:00
Steve Reinhardt
1c28004654
Clean up some inconsistencies with Request flags.
2009-08-01 22:50:13 -07:00
Steve Reinhardt
c0755e6085
Rename internal Request fields to start with '_'.
...
The inconsistency was causing a subtle bug with some of the
constructors where the params had the same name as the fields.
This is also a first step to switching the accessors over to
our new "standard", e.g., getVaddr() -> vaddr().
2009-08-01 22:50:10 -07:00
Korey Sewell
aa75b9a7a7
merge mips fix and statetrace changes
2009-07-31 10:40:42 -04:00
Korey Sewell
60063cc700
mips: fix ll/sc pairs working incorrectly because of accidental clobber of LLFLAG
2009-07-31 09:34:29 -04:00
Nathan Binkert
3dd3de5feb
compile: fix accidental conversion of == into =
2009-07-30 17:42:57 -07:00
Gabe Black
4971331b4f
ARM: Mul and mla ignore the c and v flags, but we were setting them to 1.
2009-07-29 22:24:00 -07:00
Derek Hower
d9ff3021ba
ruby: fixed clearStats
2009-07-29 13:46:58 -05:00
Gabe Black
b066e717f4
ARM: Fix an instruction in the cmpxchg kernel provided routine.
...
The instruction was encoded as a load instead of the intended store.
2009-07-29 00:18:26 -07:00
Gabe Black
c2da5bae17
ARM: Get rid of a stray line in the set_tls handler.
2009-07-29 00:17:20 -07:00
Gabe Black
1e04b6281d
ARM: Make the ARM native tracer stop M5 if control diverges.
...
If the control flow of M5's executable and statetrace's target process get out
of sync even a little, there will be a LOT of output, very little of which
will be useful. There's also almost no hope for recovery. In those cases, we
might as well give up and not generate a huge, mostly worthless trace file.
2009-07-29 00:17:11 -07:00
Gabe Black
2871a13ab3
Simple CPU: Make the simple CPU handle the IntRegs trace flag.
2009-07-29 00:15:26 -07:00
Gabe Black
873112ea99
ARM: Make sure the target process doesn't run away from statetrace.
2009-07-29 00:14:43 -07:00
Ali Saidi
0a9eb59e6f
ARM: Ignore the "times" system call.
2009-07-29 00:09:46 -07:00
Ali Saidi
19a4fb0ff3
ARM: Fix an ioctl constant.
2009-07-29 00:09:44 -07:00
Derek Hower
469256d823
ruby: removed unused/incorrect profiler state
2009-07-27 21:43:43 -05:00
Ali Saidi
daf8718da9
ARM: Update some syscall constants and delete others that are Alpha only.
2009-07-27 00:54:55 -07:00
Gabe Black
d3f2992e39
ARM: Decode fstmx and fldmx instructions. We can ignore them for now.
2009-07-27 00:54:50 -07:00
Gabe Black
52b4a7c36f
ARM: Only send information that changed between statetrace and M5.
2009-07-27 00:54:30 -07:00
Gabe Black
90d3d3535b
imported patch nativetracestreamline.patch
2009-07-27 00:54:24 -07:00
Gabe Black
8ec235c7b1
ARM: Make native trace print out what instruction caused an error.
2009-07-27 00:54:09 -07:00
Gabe Black
c18d6cb1a7
ARM: Implement a basic version of the fmxr instruction.
2009-07-27 00:53:29 -07:00
Gabe Black
2828fa459d
ARM: Implement a basic version of the fmrx instruction.
2009-07-27 00:53:24 -07:00
Gabe Black
4079792f2b
ARM: Add in spots for the VFP control registers.
2009-07-27 00:53:10 -07:00
Gabe Black
b560acfe17
ARM: Fix the CLZ instruction.
2009-07-27 00:52:59 -07:00
Gabe Black
dc0df3f396
ARM: Initialize the CPSR so that we're in user mode.
2009-07-27 00:52:48 -07:00
Gabe Black
b8bf34be05
ARM: Set up the initial stack frame to match a recent Linux.
2009-07-27 00:52:31 -07:00
Gabe Black
ebc2897673
Elf: Add in some new aux vector type constants.
2009-07-27 00:52:19 -07:00
Gabe Black
a41e132007
ARM: Make native trace only print when registers are changing value.
...
When registers have incorrect values but aren't actively changing, it's likely
they're not being modified at all. The fact that they're still wrong isn't
very important.
2009-07-27 00:52:01 -07:00
Gabe Black
519ace4dfd
ARM: Add a native tracer.
...
--HG--
rename : src/arch/sparc/SparcNativeTrace.py => src/arch/arm/ArmNativeTrace.py
rename : src/arch/sparc/nativetrace.cc => src/arch/arm/nativetrace.cc
rename : src/arch/sparc/nativetrace.hh => src/arch/arm/nativetrace.hh
2009-07-27 00:51:35 -07:00
Ali Saidi
e7640227ca
ARM: Fix fstat/fstat64 structs to match EABI definitions.
2009-07-27 00:51:20 -07:00
Ali Saidi
99831ed938
ARM: Handle register indexed system calls.
2009-07-27 00:51:01 -07:00
Ali Saidi
0a18bc0d6c
ARM: Detect OABI binaries and complain that they're no-longer supported.
2009-07-27 00:50:55 -07:00
Gabe Black
ef4e8b04a6
SPARC: Fix a minor compile bug in native trace on gcc > 4.1.
2009-07-25 15:14:00 -07:00
Korey Sewell
44f80e7ca5
o3-smt: enforce numThreads parameter for SMT SE mode
2009-07-25 00:50:27 -04:00
Polina Dudnik
e7a3bda497
Fixed the licences plus minor fixes for compilation
2009-07-22 20:28:32 -05:00
Gabe Black
9ba2ed8532
MIPS: Small fix I forgot to qrefresh into my last change.
2009-07-22 01:57:55 -07:00
Gabe Black
7f0c07bf03
MIPS: Style/formatting sweep of the decoder itself.
2009-07-22 01:51:10 -07:00
Gabe Black
c874bfae3f
MIPS: Format the register index constants like the other ISAs.
...
Also a few more style fixes.
2009-07-21 23:38:26 -07:00
Derek Hower
c635d04642
Automated merge with ssh://m5sim.org//repo/m5
2009-07-21 21:27:54 -05:00
Derek Hower
7f34ee36ec
ruby: fixed sequencer RMW data bug
2009-07-21 19:42:09 -05:00
Derek Hower
80544cda8a
ruby: libruby_init now takes parsed Ruby-lang config text
...
libruby_init now expects to get a file that contains the output of
running a ruby-lang configuration, opposed to the ruby-lang
configuration itself.
2009-07-21 18:33:05 -05:00
Gabe Black
74584d79b6
MIPS: Get MIPS_FS to compile, more style fixes.
...
Some breakage was from my BitUnion change, some was much older.
2009-07-21 01:09:05 -07:00
Gabe Black
7548082d3b
MIPS: Many style fixes.
...
White space, commented out code, some other minor fixes.
2009-07-21 01:08:53 -07:00
Gabe Black
dc0a017ed0
isa_parser: Get rid of the now unused ControlBitfieldOperand.
2009-07-20 20:20:17 -07:00
Gabe Black
5161bc19d9
MIPS: Use BitUnions instead of bits() functions and constants.
...
Also fix style issues in regions around these changes.
2009-07-20 20:14:15 -07:00
Derek Hower
225de2eaff
merge
2009-07-20 09:41:28 -05:00
Derek Hower
e59d0e3e89
ruby: moved cache stats from Profiler to CacheMemory
...
Caches are now responsible for their own statistic gathering. This
requires a direct callback from the protocol on misses, and so all
future protocols need to take this into account.
2009-07-20 09:40:43 -05:00
Gabe Black
3e8e813218
CPU: Separate out native trace into ISA (in)dependent code and SimObjects.
...
--HG--
rename : src/cpu/nativetrace.cc => src/arch/sparc/nativetrace.cc
rename : src/cpu/nativetrace.hh => src/arch/sparc/nativetrace.hh
rename : src/cpu/NativeTrace.py => src/arch/x86/X86NativeTrace.py
2009-07-19 23:54:56 -07:00
Gabe Black
a3a795769a
Tracing: Add accessors so tracers can get at data in trace records.
2009-07-19 23:54:31 -07:00
Gabe Black
f0cb698a87
X86: Move a displaced comment back to where it goes.
2009-07-19 23:51:47 -07:00
Gabe Black
563654275f
X86: Add some misc registers for FP control state.
2009-07-19 23:51:41 -07:00
Derek Hower
308419b947
scons: removed RubyConfig from scons
2009-07-19 12:34:11 -05:00
Derek Hower
7cd2d8f687
ruby: removed all refs to old RubyConfig
2009-07-18 18:20:03 -05:00
Derek Hower
4bd7fe4c53
ruby: removed dead files
2009-07-18 18:18:37 -05:00
Derek Hower
f3d8d29342
ruby: removed dead files
2009-07-18 18:17:48 -05:00
Derek Hower
926ab6e6db
merge
2009-07-18 17:40:20 -05:00
Derek Hower
4b7ea4cb51
ruby: fixed dma sequencer bug
...
The DMASequencer was still using a parameter from the old RubyConfig,
causing an offset error when the requested data wasn't block aligned.
This changeset also includes a fix to MI_example for a similar bug.
2009-07-18 17:03:51 -05:00
Derek Hower
340845b139
ruby: better debug print for DataBlock
2009-07-18 16:58:33 -05:00
Derek Hower
7433029cd5
slicc: made coherence profilers per-controller
2009-07-18 16:54:45 -05:00
Gabe Black
d85cd08113
X86: Set up a named constant for the "fold bit" for int register indices.
2009-07-17 18:49:22 -07:00
Gabe Black
7b6587fc9c
X86: Tame the wilds of def operands.
2009-07-17 00:29:56 -07:00
Gabe Black
df378285f8
X86: Shift some register flattening work into the decoder.
2009-07-17 00:29:42 -07:00
Polina Dudnik
e557b4beb5
merge
2009-07-16 15:40:48 -05:00
Gabe Black
e9eccf7225
X86: Add range checks for miscreg indexing utility functions.
2009-07-16 09:30:14 -07:00
Gabe Black
ba6b8389ee
X86: Take limitted advantage of the compilers type checking for microop operands.
2009-07-16 09:29:29 -07:00
Gabe Black
80c834ccac
X86: Fix a number of places where the wrong form of a microop was used.
2009-07-16 09:27:56 -07:00
Gabe Black
3f9b0cc5ca
X86: Fix x87 stack register indexing.
2009-07-16 09:26:38 -07:00
Polina Dudnik
23a405f5d8
Tester update
2009-07-15 10:46:22 -05:00
Gabe Black
6262b31515
Merge with head.
2009-07-14 18:06:30 -07:00
Jack Whitham
fce4412d76
ARM: Fix the "open" flag constants.
2009-07-14 21:03:33 -07:00
Polina Dudnik
289cd00326
Changed the state machine to generate code such that multiple processors can make atomic requests at once
2009-07-13 18:39:32 -05:00
Polina Dudnik
5f551d9ca2
1. Got rid of unused functions in DirectoryMemory
...
2. Reintroduced RMW_Read and RMW_Write
3. Defined -2 in the Sequencer as well as made a note about mandatory queue
Did not address the issues in the slicc because remaking the atomics altogether to allow
multiple processors to issue atomic requests at once
2009-07-13 17:22:29 -05:00
Derek Hower
100da6b326
merge
2009-07-13 14:49:51 -05:00
Derek Hower
d51445490d
regression: updated memtest-ruby stats
...
This also includes a change to the default Ruby random seed, which was
previously set using the wall clock. It is now set to 1234 so that
the stat files don't change for the regression tester.
2009-07-13 14:45:15 -05:00
Polina Dudnik
9a675a0391
Changes to add tracing and replaying command-line options
...
Trace is automatically ended upon a manual checkpoint
2009-07-13 12:50:10 -05:00
Polina Dudnik
b28058917c
Locked requests should actually be converted to ST rather than ATOMIC, because ATOMIC is for RMW.
2009-07-13 12:11:17 -05:00
Polina Dudnik
7a6bf67e47
Added atomics implementation which would work for MI_example
2009-07-13 12:06:23 -05:00
Polina Dudnik
c66af9f474
Minor fixes for compiling
2009-07-13 11:59:13 -05:00
Polina Dudnik
7606c71ea5
Replaced RMW with Locked. RMW will be used for the coherence-aided atomics other than LLSC
2009-07-13 11:37:56 -05:00
Polina Dudnik
faf823f947
Moved the lock check and clearing the lock into makeRequest
2009-07-13 11:34:38 -05:00
Polina Dudnik
86ce60e5cd
Forgot to replace one of the RubyRequest_RMW
2009-07-13 11:25:23 -05:00
Polina Dudnik
226981b2a6
Reintegrated Derek's functional implementation of atomics with a minor change: don't clear lock on failure
2009-07-13 11:13:29 -05:00
Gabe Black
60577eb4ca
ISAs: Get rid of the IControl operand type.
...
A separate operand type is not necessary to use two bitfields to generate the
index.
2009-07-10 01:21:04 -07:00
Gabe Black
64fe7af51a
SPARC: Set up a lookup table for integer register flattening.
...
Using a look up table changed the run time of the SPARC_FS solaris boot
regression from:
real 14m45.951s
user 13m57.528s
sys 0m3.452s
to:
real 12m19.777s
user 12m2.685s
sys 0m2.420s
2009-07-10 01:01:47 -07:00
Gabe Black
9993ca8280
X86: Fold the MiscRegFile all the way into the ISA object.
2009-07-09 20:29:02 -07:00
Gabe Black
60d47aa5f9
SPARC: Fold the MiscRegFile all the way into the ISA object.
2009-07-09 20:28:50 -07:00
Gabe Black
de7f462219
MIPS: Fold the MiscRegFile all the way into the ISA object.
2009-07-09 20:28:39 -07:00
Gabe Black
e14c408b62
ARM: Fold the MiscRegFile all the way into the ISA object.
2009-07-09 20:28:27 -07:00
Gabe Black
5643a222e3
Alpha: Missed a file in an earlier changeset.
2009-07-09 00:20:41 -07:00
Gabe Black
c9a27d85b9
Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions.
2009-07-08 23:02:22 -07:00
Gabe Black
3d39b62132
Alpha: Pull the MiscRegFile fully into the ISA object.
2009-07-08 23:02:22 -07:00
Gabe Black
b398b8ff1b
Registers: Add a registers.hh file as an ISA switched header.
...
This file is for register indices, Num* constants, and register types.
copyRegs and copyMiscRegs were moved to utility.hh and utility.cc.
--HG--
rename : src/arch/alpha/regfile.hh => src/arch/alpha/registers.hh
rename : src/arch/arm/regfile.hh => src/arch/arm/registers.hh
rename : src/arch/mips/regfile.hh => src/arch/mips/registers.hh
rename : src/arch/sparc/regfile.hh => src/arch/sparc/registers.hh
rename : src/arch/x86/regfile.hh => src/arch/x86/registers.hh
2009-07-08 23:02:21 -07:00
Gabe Black
997f36c711
Registers: Collapse ARM and MIPS regfile directories.
...
--HG--
rename : src/arch/arm/regfile/misc_regfile.hh => src/arch/arm/misc_regfile.hh
rename : src/arch/arm/regfile/regfile.cc => src/arch/arm/regfile.cc
rename : src/arch/mips/regfile/misc_regfile.cc => src/arch/mips/misc_regfile.cc
rename : src/arch/mips/regfile/misc_regfile.hh => src/arch/mips/misc_regfile.hh
2009-07-08 23:02:21 -07:00
Gabe Black
aa031e1c11
Alpha: Move reg_redir into its own files, and move some constants into regfile.hh.
2009-07-08 23:02:21 -07:00
Gabe Black
5c37d10624
Registers: Eliminate the ISA defined RegFile class.
2009-07-08 23:02:21 -07:00
Gabe Black
9bf22992ee
Alpha: Get rid of function prototypes with no implementations.
2009-07-08 23:02:21 -07:00
Gabe Black
43345bff6c
Registers: Move the PCs out of the ISAs and into the CPUs.
2009-07-08 23:02:21 -07:00
Gabe Black
1b29f1621d
ARM, Simple CPU: Fix an index and add assert checks.
2009-07-08 23:02:21 -07:00
Gabe Black
0338c83c9d
MIPS: Get rid of an orphaned MIPS .cc file.
2009-07-08 23:02:21 -07:00
Gabe Black
6ebce9d65a
Alpha: Phase out Alpha's intregfile.hh and intregfile.cc.
2009-07-08 23:02:21 -07:00
Gabe Black
faa6ebebe1
SPARC: Phase out SPARC's intregfile.hh.
2009-07-08 23:02:20 -07:00
Gabe Black
ecde884404
X86: Phase out x86's intregfile.hh.
2009-07-08 23:02:20 -07:00
Gabe Black
301df68c73
MIPS: Phase out MIPS's int_regfile.hh.
2009-07-08 23:02:20 -07:00
Gabe Black
27b6148f47
ARM: Flush out the ARM's int_regfile.hh.
2009-07-08 23:02:20 -07:00
Gabe Black
a480ba00b9
Registers: Eliminate the ISA defined integer register file.
2009-07-08 23:02:20 -07:00
Gabe Black
0cb180ea0d
Registers: Eliminate the ISA defined floating point register file.
2009-07-08 23:02:20 -07:00
Gabe Black
25884a8773
Registers: Get rid of the float register width parameter.
2009-07-08 23:02:20 -07:00
Gabe Black
32daf6fc3f
Registers: Add an ISA object which replaces the MiscRegFile.
...
This object encapsulates (or will eventually) the identity and characteristics
of the ISA in the CPU.
2009-07-08 23:02:20 -07:00
Gabe Black
3e2cad8370
ARM: Use custom read/write code to alias R15 with the PC.
2009-07-08 23:02:20 -07:00
Gabe Black
b8b7c7314a
ISA parser: Allow alternative read/write code for operands.
2009-07-08 23:02:19 -07:00
Gabe Black
95392d3fb8
ARM: Move the remaining microops out of the decoder and into the ISA desc.
2009-07-08 23:02:19 -07:00
Gabe Black
1d4f338b39
ARM: Move the memory microops out of the decoder and into the ISA desc.
2009-07-08 23:02:19 -07:00
Gabe Black
70a75ceb84
ARM: Move the integer microops out of the decoder and into the ISA desc.
2009-07-08 23:02:19 -07:00
Gabe Black
4eb18cc07a
ARM: Improve memory instruction disassembly.
2009-07-08 23:02:19 -07:00
Gabe Black
2fb8d481ab
ARM: Tune up predicated instruction decoding.
2009-07-08 23:02:19 -07:00
Gabe Black
ddcf084f16
ARM: Get rid of the MemAcc and EAComp static insts.
2009-07-08 23:02:19 -07:00
Gabe Black
cae870eded
ARM: Get rid of end_addr in the ArmMacroStore constructor.
2009-07-08 23:02:19 -07:00
Gabe Black
311f77f33d
ARM: Add an AddrMode2 format for memory instructions that use address mode 2.
2009-07-08 23:02:19 -07:00
Gabe Black
826a3582ea
ARM: Don't always update CPSR.
2009-07-08 23:02:19 -07:00
Gabe Black
17f0943398
ARM: Add an AddrMode3 format for memory instructions that use address mode 3.
2009-07-08 23:02:19 -07:00
Gabe Black
dac0cb5c7e
ARM: Add load/store double instructions.
2009-07-08 23:02:10 -07:00
Gabe Black
1ca0688c4c
ARM: Add operands for the load/store double instructions.
2009-07-08 23:02:01 -07:00
Gabe Black
d029110fa1
X86: Fix a bug in IRET_PROT's microcode. The immediate form of sra was intended.
2009-07-08 23:01:54 -07:00
Derek Hower
15afc87f7c
slicc: fixed MI_example bug. The directory wasn't deallocating the TBE, leading to a leak. Also increased the default max TBE size to 256 to allow memtest to pass the regression.
2009-07-08 08:40:32 -05:00
Derek Hower
6a83bd5a03
ruby: set the default values of the debug object so that nothing is printed
2009-07-08 00:34:40 -05:00
Derek Hower
2f9d8bff5b
slicc: Fixed MI_example bug. The directory was not writing data to DRAM after a PUTX.
2009-07-08 00:31:33 -05:00
Derek Hower
96c36afea9
removed stray debug print
2009-07-07 23:01:35 -05:00
Nathan Binkert
7ffb8e5914
automerge
2009-07-06 15:54:18 -07:00
Nathan Binkert
da704f52e5
ruby: Fix RubyMemory to work with the newer ruby.
2009-07-06 15:49:47 -07:00
Nathan Binkert
a7904e2cf3
ruby: apply some fixes that were overwritten by the recent ruby import.
2009-07-06 15:49:47 -07:00
Nathan Binkert
5b080ae046
slicc: update parser.py for changes in slicc language.
2009-07-06 15:49:47 -07:00
Nathan Binkert
1f6933503d
scons: update SCons files for changes in ruby.
2009-07-06 15:49:47 -07:00
Nathan Binkert
92de70b69a
ruby: Import the latest ruby changes from gems.
...
This was done with an automated process, so there could be things that were
done in this tree in the past that didn't make it. One known regression
is that atomic memory operations do not seem to work properly anymore.
2009-07-06 15:49:47 -07:00
Nathan Binkert
05f6a4a6b9
ruby: replace strings that were missed in original ruby import.
2009-07-06 15:49:47 -07:00
Gabe Black
240e214236
SPARC: Fix the parenthesis in inUserMode.
2009-07-05 16:07:09 -07:00