Commit graph

994 commits

Author SHA1 Message Date
Gabe Black
da24915181 Moved the idle event out of system_events.hh. The skipFuncEvent can be made ISA independent by making it use the #define for branch delay slots (and NNPC)
--HG--
extra : convert_revision : b2631b1163397ecc99f2f315e2b88537e2002731
2006-11-07 05:38:33 -05:00
Gabe Black
4bfb8547bb Moved the switched version of kernel_stats.hh back to kern, and moved the base kernel_stats to base_kernel_stats
--HG--
extra : convert_revision : 2a010d2eb7ea2586ff063b99b8bcde6eb1e8e017
2006-11-07 05:36:54 -05:00
Gabe Black
5424156516 Missed this file in my last changeset.
--HG--
extra : convert_revision : 94affbcfb5e5fd948010b10d481627a4dd500267
2006-11-07 05:34:14 -05:00
Gabe Black
eb4ef3ad76 Made kern a switching header file directory.
SConstruct:
    Put the code to make a switching header directory into a function so they are easy to make.
src/arch/SConscript:
    Replace switching header code with the new function call.
src/kern/SConscript:
    Created a new switching header directory in kern, and moved the declaration of some source files here.

--HG--
rename : src/kern/kernel_stats.cc => src/kern/base_kernel_stats.cc
rename : src/kern/kernel_stats.hh => src/kern/base_kernel_stats.hh
extra : convert_revision : 98f5320a5ade567c3e4f67fef123dfb0c5122545
2006-11-07 05:33:21 -05:00
Gabe Black
58f7ed2416 Cleaned up remnants of ivlb and ivle
--HG--
extra : convert_revision : 93b37dbcd3d9dd1eced0f829223f52b53fe58643
2006-11-06 20:49:48 -05:00
Gabe Black
f61cd02e13 Got rid of the ivlb and ivle kernel stats.
--HG--
extra : convert_revision : d85627bb3eafe6411355995a92ba8b151be8320d
2006-11-06 20:07:44 -05:00
Gabe Black
b156767f1e Get rid of pcifake.cc and tsunami_fake.cc to go with the merged default devices.
--HG--
extra : convert_revision : e88aaaa43843c1283f29cef0886e057412705899
2006-11-06 19:56:57 -05:00
Gabe Black
32a927b85f Only bother with the device SConscript if you're in FULL_SYSTEM
--HG--
extra : convert_revision : ac52f548afb98dd0437e7d7c2600ff9b8ebfd1fa
2006-11-06 19:55:42 -05:00
Gabe Black
02abca6b9e Merge zizzer.eecs.umich.edu:/bk/newmem/
into  zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops

src/SConscript:
    SCCS merged

--HG--
extra : convert_revision : f130c8a2d33f58d857e5d5a02bb9698c1bceb23b
2006-11-06 19:52:32 -05:00
Gabe Black
dd14c86ec8 Moved the tsunami devices into the dev/alpha directory. Other devices "generic" devices are dependent on some of those files. That will either need to change, or most likely those devices will have to be considered architecture dependent.
--HG--
rename : src/dev/tsunami.cc => src/dev/alpha/tsunami.cc
rename : src/dev/tsunami.hh => src/dev/alpha/tsunami.hh
rename : src/dev/tsunami_cchip.cc => src/dev/alpha/tsunami_cchip.cc
rename : src/dev/tsunami_cchip.hh => src/dev/alpha/tsunami_cchip.hh
rename : src/dev/tsunami_io.cc => src/dev/alpha/tsunami_io.cc
rename : src/dev/tsunami_io.hh => src/dev/alpha/tsunami_io.hh
rename : src/dev/tsunami_pchip.cc => src/dev/alpha/tsunami_pchip.cc
rename : src/dev/tsunami_pchip.hh => src/dev/alpha/tsunami_pchip.hh
rename : src/dev/tsunamireg.h => src/dev/alpha/tsunamireg.h
extra : convert_revision : ffbb6fd93341d2623a6932bf096019b8976da694
2006-11-06 19:45:00 -05:00
Gabe Black
5b152b970b Got rid of stray alpha include
--HG--
extra : convert_revision : eddd64dd9291d6656821fe6387aeab2f9ddbaf58
2006-11-06 19:10:13 -05:00
Gabe Black
b04a2653f9 Got rid of obsolete ivlb and ivle psuedo instructions.
--HG--
extra : convert_revision : c3c2dd5a6e7181ad94194146d7fa2b33b21074fb
2006-11-06 19:09:23 -05:00
Gabe Black
ef1a92eb9b Stub for SPARC interrupt handling object.
--HG--
extra : convert_revision : 7257e3387c01e84e5a1018a9cdcc09a79edfa934
2006-11-06 18:30:28 -05:00
Gabe Black
85a6079db7 Remote GDB support has been changed to use inheritance. Alpha should work, but isn't tested. Other architectures will not.
--HG--
extra : convert_revision : fc7e1e73e2f3b1a4ab9905a1eb98c5f07c6c8707
2006-11-06 18:29:58 -05:00
Gabe Black
e39de58d21 Took the Alpha prefix off of AlphaArguments, and made sure it was being used from TheISA:: rather than AlphaISA::
--HG--
extra : convert_revision : 17c143d3cbc2f58a7a9d01366a8f649810ff7f33
2006-11-06 18:28:10 -05:00
Gabe Black
1ffff78ca9 Created seperate SConscript for the dev directory. Made subdirectories for Alpha and SPARC and put SConscripts in them.
--HG--
rename : src/base/kgdb.h => src/arch/alpha/kgdb.h
rename : src/dev/alpha_access.h => src/dev/alpha/access.h
rename : src/dev/alpha_console.cc => src/dev/alpha/console.cc
rename : src/dev/alpha_console.hh => src/dev/alpha/console.hh
extra : convert_revision : a7dd466308cb83edc40528689aacb72413089cdf
2006-11-06 18:26:11 -05:00
Ali Saidi
bf3223d7ce delete pcifake, tsunamifake. Combine BadAddr/IsaFake into one
src/SConscript:
    remove pcifake and tsunami fake from sconscript
src/dev/isa_fake.cc:
src/dev/isa_fake.hh:
    combine badaddr and isa fake into one
src/python/m5/objects/Pci.py:
    remove pcifake
src/python/m5/objects/Tsunami.py:
    make badaddr derive from isafake

--HG--
extra : convert_revision : 91470db60aa1de6b85827304e27bd3414cc9d8d1
2006-11-06 16:24:25 -05:00
Kevin Lim
652281a61c Clean up clock phase drift code a bit.
src/cpu/base.cc:
    Move clock phase drift code to the base CPU so that any CPU model can use it.
src/cpu/base.hh:
    Added two functions to help get the next cycle the CPU should be scheduled.
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
    Use the function now in BaseCPU.

--HG--
extra : convert_revision : 444494b66ffc85fc473c23f57683c5f9458ad80c
2006-11-06 13:27:45 -05:00
Kevin Lim
067c9c5531 Initialize pointer to NULL.
src/cpu/o3/lsq_unit_impl.hh:
    Be sure to initialize pointer to NULL.

--HG--
extra : convert_revision : 917d5119e4bd8eae10959ed07069d8c694315c7a
2006-11-05 20:29:38 -05:00
Ali Saidi
de90ae4825 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : d7133e32cfca9f15869ee9ab7a93e3470e7d9038
2006-11-04 21:41:10 -05:00
Ali Saidi
21cf4a46b9 fixes so that M5 will compile under solaris
SConstruct:
    Add check to see if we need to include libsocket
src/arch/sparc/floatregfile.cc:
src/arch/sparc/intregfile.cc:
    use memset rather than bzero and include the appropriate headerfile
src/base/pollevent.cc:
    If we're compling under solaris we need sys/file.h
src/base/random.cc:
src/base/random.hh:
    solaris doesn't have random(), so use rint with the correct rounding mode
    if we're compiling on solaris
src/base/stats/flags.hh:
    u_int32_t??
src/base/time.hh:
    grab the timersub() define from freebsd since it doesn't exist in solaris
src/cpu/inst_seq.hh:
    we don't need to include stdint here
src/sim/byteswap.hh:
    the method to detect endianness on Solaris is a little more complex...

--HG--
extra : convert_revision : 6b7db0e900e7bccfc250d65c125065f27280dda1
2006-11-04 21:41:01 -05:00
Gabe Black
601822c6b5 Make things compile in SE again.
--HG--
extra : convert_revision : cf7faf5001b31d61c61ddce2386d61c919075800
2006-11-03 14:42:12 -05:00
Gabe Black
8778d85b2d Use a PowerOnReset to initialize the cpu.
--HG--
extra : convert_revision : 9e65af095c37c7c67db377424d2d4363fa8065f9
2006-11-03 14:41:27 -05:00
Gabe Black
6ad386f1a8 Calling syscalls from within the trap instruction's invoke method won't work because apparently you need an xc for that and not a tc. Cleaned up the TrapInstruction fault in light of this.
--HG--
extra : convert_revision : 1805c9244cfd62d0ee7862d8fd7c9983e00c5747
2006-11-03 14:40:35 -05:00
Gabe Black
4a5cb3f425 The tc needs to be protected instead of private so that the CpuEventWrapper can access it.
--HG--
extra : convert_revision : bd836d63ac3630b20dda552e7b289730f3c114ef
2006-11-03 11:05:56 -05:00
Gabe Black
29a79acb7c Gutted out the old Alpha stuff.
--HG--
extra : convert_revision : 6767dc1305a58e3e7eb0ee909d54768e51744927
2006-11-03 11:05:13 -05:00
Gabe Black
3f4b098985 Added a stub initCPU function. This would be a good place to force in a PowerOnReset fault to kick start the CPU.
--HG--
extra : convert_revision : 79e1fa2ef40e326682069639e260db255fd29d93
2006-11-03 11:04:10 -05:00
Gabe Black
6b701a6d25 Compilation fixes.
--HG--
extra : convert_revision : 44d67a3bb95f875f17586499aa4a04268aa2fd46
2006-11-03 11:03:03 -05:00
Gabe Black
ab651344dd Add the syscall number as the second parameter for the trap fault. This could be improved and syscalls could be called from the trap's invoke method.
--HG--
extra : convert_revision : 127a3673a076110fb3605c0fbc93e8d7e9fec84b
2006-11-03 10:56:47 -05:00
Gabe Black
e6fed44625 Add an invoke function for PowerOnReset
--HG--
extra : convert_revision : a1cdd35c74f6e85f42a04061b466ec7617da8ac2
2006-11-03 10:55:29 -05:00
Gabe Black
694323b7c4 Move around misc reg code
src/arch/sparc/faults.cc:
    Moved some code here from miscregfile.cc
src/arch/sparc/miscregfile.cc:
    Moved code from here to faults.cc, and merged (read|set)MiscRegWithEffect and it's FS version from ua2005.cc
src/arch/sparc/miscregfile.hh:
    readFSRegWithEffect is no longer a seperate function, and is instead done in the main readRegWith Effect.

--HG--
extra : convert_revision : 0b45f0f78e83929b32ddd2f443c8b1dbf9bc04fb
2006-11-03 10:54:34 -05:00
Gabe Black
7c5a859243 removed ua2005.cc since it's been obsorbed into the miscregfile, and added system.cc
--HG--
extra : convert_revision : 2a124adcefe0d15860632a05e8788d3fd34008c2
2006-11-03 10:52:08 -05:00
Gabe Black
118b9dc1f9 Got rid of "inPalMode". Some places are still effectively checking if they are in PAL mode, however.
--HG--
extra : convert_revision : b52d9642efc474eaf97437fa2df879efefa0062b
2006-11-03 04:25:33 -05:00
Gabe Black
c8fc116c76 Add a new file which describes an ISA's interrupt handling mechanism. It records when interrupts are requested, and returns an interrupt to execute if the
--HG--
extra : convert_revision : c535000a6a170caefd441687b60f940513d29739
2006-11-03 02:25:39 -05:00
Gabe Black
fa91832900 Fixed a comment
--HG--
extra : convert_revision : bebc701508e1d38ee74a07377c634d5e46e89abe
2006-11-03 01:15:31 -05:00
Kevin Lim
e71ccde663 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix

--HG--
extra : convert_revision : a9a41e2c292bd95aa148e1cf4d9a77c0622a462b
2006-11-02 15:20:47 -05:00
Kevin Lim
45363ea658 Have bus use the BadAddress device to handle bad addresses. The O3 CPU should be able to boot into Linux with caches on after this change.
src/mem/bus.cc:
src/mem/bus.hh:
    Bus now will be setup with a default responder, unless the user overrides it.  This default responder should return BadAddress if no matching port is found.
src/python/m5/objects/Bus.py:
    Bus now has a default responder for FS mode if the user doesn't override it.  It returns BadAddress if no matching port is found.
src/python/m5/objects/Tsunami.py:
    Add bad address device.  Also record when the user has specified their own default responder.

--HG--
extra : convert_revision : 59070477ae313ee711b2d59baa2369c9a91c5b85
2006-11-02 15:20:37 -05:00
Kevin Lim
c3485a6548 Implement device that will return BadAddress.
--HG--
extra : convert_revision : d833c20f691e01c84a0678f19f7d83f3ee50c0c1
2006-11-02 15:18:35 -05:00
Kevin Lim
8d53f298a6 Caches return a new functional port whenever asked for one.
src/mem/cache/base_cache.cc:
    Have caches return a new functional port whenever asked for them.  I'm pretty sure this is desired behavior.  Ron can correct me if it's not.

--HG--
extra : convert_revision : e1fadf895a7d714968128ff900d10e86fde53387
2006-11-02 15:17:45 -05:00
Kevin Lim
dd5e2cd959 More proper handling of the ports.
src/cpu/simple_thread.cc:
    Fix up port handling to share code.
src/cpu/thread_state.cc:
    Separate code off into a function.
src/cpu/thread_state.hh:
    Make a separate function that will get the CPU's memory's functional port.

--HG--
extra : convert_revision : 96a9bb3c5e4b9ba5511678c0fd17f0017c8cd312
2006-11-02 14:58:31 -05:00
Kevin Lim
64f8cd12c6 Remove function that should have been deleted.
src/cpu/simple_thread.cc:
    This function should have been deleted from an earlier push.
src/cpu/simple_thread.hh:
    Delete this function; it's now in thread_state.hh/.cc.

--HG--
extra : convert_revision : f78dcf9c2b388418030d48d0ea4911c8b8b1f5ff
2006-11-02 13:12:36 -05:00
Kevin Lim
ccaf80cc46 Use ISA specific makeExtMI.
src/arch/alpha/utility.hh:
    For now makeExtMI will be specific to the ISA.

--HG--
extra : convert_revision : 89959c6499efcc3df9301ad8ea039580764a1496
2006-11-02 13:11:38 -05:00
Gabe Black
b565660c42 Merge zizzer.eecs.umich.edu:/bk/newmem/
into  zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops

--HG--
extra : convert_revision : c2f7398a0d14dd11108579bb243ada7420285a22
2006-11-01 19:00:59 -05:00
Gabe Black
8dbab9f701 Added code to handle draining.
--HG--
extra : convert_revision : 3861f553bde5865cd21a8a58a4c410896726f0a3
2006-11-01 19:00:49 -05:00
Gabe Black
6f78d49410 Fix a range check on the ipr_index.
--HG--
extra : convert_revision : 84e25abd4bb2de0c877c883804d39feb019c7030
2006-11-01 18:46:18 -05:00
Gabe Black
2b11b47357 Adjustments for the AlphaTLB changing to AlphaISA::TLB and changing register file functions to not take faults
--HG--
extra : convert_revision : 1cef0734462ee2e4db12482462c2ab3c134d3675
2006-11-01 16:44:45 -05:00
Gabe Black
f3ba6d20f6 Arg!
--HG--
extra : convert_revision : 8328d002780c0291e7eb264076a62084de88b7a5
2006-10-31 18:59:50 -05:00
Gabe Black
1543c3d0a1 More typos! I need to get nfs to work.
--HG--
extra : convert_revision : f5693e96d376254f777fb0cce7b5be3d36efbea9
2006-10-31 18:51:26 -05:00
Gabe Black
1dd903e856 Fix another typo
--HG--
extra : convert_revision : ad7058babf2a13bfe543e05f2662dc49a18a8b8b
2006-10-31 18:39:17 -05:00
Gabe Black
39de635fbf Check for out of range IPR values as well.
--HG--
extra : convert_revision : 9ca241bb71d8a1d022e54485383a88d2abece663
2006-10-31 18:19:45 -05:00
Gabe Black
45368c0300 Fix stupid typo
--HG--
extra : convert_revision : fbfc82974e89b2c726b689674c9f5d957682b280
2006-10-31 18:01:31 -05:00
Gabe Black
fb5ba85abb Make two simple utility functions to determine if a MiscReg index corresponding to an IPR is readable or writable.
--HG--
extra : convert_revision : 89eebba5eec01e629213997d24c734a6acad0ecb
2006-10-31 17:50:57 -05:00
Gabe Black
ad201172c9 We don't include ipr.cc in SE builds, so don't call it.
--HG--
extra : convert_revision : 45e52d7afbf74e0ddde11f58aeb084186389fc06
2006-10-31 16:59:41 -05:00
Gabe Black
ace4f0c188 Made the old name refer to the miscreg index to prevent having to change code all over the place.
--HG--
extra : convert_revision : e890a3ce420336acdb220396dcbf66d4b9974c76
2006-10-31 16:36:45 -05:00
Gabe Black
44f2c05118 Forgot to change the index.
--HG--
extra : convert_revision : 5a444e635d20bcca445a10e43592b6c10d25e879
2006-10-31 16:18:54 -05:00
Gabe Black
ece796ab8a Make the IPRs use regular miscreg indexes, and make a table or two to find the miscreg index of a specific IPR.
--HG--
extra : convert_revision : dd235261e7086d6667b1b2bdc4a81b2573e21d53
2006-10-31 16:02:28 -05:00
Kevin Lim
2fa535f740 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem

--HG--
extra : convert_revision : 88fa7ae5cc32be068787ee381fae9d8de0e9bd0f
2006-10-31 14:44:23 -05:00
Kevin Lim
5825a6c9d8 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix

configs/example/fs.py:
configs/example/se.py:
src/mem/tport.hh:
    Hand merge.

--HG--
extra : convert_revision : b9df95534d43b3b311f24ae24717371d03d615bf
2006-10-31 14:37:19 -05:00
Kevin Lim
bfd5eb2b08 Remove mem parameter. Now the translating port asks the CPU's dcache's peer for its MemObject instead of having to have a paramter for the MemObject.
configs/example/fs.py:
configs/example/se.py:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
src/cpu/thread_state.cc:
src/cpu/thread_state.hh:
tests/configs/o3-timing-mp.py:
tests/configs/o3-timing.py:
tests/configs/simple-atomic-mp.py:
tests/configs/simple-atomic.py:
tests/configs/simple-timing-mp.py:
tests/configs/simple-timing.py:
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
    No need for mem parameter any more.
src/cpu/checker/cpu.cc:
    Use new constructor for simple thread (no more MemObject parameter).
src/cpu/checker/cpu.hh:
    Remove MemObject parameter.
src/cpu/memtest/memtest.hh:
    Ports now take in their MemObject owner.
src/cpu/o3/alpha/cpu_builder.cc:
    Remove mem parameter.
src/cpu/o3/alpha/cpu_impl.hh:
    Remove memory parameter and clean up handling of TranslatingPort.
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/mips/cpu_builder.cc:
src/cpu/o3/mips/cpu_impl.hh:
src/cpu/o3/params.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_builder.cc:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/simple_params.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/simple/atomic.cc:
    Remove memory parameter.

--HG--
extra : convert_revision : 43cb44a33b31320d44b69679dcf646c0380d07d3
2006-10-31 14:33:56 -05:00
Kevin Lim
b26355daa8 Ports now have a pointer to the MemObject that owns it (can be NULL).
src/cpu/simple/atomic.hh:
    Port now takes in the MemObject that owns it.
src/cpu/simple/timing.hh:
    Port now takes in MemObject that owns it.
src/dev/io_device.cc:
src/mem/bus.hh:
    Ports now take in the MemObject that owns it.
src/mem/cache/base_cache.cc:
    Ports now take in the MemObject that own it.
src/mem/port.hh:
src/mem/tport.hh:
    Ports now optionally take in the MemObject that owns it.

--HG--
extra : convert_revision : 890a72a871795987c2236c65937e06973412d349
2006-10-31 13:59:30 -05:00
Ali Saidi
17141a1be9 remove connectAll() and connect() code since it isn't used anymore. (The python does it all)
--HG--
extra : convert_revision : e16a1ff59d4522703b155c2e68379a3072e8f47f
2006-10-31 13:23:49 -05:00
Ali Saidi
c68f7feaa8 add the ability to insert into the middle of the timing port send list
--HG--
extra : convert_revision : 5422025f74ba7013f98d1d1dcbd1070f580aae61
2006-10-31 13:23:17 -05:00
Gabe Black
3c19c5f0f2 Missed a few instances of this function.
--HG--
extra : convert_revision : 581f97dafc2b30bd5067f6ff7f9cdbabc6890622
2006-10-31 04:12:52 -05:00
Gabe Black
eab445e1bc Get rid of old, commented out code.
--HG--
extra : convert_revision : 46e9f26917efab642b80ea9e4303ec95d43d935e
2006-10-31 03:44:39 -05:00
Gabe Black
038217049a Move IntrFlag into the MiscRegFile and get rid of specialized accessor functions.
--HG--
extra : convert_revision : e0d12a150b01d05de9bc02bcbc7c22797975a5b9
2006-10-31 03:37:01 -05:00
Gabe Black
4862879a94 Put the Alpha tlb stuff into the AlphaISA namespace, and give the classes more neutral names.
--HG--
extra : convert_revision : 702c715b7516a16602172deb1b78d6a7ab848fd4
2006-10-31 02:08:44 -05:00
Gabe Black
628a3b1d01 An attempt to serialize the state of the micro code mechanism in the simple cpu.
src/cpu/simple/base.cc:
    Make a microcoded op start at the current micropc, rather than starting at 0.
src/cpu/thread_state.cc:
    Serialize the microPC and nextMicroPC

--HG--
extra : convert_revision : 5302215f17312ecef3ff4c6548acb05297ee4ff6
2006-10-29 04:04:50 -05:00
Gabe Black
349c7aff9b Move the mem classes into util.isa so that multiple inheritance can be used in the future for micro insts.
--HG--
extra : convert_revision : c71faa5e43b56ed15d00ed5fd57c020d1c845445
2006-10-29 03:40:52 -05:00
Gabe Black
6e66de7c75 Fix when the IsDelayedCommit flag is set.
--HG--
extra : convert_revision : ab6cd69f82b2013d66a91beaa3e39d8f417a9251
2006-10-29 03:26:41 -05:00
Gabe Black
9adba8d98e Bring casa and casxa up to date
src/arch/sparc/isa/decoder.isa:
    Fix up the casa and casxa instructions.
src/arch/sparc/isa/formats/formats.isa:
    This is handled in loadstore.isa now
src/arch/sparc/isa/formats/mem/basicmem.isa:
src/arch/sparc/isa/formats/mem/blockmem.isa:
    Renamed doSplitExecute to doDualSplitExecute. This differentiates between the version that does both a register and immediate version, and one that just does a register version.
src/arch/sparc/isa/formats/mem/mem.isa:
    The cas format is handled in loadstore.isa as well now.
src/arch/sparc/isa/formats/mem/util.isa:
    Reorganized things a bit to better support cas

--HG--
extra : convert_revision : 12411e89e763287e52f9825bf7a417b263c1037f
2006-10-29 02:57:32 -05:00
Gabe Black
ce313a15d5 Fixed ldstub to use the right format, and made the load/store operations use the integer microcode register.
--HG--
extra : convert_revision : 7df5bd4bbe8a2607c7d2b4799826831d6a440926
2006-10-29 01:59:30 -05:00
Gabe Black
6dddca9511 Add an integer microcode register.
--HG--
extra : convert_revision : f23dbfdfe44e8e6cdd6948000669ad4f743b9fb4
2006-10-29 01:58:37 -05:00
Ali Saidi
61c808ae1c Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem.head

--HG--
extra : convert_revision : df73fd850d6638cbce6ff31203857f51235b8763
2006-10-28 13:17:05 -04:00
Ali Saidi
14f53b9b6b remove intel nic from SConscript
--HG--
extra : convert_revision : b01bb258c97cf42d46a94faedab31726623fe437
2006-10-28 13:16:53 -04:00
Gabe Black
ab6b6a9202 This one really needs to be arch/faults.hh
--HG--
extra : convert_revision : aad1ee04ade9f4394c9ef0386f23d6f2ca373412
2006-10-28 04:44:05 -04:00
Gabe Black
7f1463f94a Include the right version of faults.hh
--HG--
extra : convert_revision : 4762b8ab46ac755726cc658a378c2cf5b2061dc3
2006-10-28 04:00:24 -04:00
Gabe Black
477693c519 Merge zizzer.eecs.umich.edu:/bk/newmem
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem

--HG--
extra : convert_revision : 9883fb35fd9c36e1819153f9976f8bdc73dbe8f3
2006-10-28 03:48:23 -04:00
Gabe Black
27ef642a76 One last adjustment to get rid of skew in the simple atomic cpu.
--HG--
extra : convert_revision : 8e46929ed7da5dae6888f773de4e1ecc9b249fe0
2006-10-28 03:44:55 -04:00
Ali Saidi
baaadb0d43 add packet_access.hh
--HG--
extra : convert_revision : 7fe4958549101fca9613baa4a317d96f4970d432
2006-10-27 09:10:50 -04:00
Gabe Black
a46e19f738 A more complete attempt to fix the clock skew.
--HG--
extra : convert_revision : b2d505de51fc5fcae5177b2a13140729474e249e
2006-10-27 07:09:14 -04:00
Gabe Black
d5974eff73 Potential fix to clock skew problem.
--HG--
extra : convert_revision : 51572523190a886fd0ff64817edc88e260c5fa9d
2006-10-27 06:51:28 -04:00
Gabe Black
f985b752d3 Merge zizzer.eecs.umich.edu:/bk/newmem
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem

--HG--
extra : convert_revision : ec35a9276ae21e0b9fe820bd700c020e4440a350
2006-10-27 02:34:26 -04:00
Gabe Black
709d50cd6b Got rid of some outdated comments.
--HG--
extra : convert_revision : 30fa768c4a934cf5f9dc0ad84e0e421327ccbed3
2006-10-27 01:43:51 -04:00
Gabe Black
b1cc98ed54 Made the regfile compatible with the new definitions in MiscRegFile
--HG--
extra : convert_revision : d63ea6fb1e549e737204ee6653c06f89ec5e43ef
2006-10-27 01:43:26 -04:00
Gabe Black
944bfde6b3 Clean up MiscRegFile
--HG--
extra : convert_revision : 3bc792596c99df3a5c2c82da58b801a63ccf6ddb
2006-10-27 01:36:42 -04:00
Gabe Black
2cb190d1e3 Reorganized the MiscRegFile
--HG--
extra : convert_revision : 088112c9b8a4ea09c8015da5a0b65ed2fc9398d2
2006-10-26 22:48:02 -04:00
Gabe Black
f33bab2386 Cleaned up the decoder slightly.
--HG--
extra : convert_revision : a7050aa8768c132f0161f00ba17ae02d71f0b829
2006-10-26 22:47:17 -04:00
Gabe Black
f88b90dd56 Added a few functions to stuff values into bitfields in an instruction.
--HG--
extra : convert_revision : 507d7e13fd6276acf36b75eba31dff5e8080113f
2006-10-26 20:25:22 -04:00
Gabe Black
d1b30102fd Changed the number of register windows to be more realistic.
--HG--
extra : convert_revision : ae557307f377b19bae82226dafa8b4b2654cae52
2006-10-26 20:24:01 -04:00
Gabe Black
5024b20278 Got rid of some debug output
--HG--
extra : convert_revision : 6e98cf839dc92bde5f06f9b9bf11ca6ac661c907
2006-10-26 20:23:00 -04:00
Gabe Black
e441be1b82 Change the default function from setMiscRegWithEffect to setMiscReg
--HG--
extra : convert_revision : bedf422d51a52b009390b1e94f5330f752be2b87
2006-10-26 20:22:23 -04:00
Ali Saidi
d626a32c52 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem.head

--HG--
extra : convert_revision : 473901bcd44bd2c563a3293d7326cd5aed8b630f
2006-10-26 15:49:19 -04:00
Kevin Lim
e912080d12 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem

--HG--
extra : convert_revision : 30a912cf5d3f205a6301d291dd1799da21663056
2006-10-26 14:37:19 -04:00
Ali Saidi
f4be29804f Fix simple timing port keep a list of all packets, have only one event, and scan all packets on a functional access.
--HG--
extra : convert_revision : c735a6408443b5cc90d1c1841c7aeb61e02ec6ae
2006-10-25 18:34:21 -04:00
Gabe Black
93b3176d4e Fixed the priv instruction format.
src/arch/sparc/isa/formats/priv.isa:
    Fix the priv format so that it uses isa_parser operands rather than accessing the registers directly in checkCode. Also, the expressions needed to be negated.
src/arch/sparc/isa/operands.isa:
    Added an Hpstate operand, and adjusted the numbering.

--HG--
extra : convert_revision : 4a70862df061aa9e1b9eab125c4c2fc839ac3b5a
2006-10-25 17:58:44 -04:00
Gabe Black
99d9d40e6c Implemented the saved and restored instructions, fixed up register window instructions so that the cwp is modified at the correct time (when handling the fault), and fixed the "done" instruction.
--HG--
extra : convert_revision : 3c9144422f087af1d375782cce1c9b77ca7936c9
2006-10-25 17:54:14 -04:00
Gabe Black
047455625e Fixed the bitfield FCN to include the right bits.
--HG--
extra : convert_revision : 040beb4dd982784773c3c3ad04cc48c2dc98b58c
2006-10-25 17:50:39 -04:00
Gabe Black
e2eef8859b Implemented the SPARC fill and spill handlers.
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
    Added a function to do normal SPARC trap processing, and implemented the spill and fill faults for SE
src/arch/sparc/process.cc:
src/arch/sparc/process.hh:
    Added fill and spill handlers which are stuffed into the processes address space. The location of these handlers are stored in fillStart and spillStart.

--HG--
extra : convert_revision : 59adb96570cce86f373fbc2c3e4c05abe1742d3b
2006-10-25 17:49:41 -04:00
Ron Dreslinski
eda7148af2 Fix fixPacket functionality to calculate sizes properly
src/mem/packet.cc:
    Copy size is calculated by END-BEGIN not BEGIN-END

--HG--
extra : convert_revision : 0e2725c5551f8f70ff05cb285e0822afc0bb3f87
2006-10-25 14:14:37 -04:00
Gabe Black
1b1495930c Replace the Alpha No op with a SPARC one.
--HG--
extra : convert_revision : bed03e63dc80bf24f21bad08e6553d7aab92c7b3
2006-10-24 15:50:41 -04:00
Ali Saidi
0f98905ecc Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem.head

--HG--
extra : convert_revision : 4db140e6e8408b3ed39da327515b8e88a2701e6b
2006-10-24 12:59:19 -04:00
Ali Saidi
650ebe4ec3 Add more traceflags for ethernet
--HG--
extra : convert_revision : a5025f501d72626d1bcb4dcc24ee353ceb160ce7
2006-10-24 12:59:07 -04:00
Steve Reinhardt
06482e6eed Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into  zizzer.eecs.umich.edu:/z/stever/bk/newmem-head

--HG--
extra : convert_revision : a077304e608753f50f4a12216901d156469eebe4
2006-10-24 11:50:20 -04:00
Lisa Hsu
764f27a0c9 Merge zizzer:/bk/newmem
into  zed.eecs.umich.edu:/z/hsul/work/m5/newmem

--HG--
extra : convert_revision : bb58679e101570d50c040519fb08ffbabfee7416
2006-10-23 18:46:05 -04:00
Lisa Hsu
4da3938ed9 get rid of the "resume" step at the end of changeToTiming/Atomic because this will cause an assertion when you do the CPU switch. instead, push the responsibility of the resume upwards towards the user - documented in se.py and fs.py so it should be ok.
--HG--
extra : convert_revision : 7530cf140844e18cc26df80057f8760f29ec952b
2006-10-23 18:45:30 -04:00
Lisa Hsu
0a2387f38c make this parallel to the other cpu types so that resume works correctly.
--HG--
extra : convert_revision : 3c165af27ea0e6c7f2a17819c1717d8900f54cc1
2006-10-23 18:43:56 -04:00
Kevin Lim
ce4531c079 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem

--HG--
extra : convert_revision : 161c35ade82f2471e605d948dca56cfa216693fd
2006-10-23 14:32:35 -04:00
Kevin Lim
4ccccfef71 Fix fetch to stop fetching upon encountering a fault in SE mode. Also change warning to a DPRINTF.
--HG--
extra : convert_revision : 819bade049d7ffd97d316051c99146ece5e3a651
2006-10-23 14:10:37 -04:00
Kevin Lim
1926faac06 Add in support for LL/SC in the O3 CPU. Needs to be fully tested.
src/cpu/base_dyn_inst.hh:
    Extend BaseDynInst a little bit so it can be use as a TC as well (specifically for ll/sc code).
src/cpu/base_dyn_inst_impl.hh:
    Add variable to track if the result of the instruction should be recorded.
src/cpu/o3/alpha/cpu_impl.hh:
    Clear lock flag upon hwrei.
src/cpu/o3/lsq_unit.hh:
    Use ISA specified handling of locked reads.
src/cpu/o3/lsq_unit_impl.hh:
    Use ISA specified handling of locked writes.

--HG--
extra : convert_revision : 1f5c789c35deb4b016573c02af4aab60d726c0e5
2006-10-23 14:00:07 -04:00
Gabe Black
ef8b7713ca Minor compile fix. Not sure why this is broken.
--HG--
extra : convert_revision : 6f181b15f37114ca0a3965cabcb2036bd2f97916
2006-10-23 11:17:59 -04:00
Gabe Black
18b2d94b8c Move around more SPARC memory code, and make block memory operations work with the timing cpu
--HG--
extra : convert_revision : 37358504c4d05d78d08c19ba3d0c99d38c4babf5
2006-10-23 11:17:15 -04:00
Gabe Black
466c387318 Merge zizzer.eecs.umich.edu:/bk/newmem
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem

--HG--
extra : convert_revision : cb15101d24ef2969e1819d6bdeeb2dd1f23f02d1
2006-10-23 09:44:58 -04:00
Gabe Black
20208d00e6 Broke Load/Store instructions into microcode, and partially refactored memory operations in the SPARC ISA description.
--HG--
rename : src/arch/sparc/isa/formats.isa => src/arch/sparc/isa/formats/formats.isa
rename : src/arch/sparc/isa/formats/mem.isa => src/arch/sparc/isa/formats/mem/basicmem.isa
rename : src/arch/sparc/isa/formats/blockmem.isa => src/arch/sparc/isa/formats/mem/blockmem.isa
rename : src/arch/sparc/isa/formats/mem.isa => src/arch/sparc/isa/formats/mem/mem.isa
extra : convert_revision : dbbb00f997a102871b084b209b9fa08c5e1853ee
2006-10-23 07:55:52 -04:00
Gabe Black
e9908e3c85 Don't let interupts interupt microcode at undesired points.
--HG--
extra : convert_revision : a8ddc6b213b1a1b0d9c5cd194b88ac0c6bfb2a21
2006-10-23 02:39:02 -04:00
Gabe Black
a8973c6054 Files in base shouldn't depend on things in sim. Changed "sim/host.hh" to <inttypes.hh>
--HG--
extra : convert_revision : c1e46c012a26cdb0603416f8e8a99e0ecb1c09bc
2006-10-23 02:37:54 -04:00
Gabe Black
f31d73a433 Start making memory ops work with InitiateAcc and CompleteAcc, and some minor cleanups
--HG--
extra : convert_revision : 178a8c5d0506c75ad7a7e8d691c8863235ed7e95
2006-10-23 02:36:46 -04:00
Gabe Black
3d6ff82552 Change the default constructors to take ExtMachInsts rather than regular MachInsts
--HG--
extra : convert_revision : 8fa34f82e0cbf5ce81775d572b182826c578581f
2006-10-23 02:32:58 -04:00
Steve Reinhardt
e321a21e27 Clean up cache DPRINTFs
--HG--
extra : convert_revision : f836e77efd40e25259d7794dd148696586b79a09
2006-10-22 21:07:38 -07:00
Steve Reinhardt
1b21d9ba5e s/pktuest/request/ (all in comments)
--HG--
extra : convert_revision : 7ce779242a15245a20322c0b6c40d02c8ddd15ad
2006-10-22 20:38:34 -07:00
Steve Reinhardt
199084b339 Add DPRINTF for non-timed quiesce.
--HG--
extra : convert_revision : 5487f4fc07dbea6e5a651c104ea1d2fe864fb057
2006-10-22 16:22:45 -07:00
Steve Reinhardt
5e2263fc52 Small bug fixes for timing LL/SC. Better now but
not necessarily 100% there yet.

src/mem/cache/cache_impl.hh:
    Generate response packet on failed store conditional.
src/mem/packet.hh:
    Clear packet flags when reinitializing.
    (SATISFIED in particular is one we don't want to leave set.)

--HG--
extra : convert_revision : 29207c8a09afcbce43f41c480ad0c1b21d47454f
2006-10-21 23:35:00 -07:00
Steve Reinhardt
0159529343 Add Quiesce trace flag to track CPU quiesce/wakeup events.
--HG--
extra : convert_revision : 23be99d0fe6e2184523efe5d9e0a1ac7bf19d087
2006-10-21 23:32:14 -07:00
Steve Reinhardt
883ed108e4 Just give up if a store conditional misses completely
in the cache (don't treat as normal write miss).

--HG--
extra : convert_revision : c030eb6ba25318cae422e4da31e3b802049c8c74
2006-10-21 17:19:33 -07:00
Steve Reinhardt
82e90bf5e0 Fix formatting that got screwed up when tabs were removed.
--HG--
extra : convert_revision : 98596542a5774fe010e25632836ce92b66779f53
2006-10-21 13:54:48 -07:00
Steve Reinhardt
1e6aa0d0d0 Refactor coherence state table initialization.
--HG--
extra : convert_revision : eb36dd2cc1463e5076f4758a59cf68cc6b2bafc5
2006-10-21 13:43:14 -07:00
Steve Reinhardt
3ac1ca8ff6 Tweak a few things for better page fault debugging.
src/sim/faults.cc:
    Fix fault message.
src/kern/tru64/tru64.hh:
    Add DPRINTF to see where new thread stacks are allocated.
src/arch/alpha/faults.cc:
    Add print statement so we know what the faulting address is in SE mode.

--HG--
extra : convert_revision : 6eb2b513c339496a0d013b7e914953a0a066c12d
2006-10-21 05:28:05 -04:00
Nathan Binkert
dff1a022b8 Missing case
--HG--
extra : convert_revision : 128896dd1a654fe9a02e2c07ef6ce6799b62f21f
2006-10-21 00:31:46 -07:00
Gabe Black
0b5cf4ba6e Merge zizzer.eecs.umich.edu:/bk/newmem
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem

--HG--
extra : convert_revision : 2711fec2bf72801999b060e65f0bf744c18734fb
2006-10-20 16:39:47 -04:00
Nathan Binkert
6c6b78126a Construct a correct value of PYTHONHOME from the interpreter
running SCons, make it into a sticky option that can be
overridden at build time, and set it up before the interpreter
is started.  Also, fix the code that turns sticky options into
config/*.hh so that it works with types other than bool.

--HG--
extra : convert_revision : 602398b35d4da4e813f78865678ed348fdea7270
2006-10-20 11:37:59 -07:00
Ron Dreslinski
ba24ce6bb6 Get rid of a variable put back by merge.
--HG--
extra : convert_revision : 5ddb6ae5d5412f062c07c16a27b79483430b5f22
2006-10-20 13:05:39 -04:00
Ron Dreslinski
54ed57cc4c Merge zizzer:/bk/newmem
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

src/mem/tport.cc:
    Merge PacketPtr changes

--HG--
extra : convert_revision : 0329c5803a3df67af3dda89bd9d4753fd1a286d1
2006-10-20 13:04:59 -04:00
Ron Dreslinski
28e9641c2c Use fixPacket function everywhere.
Fix fixPacket assert function.
Stop timing port from forwarding the request if a response was found in its queue on a read.

src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
src/python/m5/objects/MemTest.py:
    Add parameter to configure what percentage of mem accesses are functional
src/mem/cache/base_cache.cc:
src/mem/cache/cache_impl.hh:
    Use fix Packet function
src/mem/packet.cc:
    Fix an assert that was checking the wrong thing
src/mem/tport.cc:
    Properly detect if we need to do the access to the functional device

--HG--
extra : convert_revision : 447cc1a9a65ddd2a41e937fb09dc0e7c74e9c75e
2006-10-20 13:01:21 -04:00
Ali Saidi
7be58fd5f4 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem.head

--HG--
extra : convert_revision : c0f9bde20585b3811ff906728b003072b69696b5
2006-10-20 13:00:15 -04:00
Ali Saidi
32384b2f6b still working on getting past initialization
--HG--
extra : convert_revision : 7a5fccb9a19d363e479ef24012a7b8598272eaa9
2006-10-20 13:00:05 -04:00
Nathan Binkert
a4c6f0d69e Use PacketPtr everywhere
--HG--
extra : convert_revision : d9eb83ab77ffd2d725961f295b1733137e187711
2006-10-20 00:10:12 -07:00
Nathan Binkert
7245d4530d refactor code for the packet, get rid of packet_impl.hh
and call it packet_access.hh and fix the #includes so
things compile right.

--HG--
extra : convert_revision : d3626c9715b9f7e51bb3ab8d97e971fad4e0b724
2006-10-19 23:38:45 -07:00
Nathan Binkert
5b246a0567 initialize end, clean up loop
--HG--
extra : convert_revision : e1c107f0c0fd5d535acd2d6c43571a5df57c9ed3
2006-10-19 23:35:59 -07:00
Nathan Binkert
b937d54510 Fix compile of m5.fast
--HG--
extra : convert_revision : a8a37c318e55e48e697e4aaba339328f000b3f60
2006-10-19 23:34:59 -07:00
Ron Dreslinski
780aa0a0eb Fix corner case on assertion.
I need to move over to using the fixPacket function so I don't have to make the same changes everywhere.
Still a functional access bug someplace I need to track down in timing mode.

src/mem/cache/base_cache.cc:
src/mem/cache/cache_impl.hh:
    Fix corner case on assertion
tests/configs/memtest.py:
    Updated memtester with uncacheable addresses and functional accesses

--HG--
extra : convert_revision : e6fa851621700ff9227b83cc5cac20af4fc8444f
2006-10-19 21:26:46 -04:00
Ron Dreslinski
cc1feb9f6d Fix memtester to use functional access, fix cache to work functionally now that we could test it.
src/cpu/memtest/memtest.cc:
    Fix memtest to do functional accesses
src/mem/cache/cache_impl.hh:
    Fix cache to handle functional accesses properly based on memtester changes
    Still need to fix functional accesses in timing mode now that the memtester can test it.

--HG--
extra : convert_revision : a6dbca4dc23763ca13560fbf5d41a23ddf021113
2006-10-19 21:07:53 -04:00
Ron Dreslinski
210e73f2a2 Small changes:
?? doesn't compile in warn statements
Should have been false, where I had a true.

src/cpu/o3/lsq_impl.hh:
    Apparently you can't have ?? in a warn statement (Something about trigraphs)
src/mem/cache/cache_impl.hh:
    Forgot to signal atomic mode in snoopProbe

--HG--
extra : convert_revision : c75cb76e193e852284564993440c8ea39e6de426
2006-10-19 20:18:17 -04:00
Ron Dreslinski
e34e564f79 Fixes to get single level uni-coherence to work.
Now to try L2 caches in FS.

src/mem/cache/base_cache.hh:
    Fix uni-coherence for atomic accesses in coherence protocol access to port
src/mem/cache/cache_impl.hh:
    Properly handle uni-coherence
src/mem/cache/coherence/simple_coherence.hh:
    Properly forward invalidates (not done for MSI+ protocols (assumed top level for now)
src/mem/cache/coherence/uni_coherence.cc:
src/mem/cache/coherence/uni_coherence.hh:
    Properly forward invalidates in atomic/timing uni-coherence

--HG--
extra : convert_revision : f0f11315e8e7f32c19d92287f6f9c27b079c96f7
2006-10-19 20:02:57 -04:00
Ron Dreslinski
9cf063eb8e Merge zizzer:/bk/newmem
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : c6611b32537918f5bf183788227ddf69a9a9a069
2006-10-19 19:00:43 -04:00
Ron Dreslinski
39d24f7241 Always get the functional access from the highest level of cache first.
src/mem/cache/cache_impl.hh:
    Get the read data from the highest level of cache on a functional access

--HG--
extra : convert_revision : 7437ac46fb40f3ea3b42197a1aa8aec62af60181
2006-10-19 19:00:27 -04:00
Steve Reinhardt
11f0badbaa Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into  zizzer.eecs.umich.edu:/z/stever/bk/newmem-head

--HG--
extra : convert_revision : 8a70922250092c013fa4db6d83254b438ee6c4be
2006-10-19 13:33:08 -04:00
Steve Reinhardt
a78e92381b Add "All" compund flag to enable all defined trace flags.
--HG--
extra : convert_revision : dcc699d8341f762dee659290cd35206e326e1179
2006-10-19 10:32:08 -07:00
Steve Reinhardt
e78684fc6c Add new event priority for trace enable events so
that tracing gets turned on as the very first thing
in the selected cycle (tick).

--HG--
extra : convert_revision : c08f749ca42782af1b48e5aa5f0860bf7076bd3c
2006-10-19 10:21:23 -07:00
Steve Reinhardt
bba3dfb0d3 First cut at LL/SC support in caches (atomic mode only).
configs/example/fs.py:
    Add MOESI protocol to caches (uni coherence not quite working w/FS yet).

--HG--
extra : convert_revision : 7bef7d9c5b24bf7241cc810df692408837b06b86
2006-10-19 00:33:33 -07:00
Gabe Black
54c9701a25 Zeroed out the actual LSB in addition to moving it's original value the MSB.
--HG--
extra : convert_revision : d29efe01781d72ee6e61818e7b93972262c0616b
2006-10-18 20:53:59 -04:00
Gabe Black
bb2ab310eb Fixed up exetrace.cc to deal with microcode, and to made floating point register numbers correlate to the numbers used in SPARC in m5 and statetrace.
src/cpu/exetrace.cc:
    Fixed up to deal with microcode, and to make floating point register numbers correlate to the numbers used in SPARC.
util/statetrace/arch/tracechild_sparc.cc:
util/statetrace/arch/tracechild_sparc.hh:
    Make floating point register numbers correlate to the numbers used in SPARC.

--HG--
extra : convert_revision : 878897292f696092453cf61d6eac2d1c407ca13b
2006-10-18 20:52:34 -04:00
Gabe Black
849d5e2efb Fixed a compiler error, disassembly output, and corrected the address calculation.
--HG--
extra : convert_revision : d34b3c0443064addb6f454ac70fbaeda0678e329
2006-10-18 20:48:08 -04:00
Gabe Black
94926a72e9 Fixed up ldblockf_p, implemented stdfa properly, and got rid of some old code.
--HG--
extra : convert_revision : 263b4b835d6d1bc9049acdc1398286277bede97a
2006-10-18 20:44:51 -04:00
Lisa Hsu
75ecd3be60 how did i not commit this already? the other way doesn't seem to work, need to convert to System ptr first to access System method.
src/python/m5/SimObject.py:
    how did i not commit this already?  the other way doesn't seem to work.

--HG--
extra : convert_revision : 55737d3d10742a1913a376d1febbc5809f2fab8f
2006-10-18 18:04:53 -04:00
Lisa Hsu
15770fb7b4 need some initializations before doing the loop.
--HG--
extra : convert_revision : e5e8b16ae4f119c923d8c0d295aa9569d7a8fe5b
2006-10-18 18:01:33 -04:00
Lisa Hsu
c2c48645c9 only do this assert after you know you're not switched out or idle.
--HG--
extra : convert_revision : 0cd0d31db44fe7e8e44bde90e1756873faca422f
2006-10-18 17:59:11 -04:00
Ron Dreslinski
5bcdc74fe2 Fix WriteInvalidateResp
--HG--
extra : convert_revision : ac4281944202a9a2f166b305a1eaea507e484bcc
2006-10-18 16:38:02 -04:00
Ron Dreslinski
63c2a782d6 Merge zizzer:/bk/newmem
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : 9e47881686a6c060fa28e7edfd9a0b556099bf30
2006-10-18 13:34:52 -04:00
Steve Reinhardt
0e2561710b Break a lot of overly long lines.
Factor out some asserts that were on both
sides of an if/else.

--HG--
extra : convert_revision : 78f0c2d76a81a98216b2f281159c6b6ea0147731
2006-10-18 08:41:05 -07:00
Steve Reinhardt
caf123586f Get rid of doData() lines (were already commented out).
Reindent due to resulting changes in nesting.

--HG--
extra : convert_revision : 6be099d572efb618efb08fbc06d7e0e4b5b4cab2
2006-10-18 08:24:24 -07:00
Steve Reinhardt
6cd187e1f0 Get rid of obsolete in-cache copy support.
--HG--
extra : convert_revision : a701ed9d078c67718a33f4284c0403a8aaac7b25
2006-10-18 08:16:22 -07:00
Steve Reinhardt
f735399b39 Include packet_impl.hh (need this on my laptop,
but not on zizzer... g++ 4 thing maybe?)

--HG--
extra : convert_revision : 31c49f1c55fe9daf6365411bfb5bb7f6ccc8032d
2006-10-17 21:16:17 -07:00
Steve Reinhardt
05c487ef3c Enable MP systems via cmd-line flag in fs.py.
configs/example/fs.py:
    Add flag for MP server systems.
src/python/m5/objects/AlphaConsole.py:
src/python/m5/objects/IntrControl.py:
    Change CPU from 'any' to 'cpu[0]' to work better with MP sytems.
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-timing-dual.py:
    Don't need to set console & intrcontrol cpu
    params anymore (default is fixed now).

--HG--
extra : convert_revision : 9417b12b1b395ff7d6a9f2894e4123923c754daf
2006-10-17 21:15:11 -07:00
Ali Saidi
e51b075a27 add code to serialize se structures. Lisa is working on the python side of things and will test
src/mem/page_table.cc:
src/mem/page_table.hh:
    add code to serialize/unserialize page table
src/sim/process.cc:
src/sim/process.hh:
    add code to serialize/unserialize process

--HG--
extra : convert_revision : ee9eb5e2c38c5d317a2f381972c552d455e0db9e
2006-10-17 19:38:36 -04:00
Ron Dreslinski
9c582c7e14 Fixes for uni-coherence in timing mode for FS.
Still a bug in atomic uni-coherence in FS.

src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
    Make CPU models handle coherence requests
src/mem/cache/base_cache.cc:
    Properly signal coherence CSHRs
src/mem/cache/coherence/uni_coherence.cc:
    Only deallocate once

--HG--
extra : convert_revision : c4533de421c371c5532ee505e3ecd451511f5c99
2006-10-17 18:50:19 -04:00
Ron Dreslinski
4fff6d4603 Fixes to cache eliminating the assumption that the Packet is still valid after sending out a request.
Still need to rework upgrades into this system, but works for now.

src/mem/cache/base_cache.cc:
    Re order code to be more readable
src/mem/cache/base_cache.hh:
    Be sure to delete the copy on a bus block
src/mem/cache/cache_impl.hh:
    Be sure to remove the copy on a writeback success
src/mem/cache/miss/mshr_queue.cc:
    Demorgans to make it easier to understand
src/mem/tport.cc:
    Delete writebacks

--HG--
extra : convert_revision : 9519fb37b46ead781d340de29bb342a322a6a92e
2006-10-17 16:47:22 -04:00
Ron Dreslinski
6e8bfa4e63 Properly chack the pkt pointer on upgrades to insure no segfaults when writebacks delete the packet.
--HG--
extra : convert_revision : 72b1c6296a16319f4d16c62bc7038365654dbc40
2006-10-17 15:07:40 -04:00
Ron Dreslinski
288b98eb69 Fix it so that the cache does not assume to gave the packet it sent out via sendTiming.
Still need to fix upgrades to use this path

src/mem/cache/base_cache.cc:
    Copy the pkt to the MSHR before issuing the sendTiming where it may be changed/consumed
src/mem/cache/cache_impl.hh:
    Use copy of packet, because sendTiming may have changed the pkt
    Also, delete the copy when the time comes

--HG--
extra : convert_revision : 635cde6b4f08d010affde310c46b1caf50fbe424
2006-10-17 15:05:21 -04:00
Ron Dreslinski
685e588b45 Merge zizzer:/bk/newmem
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : c3650273684f3fbdcd2e14e95d09ee3c6de8d6b6
2006-10-17 14:05:23 -04:00
Gabe Black
b55271aee9 Corrected the "Authors" line
--HG--
extra : convert_revision : 0202e130b170dcc2f45403c58cf51ec8c2e4e094
2006-10-16 15:59:48 -04:00
Gabe Black
519d11bab3 Merge zizzer.eecs.umich.edu:/bk/newmem
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem

--HG--
extra : convert_revision : 898976bbd322e55bc234035456df8090c6dcf72d
2006-10-16 15:56:53 -04:00
Gabe Black
f1661baf30 Fix up microcode support.
src/arch/sparc/isa/formats/blockmem.isa:
    Several small and medium bug fixes.
src/cpu/simple/base.cc:
    Fixed a few compiler errors and made sure the next micro pc is set to 1 to prevent the first microop from executing twice. Also fixed a fetching bug.
src/cpu/thread_state.cc:
    Made sure the microPC and nextMicroPC are initialized properly.

--HG--
extra : convert_revision : a0fc8aa18d1ade916f17c557181a793c6108a8af
2006-10-16 15:56:46 -04:00
Gabe Black
7fefa2a621 Changed how floating point register numbers are decoded to fit with the spec.
--HG--
extra : convert_revision : 155f48c84d06619c9c1c43375beb9d0a1c7495c9
2006-10-16 15:53:48 -04:00
Gabe Black
546dff6b6a Made sure the constructor for insts use ExtMachInst rather than MachInst, since otherwise the EXT_ASI field is lost.
src/arch/sparc/isa/base.isa:
src/arch/sparc/isa/formats/micro.isa:
    Switch MachInst to ExtMachInst so that the EXT_ASI field is available to the instructions.
src/arch/sparc/utility.hh:
    Made sure EXT_ASI was set to the appropriate ASI value whether or not the asi register was used.

--HG--
extra : convert_revision : cc4363dfe7da81969959cec9d5ad48528edeb8ce
2006-10-16 15:52:14 -04:00
Gabe Black
67794ace5c Added in missing portions of the stat structure copying function.
--HG--
extra : convert_revision : cfabcb07b2c0c5655a757e8c98999ec3cf791e09
2006-10-15 21:54:59 -04:00
Gabe Black
333a7c4ba2 Started implementing microcode.
--HG--
extra : convert_revision : 51df0454085e13df023efd8a0c0a12f9756c4690
2006-10-15 21:04:14 -04:00
Gabe Black
dc7d9af582 Added an execute function to the macro op so it can be instantiated.
--HG--
extra : convert_revision : 89dd46f5bbac966e6eb4f6f747419fa1d344eb87
2006-10-15 20:54:35 -04:00
Gabe Black
7009d0e523 Fix how additional template parameters are handled. Non string parameters are not processed as code.
src/arch/isa_parser.py:
    Changed the way the extra template parameters are specified. MIPS might need to be adjusted.
src/arch/sparc/isa/decoder.isa:
    Changed how Frd_N was set up.
src/arch/sparc/isa/formats/blockmem.isa:
    Fixed up handling of block memory operations
src/arch/sparc/isa/formats/integerop.isa:
src/arch/sparc/isa/formats/mem.isa:
src/arch/sparc/isa/formats/priv.isa:
    Fix up extra template parameters.

--HG--
extra : convert_revision : ebf850d192193521bb84ca36b577051f74338d23
2006-10-15 20:37:28 -04:00
Steve Reinhardt
9202422d6e Get rid of unused CacheBlk << output operator.
--HG--
extra : convert_revision : d5c0aadc35edf5c9495afcd3375f1f64716ef845
2006-10-14 02:09:05 -04:00
Kevin Lim
a50e83c134 Fix assertion. I haven't tested it fully (I can't reproduce Lisa's error) but I believe it should fix what she's running into (which was definitely a bug).
src/cpu/o3/fetch_impl.hh:
    Move assertion to area where it should really always be true.  Sometimes you might recvRetry and not necessarily be blocked (if there was a squash).

--HG--
extra : convert_revision : 76ad35357e7f4c44fa544ffed071096a62053018
2006-10-13 17:35:23 -04:00
Ron Dreslinski
1871495b8d Merge zizzer:/bk/newmem
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : f62790e46a7e3eb88a6f8c7bfaa08526285248a3
2006-10-13 15:47:35 -04:00
Ron Dreslinski
a17afb1649 Fix for DMA's in FS caches.
Fix CSHR's for flow control.
Fix for Bus Bridges reusing packets (clean flags up)

Now both timing/atomic caches with MOESI in UP fail at same point.

src/dev/io_device.hh:
    DMA's should send WriteInvalidates
src/mem/bridge.cc:
    Reusing packet, clean flags in the packet set by bus.
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/simple_coherence.hh:
src/mem/cache/coherence/uni_coherence.cc:
src/mem/cache/coherence/uni_coherence.hh:
    Fix CSHR's for flow control.
src/mem/packet.hh:
    Make a writeInvalidateResp, since the DMA expects responses to it's writes

--HG--
extra : convert_revision : 59fd6658bcc0d076f4b143169caca946472a86cd
2006-10-13 15:47:05 -04:00
Ali Saidi
ca4063ac00 fix a bug in CopyStringOut. dprintk appears to work again.
--HG--
extra : convert_revision : cd0d13a85ddc7599308db8604a8f63a48679cc05
2006-10-13 14:28:46 -04:00
Lisa Hsu
339b1f8516 Merge zizzer:/bk/newmem
into  zed.eecs.umich.edu:/z/hsul/work/m5/newmem

src/cpu/simple/timing.cc:
    hand merge

--HG--
extra : convert_revision : 083bf102249ad9bc63c447dbf85d3863f935f647
2006-10-12 18:56:57 -04:00
Gabe Black
92fd211a07 Changed the sign extension function from mine to the provided one. Mine relied on implementation specific behavior, namely right shifting a signed value.
--HG--
extra : convert_revision : 4f5ef44d012de87919ad681024fe2ed0213a412f
2006-10-12 17:39:15 -04:00
Gabe Black
98b00d92fd Some support for handling block loads and stores and ASIs properly.
src/arch/sparc/isa/bitfields.isa:
    Added a field to retrieve the asi from the ExtMachInst
src/arch/sparc/isa/decoder.isa:
    Fixed up how the size of memory operations where handled, and use the new EXT_ASI bit field.
src/arch/sparc/isa/formats.isa:
    add includes for the new formats.
src/arch/sparc/isa/formats/basic.isa:
    Add a template for BasicDecodeWithMnemonic which is needed by the unimp format.
src/arch/sparc/isa/formats/mem.isa:
    Change around the memory format to figure out the memory access width on its own.
src/arch/sparc/isa/operands.isa:
    Added support for the operands of block loads/stores which are offset from Frd.
src/arch/sparc/utility.hh:
    Encoded the ASI into the ExtMachInst

--HG--
extra : convert_revision : 5c6026a07e3a919e738d27f78beb0faf6b060643
2006-10-12 17:38:06 -04:00
Gabe Black
866dda9778 StaticInst support for microcode
--HG--
extra : convert_revision : c9e062637faf2166f0d36b914f3efa7f80626663
2006-10-12 17:32:02 -04:00
Gabe Black
6943c731ea The beginnings of an instruction format to deal with block loads and stores. This takes advantage of microcode.
--HG--
extra : convert_revision : ac912df76c781f40fc462f314451148c5cdfaf43
2006-10-12 17:30:25 -04:00
Gabe Black
b2d9c65db7 Some support for macro/micro instructions in SPARC.
--HG--
extra : convert_revision : 1f0687d58ab3a4823911a67d8d5c66b27cc211a5
2006-10-12 17:29:28 -04:00
Gabe Black
dd217a9d3f Support for returning unimplemented instruction in the decoder, lifted from Alpha
--HG--
extra : convert_revision : 7e26053696b23fbc0b8cd5827a5072dcf2526e2b
2006-10-12 17:27:06 -04:00
Ali Saidi
3d2764acf3 replace functional code in tport with fixPacket().
fixPacket() should be used anywhere a functional packet and timing packet are found to have the same address.

--HG--
extra : convert_revision : 783ec438271b24ddb0ae742b4efd1ed7d6be93f3
2006-10-12 15:30:30 -04:00
Ron Dreslinski
eddbb6801f Fix CSHR retrys
--HG--
extra : convert_revision : caa7664f6c945396fa38ce62fbda018ebed4eaa6
2006-10-12 15:02:56 -04:00
Ali Saidi
4a96779350 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem.head

--HG--
extra : convert_revision : 0e184a0784100112db5841c587bd3dd638f8bdc0
2006-10-12 15:02:50 -04:00
Ali Saidi
0615d92d33 small bus updates for functional accesses
--HG--
extra : convert_revision : c7a6b199c74ed4b4ffab14bbffb51e72d75b7742
2006-10-12 15:02:25 -04:00
Ron Dreslinski
3aaa3456dc Merge zizzer:/bk/newmem
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : fa5b2cfa79d87a0612b8116d407a8b2959d9095a
2006-10-12 14:31:31 -04:00
Ron Dreslinski
fe230ddb8f Remove bus and top level parameters from cache
src/mem/cache/base_cache.hh:
    Remove top level param from cache
src/mem/cache/coherence/uni_coherence.cc:
    Remove top level parameters from the cache

--HG--
extra : convert_revision : 4437aeedc20866869de7f9ab123dfa7baeebedf0
2006-10-12 14:21:25 -04:00
Ali Saidi
2c9d506f46 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem.head

src/mem/packet.hh:
    hand merge

--HG--
extra : convert_revision : 3f77707360235dc98c6b12a0367ca64a401313df
2006-10-12 14:18:42 -04:00
Ali Saidi
3ba2ed6aef add a traceflag for functional accesses
implement fix packet and add the ability to print a packet to a ostream
remove tabs in packet.hh (Could people stop inserting them??!?!?!)
mark const functions in packet.hh as such

src/base/traceflags.py:
    add a traceflag for functional accesses
src/mem/packet.cc:
    implement fix packet and add the ability to print a packet to a ostream
src/mem/packet.hh:
    add the ability to print a packet to an ostream
    remove tabs in file
    mark const functions as such

--HG--
extra : convert_revision : 4297bce5e1d3abbab48be5bd9eb9e982b751fc7c
2006-10-12 14:15:09 -04:00
Ron Dreslinski
f89b56b61a Check the response queue on functional accesses.
The response queue is not tying up an MSHR, should we change that or assume infinite storage for responses?

src/mem/cache/base_cache.cc:
src/mem/tport.cc:
    Add in functional check of retry queued packets.

--HG--
extra : convert_revision : 0cb40b3a96d37a5e9eec95312d660ec6a9ce526a
2006-10-12 13:59:03 -04:00
Ron Dreslinski
6ffdc7b4d7 Another memleak in the memtester (need [] with the delete)
src/cpu/memtest/memtest.cc:
    Another memleak in the memtester

--HG--
extra : convert_revision : f7ab079e90d578fb6b9d1ff238d049fcce55b01b
2006-10-12 13:45:28 -04:00
Ron Dreslinski
dd18ffe51d Fix a memory leak in the memtester
--HG--
extra : convert_revision : 93062b0f1a3ba7a5210e2f27099f20ae8f66522b
2006-10-12 13:43:12 -04:00
Ron Dreslinski
ba4c224c39 Fix problems with unCacheable addresses in timing-coherence
src/base/traceflags.py:
src/mem/physical.cc:
    Add debug falgs fro physical memory accesses
src/mem/cache/cache_impl.hh:
    Snoops to uncacheable blocks should not happen
src/mem/cache/miss/miss_queue.cc:
    Set the size properly on unCacheable accesses

--HG--
extra : convert_revision : fc78192863afb11fc7c591fba169021b9e127d16
2006-10-12 13:33:21 -04:00
Gabe Black
866cfaf9dc Merge zizzer.eecs.umich.edu:/bk/newmem
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem

--HG--
extra : convert_revision : 30b2475ba034550376455e1bc0e52e19a200fd5a
2006-10-12 10:58:45 -04:00
Ron Dreslinski
388d484269 Make default ID unique (not broadcast)
Fix a segfault associated with DefaultId

src/mem/bus.cc:
    Handle a segfault in the bus when DefaultPort was being used
src/mem/bus.hh:
    Make the Default ID more unique (it overlapped with Broadcast ID)

--HG--
extra : convert_revision : 9182805c5cf4d9fe004e6c5be8547a8f41ed7bfe
2006-10-11 20:54:06 -04:00
Ron Dreslinski
14c8e8b227 Forgot to mark myself as on the retry list
--HG--
extra : convert_revision : c20170320a284a7bf143a929e4d3aa1475a8bfe0
2006-10-11 19:47:11 -04:00
Ron Dreslinski
3c7e0ec752 Fix bus in FS mode.
src/mem/bus.cc:
    Add debugging statement
src/mem/bus.hh:
    Fix implementation of bus for subsequent recvTimings while handling a retry request.
src/mem/tport.cc:
    Rework timing port to retry properly

--HG--
extra : convert_revision : fbfb5e8b4a625e49c6cd764da1df46a4f336b1b2
2006-10-11 19:25:48 -04:00
Lisa Hsu
ba795552f5 System not global object, need to preface it with objects.
--HG--
extra : convert_revision : 5e105d7082a8c103fb5d5383c3093734bfd590f5
2006-10-11 18:54:31 -04:00
Lisa Hsu
8acecfef9b since memoryMode was put into the System (from SimObject), things got broken - this fixes it so that changeToTiming/changeToAtomic works.
src/python/m5/SimObject.py:
    now that setMemoryMode is a method in System, need to convert the SimObject * _ccObject into a system ptr to call setMemoryMode.
src/sim/main.cc:
    need this conversion now.
src/sim/sim_object.hh:
    put the enum back into SimObject.
src/sim/system.hh:
    memoryMode is now a part of SimObject, need the ::'s

--HG--
extra : convert_revision : 0ade06957fa57b497798e1f50c237ca1badc821d
2006-10-11 18:53:50 -04:00
Lisa Hsu
024b33a1ef some drain changes in timing (kevin's) and some memory mode assertion changes so that when you come out of resume, you only assert if you're really wrong.
src/cpu/simple/atomic.cc:
    memory mode assertion change so that it only goes off if it's supposed to.
src/cpu/simple/timing.cc:
    some drain changes (kevin's) and some changes to memoryMode assertions so that they don't go off when they're not supposed to.

--HG--
extra : convert_revision : 007d8610f097e08f01367b905ada49f93cf37ca3
2006-10-11 18:44:48 -04:00
Ron Dreslinski
567afbf6ce More cache fixes. Atomic coherence now works as well.
src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
    Make Memtester able to test atomic as well
src/mem/bus.cc:
src/mem/bus.hh:
    Handle atomic snoops properly for cache->cache transfers
src/mem/cache/cache_impl.hh:
    Debug output.
    Clean up memleak in atomic mode.
    Set hitLatency.
    Still need to send back reasonable number for atomic return value.
src/mem/packet.cc:
    Add command strings for new commands
src/python/m5/objects/MemTest.py:
    Add param to test atomic memory.

--HG--
extra : convert_revision : 43f880e29215776167c16ea90793ebf8122c785b
2006-10-11 18:28:33 -04:00
Ron Dreslinski
03c42ea590 Update for Atomic Coherece with Gabes bus
--HG--
extra : convert_revision : 6a23052056d1c61cba0a4c77f1030cee419c6fa3
2006-10-11 01:59:38 -04:00
Ron Dreslinski
4e35c5656f Merge zizzer:/n/wexford/x/gblack/m5/newmem_bus
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : 70187b8f04d0f8424512f64bdade05bf1aca85a3
2006-10-11 01:02:18 -04:00
Ron Dreslinski
c2012601e9 Use bus response time paramteres
Fix bug with deadlocking

src/mem/cache/base_cache.cc:
    Make sure to not wait anymore

--HG--
extra : convert_revision : 5f7b44a1c475820b9862275a0d6113ec2991735d
2006-10-11 01:01:40 -04:00
Gabe Black
7767f5af73 Don't call recvRetry if the bus is busy anyway. This takes care of a corner case as well when dealing with grants that aren't used.
--HG--
extra : convert_revision : 38f7ef1b41477fb2a2438387ef3a81cccd3e7a8a
2006-10-11 00:54:47 -04:00
Ron Dreslinski
07dad71f6f Merge zizzer:/n/wexford/x/gblack/m5/newmem_bus
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : d2d19b27533f35c6570ee84c6c83b2919f27b97f
2006-10-11 00:31:40 -04:00
Gabe Black
a139e4394d Make the bus work if the other sides recvRetry doesn't call sendTiming for some reason.
--HG--
extra : convert_revision : e722ddb0354a5c021dc7c44a3e2f0a64e962442b
2006-10-11 00:26:21 -04:00
Ron Dreslinski
04f71f1226 When turning asserts into if's don't forget to invert.
src/mem/cache/base_cache.cc:
    When turning asserts into if's don't forget to invert.
    Must be too sleepy.

--HG--
extra : convert_revision : ea38d5a4b4ddde7b5266b3b2c83bbc256218af9a
2006-10-11 00:19:31 -04:00
Ron Dreslinski
23bbd14426 Writebacks can be pulled out from under the BusRequest when snoops of uprgades to owned blocks hit in the WB buffer
--HG--
extra : convert_revision : f0502836a79ce303150daa7e571badb0bce3a97a
2006-10-11 00:13:53 -04:00
Ron Dreslinski
c9102b08fa Only issue responses if we aren;t already blocked
--HG--
extra : convert_revision : 511c0bcd44b93d5499eefa8399f36ef8b6607311
2006-10-10 23:53:10 -04:00
Ron Dreslinski
ca694ca7b1 Merge zizzer:/n/wexford/x/gblack/m5/newmem_bus
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

src/mem/bus.cc:
    SCCS merged

--HG--
extra : convert_revision : 18608114350c466a56ab499ae523b01fcb2f6ef2
2006-10-10 23:37:14 -04:00
Gabe Black
8353b1e21f Make the bus is occupied for none broadcast packets as well.
--HG--
extra : convert_revision : aef3c625172e92be8f29c4c57077fefee43046bb
2006-10-10 23:28:33 -04:00
Ron Dreslinski
477a3b0b61 Merge zizzer:/n/wexford/x/gblack/m5/newmem_bus
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

src/mem/bus.cc:
    SCCS merged

--HG--
extra : convert_revision : eaae105025635c37af06cf72bb061ce82def9dc9
2006-10-10 22:52:52 -04:00
Ron Dreslinski
1de8eae43a Debugging info
src/base/traceflags.py:
    Add new flags for cacheport
src/mem/bus.cc:
    Add debugging info
src/mem/cache/base_cache.cc:
    Add debuggin info

--HG--
extra : convert_revision : a6c4b452466a8e0b50a86e886833cb6e29edc748
2006-10-10 22:50:36 -04:00
Gabe Black
59dd317cb5 Put in an accounting mechanism and an assert to make sure something doesn't try to send another packet while it's still waiting for the bus.
--HG--
extra : convert_revision : 4a2b83111e49f71ca27e05c98b55bc3bac8d9f53
2006-10-10 22:10:08 -04:00
Gabe Black
404b2a951d Fixed a corner case and simplified the logic in Packet::intersect.
--HG--
extra : convert_revision : b57c31ca7c220e701d34e02bb07ce392370e4428
2006-10-10 17:49:31 -04:00
Ron Dreslinski
27c59dc370 Merge zizzer:/n/wexford/x/gblack/m5/newmem_bus
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : 7b7a1b03ffed36bce49595962ea57c08d1d1a4ad
2006-10-10 17:32:24 -04:00
Ron Dreslinski
aff3d92c00 Some more code cleanup
src/mem/cache/base_cache.cc:
    Add sanity checks
src/mem/cache/base_cache.hh:
    Fix for retry mechanism

--HG--
extra : convert_revision : 9298e32e64194b1ef3fe51242595eaa56dcbbcfd
2006-10-10 17:25:50 -04:00
Gabe Black
549412b333 Changed the bus to use a bool to keep track of retries rather than a pointer
src/mem/tport.cc:
    minor formatting tweak

--HG--
extra : convert_revision : 7391d142815c5876fcc0f991bd053e6a1781c101
2006-10-10 17:24:03 -04:00
Gabe Black
5f9aca531d Merge zizzer.eecs.umich.edu:/bk/newmem
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus

--HG--
extra : convert_revision : aa59d3169d84bcd13b8c97f22b52aeef43dc33c3
2006-10-10 17:18:09 -04:00
Ron Dreslinski
995146ead7 Fix some more mem leaks, still some left
Update retry mechanism

src/mem/cache/base_cache.cc:
    Rework the retry mechanism
src/mem/cache/base_cache.hh:
    Rework the retry mechanism
    Try to fix memory bug
src/mem/cache/cache_impl.hh:
    Rework upgrades to not be blocked by slave
src/mem/cache/miss/mshr_queue.cc:
    Fix mem leak on writebacks

--HG--
extra : convert_revision : 3cec234ee441edf398ec8d0f51a0c5d7ada1e2be
2006-10-10 17:10:56 -04:00
Gabe Black
012556ecf9 Merge zizzer.eecs.umich.edu:/bk/newmem
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus

--HG--
extra : convert_revision : 4036e8447fb3038d93285c6582900210d7d88d67
2006-10-10 15:56:18 -04:00
Ron Dreslinski
9e008d73d5 Fix cshr Retry's
Fix Upgrades being blocked by slave

--HG--
extra : convert_revision : cca98a38e32233145163577500f1362cd807ab15
2006-10-10 15:53:25 -04:00
Gabe Black
3a9eb598c3 Merge zizzer.eecs.umich.edu:/bk/newmem
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus

--HG--
extra : convert_revision : 6027c395af044858465eafd3ea78bcfe4c923bcc
2006-10-10 15:04:55 -04:00
Ron Dreslinski
fe8b912c03 Merge zizzer:/z/m5/Bitkeeper/newmem
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : 87f83c4edf6ea51adc767d98265d1e74c0fbb46f
2006-10-10 02:36:04 -04:00
Ron Dreslinski
3fa5e4b6b8 Yet another fix to the HasData command attribute.
--HG--
extra : convert_revision : dcf0d7eafa5168591c2b374b452821ca34dde7f9
2006-10-10 02:33:30 -04:00
Ron Dreslinski
b40798070b Actually set the HasData attribute on Read Responses
--HG--
extra : convert_revision : 129dadbf8091ab00fb7f16eace59df265fc3718c
2006-10-10 02:21:03 -04:00
Ron Dreslinski
89e80ccc20 Fix another merge issue
--HG--
extra : convert_revision : 2b33da5e8578ea6a8bdd2d89f183c2e6b942b0fc
2006-10-10 02:00:37 -04:00
Ron Dreslinski
a0472af008 Merge zizzer:/z/m5/Bitkeeper/newmem
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

src/mem/packet.hh:
    Hand merge code

--HG--
extra : convert_revision : d659418f24f4f4bf9867fec8573a5d227c0dfcea
2006-10-10 01:57:57 -04:00
Kevin Lim
e5b13138b1 Two minor fixes.
configs/common/SysPaths.py:
    Undo accidental change.
src/SConscript:
    Fix.

--HG--
extra : convert_revision : 665b186cff7d8ae560601ced7ae407a41a16cfea
2006-10-10 01:49:46 -04:00
Ron Dreslinski
cc78d86661 Fix several bugs pertaining to upgrades/mem leaks.
src/mem/cache/base_cache.cc:
    Fix a bug about not having a request to send
src/mem/cache/base_cache.hh:
    Fix a bug with the blocking code
src/mem/cache/cache.hh:
    AFix a bug with snoop hits in WB buffer
src/mem/cache/cache_impl.hh:
    Fix a bug with snoop hits in WB buffer
    Also, add better DPRINTF's
src/mem/cache/miss/miss_queue.cc:
    Fix a bug with upgrades (Need to clean it up later)
src/mem/cache/miss/mshr.cc:
    Fix a memory leak bug, still some outstanding with writebacks not being deleted
src/mem/cache/miss/mshr_queue.cc:
    Fix a bug about upgrades (need to clean up later)
src/mem/packet.hh:
    Fix for newly added cmd attribute for upgrades
tests/configs/memtest.py:
    More interesting testcase

--HG--
extra : convert_revision : fcb4f17dd58b537bb4f67a8c835f50e455e8c688
2006-10-10 01:32:18 -04:00
Gabe Black
5582e60966 Fixed a bug where a packet was attempted to be sent even though another packet was waiting for the bus.
--HG--
extra : convert_revision : 29f7a4f676884330d7b7e93517dea85fc7bbf678
2006-10-10 00:49:27 -04:00
Gabe Black
ab44417282 Fixes to the bus, and added fields to the packet.
src/mem/bus.cc:
    Put back the check to see if the bus is busy. Also, populate the fields in the packet to indicate when the first word and the entire packet will be delivered.
src/mem/bus.hh:
    Remove the occupyBus function.
src/mem/packet.hh:
    Added fields to the packet to indicate when the first chunk of a packet arrives, and when the entire packet arrives.

--HG--
extra : convert_revision : cfc7670a33913d48a04d02c6d2448290a51f2d3c
2006-10-09 23:24:21 -04:00
Kevin Lim
bdde892d66 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem

src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
src/cpu/simple/timing.hh:
tests/configs/o3-timing-mp.py:
    Hand merge.

--HG--
extra : convert_revision : a58cc439eb5e8f900d175ed8b5a85b6c8723e558
2006-10-09 22:59:56 -04:00
Kevin Lim
a9ae6c8656 Comment out code that messed up SMT (but will be needed eventually).
src/cpu/o3/cpu.cc:
    Comment out reseting CPU structures for now.  This can be updated to work in the future.

--HG--
extra : convert_revision : bc1a86e2fe47da5acb14ba8b64568b0355431f1c
2006-10-09 22:49:58 -04:00
Ron Dreslinski
ec8a437b2c Handle NACK's that occur from devices on the same bus.
Not fully implemented yet, but good enough for single level cache coherence

src/mem/packet.hh:
    Add a bit to distinguish invalidates and upgrades

--HG--
extra : convert_revision : 5bf50d535857cea37fbdaf7993915d1332cb757e
2006-10-09 20:18:00 -04:00
Gabe Black
843888c489 Merge zizzer.eecs.umich.edu:/bk/newmem
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus

--HG--
extra : convert_revision : 2adde42edead2cedeeba60cc0d2697a2d58682be
2006-10-09 19:35:53 -04:00
Ron Dreslinski
9356bcda7b Fix a typo preventing compilation
--HG--
extra : convert_revision : 9158d81231cd1d083393576744ce80afd0b74867
2006-10-09 19:20:28 -04:00
Ron Dreslinski
e03b9c9939 Fix how upgrades work.
Remove some dead code.

src/mem/cache/cache_impl.hh:
    Upgrades don't need a response.
    Moved satisfied check into bus so removed some dead code.
src/mem/cache/coherence/coherence_protocol.cc:
src/mem/packet.hh:
    Upgrades don't require a response

--HG--
extra : convert_revision : dee0440ff19ba4c9e51bf9a47a5b0991265cfc1d
2006-10-09 19:15:24 -04:00
Kevin Lim
92bf23bed6 Be sure to delete packet and sender state if the cache is blocked.
src/cpu/o3/lsq_unit.hh:
    Be sure to delete data if the cache is blocked.

--HG--
extra : convert_revision : fafbcfb8937e85555823942e69e798e557a600e5
2006-10-09 19:14:14 -04:00
Kevin Lim
af7315c7dc Fix caches plus sampling switch over.
src/cpu/o3/cpu.cc:
    Fix up caches plus sampling switch over.

--HG--
extra : convert_revision : 49d0c16d4c5e8d5ba83749d568a4efe3b42e3a97
2006-10-09 19:13:06 -04:00
Ron Dreslinski
13ac9a419d One step closet to having NACK's work.
src/cpu/memtest/memtest.cc:
    Fix functional return path
src/cpu/memtest/memtest.hh:
    Add snoop ranges in
src/mem/cache/base_cache.cc:
    Properly signal NACKED
src/mem/cache/cache_impl.hh:
    Catch nacked packet and panic for now

--HG--
extra : convert_revision : 59a64e82254dfa206681c5f987e6939167754d67
2006-10-09 18:52:20 -04:00
Gabe Black
a23c6a7193 Merge zizzer.eecs.umich.edu:/bk/newmem
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus

--HG--
extra : convert_revision : 8267487b935eaf11665841ace3a5c664751b53b0
2006-10-09 18:19:35 -04:00
Gabe Black
187dcb18bf Potentially functional partially timed bandwidth limitted bus model.
src/mem/bus.cc:
    Fixes to the previous hand merging, and put the snooping back into recvTiming and out of it's own function.
src/mem/bus.hh:
    Put snooping back into recvTiming and not in it's own function.

--HG--
extra : convert_revision : fd031b7e6051a5be07ed6926454fde73b1739dc6
2006-10-09 18:12:45 -04:00
Ron Dreslinski
c4dba7a8ed Fix a typo in the printf
--HG--
extra : convert_revision : bfa8ffae0a9bef25ceca168ff376ba816abf23f3
2006-10-09 17:30:54 -04:00
Ron Dreslinski
fd27c229b6 Fix a bitwise operation that was accidentally a logical operation.
--HG--
extra : convert_revision : 30f64bcb6bea47fd8cd6d77b0df17eff04dbbad0
2006-10-09 17:18:34 -04:00
Ron Dreslinski
b9fb4d4870 Make memtest work with 8 memtesters
src/mem/physical.cc:
    Update comment to match memtest use
src/python/m5/objects/PhysicalMemory.py:
    Make memtester have a way to connect functionally
tests/configs/memtest.py:
    Properly create 8 memtesters and connect them to the memory system

--HG--
extra : convert_revision : e5a2dd9c8918d58051b553b5c6a14785d48b34ca
2006-10-09 17:13:50 -04:00
Ron Dreslinski
d7c1557e7e Merge zizzer:/z/m5/Bitkeeper/newmem
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : b4cb1702ffa2fca298cfde47683cac019e1da900
2006-10-09 16:48:58 -04:00
Ron Dreslinski
45732376f6 Add more DPRINTF's fix a supply condition.
src/mem/cache/cache_impl.hh:
    Add more usefull DPRINTF's
    REmove the PC to get rid of asserts

--HG--
extra : convert_revision : 3f6d832b138d058dbe79bb5f42bd2db9c50b35b5
2006-10-09 16:47:55 -04:00
Ron Dreslinski
afce51d10a Set size properly on uncache accesses
Don't use the senderState after you get a succesful sendTiming.  Not guarnteed to be correct

src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/blocking_buffer.hh:
src/mem/cache/miss/miss_queue.hh:
    Don't use the senderState after you get a succesful sendTiming.  Not guarnteed to be correct

--HG--
extra : convert_revision : 2e8e812bf7fd3ba2b4cba7f7173cb41862f761af
2006-10-09 16:37:02 -04:00
Kevin Lim
d95b23b81f Fix outstanding bug (FS#158).
src/cpu/o3/cpu.cc:
    Extra debugging, fix a bug brought up on bug tracker.

--HG--
extra : convert_revision : 23f8b166ba0d0af54e15b651ed28f59a1bc9d2f2
2006-10-09 11:01:19 -04:00
Kevin Lim
6a2d6c0f83 Fix checker bug.
src/cpu/checker/thread_context.hh:
    Checker's TC should only copy state, and not fully take over from the old context (prevents it from accidentally stealing the quiesce event).

--HG--
extra : convert_revision : 5760f9c5bae749f8d1df35e4c898df13e41b0224
2006-10-09 11:00:31 -04:00
Ron Dreslinski
bc732b59fd Have cpus send snoop ranges
--HG--
extra : convert_revision : 2a1fba141e409ee1d7a0b69b5b21d236e3d4ce68
2006-10-09 01:04:37 -04:00
Ron Dreslinski
095d5991f5 Put a check in so people know not to create more than 8 memtesters.
--HG--
extra : convert_revision : 41ab297dc681b2601be1df33aba30c39f49466d8
2006-10-09 00:31:24 -04:00
Ron Dreslinski
95ca4f9d4a Merge zizzer:/z/m5/Bitkeeper/newmem
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : 77b06379a520dd91f124c0a543e30ec3a9cd1452
2006-10-09 00:28:26 -04:00
Ron Dreslinski
0087061681 Don't create a response if one isn't needed.
--HG--
extra : convert_revision : 37bd230f527f64eb12779157869aae9dcfdde7fd
2006-10-09 00:27:41 -04:00
Ron Dreslinski
4f93c43d34 Don't block responses even if the cache is blocked.
--HG--
extra : convert_revision : a1558eb55806b2a3e7e63249601df2c143e2235d
2006-10-09 00:27:03 -04:00
Ron Dreslinski
6c7ab02682 Update the Memtester, commit a config file/test for it.
src/cpu/SConscript:
    Add memtester to the compilation environment.
    Someone who knows this better should make the MemTest a cpu model parameter.

    For now attached with the build of o3 cpu.
src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
    Update Memtest for new mem system
src/python/m5/objects/MemTest.py:
    Update memtest python description

--HG--
extra : convert_revision : d6a63e08fda0975a7abfb23814a86a0caf53e482
2006-10-09 00:26:10 -04:00
Kevin Lim
4167c3c026 Update memory assertion to check for whole range.
src/mem/physical.cc:
    Update assertion to check for full range.

--HG--
extra : convert_revision : ee815702ba4dd6ae1169c0595c978dd153014c73
2006-10-09 00:09:44 -04:00
Lisa Hsu
67c20dd9dd Merge zizzer:/bk/newmem
into  zed.eecs.umich.edu:/z/hsul/work/m5/newmem

--HG--
extra : convert_revision : a0775bf59ff7049b76917b1ab551bc28efd56b3d
2006-10-08 23:19:03 -04:00
Lisa Hsu
97c1f6eff7 post checkpoint restoration the bus ranges need to be re-initialized for ALL pci devs, not just ide.
src/dev/ide_ctrl.cc:
    this range change needs to be done for all pio devices, not just the ide.
src/dev/pcidev.cc:
    range change needs to be done at here, not in the ide_ctrl file.

--HG--
extra : convert_revision : 60c65c55e965b02d671dba7aa8793e5a81f40348
2006-10-08 23:18:19 -04:00
Lisa Hsu
d52117d1e3 add in serialization of AtomicSimpleCPU _status. This is needed because right now unserializing breaks an assert since CPU status is not saved. Kev says that this will break uniform serialization across CPUs since each type of CPU has its own "status" enum set. So, the repercussions are that if you serialize in this CPU, you must first unserialize in this CPU before switching to something else you want.
src/cpu/simple/atomic.cc:
    add in serialization of AtomicSimpleCPU _status.  Kev says that this will break uniform serialization across CPUs since each type of CPU has its own "status" enum set.  So, the repercussions are that if you serialize in this CPU, you must first unserialize in this CPU before switching to something else you want.

--HG--
extra : convert_revision : 7000f660aecea6fef712bf81853d9a7b90d625ee
2006-10-08 23:16:40 -04:00
Steve Reinhardt
31f3f24214 Fixes for Port proxies and proxy parameters.
--HG--
extra : convert_revision : 76b16fe2926611bd1c12c8ad7392355ad30a5138
2006-10-08 18:26:59 -07:00
Ron Dreslinski
4cfddc0d77 Make sure to propogate sendFunctional calls with functional not atomic.
src/mem/cache/cache_impl.hh:
    Fix a error case by putting a panic in.
    Make sure to propogate sendFunctional calls with functional not atomic.

--HG--
extra : convert_revision : 05d03f729a40cfa3ecb68bcba172eb560b24e897
2006-10-08 20:47:50 -04:00
Ron Dreslinski
5cb1840b31 Fixes for functional path.
If the cpu needs to update any state when it gets a functional write (LSQ??)
then that code needs to be written.

src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
    CPU's can recieve functional accesses, they need to determine if they need to do anything with them.
src/mem/bus.cc:
src/mem/bus.hh:
    Make the fuctional path do the correct tye of snoop

--HG--
extra : convert_revision : 70d09f954b907a8aa9b8137579cd2b06e02ae2ff
2006-10-08 20:30:42 -04:00
Gabe Black
2df9053bb0 Merge zizzer.eecs.umich.edu:/bk/newmem
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus

src/mem/bus.cc:
    Hand merged. Needs to be fixed

--HG--
extra : convert_revision : df03219ccfd18431cc726a063bd29d30554944a1
2006-10-08 19:14:09 -04:00
Ron Dreslinski
e65f0cef3c Only respond if the pkt needs a response.
Fix an issue with memory handling writebacks.

src/mem/cache/base_cache.hh:
src/mem/tport.cc:
    Only respond if the pkt needs a response.
src/mem/physical.cc:
    Make physical memory respond to writebacks, set satisfied for invalidates/upgrades.

--HG--
extra : convert_revision : 7601987a7923e54a6d1a168def4f8133d8de19fd
2006-10-08 19:05:48 -04:00
Ron Dreslinski
8a539a774f Merge zizzer:/z/m5/Bitkeeper/newmem
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : f3067efb7f3ff30158d541dfc52de4ea8edae576
2006-10-08 18:49:30 -04:00
Ron Dreslinski
1345183a89 Move away from using the statusChange function on snoops. Clean up snooping code in general.
--HG--
extra : convert_revision : 5a57bfd7742a212047fc32e8cae0dc602fdc915c
2006-10-08 18:48:03 -04:00
Gabe Black
0c574f1069 missing else
--HG--
extra : convert_revision : 8fe0e00dc3ae70b4449a78c15dd249939e644f02
2006-10-08 18:45:21 -04:00
Gabe Black
a82f017591 bus changes
src/mem/bus.cc:
src/mem/bus.hh:
    minor fix and some formatting changes
src/python/m5/objects/Bus.py:
    changed bits to bytes

--HG--
extra : convert_revision : dcd22205604b7a2727eaf2094084c4858f3589c5
2006-10-08 18:44:49 -04:00
Steve Reinhardt
5df93cc1cd Replace tests of LOCKED/UNCACHEABLE flags with isLocked()/isUncacheable().
--HG--
extra : convert_revision : f22ce3221d270ecf8631d3dcaed05753accd5461
2006-10-08 14:48:24 -07:00
Gabe Black
63023ba4c2 Merge zizzer.eecs.umich.edu:/bk/newmem
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus

--HG--
extra : convert_revision : 1749397443ccb320d32f8dd23c71ed0431d30cb7
2006-10-08 14:09:13 -04:00
Gabe Black
00481d1f19 A possible implementation of a multiplexed bus.
--HG--
extra : convert_revision : 3c560eda12ffd8ca539c91024baf2770b963ede8
2006-10-08 14:08:58 -04:00
Gabe Black
34b697cd04 Add in HasData, and move the define of NUM_MEM_CMDS to a more visible location.
--HG--
extra : convert_revision : 4379efe892ca0a39363ee04009e1bbb8c8f77afa
2006-10-08 14:04:49 -04:00
Steve Reinhardt
d3fba5aa30 Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)
and PhysicalMemory.  *No* support for caches or O3CPU.
Note that properly setting cpu_id on all CPUs is now required
for correct operation.

src/arch/SConscript:
src/base/traceflags.py:
src/cpu/base.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/request.hh:
src/python/m5/objects/BaseCPU.py:
tests/configs/simple-atomic.py:
tests/configs/simple-timing.py:
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
    Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)
    and PhysicalMemory.  *No* support for caches or O3CPU.

--HG--
extra : convert_revision : 6ce982d44924cc477e049b9adf359818908e72be
2006-10-08 10:53:24 -07:00
Steve Reinhardt
be36c808f7 Rename some vars for clarity.
--HG--
extra : convert_revision : 765283ae54d2d6b5885ea44c6c1813d4bcf18488
2006-10-08 10:43:31 -07:00
Steve Reinhardt
c2f954ac69 Allocate new thread stacks and shared mem region via Process page table
for Tru64 thread library emulation.

--HG--
extra : convert_revision : dbd307536e260e24ef79130d2aa88d84e33f03d4
2006-10-08 04:29:40 -04:00
Kevin Lim
8949d813ff Clean up configs.
configs/common/FSConfig.py:
configs/common/SysPaths.py:
configs/example/fs.py:
configs/example/se.py:
tests/configs/o3-timing-mp.py:
tests/configs/o3-timing.py:
    Clean up configs by removing FullO3Config and instead using default values.
src/python/m5/objects/FUPool.py:
    Add in default FUPool.
src/python/m5/objects/O3CPU.py:
    Use defaults better.  Also set checker parameters, and fix up a config bug.

--HG--
extra : convert_revision : 5fd0c000143f4881f10a9a575c3810dc97cb290b
2006-10-08 01:12:42 -04:00
Kevin Lim
b17421da20 Record numCycles properly.
src/cpu/simple/timing.cc:
    Record numCycles stat properly.
src/cpu/simple/timing.hh:
    Extra variable to help record numCycles stat.

--HG--
extra : convert_revision : 343311902831820264878aad41dc619999726b6b
2006-10-08 00:55:05 -04:00
Kevin Lim
d48ea81ba2 Updates to O3 CPU. It should now work in FS mode, although sampling still has a bug.
src/cpu/o3/commit_impl.hh:
    Fixes for compile and sampling.
src/cpu/o3/cpu.cc:
    Deallocate and activate threads properly.  Also hopefully fix being able to use caches while switching over.
src/cpu/o3/cpu.hh:
    Fixes for deallocating and activating threads.
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_unit.hh:
    Handle getting back a BadAddress result from the access.
src/cpu/o3/iew_impl.hh:
    More debug output.
src/cpu/o3/lsq_unit_impl.hh:
    Fixup store conditional handling (still a bit of a hack, but works now).

    Also handle getting back a BadAddress result from the access.
src/cpu/o3/thread_context_impl.hh:
    Deallocate context now records if the context should be fully removed.

--HG--
extra : convert_revision : 55f81660602d0e25367ce1f5b0b9cfc62abe7bf9
2006-10-08 00:53:41 -04:00
Kevin Lim
c0e53b6d4c Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem

--HG--
extra : convert_revision : 0309a453c0d65579cfa022888d1a2ab4f0171a9f
2006-10-07 23:35:32 -04:00
Ali Saidi
abc27ae691 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem.head

--HG--
extra : convert_revision : acab791328d16daace6dfbdc667067ddc68fb6ca
2006-10-07 14:49:10 -04:00
Kevin Lim
3afc69df77 Merge ktlim@zizzer:/bk/newmem
into  zizzer.eecs.umich.edu:/.automount/zamp/z/ktlim2/clean/o3-merge/newmem

--HG--
extra : convert_revision : b013b35f5c2264712eb51bef5623b208eb6128f9
2006-10-07 13:41:49 -04:00
Kevin Lim
fe762278e7 Updates to bring MemTest closer to working with newmem. Ron still needs to do the initial setup and configuration for it to work properly.
src/SConscript:
    Include MemTest for now.  It's not complete but it compiles so it shouldn't mess anything else up.

--HG--
extra : convert_revision : 15a610c855b677fdced817850c92e4c911cf6d1c
2006-10-07 13:37:22 -04:00
Ron Dreslinski
467c17fbd9 Fix a missing pointer
--HG--
extra : convert_revision : 2056b530d48fd004ab700f09e58f44adae3ea0e9
2006-10-07 12:55:37 -04:00
Ron Dreslinski
fdaed2c7ae No need to keep trying to request the data bus if we are already waiting.
--HG--
extra : convert_revision : dbaad52ed8d0841dc9224661e3df0d8ef4989aa3
2006-10-07 12:20:29 -04:00
Ron Dreslinski
df3014a726 Add mechanism for caches to handle failure of the fast path on responses.
For now, responses have priority over requests (may want to revist this).

src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
    Add mechanism for caches to handle failure of the fast path on responses.

--HG--
extra : convert_revision : 01524c727d1bb300cc21bdc989eb862ec8bf0b7a
2006-10-07 12:02:59 -04:00
Ron Dreslinski
178d114fa5 Fix infinite writebacks bug in cache.
src/mem/cache/cache_impl.hh:
    Make sure to pop the list.  Fixes infinite writeback bug.
src/mem/cache/miss/mshr_queue.cc:
    Add an assert as sanity check in case .full() stops working again.

--HG--
extra : convert_revision : d847e49a397eeb0b7c5ac060fcfc3eaeac921311
2006-10-07 11:36:55 -04:00
Ali Saidi
c60c61b19e Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem.head

--HG--
extra : convert_revision : 326605820dce7641058eb0cdc0ddb2cc9602f67e
2006-10-06 21:46:04 -04:00
Ali Saidi
b7832555d5 system.cc:
Make new_page() check for an out of memory condition

src/sim/system.cc:
    Make new_page() check for an out of memory condition

--HG--
extra : convert_revision : daee82788464fca186eb24285b5f43c9fabc25b3
2006-10-06 21:45:34 -04:00
Gabe Black
862825f997 Merge zizzer.eecs.umich.edu:/bk/newmem
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus

--HG--
extra : convert_revision : 8b5536f276527adcc27e11e790262232aeb61b13
2006-10-06 17:10:13 -04:00
Ron Dreslinski
c42a7bc4f6 Merge zizzer:/z/m5/Bitkeeper/newmem
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : 2f1bbe84c92879fd1bfa579adc62a367ece1cddd
2006-10-06 09:28:16 -04:00
Ron Dreslinski
dfdb683fb9 Another thread number removed
--HG--
extra : convert_revision : 4cfb83b8162745d686e8697f29f74f37b1a71525
2006-10-06 09:27:59 -04:00
Ron Dreslinski
1b6653b6f7 Remove threadnum from cache everywhere for now
Fix so that blocking for the same reason doesn't fail.  I.E. multiple writebacks want to set the blocked flag.

src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/miss_queue.cc:
src/mem/cache/miss/mshr.cc:
    Remove threadnum from cache everywhere for now

--HG--
extra : convert_revision : 7890712147655280b4f1439d486feafbd5b18b2b
2006-10-06 09:15:53 -04:00
Lisa Hsu
fb3a30f87c checkpoint recovery was screwed up because a new section was created in the middle of another section and messed up unserializing.
--HG--
extra : convert_revision : 7af15fdc9e8d203b26840a2eb5fef511b6a2b21d
2006-10-06 01:29:50 -04:00
Lisa Hsu
9c901225f8 there are two main thrusts of this changeset.
1) return the periodicity of checkpoints back into the code (i.e. make m5 checkpoint n m meaningful again).
2) to do this, i had to much around with being able to repeatedly schedule and SimLoopExitEvent, which led to changes in how exit simloop events are handled to make this easier.

src/arch/alpha/isa/decoder.isa:
src/mem/cache/cache_impl.hh:
    modify arg. order for new calling convention of exitSimLoop.
src/cpu/base.cc:
src/sim/main.cc:
src/sim/pseudo_inst.cc:
src/sim/root.cc:
    now, instead of creating a new SimLoopExitEvent, call a wrapper schedExitSimLoop which handles all the default args.
src/sim/sim_events.cc:
src/sim/sim_events.hh:
src/sim/sim_exit.hh:
    add the periodicity of checkpointing back into the code.

    to facilitate this, there are now two wrappers (instead of just overloading exitSimLoop).  exitSimLoop is only for exiting NOW (i.e. at curTick), while schedExitSimLoop schedules and exit event for the future.

--HG--
extra : convert_revision : c61f4bf05517172edd2c83368fd10bb0f0678029
2006-10-06 01:27:02 -04:00
Nathan Binkert
dfa065ad16 Merge zizzer.eecs.umich.edu:/bk/newmem
into  iceaxe.:/Volumes/work/research/m5/incoming

--HG--
extra : convert_revision : b4d6a36ee07d858829369027127e00a2aec097fd
2006-10-05 21:16:42 -07:00
Nathan Binkert
8dcca68234 remove traces of binning
--HG--
extra : convert_revision : b33cc67cfde04c9af6f50cbef538104e1298bedc
2006-10-05 21:14:43 -07:00
Ron Dreslinski
212c5aefb5 Fixes for functional accesses to use the snoop path.
And small other tweaks to snooping coherence.

src/mem/cache/base_cache.hh:
    Make timing response at the time of send.
src/mem/cache/cache.hh:
src/mem/cache/cache_impl.hh:
    Update probe interface to be bi-directional for functional accesses
src/mem/packet.hh:
    Add the function to create an atomic response to a given request

--HG--
extra : convert_revision : 04075a117cf30a7df16e6d3ce485543cc77d4ca6
2006-10-05 23:28:03 -04:00
Ron Dreslinski
45f881a4ce First pass at snooping stuff that compiles and doesn't break.
Still need:
-Handle NACK's on the recieve side
-Distinguish top level caches
-Handle repsonses from caches failing the fast path
-Handle BusError and propogate it
-Fix the invalidate packet associated with snooping in the cache

src/mem/bus.cc:
    Make sure to snoop on functional accesses
src/mem/cache/base_cache.cc:
    Wait to make a request into a response until it is ready to be issued
src/mem/cache/base_cache.hh:
    Support range changes for snoops
    Set up snoop responses for cache->cache transfers
src/mem/cache/cache_impl.hh:
    Only access the cache if it wasn't satisfied by cache->cache transfer
    Handle snoop phases (detect block, then snoop)
    Fix functional access to work properly (still need to fix snoop path for functional accesses)

--HG--
extra : convert_revision : 4c25f11d7a996c1f56f4f7b55dde87a344e5fdf8
2006-10-05 21:10:03 -04:00
Gabe Black
d9172c8f46 Partial reimplementation of the bus. The "clock" and "width" parameters have been added, and the HasData flag has been partially added to packets.
--HG--
extra : convert_revision : abb2a259fcf843457abbc0bd36f9504fbe6d7d39
2006-10-05 16:26:16 -04:00
Lisa Hsu
868d112578 fix the argument to m5.simulate() on a checkpoint.
src/sim/stat_control.cc:
    add curTick to reset stats printf.

--HG--
extra : convert_revision : da8cf5921e81b73f47d6831d539ca1fbdace3d1d
2006-10-05 13:18:32 -04:00
Nathan Binkert
4142f8f7c0 Static global object don't work well, if the variables are
accessed during the construction of another static global
object because there are no guarantees on ordering of
construction, so stick the static global into a function
as a static local and return a reference to the variable.
This fixes the exit callback stuff on my Mac.

--HG--
extra : convert_revision : 63a3844d0b5ee18e2011f1bc7ca7bb703284da94
2006-10-05 03:37:43 -07:00
Gabe Black
6a31898a88 Merge zizzer.eecs.umich.edu:/bk/newmem
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem

--HG--
extra : convert_revision : f7d41fc21c7eeca6edde0b01f2e8844e3e19c51a
2006-10-02 18:35:36 -04:00
Kevin Lim
51c8eab7b3 Oops, forgot to assign the option to the param context.
--HG--
extra : convert_revision : 022c3efaa3ade3fca3dfe554ececa4eeb396dc9c
2006-10-02 18:13:42 -04:00
Kevin Lim
cada047319 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem

--HG--
extra : convert_revision : 1010a4ee8e1abec0e8290637feee523ca9ef9a9b
2006-10-02 18:12:21 -04:00
Kevin Lim
c78b6634a2 Be sure to set progress interval.
--HG--
extra : convert_revision : 793ca7d6af1deedf6b1fb4676288b11114f583a6
2006-10-02 18:10:10 -04:00
Gabe Black
e8ced44aea Merge zizzer.eecs.umich.edu:/bk/newmem
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem

src/cpu/ozone/cpu_impl.hh:
    Hand merged

--HG--
extra : convert_revision : f8a5b0205bcb78c8f5e109f456fe7bca80a7abac
2006-10-02 14:32:02 -04:00
Kevin Lim
e08aa72b3d Add in ability to start a trace at a specific cycle.
--HG--
extra : convert_revision : 54098f3974d2a05d60e57113f7ceb46cb7a26672
2006-10-02 12:04:24 -04:00
Kevin Lim
568fa11084 Updates to fix merge issues and bring almost everything up to working speed. Ozone CPU remains untested, but everything else compiles and runs.
src/arch/alpha/isa_traits.hh:
    This got changed to the wrong version by accident.
src/cpu/base.cc:
    Fix up progress event to not schedule itself if the interval is set to 0.
src/cpu/base.hh:
    Fix up the CPU Progress Event to not print itself if it's set to 0.  Also remove stats_reset_inst (something I added to m5 but isn't necessary here).
src/cpu/base_dyn_inst.hh:
src/cpu/checker/cpu.hh:
    Remove float variable of instResult; it's always held within the double part now.
src/cpu/checker/cpu_impl.hh:
    Use thread and not cpuXC.
src/cpu/o3/alpha/cpu_builder.cc:
src/cpu/o3/checker_builder.cc:
src/cpu/ozone/checker_builder.cc:
src/cpu/ozone/cpu_builder.cc:
src/python/m5/objects/BaseCPU.py:
    Remove stats_reset_inst.
src/cpu/o3/commit_impl.hh:
src/cpu/ozone/lw_back_end_impl.hh:
    Get TC, not XCProxy.
src/cpu/o3/cpu.cc:
    Switch out updates from the version of m5 I have.  Also remove serialize code that got added twice.
src/cpu/o3/iew_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/thread_state.hh:
    Remove code that was added twice.
src/cpu/o3/lsq_unit.hh:
    Add back in stats that got lost in the merge.
src/cpu/o3/lsq_unit_impl.hh:
    Use proper method to get flags.  Also wake CPU if we're coming back from a cache miss.
src/cpu/o3/thread_context_impl.hh:
src/cpu/o3/thread_state.hh:
    Support profiling.
src/cpu/ozone/cpu.hh:
    Update to use proper typename.
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/dyn_inst_impl.hh:
    Updates for newmem.
src/cpu/ozone/lw_lsq_impl.hh:
    Get flags correctly.
src/cpu/ozone/thread_state.hh:
    Reorder constructor initialization, use tc.
src/sim/pseudo_inst.cc:
    Allow for loading of symbol file.  Be sure to use ThreadContext and not ExecContext.

--HG--
extra : convert_revision : c5657f84155807475ab4a1e20d944bb6f0d79d94
2006-10-02 11:58:09 -04:00
Kevin Lim
4ed184eade Merge ktlim@zamp:./local/clean/o3-merge/m5
into  zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem

configs/boot/micro_memlat.rcS:
configs/boot/micro_tlblat.rcS:
src/arch/alpha/ev5.cc:
src/arch/alpha/isa/decoder.isa:
src/arch/alpha/isa_traits.hh:
src/cpu/base.cc:
src/cpu/base.hh:
src/cpu/base_dyn_inst.hh:
src/cpu/checker/cpu.hh:
src/cpu/checker/cpu_impl.hh:
src/cpu/o3/alpha/cpu_impl.hh:
src/cpu/o3/alpha/params.hh:
src/cpu/o3/checker_builder.cc:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue.hh:
src/cpu/o3/lsq.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/lsq_unit_impl.hh:
src/cpu/o3/regfile.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/checker_builder.cc:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_back_end.hh:
src/cpu/ozone/lw_back_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/simple/base.cc:
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
src/cpu/thread_state.hh:
src/dev/ide_disk.cc:
src/python/m5/objects/O3CPU.py:
src/python/m5/objects/Root.py:
src/python/m5/objects/System.py:
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
src/sim/system.hh:
util/m5/m5.c:
    Hand merge.

--HG--
rename : arch/alpha/ev5.cc => src/arch/alpha/ev5.cc
rename : arch/alpha/freebsd/system.cc => src/arch/alpha/freebsd/system.cc
rename : arch/alpha/isa/decoder.isa => src/arch/alpha/isa/decoder.isa
rename : arch/alpha/isa/mem.isa => src/arch/alpha/isa/mem.isa
rename : arch/alpha/isa_traits.hh => src/arch/alpha/isa_traits.hh
rename : arch/alpha/linux/system.cc => src/arch/alpha/linux/system.cc
rename : arch/alpha/system.cc => src/arch/alpha/system.cc
rename : arch/alpha/tru64/system.cc => src/arch/alpha/tru64/system.cc
rename : cpu/base.cc => src/cpu/base.cc
rename : cpu/base.hh => src/cpu/base.hh
rename : cpu/base_dyn_inst.hh => src/cpu/base_dyn_inst.hh
rename : cpu/checker/cpu.hh => src/cpu/checker/cpu.hh
rename : cpu/checker/cpu.cc => src/cpu/checker/cpu_impl.hh
rename : cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha/cpu_builder.cc
rename : cpu/checker/o3_cpu_builder.cc => src/cpu/o3/checker_builder.cc
rename : cpu/o3/commit_impl.hh => src/cpu/o3/commit_impl.hh
rename : cpu/o3/cpu.cc => src/cpu/o3/cpu.cc
rename : cpu/o3/fetch_impl.hh => src/cpu/o3/fetch_impl.hh
rename : cpu/o3/iew.hh => src/cpu/o3/iew.hh
rename : cpu/o3/iew_impl.hh => src/cpu/o3/iew_impl.hh
rename : cpu/o3/inst_queue.hh => src/cpu/o3/inst_queue.hh
rename : cpu/o3/inst_queue_impl.hh => src/cpu/o3/inst_queue_impl.hh
rename : cpu/o3/lsq_impl.hh => src/cpu/o3/lsq_impl.hh
rename : cpu/o3/lsq_unit.hh => src/cpu/o3/lsq_unit.hh
rename : cpu/o3/lsq_unit_impl.hh => src/cpu/o3/lsq_unit_impl.hh
rename : cpu/o3/mem_dep_unit_impl.hh => src/cpu/o3/mem_dep_unit_impl.hh
rename : cpu/o3/rename.hh => src/cpu/o3/rename.hh
rename : cpu/o3/rename_impl.hh => src/cpu/o3/rename_impl.hh
rename : cpu/o3/thread_state.hh => src/cpu/o3/thread_state.hh
rename : cpu/o3/tournament_pred.cc => src/cpu/o3/tournament_pred.cc
rename : cpu/o3/tournament_pred.hh => src/cpu/o3/tournament_pred.hh
rename : cpu/checker/cpu_builder.cc => src/cpu/ozone/checker_builder.cc
rename : cpu/ozone/cpu.hh => src/cpu/ozone/cpu.hh
rename : cpu/ozone/cpu_builder.cc => src/cpu/ozone/cpu_builder.cc
rename : cpu/ozone/cpu_impl.hh => src/cpu/ozone/cpu_impl.hh
rename : cpu/ozone/front_end.hh => src/cpu/ozone/front_end.hh
rename : cpu/ozone/front_end_impl.hh => src/cpu/ozone/front_end_impl.hh
rename : cpu/ozone/inorder_back_end_impl.hh => src/cpu/ozone/inorder_back_end_impl.hh
rename : cpu/ozone/inst_queue_impl.hh => src/cpu/ozone/inst_queue_impl.hh
rename : cpu/ozone/lw_back_end.hh => src/cpu/ozone/lw_back_end.hh
rename : cpu/ozone/lw_back_end_impl.hh => src/cpu/ozone/lw_back_end_impl.hh
rename : cpu/ozone/lw_lsq.hh => src/cpu/ozone/lw_lsq.hh
rename : cpu/ozone/lw_lsq_impl.hh => src/cpu/ozone/lw_lsq_impl.hh
rename : cpu/ozone/simple_params.hh => src/cpu/ozone/simple_params.hh
rename : cpu/ozone/thread_state.hh => src/cpu/ozone/thread_state.hh
rename : cpu/simple/cpu.cc => src/cpu/simple/base.cc
rename : cpu/cpu_exec_context.cc => src/cpu/simple_thread.cc
rename : cpu/thread_state.hh => src/cpu/thread_state.hh
rename : dev/ide_disk.hh => src/dev/ide_disk.hh
rename : python/m5/objects/BaseCPU.py => src/python/m5/objects/BaseCPU.py
rename : python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/O3CPU.py
rename : python/m5/objects/OzoneCPU.py => src/python/m5/objects/OzoneCPU.py
rename : python/m5/objects/Root.py => src/python/m5/objects/Root.py
rename : python/m5/objects/System.py => src/python/m5/objects/System.py
rename : sim/eventq.hh => src/sim/eventq.hh
rename : sim/pseudo_inst.cc => src/sim/pseudo_inst.cc
rename : sim/pseudo_inst.hh => src/sim/pseudo_inst.hh
rename : sim/serialize.cc => src/sim/serialize.cc
rename : sim/stat_control.cc => src/sim/stat_control.cc
rename : sim/stat_control.hh => src/sim/stat_control.hh
rename : sim/system.hh => src/sim/system.hh
extra : convert_revision : 135d90e43f6cea89f9460ba4e23f4b0b85886e7d
2006-09-30 23:43:23 -04:00
Gabe Black
333eb4efea Basic work towards supporting ASIs properly
src/arch/sparc/SConscript:
    Added a file that implements ASI utility functions. These don't go in utility.hh because they aren't supposed to be part of the generic ISA interface.
src/arch/sparc/asi.hh:
    Fixed up some mistranscriptions, and added function prototypes for some ASI utility functions.
src/arch/sparc/asi.cc:
    Implementation of some ASI utility functions.

--HG--
extra : convert_revision : 8021007027b13e91cc66908029470da49a8ca11f
2006-09-30 03:03:58 -04:00
Gabe Black
165b010b29 Some code cleanup.
src/kern/linux/linux.hh:
src/kern/solaris/solaris.hh:
    Some code cleanup. Uncommented some typedefs.
src/kern/tru64/tru64.hh:
    Some code cleanup. Deleted an obsoleted function.

--HG--
extra : convert_revision : b165fd43b9c3113d717b6ac9b02593fd750580b0
2006-09-30 03:00:50 -04:00
Gabe Black
d512d0aec0 Fixes to get the ozone cpu to compile.
--HG--
extra : convert_revision : d3654fca7ae1ae0fbe8842fed98ccf8c56bce8c7
2006-09-30 02:58:34 -04:00
Gabe Black
76708a9a6c Changed makeExtMI to take a ThreadContext instead of a pc.
--HG--
extra : convert_revision : e5b200e4e053702fc703f44149d18ce48ac4eaa6
2006-09-30 02:55:21 -04:00
Ali Saidi
17b0e9714d add boiler plate intel nic code
src/SConscript:
    add intel nic to sconscript
src/dev/pcidev.cc:
    fix bug with subsystemid value
src/python/m5/objects/Ethernet.py:
    add intel nic to ethernet.py
src/python/m5/objects/Ide.py:
src/python/m5/objects/Pci.py:
    Move config_latency into pci where it belogs

--HG--
extra : convert_revision : 7163aaf7b4098496518b0910cef62f2ce3dd574d
2006-09-18 20:12:45 -04:00
Gabe Black
30b87e90f8 Finished changing how stat structures are translated, fixed the handling of various ids as LiveProcess parameters.
src/arch/alpha/linux/process.cc:
src/arch/alpha/linux/process.hh:
src/arch/alpha/process.cc:
src/arch/alpha/process.hh:
src/arch/alpha/tru64/process.cc:
src/arch/alpha/tru64/process.hh:
src/arch/mips/linux/process.cc:
src/arch/mips/linux/process.hh:
src/arch/mips/process.cc:
src/arch/mips/process.hh:
src/arch/sparc/linux/process.cc:
src/arch/sparc/linux/process.hh:
src/arch/sparc/process.cc:
src/arch/sparc/process.hh:
src/arch/sparc/solaris/process.cc:
src/arch/sparc/solaris/process.hh:
src/sim/process.cc:
src/sim/process.hh:
src/sim/syscall_emul.cc:
src/sim/syscall_emul.hh:
    Changed Process to LiveProcess in syscall handlers and fixed the implementation of uid, euid, gid, egid, pid and ppid as LiveProcess parameters.
src/kern/tru64/tru64.hh:
    Changed Process to LiveProcess in syscall handlers and fixed the implementation of uid, euid, gid, egid, pid and ppid as LiveProcess parameters. Also fit tru64 in with the new way to handle stat calls.

--HG--
extra : convert_revision : 0198b838e5c09a730065dc6f018738145bc96269
2006-09-17 03:00:55 -04:00
Gabe Black
e4fcef5851 Changes to correct stat behavior
--HG--
extra : convert_revision : 43e5788105738aebd79acb05301bb7da68bfe129
2006-09-15 21:43:12 -04:00
Gabe Black
8abab05c83 Merge zizzer.eecs.umich.edu:/bk/newmem
into  ewok.(none):/home/gblack/m5/newmem

--HG--
extra : convert_revision : 91aacb435c223e8c37f6ba0a458b0dee55edcaf2
2006-09-15 00:59:39 -04:00
Ali Saidi
44c6f953b0 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem.head

--HG--
extra : convert_revision : 14ac24236ff65b7e489c1ce4b4e9a295966013b8
2006-09-11 17:57:30 -04:00
Ali Saidi
46502851ab add annotation code to m5
configs/common/Benchmarks.py:
    add annotate test app
src/SConscript:
    add annotate.cc to lis
src/arch/alpha/isa/decoder.isa:
    add annotate instructions
src/base/traceflags.py:
    Add annotate trace flag
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
    add annotate pseudo ops
util/m5/m5op.S:
util/m5/m5op.h:
    add anotate ops

--HG--
extra : convert_revision : 7f965c0d84e41ce34f2ec8ec27a009276d67d8d6
2006-09-11 17:57:20 -04:00
Steve Reinhardt
a7e8a78958 Add support for assigning lists of ports or proxies to VectorPorts.
Includes support for printing readable VectorPort and Proxy names
(via __str__).

--HG--
extra : convert_revision : c48534a498b3036fe6ac45ff1606656546c79afb
2006-09-08 19:10:11 -04:00
Steve Reinhardt
c15e6d8e0a Try to make unproxy order more deterministic.
--HG--
extra : convert_revision : 0bc543014dced6dfed4122d4c1b8f22e6c8d7a13
2006-09-06 22:37:35 -07:00
Steve Reinhardt
545cbec5f7 Enable proxies (Self/Parent) for specifying ports.
Significant revamp of Port code.
Some cleanup of SimObject code too, particularly to
make the SimObject and MetaSimObject implementations of
__setattr__ more consistent.
Unproxy code split out of print_ini().

src/python/m5/multidict.py:
    Make get() return None by default, to match semantics
    of built-in dictionary objects.

--HG--
extra : convert_revision : db73b6cdd004a82a08b2402afd1e16544cb902a4
2006-09-05 22:04:34 -07:00
Steve Reinhardt
89f0bc9e4c Print ports in config.ini as well.
--HG--
extra : convert_revision : 703d3a57250613315735709de8f40a9956cee6e2
2006-09-05 12:22:47 -07:00
Steve Reinhardt
c39aea440c More Python hacking to deal with config.py split
and resulting recursive import trickiness.

--HG--
extra : convert_revision : 1ea93861eb8d260c9f3920dda0b8106db3e03705
2006-09-04 17:14:07 -07:00
Steve Reinhardt
1233dbb998 Split config.py into multiple files.
Some tweaking to deal with mutually recursive imports.

--HG--
rename : src/python/m5/config.py => src/python/m5/SimObject.py
extra : convert_revision : 166f7bfabfd20100e93d26a89382469465859988
2006-09-04 10:52:26 -07:00
Steve Reinhardt
a658d25d42 config.py:
Import of changes for auto-generation of C++ param structs
from my old m5 working directory.
This code is *broken* because pieces need to be shuffled around
to satisfy name dependencies, but that really messes up the
diff, so I want to make an intermediate commit here.

src/python/m5/config.py:
    Import of changes for auto-generation of C++ param structs
    from my old m5 working directory.
    This code is *broken* because pieces need to be shuffled around
    to satisfy name dependencies, but that really messes up the
    diff, so I want to make an intermediate commit here.

--HG--
extra : convert_revision : cb25ee1f4f77d1902511ee9aa766403733dd8841
2006-09-04 10:40:33 -07:00
Gabe Black
b11018ca12 Made system calls use the uid, etc parameters from the live process.
--HG--
extra : convert_revision : 2aadb87b4602324423aadb903010f5b49fcef41b
2006-09-03 02:12:11 -04:00
Gabe Black
c32ef326d2 Fix up the parameters to getInstRecord
--HG--
extra : convert_revision : 0fac43035a2510d3a3f596d3d8f57193045570f6
2006-09-03 02:10:05 -04:00
Gabe Black
936d8c3e65 Make the ASI constants available to the decoder.
--HG--
extra : convert_revision : 65f2e02ce8f5e4f0c8727ebf16c927c7a6a4fe7f
2006-09-03 02:09:25 -04:00
Gabe Black
16f9b901be Make the auxiliary vectors use the uid, euid, gid and egid parameters from the live process
--HG--
extra : convert_revision : 945b5883a15a6df35709edea2731f54a2448e418
2006-09-03 02:08:24 -04:00
Gabe Black
387bbe40d1 Fixing up parameters of getInstRecord
--HG--
extra : convert_revision : 4ce06ac4f7d135cc04b39cf0e957a2539c7e946d
2006-09-03 02:05:44 -04:00
Gabe Black
96dabdc9b0 Added uid, euid, gid, egid, pid and ppid parameters to a live process.
--HG--
extra : convert_revision : 2101be8000bcdaf683730cfc079b4b78e34365d0
2006-09-03 02:04:25 -04:00
Gabe Black
14cc9baba5 A quick fix to isolate the tracing code to SPARC
--HG--
extra : convert_revision : 90c77f4d01101cad55f60d528b2a8be92d2f9aba
2006-09-03 02:02:56 -04:00
Steve Reinhardt
abe18be544 Merge zizzer.eecs.umich.edu:/bk/newmem
into  vm1.(none):/home/stever/bk/newmem-head

--HG--
extra : convert_revision : 8b0fbb6b1ea38d01d048381f18fd95ab63c4c0f1
2006-09-01 17:12:43 -07:00
Steve Reinhardt
30c93db065 Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into  zizzer.eecs.umich.edu:/z/stever/bk/newmem-head

--HG--
extra : convert_revision : 54c63c9a8c7146bb45ecfa9a177ab0bda9541d1b
2006-09-01 12:59:48 -04:00
Steve Reinhardt
edeb8f39a7 Tweak proxy resolution error message.
--HG--
extra : convert_revision : 3b186209515975be0d8bc9acc214425adcaa16f2
2006-08-31 17:58:46 -07:00
Korey Sewell
82862e0e15 add ISA_HAS_DELAY_SLOT directive instead of "#if THE_ISA == ALPHA_ISA" throughout CPU models
src/arch/alpha/isa_traits.hh:
src/arch/mips/isa_traits.hh:
src/arch/sparc/isa_traits.hh:
    define 'ISA_HAS_DELAY_SLOT'
src/cpu/base_dyn_inst.hh:
src/cpu/o3/bpred_unit_impl.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/simple/base.cc:
    use ISA_HAS_DELAY_SLOT instead of THE_ISA == ALPHA_ISA

--HG--
extra : convert_revision : 24c7460d9391e8d443c9fe08e17c331ae8e9c36a
2006-08-31 20:51:30 -04:00
Steve Reinhardt
f9ae0dcf10 Move more common functionality into SimpleTimingPort,
allowing derived classes to be simplified.

--HG--
extra : convert_revision : c980d3aec5e6c044d8f41e96252726fe9a256605
2006-08-30 16:24:26 -07:00
Gabe Black
fa0fca3227 Change the cpu pointer in the InstRecord object to a thread context pointer.
--HG--
extra : convert_revision : 7efb2680cef4219281b94d680a4a7c75c123f89d
2006-08-30 19:08:24 -04:00