Started implementing microcode.
--HG-- extra : convert_revision : 51df0454085e13df023efd8a0c0a12f9756c4690
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@ -396,7 +396,18 @@ BaseSimpleCPU::preExecute()
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// decode the instruction
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inst = gtoh(inst);
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curStaticInst = StaticInst::decode(makeExtMI(inst, thread->getTC()));
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//If we're not in the middle of a macro instruction
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if (!curMacroStaticInst) {
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StaticInstPtr instPtr = StaticInst::decode(makeExtMI(inst, thread->getTC()));
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if (instPtr->isMacroOp()) {
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curMacroStaticInst = instPtr;
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curStaticInst = curMacroStaticInst->fetchMicroOp(0);
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}
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} else {
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//Read the next micro op from the macro op
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curStaticInst = curMacroStaticInst->fetchMicroOp(thread->readMicroPc());
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}
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traceData = Trace::getInstRecord(curTick, tc, curStaticInst,
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thread->readPC());
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@ -446,18 +457,35 @@ BaseSimpleCPU::advancePC(Fault fault)
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{
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if (fault != NoFault) {
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fault->invoke(tc);
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}
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else {
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// go to the next instruction
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thread->setPC(thread->readNextPC());
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} else {
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//If we're at the last micro op for this instruction
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if (curStaticInst->isLastMicroOp()) {
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//We should be working with a macro op
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assert(curMacroStaticInst);
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//Close out this macro op, and clean up the
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//microcode state
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curMacroStaticInst = nullStaticInst;
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thread->setMicroPC(0);
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thread->setNextMicroPC(0);
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}
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//If we're still in a macro op
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if (curMacroStaticInst) {
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//Advance the micro pc
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thread->setMicroPC(thread->getNextMicroPC());
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//Advance the "next" micro pc. Note that there are no delay
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//slots, and micro ops are "word" addressed.
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thread->setNextMicroPC(thread->getNextMicroPC() + 1);
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} else {
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// go to the next instruction
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thread->setPC(thread->readNextPC());
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#if ISA_HAS_DELAY_SLOT
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thread->setNextPC(thread->readNextNPC());
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thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
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assert(thread->readNextPC() != thread->readNextNPC());
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thread->setNextPC(thread->readNextNPC());
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thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
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assert(thread->readNextPC() != thread->readNextNPC());
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#else
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thread->setNextPC(thread->readNextPC() + sizeof(MachInst));
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thread->setNextPC(thread->readNextPC() + sizeof(MachInst));
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#endif
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}
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}
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#if FULL_SYSTEM
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@ -128,6 +128,7 @@ class BaseSimpleCPU : public BaseCPU
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TheISA::IntReg dataReg;
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StaticInstPtr curStaticInst;
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StaticInstPtr curMacroStaticInst;
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void checkForInterrupts();
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Fault setupFetchRequest(Request *req);
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@ -377,6 +377,16 @@ class SimpleThread : public ThreadState
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regs.setPC(val);
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}
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uint64_t readMicroPC()
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{
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return microPC;
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}
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void setMicroPC(uint64_t val)
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{
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microPC = val;
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}
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uint64_t readNextPC()
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{
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return regs.readNextPC();
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@ -387,6 +397,16 @@ class SimpleThread : public ThreadState
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regs.setNextPC(val);
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}
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uint64_t readNextMicroPC()
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{
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return nextMicroPC;
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}
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void setNextMicroPC(uint64_t val)
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{
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nextMicroPC = val;
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}
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uint64_t readNextNPC()
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{
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return regs.readNextNPC();
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@ -200,6 +200,16 @@ struct ThreadState {
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*/
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TheISA::MachInst inst;
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/** The current microcode pc for the currently executing macro
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* operation.
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*/
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MicroPC microPC;
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/** The next microcode pc for the currently executing macro
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* operation.
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*/
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MicroPC nextMicroPC;
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public:
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/**
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* Temporary storage to pass the source address from copy_load to
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