More Python hacking to deal with config.py split

and resulting recursive import trickiness.

--HG--
extra : convert_revision : 1ea93861eb8d260c9f3920dda0b8106db3e03705
This commit is contained in:
Steve Reinhardt 2006-09-04 17:14:07 -07:00
parent 1233dbb998
commit c39aea440c
35 changed files with 155 additions and 102 deletions

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@ -29,11 +29,40 @@
import sys, types
import m5
from m5 import panic, cc_main
from convert import *
from util import *
from multidict import multidict
# These utility functions have to come first because they're
# referenced in params.py... otherwise they won't be defined when we
# import params below, and the recursive import of this file from
# params.py will not find these names.
def isSimObject(value):
return isinstance(value, SimObject)
def isSimObjectClass(value):
return issubclass(value, SimObject)
def isSimObjectSequence(value):
if not isinstance(value, (list, tuple)) or len(value) == 0:
return False
for val in value:
if not isNullPointer(val) and not isSimObject(val):
return False
return True
def isSimObjectOrSequence(value):
return isSimObject(value) or isSimObjectSequence(value)
# Have to import params up top since Param is referenced on initial
# load (when SimObject class references Param to create a class
# variable, the 'name' param)...
from params import *
# There are a few things we need that aren't in params.__all__ since
# normal users don't need them
from params import ParamDesc, isNullPointer, SimObjVector
noDot = False
try:
import pydot
@ -564,7 +593,7 @@ class SimObject(object):
for param in param_names:
value = self._values.get(param, None)
if value != None:
if isproxy(value):
if proxy.isproxy(value):
try:
value = value.unproxy(self)
except:
@ -679,52 +708,6 @@ class SimObject(object):
class ParamContext(SimObject):
pass
# Special class for NULL pointers. Note the special check in
# make_param_value() above that lets these be assigned where a
# SimObject is required.
# only one copy of a particular node
class NullSimObject(object):
__metaclass__ = Singleton
def __call__(cls):
return cls
def _instantiate(self, parent = None, path = ''):
pass
def ini_str(self):
return 'Null'
def unproxy(self, base):
return self
def set_path(self, parent, name):
pass
def __str__(self):
return 'Null'
# The only instance you'll ever need...
Null = NULL = NullSimObject()
def isSimObject(value):
return isinstance(value, SimObject)
def isNullPointer(value):
return isinstance(value, NullSimObject)
def isSimObjectSequence(value):
if not isinstance(value, (list, tuple)) or len(value) == 0:
return False
for val in value:
if not isNullPointer(val) and not isSimObject(val):
return False
return True
def isSimObjectOrSequence(value):
return isSimObject(value) or isSimObjectSequence(value)
# Function to provide to C++ so it can look up instances based on paths
def resolveSimObject(name):
obj = instanceDict[name]
@ -735,3 +718,7 @@ def resolveSimObject(name):
# short to avoid polluting other namespaces.
__all__ = ['SimObject', 'ParamContext']
# see comment on imports at end of __init__.py.
import proxy
import cc_main

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@ -71,8 +71,6 @@ build_env.update(defines.m5_build_env)
env = smartdict.SmartDict()
env.update(os.environ)
from main import options, arguments, main
# The final hook to generate .ini files. Called from the user script
# once the config is built.
def instantiate(root):
@ -206,5 +204,7 @@ def switchCpus(cpuList):
# you can get the wrong result if foo is only partially imported
# at the point you do that (i.e., because foo is in the middle of
# importing *you*).
from main import options
import objects
import params
from SimObject import resolveSimObject

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@ -1,4 +1,5 @@
from m5.config import *
from m5.params import *
from m5.proxy import *
from Device import BasicPioDevice
class AlphaConsole(BasicPioDevice):

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@ -1,4 +1,5 @@
from m5.config import *
from m5.SimObject import SimObject
from m5.params import *
class AlphaTLB(SimObject):
type = 'AlphaTLB'
abstract = True

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@ -1,4 +1,4 @@
from m5.config import *
from m5.params import *
from Device import BasicPioDevice
class BadDevice(BasicPioDevice):

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@ -1,5 +1,7 @@
from m5.SimObject import SimObject
from m5.params import *
from m5.proxy import *
from m5 import build_env
from m5.config import *
from AlphaTLB import AlphaDTB, AlphaITB
from Bus import Bus

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@ -1,4 +1,4 @@
from m5.config import *
from m5.params import *
from MemObject import MemObject
class Prefetch(Enum): vals = ['none', 'tagged', 'stride', 'ghb']

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@ -1,4 +1,4 @@
from m5.config import *
from m5.params import *
from MemObject import MemObject
class Bridge(MemObject):

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@ -1,4 +1,4 @@
from m5.config import *
from m5.params import *
from MemObject import MemObject
class Bus(MemObject):

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@ -1,4 +1,5 @@
from m5.config import *
from m5.SimObject import SimObject
from m5.params import *
class Coherence(Enum): vals = ['uni', 'msi', 'mesi', 'mosi', 'moesi']
class CoherenceProtocol(SimObject):

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@ -1,4 +1,5 @@
from m5.config import *
from m5.params import *
from m5.proxy import *
from MemObject import MemObject
class PioDevice(MemObject):

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@ -1,4 +1,5 @@
from m5.config import *
from m5.SimObject import SimObject
from m5.params import *
class DiskImage(SimObject):
type = 'DiskImage'
abstract = True

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@ -1,5 +1,7 @@
from m5.SimObject import SimObject
from m5.params import *
from m5.proxy import *
from m5 import build_env
from m5.config import *
from Device import DmaDevice
from Pci import PciDevice, PciConfigData

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@ -1,4 +1,5 @@
from m5.config import *
from m5.SimObject import SimObject
from m5.params import *
class FUPool(SimObject):
type = 'FUPool'

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@ -1,4 +1,5 @@
from m5.config import *
from m5.SimObject import SimObject
from m5.params import *
class OpType(Enum):
vals = ['(null)', 'IntAlu', 'IntMult', 'IntDiv', 'FloatAdd',

View file

@ -1,4 +1,5 @@
from m5.config import *
from m5.SimObject import SimObject
from m5.params import *
from Pci import PciDevice, PciConfigData
class IdeID(Enum): vals = ['master', 'slave']

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@ -1,4 +1,6 @@
from m5.config import *
from m5.SimObject import SimObject
from m5.params import *
from m5.proxy import *
class IntrControl(SimObject):
type = 'IntrControl'
cpu = Param.BaseCPU(Parent.any, "the cpu")

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@ -1,4 +1,5 @@
from m5.config import *
from m5.SimObject import SimObject
from m5.SimObject import SimObject
class MemObject(SimObject):
type = 'MemObject'

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@ -1,4 +1,5 @@
from m5.config import *
from m5.SimObject import SimObject
from m5.params import *
class MemTest(SimObject):
type = 'MemTest'
cache = Param.BaseCache("L1 cache")

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@ -1,5 +1,6 @@
from m5.params import *
from m5.proxy import *
from m5 import build_env
from m5.config import *
from BaseCPU import BaseCPU
from Checker import O3Checker

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@ -1,5 +1,5 @@
from m5.params import *
from m5 import build_env
from m5.config import *
from BaseCPU import BaseCPU
class DerivOzoneCPU(BaseCPU):

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@ -1,4 +1,6 @@
from m5.config import *
from m5.SimObject import SimObject
from m5.params import *
from m5.proxy import *
from Device import BasicPioDevice, DmaDevice, PioDevice
class PciConfigData(SimObject):

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@ -1,4 +1,5 @@
from m5.config import *
from m5.params import *
from m5.proxy import *
from MemObject import *
class PhysicalMemory(MemObject):

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@ -1,4 +1,6 @@
from m5.config import *
from m5.SimObject import SimObject
from m5.params import *
from m5.proxy import *
class Platform(SimObject):
type = 'Platform'
abstract = True

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@ -1,4 +1,6 @@
from m5.config import *
from m5.SimObject import SimObject
from m5.params import *
from m5.proxy import *
class Process(SimObject):
type = 'Process'
abstract = True

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@ -1,4 +1,5 @@
from m5.config import *
from m5.SimObject import SimObject
from m5.params import *
class Repl(SimObject):
type = 'Repl'
abstract = True

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@ -1,4 +1,5 @@
from m5.config import *
from m5.SimObject import SimObject
from m5.params import *
from Serialize import Serialize
from Statistics import Statistics
from Trace import Trace

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@ -1,4 +1,6 @@
from m5.config import *
from m5.SimObject import SimObject
from m5.params import *
from m5.proxy import *
class ConsoleListener(SimObject):
type = 'ConsoleListener'
port = Param.TcpPort(3456, "listen port")

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@ -1,4 +1,6 @@
from m5.config import *
from m5.SimObject import SimObject
from m5.params import *
from m5.proxy import *
class SimpleDisk(SimObject):
type = 'SimpleDisk'
disk = Param.DiskImage("Disk Image")

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@ -1,5 +1,5 @@
from m5.params import *
from m5 import build_env
from m5.config import *
from BaseCPU import BaseCPU
class SimpleOzoneCPU(BaseCPU):

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@ -1,5 +1,7 @@
from m5.SimObject import SimObject
from m5.params import *
from m5.proxy import *
from m5 import build_env
from m5.config import *
class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing']

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@ -1,4 +1,5 @@
from m5.config import *
from m5.params import *
from m5.proxy import *
from Device import BasicPioDevice
from Platform import Platform
from AlphaConsole import AlphaConsole

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@ -1,5 +1,6 @@
from m5.params import *
from m5.proxy import *
from m5 import build_env
from m5.config import *
from Device import BasicPioDevice
class Uart(BasicPioDevice):

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@ -46,6 +46,7 @@
import sys, inspect, copy
import convert
from util import *
# Dummy base class to identify types that are legitimate for SimObject
# parameters.
@ -100,13 +101,14 @@ class ParamDesc(object):
def __getattr__(self, attr):
if attr == 'ptype':
try:
ptype = eval(self.ptype_str, m5.objects.__dict__)
ptype = eval(self.ptype_str, objects.__dict__)
if not isinstance(ptype, type):
panic("Param qualifier is not a type: %s" % self.ptype)
raise NameError
self.ptype = ptype
return ptype
except NameError:
pass
raise TypeError, \
"Param qualifier '%s' is not a type" % self.ptype_str
raise AttributeError, "'%s' object has no attribute '%s'" % \
(type(self).__name__, attr)
@ -120,7 +122,7 @@ class ParamDesc(object):
return value
if isinstance(value, self.ptype):
return value
if isNullPointer(value) and issubclass(self.ptype, SimObject):
if isNullPointer(value) and isSimObjectClass(self.ptype):
return value
return self.ptype(value)
@ -305,7 +307,7 @@ class CheckedInt(NumericParamValue):
def __init__(self, value):
if isinstance(value, str):
self.value = toInteger(value)
self.value = convert.toInteger(value)
elif isinstance(value, (int, long, float)):
self.value = long(value)
self._check()
@ -340,7 +342,7 @@ class MemorySize(CheckedInt):
if isinstance(value, MemorySize):
self.value = value.value
else:
self.value = toMemorySize(value)
self.value = convert.toMemorySize(value)
self._check()
class MemorySize32(CheckedInt):
@ -350,7 +352,7 @@ class MemorySize32(CheckedInt):
if isinstance(value, MemorySize):
self.value = value.value
else:
self.value = toMemorySize(value)
self.value = convert.toMemorySize(value)
self._check()
class Addr(CheckedInt):
@ -363,7 +365,7 @@ class Addr(CheckedInt):
self.value = value.value
else:
try:
self.value = toMemorySize(value)
self.value = convert.toMemorySize(value)
except TypeError:
self.value = long(value)
self._check()
@ -430,7 +432,7 @@ class Bool(ParamValue):
cxx_type = 'bool'
def __init__(self, value):
try:
self.value = toBool(value)
self.value = convert.toBool(value)
except TypeError:
self.value = bool(value)
@ -586,10 +588,10 @@ def getLatency(value):
return 1 / value.value
elif isinstance(value, str):
try:
return toLatency(value)
return convert.toLatency(value)
except ValueError:
try:
return 1 / toFrequency(value)
return 1 / convert.toFrequency(value)
except ValueError:
pass # fall through
raise ValueError, "Invalid Frequency/Latency value '%s'" % value
@ -678,7 +680,7 @@ class Clock(ParamValue):
class NetworkBandwidth(float,ParamValue):
cxx_type = 'float'
def __new__(cls, value):
val = toNetworkBandwidth(value) / 8.0
val = convert.toNetworkBandwidth(value) / 8.0
return super(cls, NetworkBandwidth).__new__(cls, val)
def __str__(self):
@ -690,7 +692,7 @@ class NetworkBandwidth(float,ParamValue):
class MemoryBandwidth(float,ParamValue):
cxx_type = 'float'
def __new__(self, value):
val = toMemoryBandwidth(value)
val = convert.toMemoryBandwidth(value)
return super(cls, MemoryBandwidth).__new__(cls, val)
def __str__(self):
@ -703,6 +705,36 @@ class MemoryBandwidth(float,ParamValue):
# "Constants"... handy aliases for various values.
#
# Special class for NULL pointers. Note the special check in
# make_param_value() above that lets these be assigned where a
# SimObject is required.
# only one copy of a particular node
class NullSimObject(object):
__metaclass__ = Singleton
def __call__(cls):
return cls
def _instantiate(self, parent = None, path = ''):
pass
def ini_str(self):
return 'Null'
def unproxy(self, base):
return self
def set_path(self, parent, name):
pass
def __str__(self):
return 'Null'
# The only instance you'll ever need...
NULL = NullSimObject()
def isNullPointer(value):
return isinstance(value, NullSimObject)
# Some memory range specifications use this as a default upper bound.
MaxAddr = Addr.max
MaxTick = Tick.max
@ -821,11 +853,11 @@ __all__ = ['Param', 'VectorParam',
'NetworkBandwidth', 'MemoryBandwidth',
'Range', 'AddrRange', 'TickRange',
'MaxAddr', 'MaxTick', 'AllMemory',
'Null', 'NULL',
'NextEthernetAddr',
'NextEthernetAddr', 'NULL',
'Port', 'VectorPort']
# see comment on imports at end of __init__.py.
from SimObject import SimObject, isSimObject, isSimObjectSequence, \
isNullPointer
from SimObject import isSimObject, isSimObjectSequence, isSimObjectClass
import proxy
import objects
import cc_main

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@ -151,8 +151,8 @@ main(int argc, char **argv)
// initialize SWIG 'cc_main' module
init_cc_main();
PyRun_SimpleString("import m5");
PyRun_SimpleString("m5.main()");
PyRun_SimpleString("import m5.main");
PyRun_SimpleString("m5.main.main()");
// clean up Python intepreter.
Py_Finalize();