Move IntrFlag into the MiscRegFile and get rid of specialized accessor functions.
--HG-- extra : convert_revision : e0d12a150b01d05de9bc02bcbc7c22797975a5b9
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4862879a94
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038217049a
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@ -661,12 +661,12 @@ decode OPCODE default Unknown::unknown() {
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#if FULL_SYSTEM
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format BasicOperate {
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0xe000: rc({{
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Ra = xc->readIntrFlag();
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xc->setIntrFlag(0);
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Ra = IntrFlag;
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IntrFlag = 0;
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}}, IsNonSpeculative, IsUnverifiable);
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0xf000: rs({{
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Ra = xc->readIntrFlag();
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xc->setIntrFlag(1);
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Ra = IntrFlag;
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IntrFlag = 1;
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}}, IsNonSpeculative, IsUnverifiable);
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}
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#else
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@ -183,8 +183,9 @@ def operands {{
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'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
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'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
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'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
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'Runiq': ('ControlReg', 'uq', 'TheISA::Uniq_DepTag', None, 1),
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'FPCR': (' ControlReg', 'uq', 'TheISA::Fpcr_DepTag', None, 1),
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'Runiq': ('ControlReg', 'uq', 'AlphaISA::Uniq_DepTag', None, 1),
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'FPCR': ('ControlReg', 'uq', 'AlphaISA::Fpcr_DepTag', None, 1),
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'IntrFlag': ('ControlReg', 'uq', 'AlphaISA::Intr_Flag_DepTag', None, 1),
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# The next two are hacks for non-full-system call-pal emulation
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'R0': ('IntReg', 'uq', '0', None, 1),
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'R16': ('IntReg', 'uq', '16', None, 1),
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@ -54,7 +54,8 @@ namespace AlphaISA
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Uniq_DepTag = 73,
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Lock_Flag_DepTag = 74,
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Lock_Addr_DepTag = 75,
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IPR_Base_DepTag = 76
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Intr_Flag_DepTag = 76,
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IPR_Base_DepTag = 77
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};
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StaticInstPtr decodeInst(ExtMachInst);
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@ -109,6 +109,7 @@ namespace AlphaISA
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uint64_t uniq; // process-unique register
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bool lock_flag; // lock flag for LL/SC
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Addr lock_addr; // lock address for LL/SC
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int intr_flag;
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public:
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MiscReg readReg(int misc_reg);
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@ -131,6 +132,7 @@ namespace AlphaISA
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fpcr = uniq = 0;
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lock_flag = 0;
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lock_addr = 0;
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intr_flag = 0;
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}
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void serialize(std::ostream &os);
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@ -328,8 +328,6 @@ class CheckerCPU : public BaseCPU
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#if FULL_SYSTEM
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Fault hwrei() { return thread->hwrei(); }
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int readIntrFlag() { return thread->readIntrFlag(); }
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void setIntrFlag(int val) { thread->setIntrFlag(val); }
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bool inPalMode() { return thread->inPalMode(); }
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void ev5_trap(Fault fault) { fault->invoke(tc); }
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bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
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@ -144,10 +144,6 @@ class ExecContext {
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/** Somewhat Alpha-specific function that handles returning from
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* an error or interrupt. */
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Fault hwrei();
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/** Reads the interrupt flags. */
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int readIntrFlag();
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/** Sets the interrupt flags to a value. */
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void setIntrFlag(int val);
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/**
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* Check for special simulator handling of specific PAL calls. If
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@ -145,10 +145,6 @@ class AlphaO3CPU : public FullO3CPU<Impl>
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#if FULL_SYSTEM
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/** Posts an interrupt. */
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void post_interrupt(int int_num, int index);
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/** Reads the interrupt flag. */
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int readIntrFlag();
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/** Sets the interrupt flags. */
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void setIntrFlag(int val);
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/** HW return from error interrupt. */
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Fault hwrei(unsigned tid);
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/** Returns if a specific PC is a PAL mode PC. */
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@ -241,20 +241,6 @@ AlphaO3CPU<Impl>::post_interrupt(int int_num, int index)
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}
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}
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template <class Impl>
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int
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AlphaO3CPU<Impl>::readIntrFlag()
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{
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return this->regFile.readIntrFlag();
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}
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template <class Impl>
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void
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AlphaO3CPU<Impl>::setIntrFlag(int val)
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{
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this->regFile.setIntrFlag(val);
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}
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template <class Impl>
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Fault
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AlphaO3CPU<Impl>::hwrei(unsigned tid)
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@ -127,20 +127,6 @@ AlphaDynInst<Impl>::hwrei()
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return NoFault;
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}
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template <class Impl>
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int
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AlphaDynInst<Impl>::readIntrFlag()
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{
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return this->cpu->readIntrFlag();
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}
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template <class Impl>
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void
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AlphaDynInst<Impl>::setIntrFlag(int val)
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{
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this->cpu->setIntrFlag(val);
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}
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template <class Impl>
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bool
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AlphaDynInst<Impl>::inPalMode()
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@ -251,12 +251,6 @@ class PhysRegFile
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cpu->tcBase(thread_id));
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}
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#if FULL_SYSTEM
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int readIntrFlag() { return intrflag; }
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/** Sets an interrupt flag. */
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void setIntrFlag(int val) { intrflag = val; }
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#endif
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public:
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/** (signed) integer register file. */
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IntReg *intRegFile;
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@ -583,8 +583,6 @@ class OzoneCPU : public BaseCPU
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#if FULL_SYSTEM
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Fault hwrei();
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int readIntrFlag() { return thread.intrflag; }
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void setIntrFlag(int val) { thread.intrflag = val; }
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bool inPalMode() { return AlphaISA::PcPAL(thread.PC); }
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bool inPalMode(Addr pc) { return AlphaISA::PcPAL(pc); }
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bool simPalCheck(int palFunc);
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@ -238,8 +238,6 @@ class OzoneDynInst : public BaseDynInst<Impl>
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#if FULL_SYSTEM
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Fault hwrei();
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int readIntrFlag();
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void setIntrFlag(int val);
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bool inPalMode();
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void trap(Fault fault);
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bool simPalCheck(int palFunc);
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@ -260,20 +260,6 @@ OzoneDynInst<Impl>::hwrei()
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return NoFault;
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}
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template <class Impl>
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int
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OzoneDynInst<Impl>::readIntrFlag()
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{
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return this->cpu->readIntrFlag();
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}
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template <class Impl>
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void
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OzoneDynInst<Impl>::setIntrFlag(int val)
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{
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this->cpu->setIntrFlag(val);
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}
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template <class Impl>
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bool
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OzoneDynInst<Impl>::inPalMode()
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@ -305,8 +305,6 @@ class BaseSimpleCPU : public BaseCPU
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#if FULL_SYSTEM
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Fault hwrei() { return thread->hwrei(); }
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int readIntrFlag() { return thread->readIntrFlag(); }
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void setIntrFlag(int val) { thread->setIntrFlag(val); }
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bool inPalMode() { return thread->inPalMode(); }
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void ev5_trap(Fault fault) { fault->invoke(tc); }
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bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
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@ -168,8 +168,6 @@ class SimpleThread : public ThreadState
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void dumpFuncProfile();
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int readIntrFlag() { return regs.intrflag; }
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void setIntrFlag(int val) { regs.intrflag = val; }
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Fault hwrei();
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bool simPalCheck(int palFunc);
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