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Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem

Browse source 
into  zizzer.eecs.umich.edu:/z/stever/bk/newmem-head

--HG--
extra : convert_revision : 8a70922250092c013fa4db6d83254b438ee6c4be
This commit is contained in:
Steve Reinhardt 2006-10-19 13:33:08 -04:00
commit 11f0badbaa
2 changed files with 16 additions and 9 deletions
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3
src/base/traceflags.py
View file

@ -182,7 +182,8 @@ compoundFlagMap = {
'EthernetNoData' : [ 'Ethernet', 'EthernetPIO', 'EthernetDesc', 'EthernetIntr', 'EthernetSM', 'EthernetCksum' ],
'IdeAll' : [ 'IdeCtrl', 'IdeDisk' ],
'O3CPUAll' : [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit', 'IQ', 'ROB', 'FreeList', 'RenameMap', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit', 'DynInst', 'FullCPU', 'O3CPU', 'Activity','Scoreboard','Writeback'],
'OzoneCPUAll' : [ 'BE', 'FE', 'IBE', 'OzoneLSQ', 'OzoneCPU']
'OzoneCPUAll' : [ 'BE', 'FE', 'IBE', 'OzoneLSQ', 'OzoneCPU'],
'All' : baseFlags
}
#############################################################

22
src/sim/eventq.hh
View file

@ -120,10 +120,22 @@ class Event : public Serializable, public FastAlloc
/// priority; these values are used to control events that need to
/// be ordered within a cycle.
enum Priority {
/// Breakpoints should happen before anything else, so we
/// don't miss any action when debugging.
/// If we enable tracing on a particular cycle, do that as the
/// very first thing so we don't miss any of the events on
/// that cycle (even if we enter the debugger).
Trace_Enable_Pri = -101,
/// Breakpoints should happen before anything else (except
/// enabling trace output), so we don't miss any action when
/// debugging.
Debug_Break_Pri = -100,
/// CPU switches schedule the new CPU's tick event for the
/// same cycle (after unscheduling the old CPU's tick event).
/// The switch needs to come before any tick events to make
/// sure we don't tick both CPUs in the same cycle.
CPU_Switch_Pri = -31,
/// For some reason "delayed" inter-cluster writebacks are
/// scheduled before regular writebacks (which have default
/// priority). Steve?
@ -132,12 +144,6 @@ class Event : public Serializable, public FastAlloc
/// Default is zero for historical reasons.
Default_Pri = 0,
/// CPU switches schedule the new CPU's tick event for the
/// same cycle (after unscheduling the old CPU's tick event).
/// The switch needs to come before any tick events to make
/// sure we don't tick both CPUs in the same cycle.
CPU_Switch_Pri = -31,
/// Serailization needs to occur before tick events also, so
/// that a serialize/unserialize is identical to an on-line
/// CPU switch.