Start making memory ops work with InitiateAcc and CompleteAcc, and some minor cleanups
--HG-- extra : convert_revision : 178a8c5d0506c75ad7a7e8d691c8863235ed7e95
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@ -111,9 +111,8 @@ def template LoadExecute {{
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%(priv_check)s;
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%(ea_code)s;
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DPRINTF(Sparc, "The address is 0x%x\n", EA);
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xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, 0);
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fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, 0);
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%(code)s;
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if(fault == NoFault)
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{
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//Write the resulting state to the execution context
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@ -122,6 +121,35 @@ def template LoadExecute {{
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return fault;
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}
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Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc,
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Trace::InstRecord * traceData) const
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{
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Fault fault = NoFault;
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Addr EA;
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uint%(mem_acc_size)s_t Mem;
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%(ea_decl)s;
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%(ea_rd)s;
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%(priv_check)s;
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%(ea_code)s;
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fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, 0);
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return fault;
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}
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Fault %(class_name)s::completeAcc(PacketPtr pkt, %(CPU_exec_context)s * xc,
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Trace::InstRecord * traceData) const
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{
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Fault fault = NoFault;
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%(code_decl)s;
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%(code_rd)s;
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Mem = pkt->get<typeof(Mem)>();
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%(code)s;
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if(fault == NoFault)
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{
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%(code_wb)s;
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}
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return fault;
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}
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}};
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def template StoreExecute {{
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@ -140,13 +168,46 @@ def template StoreExecute {{
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if(fault == NoFault)
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{
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xc->write((uint%(mem_acc_size)s_t)Mem, EA, 0, &write_result);
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fault = xc->write((uint%(mem_acc_size)s_t)Mem, EA, 0, &write_result);
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}
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if(fault == NoFault)
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{
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//Write the resulting state to the execution context
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%(op_wb)s;
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}
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return fault;
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}
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Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc,
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Trace::InstRecord * traceData) const
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{
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Fault fault = NoFault;
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uint64_t write_result = 0;
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Addr EA;
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%(op_decl)s;
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%(op_rd)s;
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%(priv_check)s;
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%(ea_code)s;
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DPRINTF(Sparc, "The address is 0x%x\n", EA);
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%(code)s;
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if(fault == NoFault)
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{
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fault = xc->write((uint%(mem_acc_size)s_t)Mem, EA, 0, &write_result);
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}
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if(fault == NoFault)
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{
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//Write the resulting state to the execution context
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%(op_wb)s;
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}
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return fault;
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}
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Fault %(class_name)s::completeAcc(PacketPtr, %(CPU_exec_context)s * xc,
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Trace::InstRecord * traceData) const
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{
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return NoFault;
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}
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}};
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def template LoadStoreExecute {{
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@ -175,6 +236,34 @@ def template LoadStoreExecute {{
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}
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}};
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def template MemDeclare {{
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/**
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* Static instruction class for "%(mnemonic)s".
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*/
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class %(class_name)s : public %(base_class)s
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{
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public:
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/// Constructor.
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%(class_name)s(ExtMachInst machInst);
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%(BasicExecDeclare)s
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%(InitiateAccDeclare)s
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%(CompleteAccDeclare)s
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};
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}};
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def template InitiateAccDeclare {{
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Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
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}};
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def template CompleteAccDeclare {{
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Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
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}};
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let {{
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# XXX Need to take care of pstate.hpriv as well. The lower ASIs are split
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# into ones that are available in priv and hpriv, and those that are only
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@ -187,13 +276,30 @@ let {{
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def doMemFormat(code, execute, priv, name, Name, opt_flags):
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addrCalcReg = 'EA = Rs1 + Rs2;'
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addrCalcImm = 'EA = Rs1 + imm;'
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ea_iop = InstObjParams(name, Name, 'Mem',
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addrCalcReg, opt_flags, {"priv_check": priv})
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ea_iop_imm = InstObjParams(name, Name, 'MemImm',
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addrCalcImm, opt_flags, {"priv_check": priv})
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code_iop = InstObjParams(name, Name, 'Mem', code, opt_flags)
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iop = InstObjParams(name, Name, 'Mem', code,
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opt_flags, {"ea_code": addrCalcReg,
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"priv_check": priv})
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(iop.ea_decl,
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iop.ea_rd,
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iop.ea_wb) = (ea_iop.op_decl, ea_iop.op_rd, ea_iop.op_wb)
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(iop.code_decl,
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iop.code_rd,
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iop.code_wb) = (code_iop.op_decl, code_iop.op_rd, code_iop.op_wb)
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iop_imm = InstObjParams(name, Name + 'Imm', 'MemImm', code,
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opt_flags, {"ea_code": addrCalcImm,
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"priv_check": priv})
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header_output = BasicDeclare.subst(iop) + BasicDeclare.subst(iop_imm)
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(iop_imm.ea_decl,
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iop_imm.ea_rd,
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iop_imm.ea_wb) = (ea_iop_imm.op_decl, ea_iop_imm.op_rd, ea_iop_imm.op_wb)
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(iop_imm.code_decl,
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iop_imm.code_rd,
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iop_imm.code_wb) = (code_iop.op_decl, code_iop.op_rd, code_iop.op_wb)
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header_output = MemDeclare.subst(iop) + MemDeclare.subst(iop_imm)
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decoder_output = BasicConstructor.subst(iop) + BasicConstructor.subst(iop_imm)
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decode_block = ROrImmDecode.subst(iop)
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exec_output = execute.subst(iop) + execute.subst(iop_imm)
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@ -40,6 +40,7 @@ output header {{
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#include "cpu/static_inst.hh"
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#include "arch/sparc/faults.hh"
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#include "mem/request.hh" // some constructors use MemReq flags
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#include "mem/packet.hh"
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#include "arch/sparc/isa_traits.hh"
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#include "arch/sparc/regfile.hh"
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}};
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