Got rid of "inPalMode". Some places are still effectively checking if they are in PAL mode, however.
--HG-- extra : convert_revision : b52d9642efc474eaf97437fa2df879efefa0062b
This commit is contained in:
parent
c8fc116c76
commit
118b9dc1f9
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@ -147,7 +147,7 @@ AlphaISA::zeroRegisters(CPU *cpu)
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Fault
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SimpleThread::hwrei()
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{
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if (!inPalMode())
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if (!(readPC() & 0x3))
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return new UnimplementedOpcodeFault;
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setNextPC(readMiscReg(AlphaISA::IPR_EXC_ADDR));
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@ -125,7 +125,7 @@ void AlphaFault::invoke(ThreadContext * tc)
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countStat()++;
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// exception restart address
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if (setRestartAddress() || !tc->inPalMode())
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if (setRestartAddress() || !(tc->readPC() & 0x3))
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tc->setMiscReg(AlphaISA::IPR_EXC_ADDR, tc->readPC());
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if (skipFaultingInstruction()) {
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@ -88,15 +88,6 @@ namespace AlphaISA
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intstatus = 0;
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}
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bool check_interrupt(int int_num) const {
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if (int_num > NumInterruptLevels)
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panic("int_num out of bounds\n");
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return interrupts[int_num] != 0;
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}
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bool check_interrupts() const { return intstatus != 0; }
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void serialize(std::ostream &os)
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{
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SERIALIZE_ARRAY(interrupts, NumInterruptLevels);
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@ -109,6 +100,11 @@ namespace AlphaISA
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UNSERIALIZE_SCALAR(intstatus);
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}
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bool check_interrupts(ThreadContext * tc) const
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{
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return (intstatus != 0) && !(tc->readPC() & 0x3);
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}
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Fault getInterrupt(ThreadContext * tc)
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{
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int ipl = 0;
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@ -163,7 +159,6 @@ namespace AlphaISA
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}
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private:
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uint64_t intr_status() const { return intstatus; }
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};
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}
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@ -89,12 +89,8 @@ class BaseCPU : public MemObject
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virtual void clear_interrupts();
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bool checkInterrupts;
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bool check_interrupt(int int_num) const {
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return interrupts.check_interrupt(int_num);
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}
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bool check_interrupts() const { return interrupts.check_interrupts(); }
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//uint64_t intr_status() const { return interrupts.intr_status(); }
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bool check_interrupts(ThreadContext * tc) const
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{ return interrupts.check_interrupts(tc); }
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class ProfileEvent : public Event
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{
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@ -327,7 +327,6 @@ class CheckerCPU : public BaseCPU
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#if FULL_SYSTEM
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Fault hwrei() { return thread->hwrei(); }
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bool inPalMode() { return thread->inPalMode(); }
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void ev5_trap(Fault fault) { fault->invoke(tc); }
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bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
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#else
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@ -271,9 +271,6 @@ class CheckerThreadContext : public ThreadContext
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checkerTC->setStCondFailures(sc_failures);
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actualTC->setStCondFailures(sc_failures);
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}
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#if FULL_SYSTEM
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bool inPalMode() { return actualTC->inPalMode(); }
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#endif
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// @todo: Fix this!
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bool misspeculating() { return actualTC->misspeculating(); }
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@ -153,9 +153,6 @@ class AlphaO3CPU : public FullO3CPU<Impl>
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void post_interrupt(int int_num, int index);
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/** HW return from error interrupt. */
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Fault hwrei(unsigned tid);
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/** Returns if a specific PC is a PAL mode PC. */
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bool inPalMode(uint64_t PC)
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{ return AlphaISA::PcPAL(PC); }
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bool simPalCheck(int palFunc, unsigned tid);
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@ -278,11 +278,12 @@ AlphaO3CPU<Impl>::processInterrupts()
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// Check if there are any outstanding interrupts
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//Handle the interrupts
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this->checkInterrupts = false;
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Fault interrupt = this->interrupts.getInterrupt(this->tcBase(0));
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if (interrupt != NoFault)
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if (interrupt != NoFault) {
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this->checkInterrupts = false;
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this->trap(interrupt, 0);
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}
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}
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#endif // FULL_SYSTEM
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@ -126,8 +126,6 @@ class AlphaDynInst : public BaseDynInst<Impl>
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#if FULL_SYSTEM
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/** Calls hardware return from error interrupt. */
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Fault hwrei();
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/** Checks if system is in PAL mode. */
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bool inPalMode();
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/** Traps to handle specified fault. */
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void trap(Fault fault);
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bool simPalCheck(int palFunc);
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@ -113,7 +113,7 @@ Fault
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AlphaDynInst<Impl>::hwrei()
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{
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// Can only do a hwrei when in pal mode.
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if (!this->cpu->inPalMode(this->readPC()))
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if (!(this->readPC() & 0x3))
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return new AlphaISA::UnimplementedOpcodeFault;
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// Set the next PC based on the value of the EXC_ADDR IPR.
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@ -127,13 +127,6 @@ AlphaDynInst<Impl>::hwrei()
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return NoFault;
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}
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template <class Impl>
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bool
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AlphaDynInst<Impl>::inPalMode()
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{
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return this->cpu->inPalMode(this->PC);
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}
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template <class Impl>
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void
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AlphaDynInst<Impl>::trap(Fault fault)
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@ -47,11 +47,6 @@ class AlphaTC : public O3ThreadContext<Impl>
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{
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return this->thread->quiesceEvent;
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}
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/** Returns if the thread is currently in PAL mode, based on
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* the PC's value. */
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virtual bool inPalMode()
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{ return TheISA::PcPAL(this->cpu->readPC(this->thread->readTid())); }
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#endif
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virtual uint64_t readNextNPC()
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@ -638,8 +638,7 @@ DefaultCommit<Impl>::commit()
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// and no other traps or external squashes are currently pending.
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// @todo: Allow other threads to handle interrupts.
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if (cpu->checkInterrupts &&
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cpu->check_interrupts() &&
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!cpu->inPalMode(readPC()) &&
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cpu->check_interrupts(cpu->tcBase(0)) &&
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!trapSquash[0] &&
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!tcSquash[0]) {
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// Tell fetch that there is an interrupt pending. This will
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@ -559,14 +559,9 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid
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{
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Fault fault = NoFault;
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#if FULL_SYSTEM
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// Flag to say whether or not address is physical addr.
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unsigned flags = cpu->inPalMode(fetch_PC) ? PHYSICAL : 0;
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#else
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unsigned flags = 0;
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#endif // FULL_SYSTEM
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if (cacheBlocked || isSwitchedOut() || (interruptPending && flags == 0)) {
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//AlphaDep
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if (cacheBlocked || isSwitchedOut() ||
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(interruptPending && (fetch_PC & 0x3))) {
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// Hold off fetch from getting new instructions when:
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// Cache is blocked, or
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// while an interrupt is pending and we're not in PAL mode, or
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@ -585,7 +580,7 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid
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// Setup the memReq to do a read of the first instruction's address.
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// Set the appropriate read size and flags as well.
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// Build request here.
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RequestPtr mem_req = new Request(tid, fetch_PC, cacheBlkSize, flags,
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RequestPtr mem_req = new Request(tid, fetch_PC, cacheBlkSize, 0,
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fetch_PC, cpu->readCpuId(), tid);
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memReq[tid] = mem_req;
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@ -239,10 +239,6 @@ class OzoneCPU : public BaseCPU
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void setStCondFailures(unsigned sc_failures)
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{ thread->storeCondFailures = sc_failures; }
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#if FULL_SYSTEM
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bool inPalMode() { return cpu->inPalMode(); }
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#endif
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bool misspeculating() { return false; }
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#if !FULL_SYSTEM
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@ -584,8 +580,6 @@ class OzoneCPU : public BaseCPU
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#if FULL_SYSTEM
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Fault hwrei();
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bool inPalMode() { return AlphaISA::PcPAL(thread.PC); }
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bool inPalMode(Addr pc) { return AlphaISA::PcPAL(pc); }
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bool simPalCheck(int palFunc);
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void processInterrupts();
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#else
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@ -238,7 +238,6 @@ class OzoneDynInst : public BaseDynInst<Impl>
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#if FULL_SYSTEM
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Fault hwrei();
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bool inPalMode();
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void trap(Fault fault);
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bool simPalCheck(int palFunc);
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#else
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@ -249,7 +249,7 @@ template <class Impl>
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Fault
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OzoneDynInst<Impl>::hwrei()
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{
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if (!this->cpu->inPalMode(this->readPC()))
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if (!(this->readPC() & 0x3))
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return new AlphaISA::UnimplementedOpcodeFault;
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this->setNextPC(this->thread->readMiscReg(AlphaISA::IPR_EXC_ADDR));
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return NoFault;
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}
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template <class Impl>
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bool
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OzoneDynInst<Impl>::inPalMode()
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{
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return this->cpu->inPalMode();
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}
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template <class Impl>
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void
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OzoneDynInst<Impl>::trap(Fault fault)
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@ -462,15 +462,10 @@ Fault
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FrontEnd<Impl>::fetchCacheLine()
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{
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// Read a cache line, based on the current PC.
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#if FULL_SYSTEM
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// Flag to say whether or not address is physical addr.
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unsigned flags = cpu->inPalMode(PC) ? PHYSICAL : 0;
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#else
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unsigned flags = 0;
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#endif // FULL_SYSTEM
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Fault fault = NoFault;
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if (interruptPending && flags == 0) {
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//AlphaDep
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if (interruptPending && (PC & 0x3)) {
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return fault;
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}
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@ -152,11 +152,11 @@ InorderBackEnd<Impl>::tick()
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#if FULL_SYSTEM
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if (interruptBlocked ||
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(cpu->checkInterrupts &&
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cpu->check_interrupts() &&
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!cpu->inPalMode())) {
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cpu->check_interrupts(tc))) {
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if (!robEmpty()) {
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interruptBlocked = true;
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} else if (robEmpty() && cpu->inPalMode()) {
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//AlphaDep
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} else if (robEmpty() && (PC & 0x3)) {
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// Will need to let the front end continue a bit until
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// we're out of pal mode. Hopefully we never get into an
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// infinite loop...
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@ -526,8 +526,7 @@ void
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LWBackEnd<Impl>::checkInterrupts()
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{
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if (cpu->checkInterrupts &&
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cpu->check_interrupts() &&
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!cpu->inPalMode(thread->readPC()) &&
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cpu->check_interrupts(tc) &&
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!trapSquash &&
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!tcSquash) {
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frontEnd->interruptPending = true;
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@ -311,11 +311,11 @@ void
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BaseSimpleCPU::checkForInterrupts()
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{
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#if FULL_SYSTEM
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if (checkInterrupts && check_interrupts() && !thread->inPalMode()) {
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checkInterrupts = false;
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if (checkInterrupts && check_interrupts(tc)) {
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Fault interrupt = interrupts.getInterrupt(tc);
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if (interrupt != NoFault) {
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checkInterrupts = false;
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interrupt->invoke(tc);
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}
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}
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@ -371,6 +371,10 @@ BaseSimpleCPU::preExecute()
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StaticInstPtr instPtr = StaticInst::decode(makeExtMI(inst, thread->readPC()));
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#elif THE_ISA == SPARC_ISA
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StaticInstPtr instPtr = StaticInst::decode(makeExtMI(inst, thread->getTC()));
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#elif THE_ISA == MIPS_ISA
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//Mips doesn't do anything in it's MakeExtMI function right now,
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//so it won't be called.
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StaticInstPtr instPtr = StaticInst::decode(inst);
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#endif
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if (instPtr->isMacroOp()) {
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curMacroStaticInst = instPtr;
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@ -302,7 +302,6 @@ class BaseSimpleCPU : public BaseCPU
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#if FULL_SYSTEM
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Fault hwrei() { return thread->hwrei(); }
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bool inPalMode() { return thread->inPalMode(); }
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void ev5_trap(Fault fault) { fault->invoke(tc); }
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bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
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#else
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@ -440,10 +440,6 @@ class SimpleThread : public ThreadState
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void setStCondFailures(unsigned sc_failures)
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{ storeCondFailures = sc_failures; }
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#if FULL_SYSTEM
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bool inPalMode() { return AlphaISA::PcPAL(regs.readPC()); }
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#endif
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#if !FULL_SYSTEM
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TheISA::IntReg getSyscallArg(int i)
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{
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@ -236,10 +236,6 @@ class ThreadContext
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virtual void setStCondFailures(unsigned sc_failures) = 0;
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#if FULL_SYSTEM
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virtual bool inPalMode() = 0;
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#endif
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// Only really makes sense for old CPU model. Still could be useful though.
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virtual bool misspeculating() = 0;
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@ -424,9 +420,6 @@ class ProxyThreadContext : public ThreadContext
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void setStCondFailures(unsigned sc_failures)
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{ actualTC->setStCondFailures(sc_failures); }
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#if FULL_SYSTEM
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bool inPalMode() { return actualTC->inPalMode(); }
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#endif
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// @todo: Fix this!
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bool misspeculating() { return actualTC->misspeculating(); }
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