289 lines
9.6 KiB
C++
289 lines
9.6 KiB
C++
/*
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* Copyright (c) 2004-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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*/
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#ifndef __CPU_O3_ALPHA_DYN_INST_HH__
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#define __CPU_O3_ALPHA_DYN_INST_HH__
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#include "arch/isa_traits.hh"
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#include "cpu/base_dyn_inst.hh"
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#include "cpu/inst_seq.hh"
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#include "cpu/o3/alpha/cpu.hh"
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#include "cpu/o3/alpha/impl.hh"
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class Packet;
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/**
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* Mostly implementation & ISA specific AlphaDynInst. As with most
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* other classes in the new CPU model, it is templated on the Impl to
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* allow for passing in of all types, such as the CPU type and the ISA
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* type. The AlphaDynInst serves as the primary interface to the CPU
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* for instructions that are executing.
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*/
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template <class Impl>
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class AlphaDynInst : public BaseDynInst<Impl>
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{
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public:
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/** Typedef for the CPU. */
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typedef typename Impl::O3CPU O3CPU;
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/** Binary machine instruction type. */
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typedef TheISA::MachInst MachInst;
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/** Extended machine instruction type. */
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typedef TheISA::ExtMachInst ExtMachInst;
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/** Logical register index type. */
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typedef TheISA::RegIndex RegIndex;
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/** Integer register index type. */
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typedef TheISA::IntReg IntReg;
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typedef TheISA::FloatReg FloatReg;
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typedef TheISA::FloatRegBits FloatRegBits;
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/** Misc register index type. */
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typedef TheISA::MiscReg MiscReg;
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enum {
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MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
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MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs
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};
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public:
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/** BaseDynInst constructor given a binary instruction. */
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AlphaDynInst(ExtMachInst inst, Addr PC, Addr Pred_PC, InstSeqNum seq_num,
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O3CPU *cpu);
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/** BaseDynInst constructor given a static inst pointer. */
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AlphaDynInst(StaticInstPtr &_staticInst);
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/** Executes the instruction.*/
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Fault execute();
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/** Initiates the access. Only valid for memory operations. */
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Fault initiateAcc();
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/** Completes the access. Only valid for memory operations. */
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Fault completeAcc(PacketPtr pkt);
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private:
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/** Initializes variables. */
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void initVars();
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public:
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/** Reads a miscellaneous register. */
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MiscReg readMiscReg(int misc_reg)
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{
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return this->cpu->readMiscReg(misc_reg, this->threadNumber);
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}
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/** Reads a misc. register, including any side-effects the read
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* might have as defined by the architecture.
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*/
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MiscReg readMiscRegWithEffect(int misc_reg)
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{
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return this->cpu->readMiscRegWithEffect(misc_reg, this->threadNumber);
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}
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/** Sets a misc. register. */
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void setMiscReg(int misc_reg, const MiscReg &val)
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{
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this->instResult.integer = val;
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return this->cpu->setMiscReg(misc_reg, val, this->threadNumber);
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}
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/** Sets a misc. register, including any side-effects the write
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* might have as defined by the architecture.
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*/
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void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
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{
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return this->cpu->setMiscRegWithEffect(misc_reg, val,
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this->threadNumber);
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}
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#if FULL_SYSTEM
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/** Calls hardware return from error interrupt. */
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Fault hwrei();
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/** Traps to handle specified fault. */
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void trap(Fault fault);
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bool simPalCheck(int palFunc);
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#else
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/** Calls a syscall. */
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void syscall(int64_t callnum);
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#endif
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private:
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/** Physical register index of the destination registers of this
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* instruction.
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*/
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PhysRegIndex _destRegIdx[MaxInstDestRegs];
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/** Physical register index of the source registers of this
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* instruction.
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*/
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PhysRegIndex _srcRegIdx[MaxInstSrcRegs];
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/** Physical register index of the previous producers of the
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* architected destinations.
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*/
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PhysRegIndex _prevDestRegIdx[MaxInstDestRegs];
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public:
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// The register accessor methods provide the index of the
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// instruction's operand (e.g., 0 or 1), not the architectural
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// register index, to simplify the implementation of register
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// renaming. We find the architectural register index by indexing
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// into the instruction's own operand index table. Note that a
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// raw pointer to the StaticInst is provided instead of a
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// ref-counted StaticInstPtr to redice overhead. This is fine as
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// long as these methods don't copy the pointer into any long-term
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// storage (which is pretty hard to imagine they would have reason
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// to do).
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uint64_t readIntReg(const StaticInst *si, int idx)
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{
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return this->cpu->readIntReg(_srcRegIdx[idx]);
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}
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FloatReg readFloatReg(const StaticInst *si, int idx, int width)
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{
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return this->cpu->readFloatReg(_srcRegIdx[idx], width);
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}
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FloatReg readFloatReg(const StaticInst *si, int idx)
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{
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return this->cpu->readFloatReg(_srcRegIdx[idx]);
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}
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FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
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{
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return this->cpu->readFloatRegBits(_srcRegIdx[idx], width);
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}
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FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
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{
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return this->cpu->readFloatRegBits(_srcRegIdx[idx]);
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}
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/** @todo: Make results into arrays so they can handle multiple dest
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* registers.
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*/
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void setIntReg(const StaticInst *si, int idx, uint64_t val)
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{
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this->cpu->setIntReg(_destRegIdx[idx], val);
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BaseDynInst<Impl>::setIntReg(si, idx, val);
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}
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void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
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{
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this->cpu->setFloatReg(_destRegIdx[idx], val, width);
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BaseDynInst<Impl>::setFloatReg(si, idx, val, width);
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}
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void setFloatReg(const StaticInst *si, int idx, FloatReg val)
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{
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this->cpu->setFloatReg(_destRegIdx[idx], val);
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BaseDynInst<Impl>::setFloatReg(si, idx, val);
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}
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void setFloatRegBits(const StaticInst *si, int idx,
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FloatRegBits val, int width)
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{
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this->cpu->setFloatRegBits(_destRegIdx[idx], val, width);
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BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
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}
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void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
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{
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this->cpu->setFloatRegBits(_destRegIdx[idx], val);
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BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
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}
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/** Returns the physical register index of the i'th destination
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* register.
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*/
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PhysRegIndex renamedDestRegIdx(int idx) const
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{
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return _destRegIdx[idx];
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}
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/** Returns the physical register index of the i'th source register. */
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PhysRegIndex renamedSrcRegIdx(int idx) const
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{
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return _srcRegIdx[idx];
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}
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/** Returns the physical register index of the previous physical register
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* that remapped to the same logical register index.
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*/
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PhysRegIndex prevDestRegIdx(int idx) const
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{
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return _prevDestRegIdx[idx];
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}
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/** Renames a destination register to a physical register. Also records
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* the previous physical register that the logical register mapped to.
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*/
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void renameDestReg(int idx,
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PhysRegIndex renamed_dest,
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PhysRegIndex previous_rename)
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{
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_destRegIdx[idx] = renamed_dest;
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_prevDestRegIdx[idx] = previous_rename;
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}
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/** Renames a source logical register to the physical register which
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* has/will produce that logical register's result.
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* @todo: add in whether or not the source register is ready.
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*/
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void renameSrcReg(int idx, PhysRegIndex renamed_src)
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{
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_srcRegIdx[idx] = renamed_src;
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}
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public:
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/** Calculates EA part of a memory instruction. Currently unused,
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* though it may be useful in the future if we want to split
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* memory operations into EA calculation and memory access parts.
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*/
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Fault calcEA()
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{
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return this->staticInst->eaCompInst()->execute(this, this->traceData);
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}
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/** Does the memory access part of a memory instruction. Currently unused,
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* though it may be useful in the future if we want to split
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* memory operations into EA calculation and memory access parts.
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*/
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Fault memAccess()
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{
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return this->staticInst->memAccInst()->execute(this, this->traceData);
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}
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};
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#endif // __CPU_O3_ALPHA_DYN_INST_HH__
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