Be sure to delete packet and sender state if the cache is blocked.
src/cpu/o3/lsq_unit.hh: Be sure to delete data if the cache is blocked. --HG-- extra : convert_revision : fafbcfb8937e85555823942e69e798e557a600e5
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1 changed files with 18 additions and 21 deletions
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@ -626,20 +626,27 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
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++usedPorts;
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PacketPtr data_pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast);
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data_pkt->dataStatic(load_inst->memData);
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LSQSenderState *state = new LSQSenderState;
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state->isLoad = true;
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state->idx = load_idx;
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state->inst = load_inst;
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data_pkt->senderState = state;
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// if we the cache is not blocked, do cache access
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if (!lsq->cacheBlocked()) {
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PacketPtr data_pkt =
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new Packet(req, Packet::ReadReq, Packet::Broadcast);
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data_pkt->dataStatic(load_inst->memData);
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LSQSenderState *state = new LSQSenderState;
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state->isLoad = true;
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state->idx = load_idx;
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state->inst = load_inst;
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data_pkt->senderState = state;
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if (!dcachePort->sendTiming(data_pkt)) {
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if (data_pkt->result == Packet::BadAddress) {
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delete data_pkt;
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Packet::Result result = data_pkt->result;
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// Delete state and data packet because a load retry
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// initiates a pipeline restart; it does not retry.
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delete state;
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delete data_pkt;
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if (result == Packet::BadAddress) {
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return TheISA::genMachineCheckFault();
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}
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@ -669,16 +676,6 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
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return NoFault;
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}
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if (data_pkt->result != Packet::Success) {
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DPRINTF(LSQUnit, "LSQUnit: D-cache miss!\n");
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DPRINTF(Activity, "Activity: ld accessing mem miss [sn:%lli]\n",
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load_inst->seqNum);
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} else {
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DPRINTF(LSQUnit, "LSQUnit: D-cache hit!\n");
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DPRINTF(Activity, "Activity: ld accessing mem hit [sn:%lli]\n",
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load_inst->seqNum);
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}
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return NoFault;
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}
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