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Merge zizzer:/n/wexford/x/gblack/m5/newmem_bus

Browse source 
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : 7b7a1b03ffed36bce49595962ea57c08d1d1a4ad
This commit is contained in:
Ron Dreslinski 2006-10-10 17:32:24 -04:00
parent 549412b333 aff3d92c00
commit 27c59dc370
2 changed files with 3 additions and 1 deletions
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2
src/mem/cache/base_cache.cc vendored
View file

@ -221,6 +221,7 @@ BaseCache::CacheEvent::process()
}
else if (!cachePort->isCpuSide)
{
assert(cachePort->cache->doMasterRequest());
//MSHR
pkt = cachePort->cache->getPacket();
MSHR* mshr = (MSHR*) pkt->senderState;
@ -238,6 +239,7 @@ BaseCache::CacheEvent::process()
}
else
{
assert(cachePort->cache->doSlaveRequest());
//CSHR
pkt = cachePort->cache->getCoherencePacket();
bool success = cachePort->sendTiming(pkt);

2
src/mem/cache/base_cache.hh vendored
View file

@ -467,7 +467,7 @@ class BaseCache : public MemObject
*/
void setMasterRequest(RequestCause cause, Tick time)
{
if (!doMasterRequest() && memSidePort->drainList.empty())
if (!doMasterRequest() && !memSidePort->waitingOnRetry)
{
BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(memSidePort);
reqCpu->schedule(time);