Have bus use the BadAddress device to handle bad addresses. The O3 CPU should be able to boot into Linux with caches on after this change.
src/mem/bus.cc: src/mem/bus.hh: Bus now will be setup with a default responder, unless the user overrides it. This default responder should return BadAddress if no matching port is found. src/python/m5/objects/Bus.py: Bus now has a default responder for FS mode if the user doesn't override it. It returns BadAddress if no matching port is found. src/python/m5/objects/Tsunami.py: Add bad address device. Also record when the user has specified their own default responder. --HG-- extra : convert_revision : 59070477ae313ee711b2d59baa2369c9a91c5b85
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c3485a6548
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4 changed files with 46 additions and 14 deletions
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@ -42,13 +42,14 @@
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Port *
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Bus::getPort(const std::string &if_name, int idx)
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{
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if (if_name == "default")
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if (if_name == "default") {
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if (defaultPort == NULL) {
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defaultPort = new BusPort(csprintf("%s-default",name()), this,
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defaultId);
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defaultId);
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return defaultPort;
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} else
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fatal("Default port already set\n");
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}
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// if_name ignored? forced to be empty?
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int id = interfaces.size();
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@ -269,7 +270,16 @@ Bus::findPort(Addr addr, int id)
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return defaultPort;
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}
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}
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panic("Unable to find destination for addr: %#llx", addr);
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if (responderSet) {
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panic("Unable to find destination for addr (user set default "
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"responder): %#llx", addr);
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} else {
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DPRINTF(Bus, "Unable to find destination for addr: %#llx, will use "
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"default port", addr);
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return defaultPort;
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}
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}
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@ -392,12 +402,15 @@ Bus::recvStatusChange(Port::Status status, int id)
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if (id == defaultId) {
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defaultRange.clear();
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defaultPort->getPeerAddressRanges(ranges, snoops);
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assert(snoops.size() == 0);
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for(iter = ranges.begin(); iter != ranges.end(); iter++) {
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defaultRange.push_back(*iter);
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DPRINTF(BusAddrRanges, "Adding range %#llx - %#llx for default range\n",
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iter->start, iter->end);
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// Only try to update these ranges if the user set a default responder.
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if (responderSet) {
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defaultPort->getPeerAddressRanges(ranges, snoops);
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assert(snoops.size() == 0);
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for(iter = ranges.begin(); iter != ranges.end(); iter++) {
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defaultRange.push_back(*iter);
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DPRINTF(BusAddrRanges, "Adding range %#llx - %#llx for default range\n",
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iter->start, iter->end);
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}
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}
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} else {
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@ -503,18 +516,20 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(Bus)
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Param<int> bus_id;
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Param<int> clock;
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Param<int> width;
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Param<bool> responder_set;
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END_DECLARE_SIM_OBJECT_PARAMS(Bus)
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BEGIN_INIT_SIM_OBJECT_PARAMS(Bus)
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INIT_PARAM(bus_id, "a globally unique bus id"),
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INIT_PARAM(clock, "bus clock speed"),
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INIT_PARAM(width, "width of the bus (bits)")
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INIT_PARAM(width, "width of the bus (bits)"),
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INIT_PARAM(responder_set, "Is a default responder set by the user")
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END_INIT_SIM_OBJECT_PARAMS(Bus)
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CREATE_SIM_OBJECT(Bus)
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{
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return new Bus(getInstanceName(), bus_id, clock, width);
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return new Bus(getInstanceName(), bus_id, clock, width, responder_set);
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}
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REGISTER_SIM_OBJECT("Bus", Bus)
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@ -240,6 +240,9 @@ class Bus : public MemObject
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/** Port that handles requests that don't match any of the interfaces.*/
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BusPort *defaultPort;
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/** Has the user specified their own default responder? */
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bool responderSet;
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public:
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/** A function used to return the port associated with this bus object. */
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@ -247,9 +250,11 @@ class Bus : public MemObject
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virtual void init();
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Bus(const std::string &n, int bus_id, int _clock, int _width)
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Bus(const std::string &n, int bus_id, int _clock, int _width,
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bool responder_set)
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: MemObject(n), busId(bus_id), clock(_clock), width(_width),
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tickNextIdle(0), busIdle(this), inRetry(false), defaultPort(NULL)
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tickNextIdle(0), busIdle(this), inRetry(false), defaultPort(NULL),
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responderSet(responder_set)
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{
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//Both the width and clock period must be positive
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if (width <= 0)
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@ -1,10 +1,18 @@
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from m5 import build_env
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from m5.params import *
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from m5.proxy import *
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from MemObject import MemObject
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from Tsunami import BadAddr
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class Bus(MemObject):
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type = 'Bus'
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port = VectorPort("vector port for connecting devices")
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default = Port("Default port for requests that aren't handeled by a device.")
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bus_id = Param.Int(0, "blah")
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clock = Param.Clock("1GHz", "bus clock speed")
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width = Param.Int(64, "bus width (bytes)")
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responder_set = Param.Bool(False, "Did the user specify a default responder.")
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if build_env['FULL_SYSTEM']:
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default = Port(Self.responder.pio, "Default port for requests that aren't handled by a device.")
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responder = BadAddr(pio_addr=0x0, pio_latency="1ps")
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else:
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default = Port("Default port for requests that aren't handled by a device.")
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@ -15,6 +15,9 @@ class IsaFake(BasicPioDevice):
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type = 'IsaFake'
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pio_size = Param.Addr(0x8, "Size of address range")
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class BadAddr(BasicPioDevice):
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type = 'BadAddr'
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class TsunamiIO(BasicPioDevice):
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type = 'TsunamiIO'
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time = Param.UInt64(1136073600,
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@ -70,6 +73,7 @@ class Tsunami(Platform):
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self.cchip.pio = bus.port
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self.pchip.pio = bus.port
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self.pciconfig.pio = bus.default
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bus.responder_set = True
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self.fake_sm_chip.pio = bus.port
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self.fake_uart1.pio = bus.port
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self.fake_uart2.pio = bus.port
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