Change the cpu pointer in the InstRecord object to a thread context pointer.
--HG-- extra : convert_revision : 7efb2680cef4219281b94d680a4a7c75c123f89d
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05177abbc9
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@ -66,20 +66,19 @@ Trace::InstRecord::dump(ostream &outs)
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static const char * prefixes[4] = {"G", "O", "L", "I"};
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if (flags[PRINT_REG_DELTA])
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{
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ThreadContext * context = cpu->threadContexts[0];
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char buf[256];
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sprintf(buf, "PC = 0x%016llx", context->readNextPC());
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sprintf(buf, "PC = 0x%016llx", thread->readNextPC());
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outs << buf;
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sprintf(buf, " NPC = 0x%016llx", context->readNextNPC());
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sprintf(buf, " NPC = 0x%016llx", thread->readNextNPC());
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outs << buf;
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newVal = context->readMiscReg(SparcISA::MISCREG_CCR);
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newVal = thread->readMiscReg(SparcISA::MISCREG_CCR);
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if(newVal != ccr)
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{
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sprintf(buf, " CCR = 0x%016llx", newVal);
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outs << buf;
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ccr = newVal;
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}
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newVal = context->readMiscReg(SparcISA::MISCREG_Y);
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newVal = thread->readMiscReg(SparcISA::MISCREG_Y);
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if(newVal != y)
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{
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sprintf(buf, " Y = 0x%016llx", newVal);
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@ -91,7 +90,7 @@ Trace::InstRecord::dump(ostream &outs)
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for(int x = 0; x < 8; x++)
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{
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int index = x + 8 * y;
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newVal = context->readIntReg(index);
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newVal = thread->readIntReg(index);
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if(regs[index] != newVal)
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{
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sprintf(buf, " %s%d = 0x%016llx", prefixes[y], x, newVal);
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@ -102,7 +101,7 @@ Trace::InstRecord::dump(ostream &outs)
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}
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for(int y = 0; y < 32; y++)
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{
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newVal = context->readFloatRegBits(2 * y, 64);
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newVal = thread->readFloatRegBits(2 * y, 64);
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if(floats[y] != newVal)
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{
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sprintf(buf, " F%d = 0x%016llx", y, newVal);
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@ -111,37 +110,10 @@ Trace::InstRecord::dump(ostream &outs)
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}
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}
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outs << endl;
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/*
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int numSources = staticInst->numSrcRegs();
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int numDests = staticInst->numDestRegs();
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outs << "Sources:";
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for(int x = 0; x < numSources; x++)
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{
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int sourceNum = staticInst->srcRegIdx(x);
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if(sourceNum < FP_Base_DepTag)
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outs << " " << getIntRegName(sourceNum);
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else if(sourceNum < Ctrl_Base_DepTag)
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outs << " " << getFloatRegName(sourceNum - FP_Base_DepTag);
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else
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outs << " " << getMiscRegName(sourceNum - Ctrl_Base_DepTag);
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}
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outs << endl;
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outs << "Destinations:";
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for(int x = 0; x < numDests; x++)
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{
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int destNum = staticInst->destRegIdx(x);
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if(destNum < FP_Base_DepTag)
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outs << " " << getIntRegName(destNum);
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else if(destNum < Ctrl_Base_DepTag)
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outs << " " << getFloatRegName(destNum - FP_Base_DepTag);
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else
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outs << " " << getMiscRegName(destNum - Ctrl_Base_DepTag);
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}
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outs << endl;*/
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}
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else if (flags[INTEL_FORMAT]) {
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#if FULL_SYSTEM
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bool is_trace_system = (cpu->system->name() == trace_system);
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bool is_trace_system = (thread->getCpuPtr()->system->name() == trace_system);
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#else
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bool is_trace_system = true;
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#endif
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@ -161,13 +133,13 @@ Trace::InstRecord::dump(ostream &outs)
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if (flags[PRINT_CYCLE])
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ccprintf(outs, "%7d: ", cycle);
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outs << cpu->name() << " ";
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outs << thread->getCpuPtr()->name() << " ";
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if (flags[TRACE_MISSPEC])
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outs << (misspeculating ? "-" : "+") << " ";
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if (flags[PRINT_THREAD_NUM])
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outs << "T" << thread << " : ";
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outs << "T" << thread->getThreadNum() << " : ";
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std::string sym_str;
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@ -41,7 +41,7 @@
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#include "cpu/thread_context.hh"
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#include "cpu/static_inst.hh"
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class BaseCPU;
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class ThreadContext;
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namespace Trace {
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@ -53,13 +53,12 @@ class InstRecord : public Record
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// The following fields are initialized by the constructor and
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// thus guaranteed to be valid.
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BaseCPU *cpu;
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ThreadContext *thread;
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// need to make this ref-counted so it doesn't go away before we
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// dump the record
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StaticInstPtr staticInst;
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Addr PC;
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bool misspeculating;
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unsigned thread;
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// The remaining fields are only valid for particular instruction
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// types (e.g, addresses for memory ops) or when particular
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@ -95,11 +94,12 @@ class InstRecord : public Record
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bool regs_valid;
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public:
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InstRecord(Tick _cycle, BaseCPU *_cpu,
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InstRecord(Tick _cycle, ThreadContext *_thread,
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const StaticInstPtr &_staticInst,
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Addr _pc, bool spec, int _thread)
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: Record(_cycle), cpu(_cpu), staticInst(_staticInst), PC(_pc),
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misspeculating(spec), thread(_thread)
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Addr _pc, bool spec)
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: Record(_cycle), thread(_thread),
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staticInst(_staticInst), PC(_pc),
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misspeculating(spec)
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{
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data_status = DataInvalid;
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addr_valid = false;
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@ -174,14 +174,14 @@ InstRecord::setRegs(const IntRegFile ®s)
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inline
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InstRecord *
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getInstRecord(Tick cycle, ThreadContext *tc, BaseCPU *cpu,
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getInstRecord(Tick cycle, ThreadContext *tc,
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const StaticInstPtr staticInst,
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Addr pc, int thread = 0)
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Addr pc)
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{
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if (DTRACE(InstExec) &&
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(InstRecord::traceMisspec() || !tc->misspeculating())) {
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return new InstRecord(cycle, cpu, staticInst, pc,
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tc->misspeculating(), thread);
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return new InstRecord(cycle, tc, staticInst, pc,
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tc->misspeculating());
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}
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return NULL;
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@ -398,7 +398,7 @@ BaseSimpleCPU::preExecute()
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inst = gtoh(inst);
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curStaticInst = StaticInst::decode(makeExtMI(inst, thread->readPC()));
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traceData = Trace::getInstRecord(curTick, tc, this, curStaticInst,
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traceData = Trace::getInstRecord(curTick, tc, curStaticInst,
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thread->readPC());
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DPRINTF(Decode,"Decode: Decoded %s instruction (opcode: 0x%x): 0x%x\n",
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