Enable proxies (Self/Parent) for specifying ports.
Significant revamp of Port code.
Some cleanup of SimObject code too, particularly to
make the SimObject and MetaSimObject implementations of
__setattr__ more consistent.
Unproxy code split out of print_ini().
src/python/m5/multidict.py:
Make get() return None by default, to match semantics
of built-in dictionary objects.
--HG--
extra : convert_revision : db73b6cdd004a82a08b2402afd1e16544cb902a4
This commit is contained in:
Steve Reinhardt
parent
6c7a490c2b
commit
545cbec5f7
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@ -66,11 +66,7 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None):
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self.tsunami = BaseTsunami()
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self.tsunami.attachIO(self.iobus)
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self.tsunami.ide.pio = self.iobus.port
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self.tsunami.ide.dma = self.iobus.port
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self.tsunami.ide.config = self.iobus.port
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self.tsunami.ethernet.pio = self.iobus.port
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self.tsunami.ethernet.dma = self.iobus.port
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self.tsunami.ethernet.config = self.iobus.port
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self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
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read_only = True))
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self.intrctrl = IntrControl()
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@ -161,7 +161,7 @@ class MetaSimObject(type):
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# class or instance attributes
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cls._values = multidict() # param values
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cls._port_map = multidict() # port bindings
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cls._port_refs = multidict() # port ref objects
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cls._instantiated = False # really instantiated, cloned, or subclassed
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# We don't support multiple inheritance. If you want to, you
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@ -179,7 +179,7 @@ class MetaSimObject(type):
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cls._params.parent = base._params
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cls._ports.parent = base._ports
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cls._values.parent = base._values
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cls._port_map.parent = base._port_map
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cls._port_refs.parent = base._port_refs
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# mark base as having been subclassed
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base._instantiated = True
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@ -197,7 +197,7 @@ class MetaSimObject(type):
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# port objects
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elif isinstance(val, Port):
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cls._ports[key] = val
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cls._new_port(key, val)
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# init-time-only keywords
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elif cls.init_keywords.has_key(key):
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@ -227,7 +227,36 @@ class MetaSimObject(type):
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pdesc.name = name
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cls._params[name] = pdesc
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if hasattr(pdesc, 'default'):
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setattr(cls, name, pdesc.default)
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cls._set_param(name, pdesc.default, pdesc)
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def _set_param(cls, name, value, param):
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assert(param.name == name)
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try:
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cls._values[name] = param.convert(value)
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except Exception, e:
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msg = "%s\nError setting param %s.%s to %s\n" % \
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(e, cls.__name__, name, value)
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e.args = (msg, )
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raise
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def _new_port(cls, name, port):
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# each port should be uniquely assigned to one variable
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assert(not hasattr(port, 'name'))
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port.name = name
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cls._ports[name] = port
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if hasattr(port, 'default'):
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cls._cls_get_port_ref(name).connect(port.default)
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# same as _get_port_ref, effectively, but for classes
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def _cls_get_port_ref(cls, attr):
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# Return reference that can be assigned to another port
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# via __setattr__. There is only ever one reference
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# object per port, but we create them lazily here.
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ref = cls._port_refs.get(attr)
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if not ref:
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ref = cls._ports[attr].makeRef(cls)
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cls._port_refs[attr] = ref
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return ref
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# Set attribute (called on foo.attr = value when foo is an
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# instance of class cls).
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@ -242,7 +271,7 @@ class MetaSimObject(type):
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return
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if cls._ports.has_key(attr):
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self._ports[attr].connect(self, attr, value)
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cls._cls_get_port_ref(attr).connect(value)
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return
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if isSimObjectOrSequence(value) and cls._instantiated:
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@ -252,21 +281,23 @@ class MetaSimObject(type):
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% (attr, cls.__name__)
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# check for param
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param = cls._params.get(attr, None)
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param = cls._params.get(attr)
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if param:
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try:
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cls._values[attr] = param.convert(value)
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except Exception, e:
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msg = "%s\nError setting param %s.%s to %s\n" % \
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(e, cls.__name__, attr, value)
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e.args = (msg, )
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raise
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elif isSimObjectOrSequence(value):
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# if RHS is a SimObject, it's an implicit child assignment
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cls._set_param(attr, value, param)
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return
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if isSimObjectOrSequence(value):
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# If RHS is a SimObject, it's an implicit child assignment.
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# Classes don't have children, so we just put this object
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# in _values; later, each instance will do a 'setattr(self,
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# attr, _values[attr])' in SimObject.__init__ which will
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# add this object as a child.
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cls._values[attr] = value
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else:
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raise AttributeError, \
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"Class %s has no parameter \'%s\'" % (cls.__name__, attr)
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return
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# no valid assignment... raise exception
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raise AttributeError, \
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"Class %s has no parameter \'%s\'" % (cls.__name__, attr)
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def __getattr__(cls, attr):
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if cls._values.has_key(attr):
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@ -422,9 +453,9 @@ class SimObject(object):
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setattr(self, key, [ v(_memo=memo_dict) for v in val ])
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# clone port references. no need to use a multidict here
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# since we will be creating new references for all ports.
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self._port_map = {}
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for key,val in ancestor._port_map.iteritems():
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self._port_map[key] = applyOrMap(val, 'clone', memo_dict)
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self._port_refs = {}
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for key,val in ancestor._port_refs.iteritems():
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self._port_refs[key] = val.clone(self, memo_dict)
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# apply attribute assignments from keyword args, if any
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for key,val in kwargs.iteritems():
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setattr(self, key, val)
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@ -451,11 +482,19 @@ class SimObject(object):
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return memo_dict[self]
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return self.__class__(_ancestor = self, **kwargs)
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def _get_port_ref(self, attr):
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# Return reference that can be assigned to another port
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# via __setattr__. There is only ever one reference
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# object per port, but we create them lazily here.
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ref = self._port_refs.get(attr)
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if not ref:
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ref = self._ports[attr].makeRef(self)
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self._port_refs[attr] = ref
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return ref
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def __getattr__(self, attr):
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if self._ports.has_key(attr):
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# return reference that can be assigned to another port
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# via __setattr__
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return self._ports[attr].makeRef(self, attr)
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return self._get_port_ref(attr)
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if self._values.has_key(attr):
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return self._values[attr]
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@ -473,7 +512,7 @@ class SimObject(object):
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if self._ports.has_key(attr):
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# set up port connection
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self._ports[attr].connect(self, attr, value)
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self._get_port_ref(attr).connect(value)
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return
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if isSimObjectOrSequence(value) and self._instantiated:
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@ -482,7 +521,7 @@ class SimObject(object):
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" instance been cloned %s" % (attr, `self`)
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# must be SimObject param
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param = self._params.get(attr, None)
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param = self._params.get(attr)
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if param:
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try:
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value = param.convert(value)
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@ -491,22 +530,17 @@ class SimObject(object):
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(e, self.__class__.__name__, attr, value)
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e.args = (msg, )
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raise
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elif isSimObjectOrSequence(value):
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pass
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else:
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raise AttributeError, "Class %s has no parameter %s" \
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% (self.__class__.__name__, attr)
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self._set_child(attr, value)
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return
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# clear out old child with this name, if any
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self.clear_child(attr)
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if isSimObjectOrSequence(value):
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self._set_child(attr, value)
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return
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if isSimObject(value):
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value.set_path(self, attr)
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elif isSimObjectSequence(value):
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value = SimObjVector(value)
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[v.set_path(self, "%s%d" % (attr, i)) for i,v in enumerate(value)]
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# no valid assignment... raise exception
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raise AttributeError, "Class %s has no parameter %s" \
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% (self.__class__.__name__, attr)
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self._values[attr] = value
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# this hack allows tacking a '[0]' onto parameters that may or may
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# not be vectors, and always getting the first element (e.g. cpus)
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@ -528,12 +562,26 @@ class SimObject(object):
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def add_child(self, name, value):
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self._children[name] = value
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def set_path(self, parent, name):
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def _maybe_set_parent(self, parent, name):
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if not self._parent:
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self._parent = parent
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self._name = name
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parent.add_child(name, self)
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def _set_child(self, attr, value):
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# if RHS is a SimObject, it's an implicit child assignment
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# clear out old child with this name, if any
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self.clear_child(attr)
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if isSimObject(value):
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value._maybe_set_parent(self, attr)
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elif isSimObjectSequence(value):
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value = SimObjVector(value)
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[v._maybe_set_parent(self, "%s%d" % (attr, i))
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for i,v in enumerate(value)]
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self._values[attr] = value
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def path(self):
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if not self._parent:
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return 'root'
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@ -573,6 +621,26 @@ class SimObject(object):
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def unproxy(self, base):
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return self
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def unproxy_all(self):
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for param in self._params.iterkeys():
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value = self._values.get(param)
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if value != None and proxy.isproxy(value):
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try:
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value = value.unproxy(self)
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except:
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print "Error in unproxying param '%s' of %s" % \
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(param, self.path())
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raise
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setattr(self, param, value)
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for port_name in self._ports.iterkeys():
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port = self._port_refs.get(port_name)
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if port != None:
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port.unproxy(self)
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for child in self._children.itervalues():
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child.unproxy_all()
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def print_ini(self):
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print '[' + self.path() + ']' # .ini section header
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@ -591,32 +659,16 @@ class SimObject(object):
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param_names = self._params.keys()
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param_names.sort()
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for param in param_names:
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value = self._values.get(param, None)
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value = self._values.get(param)
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if value != None:
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if proxy.isproxy(value):
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try:
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value = value.unproxy(self)
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except:
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print >> sys.stderr, \
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"Error in unproxying param '%s' of %s" % \
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(param, self.path())
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raise
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setattr(self, param, value)
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print '%s=%s' % (param, self._values[param].ini_str())
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port_names = self._ports.keys()
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port_names.sort()
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for port_name in port_names:
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port = self._port_map.get(port_name, None)
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if port == None:
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default = getattr(self._ports[port_name], 'default', None)
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if default == None:
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# port is unbound... that's OK, go to next port
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continue
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else:
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print port_name, default
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port = m5.makeList(port) # make list even if it's a scalar port
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print '%s=%s' % (port_name, ' '.join([str(p) for p in port]))
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port = self._port_refs.get(port_name, None)
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if port != None:
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print '%s=%s' % (port_name, port.ini_str())
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print # blank line between objects
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@ -643,10 +695,10 @@ class SimObject(object):
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return self._ccObject
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# Create C++ port connections corresponding to the connections in
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# _port_map (& recursively for all children)
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# _port_refs (& recursively for all children)
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def connectPorts(self):
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for portRef in self._port_map.itervalues():
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applyOrMap(portRef, 'ccConnect')
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for portRef in self._port_refs.itervalues():
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portRef.ccConnect()
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for child in self._children.itervalues():
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child.connectPorts()
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|
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@ -44,6 +44,7 @@ def panic(string):
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print >>sys.stderr, 'panic:', string
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sys.exit(1)
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# force scalars to one-element lists for uniformity
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def makeList(objOrList):
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if isinstance(objOrList, list):
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return objOrList
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@ -75,6 +76,7 @@ env.update(os.environ)
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# once the config is built.
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def instantiate(root):
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params.ticks_per_sec = float(root.clock.frequency)
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root.unproxy_all()
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# ugly temporary hack to get output to config.ini
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sys.stdout = file(os.path.join(options.outdir, 'config.ini'), 'w')
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root.print_ini()
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@ -29,7 +29,6 @@
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__all__ = [ 'multidict' ]
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class multidict(object):
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__nodefault = object()
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def __init__(self, parent = {}, **kwargs):
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self.local = dict(**kwargs)
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self.parent = parent
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@ -102,14 +101,11 @@ class multidict(object):
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def values(self):
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return [ value for key,value in self.next() ]
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def get(self, key, default=__nodefault):
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def get(self, key, default=None):
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try:
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return self[key]
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except KeyError, e:
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if default != self.__nodefault:
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return default
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else:
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raise KeyError, e
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return default
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def setdefault(self, key, default):
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try:
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|
|
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@ -18,4 +18,4 @@ class BasicPioDevice(PioDevice):
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class DmaDevice(PioDevice):
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type = 'DmaDevice'
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abstract = True
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dma = Port("DMA port")
|
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dma = Port(Self.pio.peerObj.port, "DMA port")
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|
|
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|||
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@ -50,7 +50,7 @@ class PciConfigAll(PioDevice):
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class PciDevice(DmaDevice):
|
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type = 'PciDevice'
|
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abstract = True
|
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config = Port("PCI configuration space port")
|
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config = Port(Self.pio.peerObj.port, "PCI configuration space port")
|
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pci_bus = Param.Int("PCI bus")
|
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pci_dev = Param.Int("PCI device number")
|
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pci_func = Param.Int("PCI function code")
|
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|
|
|
|||
|
|
@ -752,61 +752,72 @@ AllMemory = AddrRange(0, MaxAddr)
|
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# Port reference: encapsulates a reference to a particular port on a
|
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# particular SimObject.
|
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class PortRef(object):
|
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def __init__(self, simobj, name, isVec):
|
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assert(isSimObject(simobj))
|
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def __init__(self, simobj, name):
|
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assert(isSimObject(simobj) or isSimObjectClass(simobj))
|
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self.simobj = simobj
|
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self.name = name
|
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self.index = -1
|
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self.isVec = isVec # is this a vector port?
|
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self.peer = None # not associated with another port yet
|
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self.ccConnected = False # C++ port connection done?
|
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self.index = -1 # always -1 for non-vector ports
|
||||
|
||||
def __str__(self):
|
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ext = ''
|
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if self.isVec:
|
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ext = '[%d]' % self.index
|
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return '%s.%s%s' % (self.simobj.path(), self.name, ext)
|
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return '%s.%s' % (self.simobj, self.name)
|
||||
|
||||
# Set peer port reference. Called via __setattr__ as a result of
|
||||
# a port assignment, e.g., "obj1.port1 = obj2.port2".
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def setPeer(self, other):
|
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if self.isVec:
|
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curMap = self.simobj._port_map.get(self.name, [])
|
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self.index = len(curMap)
|
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curMap.append(other)
|
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else:
|
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curMap = self.simobj._port_map.get(self.name)
|
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if curMap and not self.isVec:
|
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print "warning: overwriting port", self.simobj, self.name
|
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curMap = other
|
||||
self.simobj._port_map[self.name] = curMap
|
||||
# for config.ini, print peer's name (not ours)
|
||||
def ini_str(self):
|
||||
return str(self.peer)
|
||||
|
||||
def __getattr__(self, attr):
|
||||
if attr == 'peerObj':
|
||||
# shorthand for proxies
|
||||
return self.peer.simobj
|
||||
raise AttributeError, "'%s' object has no attribute '%s'" % \
|
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(self.__class__.__name__, attr)
|
||||
|
||||
# Full connection is symmetric (both ways). Called via
|
||||
# SimObject.__setattr__ as a result of a port assignment, e.g.,
|
||||
# "obj1.portA = obj2.portB", or via VectorPortRef.__setitem__,
|
||||
# e.g., "obj1.portA[3] = obj2.portB".
|
||||
def connect(self, other):
|
||||
if isinstance(other, VectorPortRef):
|
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# reference to plain VectorPort is implicit append
|
||||
other = other._get_next()
|
||||
if not (isinstance(other, PortRef) or proxy.isproxy(other)):
|
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raise TypeError, \
|
||||
"assigning non-port reference '%s' to port '%s'" \
|
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% (other, self)
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if self.peer and not proxy.isproxy(self.peer):
|
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print "warning: overwriting port", self, \
|
||||
"value", self.peer, "with", other
|
||||
self.peer = other
|
||||
assert(not isinstance(self.peer, VectorPortRef))
|
||||
if isinstance(other, PortRef) and other.peer is not self:
|
||||
other.connect(self)
|
||||
|
||||
def clone(self, memo):
|
||||
def clone(self, simobj, memo):
|
||||
if memo.has_key(self):
|
||||
return memo[self]
|
||||
newRef = copy.copy(self)
|
||||
memo[self] = newRef
|
||||
newRef.simobj = simobj
|
||||
assert(isSimObject(newRef.simobj))
|
||||
newRef.simobj = newRef.simobj(_memo=memo)
|
||||
# Tricky: if I'm the *second* PortRef in the pair to be
|
||||
# cloned, then my peer is still in the middle of its clone
|
||||
# method, and thus hasn't returned to its owner's
|
||||
# SimObject.__init__ to get installed in _port_map. As a
|
||||
# result I have no way of finding the *new* peer object. So I
|
||||
# mark myself as "waiting" for my peer, and I let the *first*
|
||||
# PortRef clone call set up both peer pointers after I return.
|
||||
newPeer = newRef.simobj._port_map.get(self.name)
|
||||
if newPeer:
|
||||
if self.isVec:
|
||||
assert(self.index != -1)
|
||||
newPeer = newPeer[self.index]
|
||||
# other guy is all set up except for his peer pointer
|
||||
assert(newPeer.peer == -1) # peer must be waiting for handshake
|
||||
newPeer.peer = newRef
|
||||
newRef.peer = newPeer
|
||||
else:
|
||||
# other guy is in clone; just wait for him to do the work
|
||||
newRef.peer = -1 # mark as waiting for handshake
|
||||
if self.peer and not proxy.isproxy(self.peer):
|
||||
peerObj = memo[self.peer.simobj]
|
||||
newRef.peer = self.peer.clone(peerObj, memo)
|
||||
assert(not isinstance(newRef.peer, VectorPortRef))
|
||||
return newRef
|
||||
|
||||
def unproxy(self, simobj):
|
||||
assert(simobj is self.simobj)
|
||||
if proxy.isproxy(self.peer):
|
||||
try:
|
||||
realPeer = self.peer.unproxy(self.simobj)
|
||||
except:
|
||||
print "Error in unproxying port '%s' of %s" % \
|
||||
(self.name, self.simobj.path())
|
||||
raise
|
||||
self.connect(realPeer)
|
||||
|
||||
# Call C++ to create corresponding port connection between C++ objects
|
||||
def ccConnect(self):
|
||||
if self.ccConnected: # already done this
|
||||
|
|
@ -817,36 +828,94 @@ class PortRef(object):
|
|||
self.ccConnected = True
|
||||
peer.ccConnected = True
|
||||
|
||||
# A reference to an individual element of a VectorPort... much like a
|
||||
# PortRef, but has an index.
|
||||
class VectorPortElementRef(PortRef):
|
||||
def __init__(self, simobj, name, index):
|
||||
PortRef.__init__(self, simobj, name)
|
||||
self.index = index
|
||||
|
||||
def __str__(self):
|
||||
return '%s.%s[%d]' % (self.simobj, self.name, self.index)
|
||||
|
||||
# A reference to a complete vector-valued port (not just a single element).
|
||||
# Can be indexed to retrieve individual VectorPortElementRef instances.
|
||||
class VectorPortRef(object):
|
||||
def __init__(self, simobj, name):
|
||||
assert(isSimObject(simobj) or isSimObjectClass(simobj))
|
||||
self.simobj = simobj
|
||||
self.name = name
|
||||
self.elements = []
|
||||
|
||||
# for config.ini, print peer's name (not ours)
|
||||
def ini_str(self):
|
||||
return ' '.join([el.ini_str() for el in self.elements])
|
||||
|
||||
def __getitem__(self, key):
|
||||
if not isinstance(key, int):
|
||||
raise TypeError, "VectorPort index must be integer"
|
||||
if key >= len(self.elements):
|
||||
# need to extend list
|
||||
ext = [VectorPortElementRef(self.simobj, self.name, i)
|
||||
for i in range(len(self.elements), key+1)]
|
||||
self.elements.extend(ext)
|
||||
return self.elements[key]
|
||||
|
||||
def _get_next(self):
|
||||
return self[len(self.elements)]
|
||||
|
||||
def __setitem__(self, key, value):
|
||||
if not isinstance(key, int):
|
||||
raise TypeError, "VectorPort index must be integer"
|
||||
self[key].connect(value)
|
||||
|
||||
def connect(self, other):
|
||||
# reference to plain VectorPort is implicit append
|
||||
self._get_next().connect(other)
|
||||
|
||||
def unproxy(self, simobj):
|
||||
[el.unproxy(simobj) for el in self.elements]
|
||||
|
||||
def ccConnect(self):
|
||||
[el.ccConnect() for el in self.elements]
|
||||
|
||||
# Port description object. Like a ParamDesc object, this represents a
|
||||
# logical port in the SimObject class, not a particular port on a
|
||||
# SimObject instance. The latter are represented by PortRef objects.
|
||||
class Port(object):
|
||||
def __init__(self, desc):
|
||||
self.desc = desc
|
||||
self.isVec = False
|
||||
# Port("description") or Port(default, "description")
|
||||
def __init__(self, *args):
|
||||
if len(args) == 1:
|
||||
self.desc = args[0]
|
||||
elif len(args) == 2:
|
||||
self.default = args[0]
|
||||
self.desc = args[1]
|
||||
else:
|
||||
raise TypeError, 'wrong number of arguments'
|
||||
# self.name is set by SimObject class on assignment
|
||||
# e.g., pio_port = Port("blah") sets self.name to 'pio_port'
|
||||
|
||||
# Generate a PortRef for this port on the given SimObject with the
|
||||
# given name
|
||||
def makeRef(self, simobj, name):
|
||||
return PortRef(simobj, name, self.isVec)
|
||||
def makeRef(self, simobj):
|
||||
return PortRef(simobj, self.name)
|
||||
|
||||
# Connect an instance of this port (on the given SimObject with
|
||||
# the given name) with the port described by the supplied PortRef
|
||||
def connect(self, simobj, name, ref):
|
||||
if not isinstance(ref, PortRef):
|
||||
raise TypeError, \
|
||||
"assigning non-port reference port '%s'" % name
|
||||
myRef = self.makeRef(simobj, name)
|
||||
myRef.setPeer(ref)
|
||||
ref.setPeer(myRef)
|
||||
def connect(self, simobj, ref):
|
||||
self.makeRef(simobj).connect(ref)
|
||||
|
||||
# VectorPort description object. Like Port, but represents a vector
|
||||
# of connections (e.g., as on a Bus).
|
||||
class VectorPort(Port):
|
||||
def __init__(self, desc):
|
||||
Port.__init__(self, desc)
|
||||
def __init__(self, *args):
|
||||
Port.__init__(self, *args)
|
||||
self.isVec = True
|
||||
|
||||
def makeRef(self, simobj):
|
||||
return VectorPortRef(simobj, self.name)
|
||||
|
||||
|
||||
|
||||
__all__ = ['Param', 'VectorParam',
|
||||
'Enum', 'Bool', 'String', 'Float',
|
||||
|
|
|
|||
|
|
@ -41,7 +41,8 @@ class BaseProxy(object):
|
|||
|
||||
def __setattr__(self, attr, value):
|
||||
if not attr.startswith('_'):
|
||||
raise AttributeError, 'cannot set attribute on proxy object'
|
||||
raise AttributeError, \
|
||||
"cannot set attribute '%s' on proxy object" % attr
|
||||
super(BaseProxy, self).__setattr__(attr, value)
|
||||
|
||||
# support multiplying proxies by constants
|
||||
|
|
|
|||
Loading…
Reference in a new issue