Fix up microcode support.
src/arch/sparc/isa/formats/blockmem.isa:
Several small and medium bug fixes.
src/cpu/simple/base.cc:
Fixed a few compiler errors and made sure the next micro pc is set to 1 to prevent the first microop from executing twice. Also fixed a fetching bug.
src/cpu/thread_state.cc:
Made sure the microPC and nextMicroPC are initialized properly.
--HG--
extra : convert_revision : a0fc8aa18d1ade916f17c557181a793c6108a8af
This commit is contained in:
Gabe Black
parent
7fefa2a621
commit
f1661baf30
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@ -16,9 +16,6 @@ output header {{
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ExtMachInst _machInst, OpClass __opClass) :
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SparcMacroInst(mnem, _machInst, __opClass, 8)
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{}
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std::string generateDisassembly(Addr pc,
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const SymbolTable *symtab) const;
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};
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class BlockMemImm : public BlockMem
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@ -32,9 +29,6 @@ output header {{
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imm(sext<13>(SIMM13))
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{}
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std::string generateDisassembly(Addr pc,
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const SymbolTable *symtab) const;
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const int32_t imm;
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};
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@ -74,7 +68,7 @@ output header {{
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}};
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output decoder {{
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std::string BlockMem::generateDisassembly(Addr pc,
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std::string BlockMemMicro::generateDisassembly(Addr pc,
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const SymbolTable *symtab) const
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{
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std::stringstream response;
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@ -101,7 +95,7 @@ output decoder {{
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return response.str();
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}
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std::string BlockMemImm::generateDisassembly(Addr pc,
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std::string BlockMemImmMicro::generateDisassembly(Addr pc,
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const SymbolTable *symtab) const
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{
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std::stringstream response;
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@ -165,17 +159,14 @@ def template BlockMemDeclare {{
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{
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public:
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//Constructor
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%(class_name)s(MachInst machInst);
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%(class_name)s(ExtMachInst machInst);
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protected:
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class %(class_name)s_0 : public %(base_class)sMicro
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{
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public:
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//Constructor
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%(class_name)s_0(MachInst machInst) :
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%(base_class)sMicro("%(mnemonic)s[0]",
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machInst, %(op_class)s, 0*8)
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{;}
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%(class_name)s_0(ExtMachInst machInst);
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%(BasicExecDeclare)s
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};
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@ -183,10 +174,7 @@ def template BlockMemDeclare {{
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{
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public:
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//Constructor
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%(class_name)s_1(MachInst machInst) :
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%(base_class)sMicro("%(mnemonic)s[1]",
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machInst, %(op_class)s, 1*8)
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{;}
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%(class_name)s_1(ExtMachInst machInst);
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%(BasicExecDeclare)s
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};
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@ -194,10 +182,7 @@ def template BlockMemDeclare {{
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{
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public:
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//Constructor
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%(class_name)s_2(MachInst machInst) :
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%(base_class)sMicro("%(mnemonic)s[2]",
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machInst, %(op_class)s, 2*8)
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{;}
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%(class_name)s_2(ExtMachInst machInst);
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%(BasicExecDeclare)s
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};
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@ -205,10 +190,7 @@ def template BlockMemDeclare {{
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{
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public:
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//Constructor
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%(class_name)s_3(MachInst machInst) :
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%(base_class)sMicro("%(mnemonic)s[3]",
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machInst, %(op_class)s, 3*8)
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{;}
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%(class_name)s_3(ExtMachInst machInst);
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%(BasicExecDeclare)s
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};
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@ -216,10 +198,7 @@ def template BlockMemDeclare {{
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{
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public:
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//Constructor
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%(class_name)s_4(MachInst machInst) :
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%(base_class)sMicro("%(mnemonic)s[4]",
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machInst, %(op_class)s, 4*8)
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{;}
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%(class_name)s_4(ExtMachInst machInst);
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%(BasicExecDeclare)s
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};
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@ -227,10 +206,7 @@ def template BlockMemDeclare {{
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{
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public:
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//Constructor
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%(class_name)s_5(MachInst machInst) :
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%(base_class)sMicro("%(mnemonic)s[5]",
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machInst, %(op_class)s, 5*8)
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{;}
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%(class_name)s_5(ExtMachInst machInst);
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%(BasicExecDeclare)s
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};
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@ -238,10 +214,7 @@ def template BlockMemDeclare {{
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{
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public:
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//Constructor
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%(class_name)s_6(MachInst machInst) :
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%(base_class)sMicro("%(mnemonic)s[6]",
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machInst, %(op_class)s, 6*8)
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{;}
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%(class_name)s_6(ExtMachInst machInst);
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%(BasicExecDeclare)s
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};
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@ -249,12 +222,7 @@ def template BlockMemDeclare {{
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{
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public:
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//Constructor
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%(class_name)s_7(MachInst machInst) :
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%(base_class)sMicro("%(mnemonic)s[7]",
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machInst, %(op_class)s, 7*8)
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{
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flags[IsLastMicroOp] = true;
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}
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%(class_name)s_7(ExtMachInst machInst);
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%(BasicExecDeclare)s
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};
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};
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@ -262,7 +230,7 @@ def template BlockMemDeclare {{
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// Basic instruction class constructor template.
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def template BlockMemConstructor {{
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inline %(class_name)s::%(class_name)s(MachInst machInst)
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inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
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{
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%(constructor)s;
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@ -277,16 +245,28 @@ def template BlockMemConstructor {{
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}
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}};
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def template BlockMemMicroConstructor {{
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inline %(class_name)s::
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%(class_name)s_%(micro_pc)s::
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%(class_name)s_%(micro_pc)s(ExtMachInst machInst) :
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%(base_class)sMicro("%(mnemonic)s[%(micro_pc)s]",
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machInst, %(op_class)s, %(micro_pc)s * 8)
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{
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%(constructor)s;
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%(set_flags)s;
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}
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}};
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def template MicroLoadExecute {{
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Fault %(class_name)s_%(micro_pc)s::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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Fault %(class_name)s::%(class_name)s_%(micro_pc)s::execute(
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%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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Addr EA;
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%(op_decl)s;
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%(op_rd)s;
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%(fault_check)s;
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%(ea_code)s;
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%(fault_check)s;
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DPRINTF(Sparc, "The address is 0x%x\n", EA);
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xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, 0);
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%(code)s;
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@ -310,8 +290,8 @@ def template MicroStoreExecute {{
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Addr EA;
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%(op_decl)s;
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%(op_rd)s;
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%(fault_check)s;
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%(ea_code)s;
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%(fault_check)s;
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DPRINTF(Sparc, "The address is 0x%x\n", EA);
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%(code)s;
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@ -334,14 +314,17 @@ let {{
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# those that are only available in hpriv
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faultCheck = '''if(bits(Pstate,2,2) == 0 && (EXT_ASI & 0x80) == 0)
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return new PrivilegedAction;
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if(AsiIsAsIfUser(EXT_ASI) && !bits(Pstate,2,2))
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if(AsiIsAsIfUser((ASI)EXT_ASI) && !bits(Pstate,2,2))
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return new PrivilegedAction;
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if(RD & 0xf)
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//The LSB can be zero, since it's really the MSB in doubles
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//and quads
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if(RD & 0xe)
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return new IllegalInstruction;
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if(EA & 0x3f)
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return new MemAddressNotAligned;'''
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addrCalcReg = 'EA = Rs1 + Rs2 + offset;'
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addrCalcImm = 'EA = Rs1 + imm + offset;'
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return new MemAddressNotAligned;
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'''
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addrCalcReg = 'EA = Rs1 + Rs2 + offset * 8;'
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addrCalcImm = 'EA = Rs1 + imm + offset * 8;'
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iop = InstObjParams(name, Name, 'BlockMem', code, opt_flags)
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iop_imm = InstObjParams(name, Name + 'Imm', 'BlockMemImm', code, opt_flags)
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header_output = BlockMemDeclare.subst(iop) + BlockMemDeclare.subst(iop_imm)
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@ -350,15 +333,22 @@ let {{
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matcher = re.compile(r'Frd_N')
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exec_output = ''
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for microPC in range(8):
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flag_code = ''
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if (microPC == 7):
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flag_code = "flags[IsLastMicroOp] = true"
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pcedCode = matcher.sub("Frd_%d" % microPC, code)
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iop = InstObjParams(name, Name, 'BlockMem', pcedCode,
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opt_flags, {"ea_code": addrCalcReg,
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"fault_check": faultCheck, "micro_pc": microPC})
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"fault_check": faultCheck, "micro_pc": microPC,
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"set_flags": flag_code})
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iop_imm = InstObjParams(name, Name + 'Imm', 'BlockMemImm', pcedCode,
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opt_flags, {"ea_code": addrCalcImm,
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"fault_check": faultCheck, "micro_pc": microPC})
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"fault_check": faultCheck, "micro_pc": microPC,
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"set_flags": flag_code})
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exec_output += execute.subst(iop)
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exec_output += execute.subst(iop_imm)
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decoder_output += BlockMemMicroConstructor.subst(iop)
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decoder_output += BlockMemMicroConstructor.subst(iop_imm)
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faultCheck = ''
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return (header_output, decoder_output, exec_output, decode_block)
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}};
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@ -402,10 +402,12 @@ BaseSimpleCPU::preExecute()
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if (instPtr->isMacroOp()) {
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curMacroStaticInst = instPtr;
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curStaticInst = curMacroStaticInst->fetchMicroOp(0);
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} else {
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curStaticInst = instPtr;
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}
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} else {
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//Read the next micro op from the macro op
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curStaticInst = curMacroStaticInst->fetchMicroOp(thread->readMicroPc());
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curStaticInst = curMacroStaticInst->fetchMicroOp(thread->readMicroPC());
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}
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@ -464,17 +466,17 @@ BaseSimpleCPU::advancePC(Fault fault)
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assert(curMacroStaticInst);
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//Close out this macro op, and clean up the
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//microcode state
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curMacroStaticInst = nullStaticInst;
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curMacroStaticInst = StaticInst::nullStaticInstPtr;
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thread->setMicroPC(0);
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thread->setNextMicroPC(0);
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thread->setNextMicroPC(1);
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}
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//If we're still in a macro op
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if (curMacroStaticInst) {
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//Advance the micro pc
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thread->setMicroPC(thread->getNextMicroPC());
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thread->setMicroPC(thread->readNextMicroPC());
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//Advance the "next" micro pc. Note that there are no delay
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//slots, and micro ops are "word" addressed.
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thread->setNextMicroPC(thread->getNextMicroPC() + 1);
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thread->setNextMicroPC(thread->readNextMicroPC() + 1);
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} else {
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// go to the next instruction
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thread->setPC(thread->readNextPC());
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@ -42,13 +42,13 @@
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ThreadState::ThreadState(int _cpuId, int _tid)
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: cpuId(_cpuId), tid(_tid), lastActivate(0), lastSuspend(0),
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profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL),
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funcExeInst(0), storeCondFailures(0)
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microPC(0), nextMicroPC(1), funcExeInst(0), storeCondFailures(0)
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#else
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ThreadState::ThreadState(int _cpuId, int _tid, Process *_process,
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short _asid, MemObject *mem)
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: cpuId(_cpuId), tid(_tid), lastActivate(0), lastSuspend(0),
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process(_process), asid(_asid),
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funcExeInst(0), storeCondFailures(0)
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microPC(0), nextMicroPC(1), funcExeInst(0), storeCondFailures(0)
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#endif
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{
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numInst = 0;
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