Changed how floating point register numbers are decoded to fit with the spec.
--HG-- extra : convert_revision : 155f48c84d06619c9c1c43375beb9d0a1c7495c9
This commit is contained in:
Gabe Black
parent
546dff6b6a
commit
7fefa2a621
2 changed files with 46 additions and 31 deletions
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@ -441,7 +441,7 @@ decode OP default Unknown::unknown()
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0x34: decode OPF{
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format BasicOperate{
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0x01: fmovs({{
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Frd.uw = Frs2.uw;
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Frds.uw = Frs2s.uw;
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//fsr.ftt = fsr.cexc = 0
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Fsr &= ~(7 << 14);
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Fsr &= ~(0x1F);
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@ -454,7 +454,7 @@ decode OP default Unknown::unknown()
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}});
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0x03: Trap::fmovq({{fault = new FpDisabled;}});
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0x05: fnegs({{
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Frd.uw = Frs2.uw ^ (1UL << 31);
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Frds.uw = Frs2s.uw ^ (1UL << 31);
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//fsr.ftt = fsr.cexc = 0
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Fsr &= ~(7 << 14);
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Fsr &= ~(0x1F);
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@ -467,7 +467,7 @@ decode OP default Unknown::unknown()
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}});
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0x07: Trap::fnegq({{fault = new FpDisabled;}});
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0x09: fabss({{
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Frd.uw = ((1UL << 31) - 1) & Frs2.uw;
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Frds.uw = ((1UL << 31) - 1) & Frs2s.uw;
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//fsr.ftt = fsr.cexc = 0
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Fsr &= ~(7 << 14);
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Fsr &= ~(0x1F);
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@ -479,55 +479,55 @@ decode OP default Unknown::unknown()
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Fsr &= ~(0x1F);
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}});
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0x0B: Trap::fabsq({{fault = new FpDisabled;}});
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0x29: fsqrts({{Frd.sf = sqrt(Frs2.sf);}});
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0x29: fsqrts({{Frds.sf = sqrt(Frs2s.sf);}});
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0x2A: fsqrtd({{Frd.df = sqrt(Frs2.df);}});
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0x2B: Trap::fsqrtq({{fault = new FpDisabled;}});
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0x41: fadds({{Frd.sf = Frs1.sf + Frs2.sf;}});
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0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}});
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0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}});
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0x43: Trap::faddq({{fault = new FpDisabled;}});
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0x45: fsubs({{Frd.sf = Frs1.sf - Frs2.sf;}});
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0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}});
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0x46: fsubd({{Frd.df = Frs1.df - Frs2.df;}});
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0x47: Trap::fsubq({{fault = new FpDisabled;}});
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0x49: fmuls({{Frd.sf = Frs1.sf * Frs2.sf;}});
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0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}});
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0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}});
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0x4B: Trap::fmulq({{fault = new FpDisabled;}});
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0x4D: fdivs({{Frd.sf = Frs1.sf / Frs2.sf;}});
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0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}});
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0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}});
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0x4F: Trap::fdivq({{fault = new FpDisabled;}});
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0x69: fsmuld({{Frd.df = Frs1.sf * Frs2.sf;}});
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0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}});
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0x6E: Trap::fdmulq({{fault = new FpDisabled;}});
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0x81: fstox({{
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Frd.df = (double)static_cast<int64_t>(Frs2.sf);
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Frd.df = (double)static_cast<int64_t>(Frs2s.sf);
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}});
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0x82: fdtox({{
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Frd.df = (double)static_cast<int64_t>(Frs2.df);
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}});
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0x83: Trap::fqtox({{fault = new FpDisabled;}});
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0x84: fxtos({{
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Frd.sf = static_cast<float>((int64_t)Frs2.df);
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Frds.sf = static_cast<float>((int64_t)Frs2.df);
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}});
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0x88: fxtod({{
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Frd.df = static_cast<double>((int64_t)Frs2.df);
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}});
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0x8C: Trap::fxtoq({{fault = new FpDisabled;}});
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0xC4: fitos({{
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Frd.sf = static_cast<float>((int32_t)Frs2.sf);
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Frds.sf = static_cast<float>((int32_t)Frs2s.sf);
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}});
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0xC6: fdtos({{Frd.sf = Frs2.df;}});
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0xC6: fdtos({{Frds.sf = Frs2.df;}});
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0xC7: Trap::fqtos({{fault = new FpDisabled;}});
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0xC8: fitod({{
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Frd.df = static_cast<double>((int32_t)Frs2.sf);
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Frd.df = static_cast<double>((int32_t)Frs2s.sf);
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}});
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0xC9: fstod({{Frd.df = Frs2.sf;}});
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0xC9: fstod({{Frd.df = Frs2s.sf;}});
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0xCB: Trap::fqtod({{fault = new FpDisabled;}});
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0xCC: Trap::fitoq({{fault = new FpDisabled;}});
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0xCD: Trap::fstoq({{fault = new FpDisabled;}});
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0xCE: Trap::fdtoq({{fault = new FpDisabled;}});
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0xD1: fstoi({{
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Frd.sf = (float)static_cast<int32_t>(Frs2.sf);
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Frds.sf = (float)static_cast<int32_t>(Frs2s.sf);
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}});
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0xD2: fdtoi({{
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Frd.sf = (float)static_cast<int32_t>(Frs2.df);
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Frds.sf = (float)static_cast<int32_t>(Frs2.df);
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}});
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0xD3: Trap::fqtoi({{fault = new FpDisabled;}});
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default: Trap::fpop1({{fault = new FpDisabled;}});
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@ -620,7 +620,7 @@ decode OP default Unknown::unknown()
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0x56: Trap::fpsub32({{fault = new IllegalInstruction;}});
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0x57: Trap::fpsub32s({{fault = new IllegalInstruction;}});
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0x60: BasicOperate::fzero({{Frd.df = 0;}});
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0x61: BasicOperate::fzeros({{Frd.sf = 0;}});
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0x61: BasicOperate::fzeros({{Frds.sf = 0;}});
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0x62: Trap::fnor({{fault = new IllegalInstruction;}});
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0x63: Trap::fnors({{fault = new IllegalInstruction;}});
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0x64: Trap::fandnot2({{fault = new IllegalInstruction;}});
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@ -629,7 +629,7 @@ decode OP default Unknown::unknown()
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Frd.df = (double)(~((uint64_t)Frs2.df));
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}});
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0x67: BasicOperate::fnot2s({{
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Frd.sf = (float)(~((uint32_t)Frs2.sf));
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Frds.sf = (float)(~((uint32_t)Frs2s.sf));
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}});
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0x68: Trap::fandnot1({{fault = new IllegalInstruction;}});
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0x69: Trap::fandnot1s({{fault = new IllegalInstruction;}});
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@ -637,7 +637,7 @@ decode OP default Unknown::unknown()
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Frd.df = (double)(~((uint64_t)Frs1.df));
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}});
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0x6B: BasicOperate::fnot1s({{
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Frd.sf = (float)(~((uint32_t)Frs1.sf));
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Frds.sf = (float)(~((uint32_t)Frs1s.sf));
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}});
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0x6C: Trap::fxor({{fault = new IllegalInstruction;}});
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0x6D: Trap::fxors({{fault = new IllegalInstruction;}});
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@ -42,6 +42,16 @@ def operand_types {{
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'qf' : ('float', 128)
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}};
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output header {{
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// A function to "decompress" double and quad floating point
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// register numbers stuffed into 5 bit fields. These have their
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// MSB put in the LSB position but are otherwise normal.
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static inline unsigned int dfpr(unsigned int regNum)
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{
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return regNum | ((regNum & 1) << 5);
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}
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}};
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def operands {{
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# Int regs default to unsigned, but code should not count on this.
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# For clarity, descriptions that depend on unsigned behavior should
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@ -51,17 +61,22 @@ def operands {{
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'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 3),
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'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 4),
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'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 5),
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'Frd': ('FloatReg', 'df', 'RD', 'IsFloating', 10),
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'Frd_0': ('FloatReg', 'df', 'RD', 'IsFloating', 10),
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'Frd_1': ('FloatReg', 'df', 'RD + 1', 'IsFloating', 10),
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'Frd_2': ('FloatReg', 'df', 'RD + 2', 'IsFloating', 10),
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'Frd_3': ('FloatReg', 'df', 'RD + 3', 'IsFloating', 10),
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'Frd_4': ('FloatReg', 'df', 'RD + 4', 'IsFloating', 10),
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'Frd_5': ('FloatReg', 'df', 'RD + 5', 'IsFloating', 10),
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'Frd_6': ('FloatReg', 'df', 'RD + 6', 'IsFloating', 10),
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'Frd_7': ('FloatReg', 'df', 'RD + 7', 'IsFloating', 10),
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'Frs1': ('FloatReg', 'df', 'RS1', 'IsFloating', 11),
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'Frs2': ('FloatReg', 'df', 'RS2', 'IsFloating', 12),
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'Frds': ('FloatReg', 'sf', 'RD', 'IsFloating', 10),
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'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
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# Each Frd_N refers to the Nth double precision register from Frd.
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# Note that this adds twice N to the register number.
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'Frd_0': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
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'Frd_1': ('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10),
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'Frd_2': ('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10),
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'Frd_3': ('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10),
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'Frd_4': ('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10),
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'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10),
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'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10),
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'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10),
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'Frs1s': ('FloatReg', 'df', 'RS1', 'IsFloating', 11),
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'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11),
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'Frs2s': ('FloatReg', 'df', 'RS2', 'IsFloating', 12),
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'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12),
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'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 20),
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'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31),
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'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32),
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