gem5/src
Gabe Black 93b3176d4e Fixed the priv instruction format.
src/arch/sparc/isa/formats/priv.isa:
    Fix the priv format so that it uses isa_parser operands rather than accessing the registers directly in checkCode. Also, the expressions needed to be negated.
src/arch/sparc/isa/operands.isa:
    Added an Hpstate operand, and adjusted the numbering.

--HG--
extra : convert_revision : 4a70862df061aa9e1b9eab125c4c2fc839ac3b5a
2006-10-25 17:58:44 -04:00
..
arch Fixed the priv instruction format. 2006-10-25 17:58:44 -04:00
base Merge zizzer.eecs.umich.edu:/bk/newmem 2006-10-23 09:44:58 -04:00
cpu Minor compile fix. Not sure why this is broken. 2006-10-23 11:17:59 -04:00
dev Missing case 2006-10-21 00:31:46 -07:00
doxygen Fix up doxygen. 2006-08-14 19:25:07 -04:00
kern Merge zizzer.eecs.umich.edu:/bk/newmem 2006-10-23 09:44:58 -04:00
mem Small bug fixes for timing LL/SC. Better now but 2006-10-21 23:35:00 -07:00
python Use fixPacket function everywhere. 2006-10-20 13:01:21 -04:00
sim Merge zizzer.eecs.umich.edu:/bk/newmem 2006-10-23 09:44:58 -04:00
unittest Merge iceaxe.:/Volumes/work/research/m5/head 2006-06-11 22:01:34 -04:00
Doxyfile Fix up doxygen. 2006-08-14 19:25:07 -04:00
SConscript Two minor fixes. 2006-10-10 01:49:46 -04:00