Merge zizzer.eecs.umich.edu:/bk/newmem
into zeep.eecs.umich.edu:/home/gblack/m5/newmem --HG-- extra : convert_revision : ec35a9276ae21e0b9fe820bd700c020e4440a350
This commit is contained in:
Gabe Black
commit
f985b752d3
21 changed files with 559 additions and 392 deletions
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@ -1316,7 +1316,7 @@ class ControlRegOperand(Operand):
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def makeWrite(self):
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if (self.ctype == 'float' or self.ctype == 'double'):
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error(0, 'Attempt to write control register as FP')
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wb = 'xc->setMiscReg(%s, %s);\n' % (self.reg_spec, self.base_name)
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wb = 'xc->setMiscRegWithEffect(%s, %s);\n' % (self.reg_spec, self.base_name)
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wb += 'if (traceData) { traceData->setData(%s); }' % \
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self.base_name
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return wb
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@ -29,15 +29,22 @@
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* Kevin Lim
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*/
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#include <algorithm>
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#include "arch/sparc/faults.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/base.hh"
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#include "arch/sparc/isa_traits.hh"
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#include "arch/sparc/process.hh"
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#include "base/bitfield.hh"
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#include "base/trace.hh"
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#include "cpu/base.hh"
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#include "cpu/thread_context.hh"
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#if !FULL_SYSTEM
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#include "sim/process.hh"
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#include "mem/page_table.hh"
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#include "sim/process.hh"
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#endif
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using namespace std;
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namespace SparcISA
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{
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@ -229,6 +236,121 @@ FaultPriority PageTableFault::_priority = 0;
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FaultStat PageTableFault::_count;
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#endif
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/**
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* This sets everything up for a normal trap except for actually jumping to
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* the handler. It will need to be expanded to include the state machine in
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* the manual. Right now it assumes that traps will always be to the
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* privileged level.
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*/
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void doNormalFault(ThreadContext *tc, TrapType tt)
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{
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uint64_t TL = tc->readMiscReg(MISCREG_TL);
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uint64_t TSTATE = tc->readMiscReg(MISCREG_TSTATE);
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uint64_t PSTATE = tc->readMiscReg(MISCREG_PSTATE);
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uint64_t HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
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uint64_t CCR = tc->readMiscReg(MISCREG_CCR);
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uint64_t ASI = tc->readMiscReg(MISCREG_ASI);
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uint64_t CWP = tc->readMiscReg(MISCREG_CWP);
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uint64_t CANSAVE = tc->readMiscReg(MISCREG_CANSAVE);
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uint64_t GL = tc->readMiscReg(MISCREG_GL);
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uint64_t PC = tc->readPC();
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uint64_t NPC = tc->readNextPC();
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//Increment the trap level
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TL++;
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tc->setMiscReg(MISCREG_TL, TL);
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//Save off state
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//set TSTATE.gl to gl
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replaceBits(TSTATE, 42, 40, GL);
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//set TSTATE.ccr to ccr
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replaceBits(TSTATE, 39, 32, CCR);
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//set TSTATE.asi to asi
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replaceBits(TSTATE, 31, 24, ASI);
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//set TSTATE.pstate to pstate
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replaceBits(TSTATE, 20, 8, PSTATE);
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//set TSTATE.cwp to cwp
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replaceBits(TSTATE, 4, 0, CWP);
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//Write back TSTATE
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tc->setMiscReg(MISCREG_TSTATE, TSTATE);
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//set TPC to PC
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tc->setMiscReg(MISCREG_TPC, PC);
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//set TNPC to NPC
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tc->setMiscReg(MISCREG_TNPC, NPC);
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//set HTSTATE.hpstate to hpstate
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tc->setMiscReg(MISCREG_HTSTATE, HPSTATE);
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//TT = trap type;
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tc->setMiscReg(MISCREG_TT, tt);
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//Update the global register level
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if(1/*We're delivering the trap in priveleged mode*/)
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tc->setMiscReg(MISCREG_GL, max<int>(GL+1, MaxGL));
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else
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tc->setMiscReg(MISCREG_GL, max<int>(GL+1, MaxPGL));
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//PSTATE.mm is unchanged
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//PSTATE.pef = whether or not an fpu is present
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//XXX We'll say there's one present, even though there aren't
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//implementations for a decent number of the instructions
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PSTATE |= (1 << 4);
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//PSTATE.am = 0
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PSTATE &= ~(1 << 3);
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if(1/*We're delivering the trap in priveleged mode*/)
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{
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//PSTATE.priv = 1
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PSTATE |= (1 << 2);
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//PSTATE.cle = PSTATE.tle
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replaceBits(PSTATE, 9, 9, PSTATE >> 8);
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}
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else
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{
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//PSTATE.priv = 0
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PSTATE &= ~(1 << 2);
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//PSTATE.cle = 0
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PSTATE &= ~(1 << 9);
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}
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//PSTATE.ie = 0
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PSTATE &= ~(1 << 1);
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//PSTATE.tle is unchanged
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//PSTATE.tct = 0
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//XXX Where exactly is this field?
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tc->setMiscReg(MISCREG_PSTATE, PSTATE);
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if(0/*We're delivering the trap in hyperprivileged mode*/)
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{
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//HPSTATE.red = 0
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HPSTATE &= ~(1 << 5);
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//HPSTATE.hpriv = 1
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HPSTATE |= (1 << 2);
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//HPSTATE.ibe = 0
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HPSTATE &= ~(1 << 10);
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//HPSTATE.tlz is unchanged
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tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
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}
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bool changedCWP = true;
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if(tt == 0x24)
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CWP++;
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else if(0x80 <= tt && tt <= 0xbf)
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CWP += (CANSAVE + 2);
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else if(0xc0 <= tt && tt <= 0xff)
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CWP--;
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else
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changedCWP = false;
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if(changedCWP)
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{
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CWP = (CWP + NWindows) % NWindows;
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tc->setMiscRegWithEffect(MISCREG_CWP, CWP);
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}
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}
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#if FULL_SYSTEM
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void SparcFault::invoke(ThreadContext * tc)
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@ -263,6 +385,40 @@ void TrapInstruction::invoke(ThreadContext * tc)
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// Should be handled in ISA.
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}
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void SpillNNormal::invoke(ThreadContext *tc)
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{
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doNormalFault(tc, trapType());
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Process *p = tc->getProcessPtr();
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//This will only work in faults from a SparcLiveProcess
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SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
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assert(lp);
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//Then adjust the PC and NPC
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Addr spillStart = lp->readSpillStart();
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tc->setPC(spillStart);
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tc->setNextPC(spillStart + sizeof(MachInst));
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tc->setNextNPC(spillStart + 2*sizeof(MachInst));
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}
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void FillNNormal::invoke(ThreadContext *tc)
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{
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doNormalFault(tc, trapType());
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Process * p = tc->getProcessPtr();
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//This will only work in faults from a SparcLiveProcess
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SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
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assert(lp);
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//The adjust the PC and NPC
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Addr fillStart = lp->readFillStart();
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tc->setPC(fillStart);
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tc->setNextPC(fillStart + sizeof(MachInst));
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tc->setNextNPC(fillStart + 2*sizeof(MachInst));
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}
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void PageTableFault::invoke(ThreadContext *tc)
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{
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Process *p = tc->getProcessPtr();
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@ -282,6 +438,7 @@ void PageTableFault::invoke(ThreadContext *tc)
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FaultBase::invoke(tc);
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}
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}
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#endif
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} // namespace SparcISA
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@ -39,8 +39,8 @@
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namespace SparcISA
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{
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typedef const uint32_t TrapType;
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typedef const uint32_t FaultPriority;
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typedef uint32_t TrapType;
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typedef uint32_t FaultPriority;
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class SparcFault : public FaultBase
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{
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@ -547,6 +547,7 @@ class SpillNNormal : public EnumeratedFault
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FaultName name() {return _name;}
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FaultPriority priority() {return _priority;}
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FaultStat & countStat() {return _count;}
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void invoke(ThreadContext * tc);
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};
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class SpillNOther : public EnumeratedFault
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@ -577,6 +578,7 @@ class FillNNormal : public EnumeratedFault
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FaultName name() {return _name;}
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FaultPriority priority() {return _priority;}
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FaultStat & countStat() {return _count;}
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void invoke(ThreadContext * tc);
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};
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class FillNOther : public EnumeratedFault
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@ -50,7 +50,7 @@ def bitfield D16LO <13:0>;
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def bitfield DISP19 <18:0>;
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def bitfield DISP22 <21:0>;
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def bitfield DISP30 <29:0>;
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def bitfield FCN <29:26>;
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def bitfield FCN <29:25>;
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def bitfield I <13>;
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def bitfield IMM_ASI <12:5>;
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def bitfield IMM22 <21:0>;
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@ -357,13 +357,9 @@ decode OP default Unknown::unknown()
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}});
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}
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0x29: HPriv::rdhpr({{
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// XXX Need to protect with format that traps non-priv/priv
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// access
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Rd = xc->readMiscRegWithEffect(RS1 + HprStart, fault);
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}});
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0x2A: Priv::rdpr({{
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// XXX Need to protect with format that traps non-priv
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// access
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Rd = xc->readMiscRegWithEffect(RS1 + PrStart, fault);
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}});
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0x2B: BasicOperate::flushw({{
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@ -425,18 +421,34 @@ decode OP default Unknown::unknown()
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xc->setMiscRegWithEffect(RD + AsrStart, Rs1 ^ Rs2_or_imm13);
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}});
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0x31: decode FCN {
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0x0: BasicOperate::saved({{/*Boogy Boogy*/}});
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0x1: BasicOperate::restored({{/*Boogy Boogy*/}});
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0x0: Priv::saved({{
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assert(Cansave < NWindows - 2);
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assert(Otherwin || Canrestore);
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Cansave = Cansave + 1;
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if(Otherwin == 0)
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Canrestore = Canrestore - 1;
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else
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Otherwin = Otherwin - 1;
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}});
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0x1: BasicOperate::restored({{
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assert(Cansave || Otherwin);
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assert(Canrestore < NWindows - 2);
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Canrestore = Canrestore + 1;
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if(Otherwin == 0)
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Cansave = Cansave - 1;
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else
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Otherwin = Otherwin - 1;
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}});
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}
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0x32: Priv::wrpr({{
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// XXX Need to protect with format that traps non-priv
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// access
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fault = xc->setMiscRegWithEffect(RD + PrStart, Rs1 ^ Rs2_or_imm13);
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xc->setMiscRegWithEffect(RD + PrStart, Rs1 ^ Rs2_or_imm13);
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}});
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0x33: HPriv::wrhpr({{
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// XXX Need to protect with format that traps non-priv/priv
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// access
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fault = xc->setMiscRegWithEffect(RD + HprStart, Rs1 ^ Rs2_or_imm13);
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xc->setMiscRegWithEffect(RD + HprStart, Rs1 ^ Rs2_or_imm13);
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}});
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0x34: decode OPF{
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format BasicOperate{
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@ -684,10 +696,6 @@ decode OP default Unknown::unknown()
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NNPC = target;
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if(fault == NoFault)
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{
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//CWP should be set directly so that it always happens
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//Also, this will allow writing to the new window and
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//reading from the old one
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Cwp = (Cwp - 1 + NWindows) % NWindows;
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if(Canrestore == 0)
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{
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if(Otherwin)
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@ -697,14 +705,17 @@ decode OP default Unknown::unknown()
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}
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else
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{
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Rd = Rs1 + Rs2_or_imm13;
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//CWP should be set directly so that it always happens
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//Also, this will allow writing to the new window and
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//reading from the old one
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Cwp = (Cwp - 1 + NWindows) % NWindows;
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Cansave = Cansave + 1;
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Canrestore = Canrestore - 1;
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//This is here to make sure the CWP is written
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//no matter what. This ensures that the results
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//are written in the new window as well.
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xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
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}
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//This is here to make sure the CWP is written
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//no matter what. This ensures that the results
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//are written in the new window as well.
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xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
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}
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}});
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0x3A: decode CC
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@ -747,11 +758,11 @@ decode OP default Unknown::unknown()
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fault = new SpillNOther(Wstate<5:3>);
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else
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fault = new SpillNNormal(Wstate<2:0>);
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Cwp = (Cwp + 2) % NWindows;
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//Cwp = (Cwp + 2) % NWindows;
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}
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else if(Cleanwin - Canrestore == 0)
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{
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Cwp = (Cwp + 1) % NWindows;
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//Cwp = (Cwp + 1) % NWindows;
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fault = new CleanWindow;
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}
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else
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@ -760,17 +771,13 @@ decode OP default Unknown::unknown()
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Rd = Rs1 + Rs2_or_imm13;
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Cansave = Cansave - 1;
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Canrestore = Canrestore + 1;
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//This is here to make sure the CWP is written
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//no matter what. This ensures that the results
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//are written in the new window as well.
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xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
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}
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//This is here to make sure the CWP is written
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//no matter what. This ensures that the results
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//are written in the new window as well.
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xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
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}});
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0x3D: restore({{
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//CWP should be set directly so that it always happens
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//Also, this will allow writing to the new window and
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//reading from the old one
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Cwp = (Cwp - 1 + NWindows) % NWindows;
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if(Canrestore == 0)
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{
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if(Otherwin)
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@ -780,14 +787,18 @@ decode OP default Unknown::unknown()
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}
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else
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{
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//CWP should be set directly so that it always happens
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//Also, this will allow writing to the new window and
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//reading from the old one
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Cwp = (Cwp - 1 + NWindows) % NWindows;
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Rd = Rs1 + Rs2_or_imm13;
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Cansave = Cansave + 1;
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Canrestore = Canrestore - 1;
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//This is here to make sure the CWP is written
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//no matter what. This ensures that the results
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//are written in the new window as well.
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xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
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}
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//This is here to make sure the CWP is written
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//no matter what. This ensures that the results
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//are written in the new window as well.
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xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
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}});
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0x3E: decode FCN {
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0x0: Priv::done({{
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@ -812,7 +823,7 @@ decode OP default Unknown::unknown()
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Ccr = Tstate<39:32>;
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Gl = Tstate<42:40>;
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NPC = Tpc;
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NNPC = Tnpc + 4;
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NNPC = Tnpc;
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Tl = Tl - 1;
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}});
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}
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||||
|
|
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|||
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|
@ -121,15 +121,14 @@ let {{
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// Primary format for integer operate instructions:
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def format Priv(code, *opt_flags) {{
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checkCode = '''((xc->readMiscReg(PrStart + MISCREG_PSTATE))<2:2>) ||
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((xc->readMiscReg(HprStart + MISCREG_HPSTATE))<2:2>)'''
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checkCode = "!(Pstate<2:2> || Hpstate<2:2>)"
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(header_output, decoder_output,
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exec_output, decode_block) = doPrivFormat(code,
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checkCode, name, Name, opt_flags + ('IprAccessOp',))
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}};
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def format HPriv(code, *opt_flags) {{
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checkCode = "((xc->readMiscReg(HprStart + MISCREG_HPSTATE))<2:2>)"
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checkCode = "!Hpstate<2:2>"
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(header_output, decoder_output,
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exec_output, decode_block) = doPrivFormat(code,
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checkCode, name, Name, opt_flags + ('IprAccessOp',))
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|
|
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|
@ -95,18 +95,19 @@ def operands {{
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'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 44),
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'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 45),
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'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 46),
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'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 47),
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'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 47),
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'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 48),
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'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 48),
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'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 49),
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'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 50),
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'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 51),
|
||||
'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 52),
|
||||
'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 53),
|
||||
'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 54),
|
||||
'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 49),
|
||||
'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 50),
|
||||
'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 51),
|
||||
'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 52),
|
||||
'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 53),
|
||||
'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 54),
|
||||
'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 55),
|
||||
|
||||
'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 55),
|
||||
'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 56),
|
||||
'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 56),
|
||||
'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 57),
|
||||
# Mem gets a large number so it's always last
|
||||
'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
|
||||
|
||||
|
|
|
|||
|
|
@ -57,12 +57,11 @@ namespace SparcISA
|
|||
//This makes sure the big endian versions of certain functions are used.
|
||||
using namespace BigEndianGuest;
|
||||
|
||||
// Alpha Does NOT have a delay slot
|
||||
// SPARC have a delay slot
|
||||
#define ISA_HAS_DELAY_SLOT 1
|
||||
|
||||
//TODO this needs to be a SPARC Noop
|
||||
// Alpha UNOP (ldq_u r31,0(r0))
|
||||
const MachInst NoopMachInst = 0x2ffe0000;
|
||||
// SPARC NOP (sethi %(hi(0), g0)
|
||||
const MachInst NoopMachInst = 0x01000000;
|
||||
|
||||
const int NumIntRegs = 32;
|
||||
const int NumFloatRegs = 64;
|
||||
|
|
@ -87,7 +86,7 @@ namespace SparcISA
|
|||
const int MaxPGL = 2;
|
||||
|
||||
// NWINDOWS - number of register windows, can be 3 to 32
|
||||
const int NWindows = 32;
|
||||
const int NWindows = 8;
|
||||
|
||||
// semantically meaningful register indices
|
||||
const int ZeroReg = 0; // architecturally meaningful
|
||||
|
|
|
|||
|
|
@ -202,282 +202,164 @@ MiscReg MiscRegFile::readReg(int miscReg)
|
|||
}
|
||||
}
|
||||
|
||||
MiscReg MiscRegFile::readRegWithEffect(int miscReg,
|
||||
Fault &fault, ThreadContext * tc)
|
||||
MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
|
||||
{
|
||||
fault = NoFault;
|
||||
switch (miscReg) {
|
||||
case MISCREG_Y:
|
||||
case MISCREG_CCR:
|
||||
case MISCREG_ASI:
|
||||
return readReg(miscReg);
|
||||
|
||||
case MISCREG_TICK:
|
||||
case MISCREG_PRIVTICK:
|
||||
// Check for reading privilege
|
||||
if (tickFields.npt && !isNonPriv()) {
|
||||
fault = new PrivilegedAction;
|
||||
return 0;
|
||||
}
|
||||
return tc->getCpuPtr()->curCycle() - tickFields.counter |
|
||||
tickFields.npt << 63;
|
||||
case MISCREG_PC:
|
||||
return tc->readPC();
|
||||
case MISCREG_FPRS:
|
||||
fault = new UnimpFault("FPU not implemented\n");
|
||||
return 0;
|
||||
panic("FPU not implemented\n");
|
||||
case MISCREG_PCR:
|
||||
fault = new UnimpFault("Performance Instrumentation not impl\n");
|
||||
return 0;
|
||||
case MISCREG_PIC:
|
||||
fault = new UnimpFault("Performance Instrumentation not impl\n");
|
||||
return 0;
|
||||
case MISCREG_GSR:
|
||||
return readReg(miscReg);
|
||||
|
||||
/** Privilged Registers */
|
||||
case MISCREG_TPC:
|
||||
case MISCREG_TNPC:
|
||||
case MISCREG_TSTATE:
|
||||
case MISCREG_TT:
|
||||
if (tl == 0) {
|
||||
fault = new IllegalInstruction;
|
||||
return 0;
|
||||
} // NOTE THE FALL THROUGH!
|
||||
case MISCREG_PSTATE:
|
||||
case MISCREG_TL:
|
||||
return readReg(miscReg);
|
||||
|
||||
case MISCREG_TBA:
|
||||
return readReg(miscReg) & ULL(~0x7FFF);
|
||||
|
||||
case MISCREG_PIL:
|
||||
|
||||
case MISCREG_CWP:
|
||||
case MISCREG_CANSAVE:
|
||||
case MISCREG_CANRESTORE:
|
||||
case MISCREG_CLEANWIN:
|
||||
case MISCREG_OTHERWIN:
|
||||
case MISCREG_WSTATE:
|
||||
case MISCREG_GL:
|
||||
return readReg(miscReg);
|
||||
panic("Performance Instrumentation not impl\n");
|
||||
|
||||
/** Floating Point Status Register */
|
||||
case MISCREG_FSR:
|
||||
panic("Floating Point not implemented\n");
|
||||
default:
|
||||
#if FULL_SYSTEM
|
||||
return readFSRegWithEffect(miscReg, fault, tc);
|
||||
#else
|
||||
fault = new IllegalInstruction;
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
return readReg(miscReg);
|
||||
}
|
||||
|
||||
Fault MiscRegFile::setReg(int miscReg, const MiscReg &val)
|
||||
void MiscRegFile::setReg(int miscReg, const MiscReg &val)
|
||||
{
|
||||
switch (miscReg) {
|
||||
case MISCREG_Y:
|
||||
y = val;
|
||||
return NoFault;
|
||||
break;
|
||||
case MISCREG_CCR:
|
||||
ccr = val;
|
||||
return NoFault;
|
||||
break;
|
||||
case MISCREG_ASI:
|
||||
asi = val;
|
||||
return NoFault;
|
||||
break;
|
||||
case MISCREG_FPRS:
|
||||
fprs = val;
|
||||
return NoFault;
|
||||
break;
|
||||
case MISCREG_TICK:
|
||||
tick = val;
|
||||
return NoFault;
|
||||
tick = val;
|
||||
break;
|
||||
case MISCREG_PCR:
|
||||
case MISCREG_PIC:
|
||||
panic("ASR number %d not implemented\n", miscReg - AsrStart);
|
||||
case MISCREG_GSR:
|
||||
gsr = val;
|
||||
break;
|
||||
case MISCREG_SOFTINT:
|
||||
softint = val;
|
||||
return NoFault;
|
||||
softint = val;
|
||||
break;
|
||||
case MISCREG_TICK_CMPR:
|
||||
tick_cmpr = val;
|
||||
return NoFault;
|
||||
tick_cmpr = val;
|
||||
break;
|
||||
case MISCREG_STICK:
|
||||
stick = val;
|
||||
return NoFault;
|
||||
stick = val;
|
||||
break;
|
||||
case MISCREG_STICK_CMPR:
|
||||
stick_cmpr = val;
|
||||
return NoFault;
|
||||
stick_cmpr = val;
|
||||
break;
|
||||
|
||||
/** Privilged Registers */
|
||||
case MISCREG_TPC:
|
||||
tpc[tl-1] = val;
|
||||
return NoFault;
|
||||
break;
|
||||
case MISCREG_TNPC:
|
||||
tnpc[tl-1] = val;
|
||||
return NoFault;
|
||||
break;
|
||||
case MISCREG_TSTATE:
|
||||
tstate[tl-1] = val;
|
||||
return NoFault;
|
||||
break;
|
||||
case MISCREG_TT:
|
||||
tt[tl-1] = val;
|
||||
return NoFault;
|
||||
break;
|
||||
case MISCREG_PRIVTICK:
|
||||
panic("Priviliged access to tick regesiters not implemented\n");
|
||||
case MISCREG_TBA:
|
||||
tba = val;
|
||||
return NoFault;
|
||||
// clear lower 7 bits on writes.
|
||||
tba = val & ULL(~0x7FFF);
|
||||
break;
|
||||
case MISCREG_PSTATE:
|
||||
pstate = val;
|
||||
return NoFault;
|
||||
break;
|
||||
case MISCREG_TL:
|
||||
tl = val;
|
||||
return NoFault;
|
||||
break;
|
||||
case MISCREG_PIL:
|
||||
pil = val;
|
||||
return NoFault;
|
||||
break;
|
||||
case MISCREG_CWP:
|
||||
cwp = val;
|
||||
return NoFault;
|
||||
break;
|
||||
case MISCREG_CANSAVE:
|
||||
cansave = val;
|
||||
return NoFault;
|
||||
break;
|
||||
case MISCREG_CANRESTORE:
|
||||
canrestore = val;
|
||||
return NoFault;
|
||||
break;
|
||||
case MISCREG_CLEANWIN:
|
||||
cleanwin = val;
|
||||
return NoFault;
|
||||
break;
|
||||
case MISCREG_OTHERWIN:
|
||||
otherwin = val;
|
||||
return NoFault;
|
||||
break;
|
||||
case MISCREG_WSTATE:
|
||||
wstate = val;
|
||||
return NoFault;
|
||||
break;
|
||||
case MISCREG_GL:
|
||||
gl = val;
|
||||
return NoFault;
|
||||
break;
|
||||
|
||||
/** Hyper privileged registers */
|
||||
case MISCREG_HPSTATE:
|
||||
hpstate = val;
|
||||
return NoFault;
|
||||
break;
|
||||
case MISCREG_HTSTATE:
|
||||
htstate[tl-1] = val;
|
||||
return NoFault;
|
||||
break;
|
||||
case MISCREG_HINTP:
|
||||
panic("HINTP not implemented\n");
|
||||
case MISCREG_HTBA:
|
||||
htba = val;
|
||||
return NoFault;
|
||||
break;
|
||||
case MISCREG_STRAND_STS_REG:
|
||||
strandStatusReg = val;
|
||||
return NoFault;
|
||||
break;
|
||||
case MISCREG_HSTICK_CMPR:
|
||||
hstick_cmpr = val;
|
||||
return NoFault;
|
||||
break;
|
||||
|
||||
/** Floating Point Status Register */
|
||||
case MISCREG_FSR:
|
||||
fsr = val;
|
||||
return NoFault;
|
||||
break;
|
||||
default:
|
||||
panic("Miscellaneous register %d not implemented\n", miscReg);
|
||||
}
|
||||
}
|
||||
|
||||
Fault MiscRegFile::setRegWithEffect(int miscReg,
|
||||
void MiscRegFile::setRegWithEffect(int miscReg,
|
||||
const MiscReg &val, ThreadContext * tc)
|
||||
{
|
||||
const uint64_t Bit64 = (1ULL << 63);
|
||||
switch (miscReg) {
|
||||
case MISCREG_Y:
|
||||
case MISCREG_CCR:
|
||||
case MISCREG_ASI:
|
||||
setReg(miscReg, val);
|
||||
return NoFault;
|
||||
case MISCREG_PRIVTICK:
|
||||
case MISCREG_TICK:
|
||||
if (isNonPriv())
|
||||
return new PrivilegedOpcode;
|
||||
if (isPriv())
|
||||
return new PrivilegedAction;
|
||||
tickFields.counter = tc->getCpuPtr()->curCycle() - val & ~Bit64;
|
||||
tickFields.npt = val & Bit64 ? 1 : 0;
|
||||
return NoFault;
|
||||
case MISCREG_PC:
|
||||
return new IllegalInstruction;
|
||||
break;
|
||||
case MISCREG_FPRS:
|
||||
return new UnimpFault("FPU not implemented\n");
|
||||
//Configure the fpu based on the fprs
|
||||
break;
|
||||
case MISCREG_PCR:
|
||||
return new UnimpFault("Performance Instrumentation not impl\n");
|
||||
case MISCREG_PIC:
|
||||
return new UnimpFault("Performance Instrumentation not impl\n");
|
||||
case MISCREG_GSR:
|
||||
return setReg(miscReg, val);
|
||||
|
||||
/** Privilged Registers */
|
||||
case MISCREG_TPC:
|
||||
case MISCREG_TNPC:
|
||||
case MISCREG_TSTATE:
|
||||
case MISCREG_TT:
|
||||
if (tl == 0)
|
||||
return new IllegalInstruction;
|
||||
setReg(miscReg, val);
|
||||
return NoFault;
|
||||
|
||||
case MISCREG_TBA:
|
||||
// clear lower 7 bits on writes.
|
||||
setReg(miscReg, val & ULL(~0x7FFF));
|
||||
return NoFault;
|
||||
|
||||
case MISCREG_PSTATE:
|
||||
setReg(miscReg, val);
|
||||
return NoFault;
|
||||
|
||||
case MISCREG_TL:
|
||||
if (isHyperPriv() && val > MaxTL)
|
||||
setReg(miscReg, MaxTL);
|
||||
else if (isPriv() && !isHyperPriv() && val > MaxPTL)
|
||||
setReg(miscReg, MaxPTL);
|
||||
else
|
||||
setReg(miscReg, val);
|
||||
return NoFault;
|
||||
|
||||
//Set up performance counting based on pcr value
|
||||
break;
|
||||
case MISCREG_CWP:
|
||||
tc->changeRegFileContext(CONTEXT_CWP, val);
|
||||
case MISCREG_CANSAVE:
|
||||
case MISCREG_CANRESTORE:
|
||||
case MISCREG_CLEANWIN:
|
||||
case MISCREG_OTHERWIN:
|
||||
case MISCREG_WSTATE:
|
||||
setReg(miscReg, val);
|
||||
return NoFault;
|
||||
|
||||
break;
|
||||
case MISCREG_GL:
|
||||
int newval;
|
||||
if (isHyperPriv() && val > MaxGL)
|
||||
newval = MaxGL;
|
||||
else if (isPriv() && !isHyperPriv() && val > MaxPGL)
|
||||
newval = MaxPGL;
|
||||
else
|
||||
newval = val;
|
||||
tc->changeRegFileContext(CONTEXT_GLOBALS, newval);
|
||||
setReg(miscReg, newval);
|
||||
return NoFault;
|
||||
|
||||
/** Floating Point Status Register */
|
||||
case MISCREG_FSR:
|
||||
panic("Floating Point not implemented\n");
|
||||
default:
|
||||
#if FULL_SYSTEM
|
||||
setFSRegWithEffect(miscReg, val, tc);
|
||||
#else
|
||||
return new IllegalInstruction;
|
||||
#endif
|
||||
tc->changeRegFileContext(CONTEXT_GLOBALS, val);
|
||||
break;
|
||||
}
|
||||
setReg(miscReg, val);
|
||||
}
|
||||
|
||||
void MiscRegFile::serialize(std::ostream & os)
|
||||
|
|
|
|||
|
|
@ -56,7 +56,6 @@ namespace SparcISA
|
|||
MISCREG_CCR = AsrStart + 2,
|
||||
MISCREG_ASI = AsrStart + 3,
|
||||
MISCREG_TICK = AsrStart + 4,
|
||||
MISCREG_PC = AsrStart + 5,
|
||||
MISCREG_FPRS = AsrStart + 6,
|
||||
MISCREG_PCR = AsrStart + 16,
|
||||
MISCREG_PIC = AsrStart + 17,
|
||||
|
|
@ -366,31 +365,13 @@ namespace SparcISA
|
|||
reset();
|
||||
}
|
||||
|
||||
/** read a value out of an either an SE or FS IPR. No checking is done
|
||||
* about SE vs. FS as this is mostly used to copy the regfile. Thus more
|
||||
* register are copied that are necessary for FS. However this prevents
|
||||
* a bunch of ifdefs and is rarely called so is not performance
|
||||
* criticial. */
|
||||
MiscReg readReg(int miscReg);
|
||||
|
||||
/** Read a value from an IPR. Only the SE iprs are here and the rest
|
||||
* are are readFSRegWithEffect (which is called by readRegWithEffect()).
|
||||
* Checking is done for permission based on state bits in the miscreg
|
||||
* file. */
|
||||
MiscReg readRegWithEffect(int miscReg, Fault &fault, ThreadContext *tc);
|
||||
MiscReg readRegWithEffect(int miscReg, ThreadContext *tc);
|
||||
|
||||
/** write a value into an either an SE or FS IPR. No checking is done
|
||||
* about SE vs. FS as this is mostly used to copy the regfile. Thus more
|
||||
* register are copied that are necessary for FS. However this prevents
|
||||
* a bunch of ifdefs and is rarely called so is not performance
|
||||
* criticial.*/
|
||||
Fault setReg(int miscReg, const MiscReg &val);
|
||||
void setReg(int miscReg, const MiscReg &val);
|
||||
|
||||
/** Write a value into an IPR. Only the SE iprs are here and the rest
|
||||
* are are setFSRegWithEffect (which is called by setRegWithEffect()).
|
||||
* Checking is done for permission based on state bits in the miscreg
|
||||
* file. */
|
||||
Fault setRegWithEffect(int miscReg,
|
||||
void setRegWithEffect(int miscReg,
|
||||
const MiscReg &val, ThreadContext * tc);
|
||||
|
||||
void serialize(std::ostream & os);
|
||||
|
|
|
|||
|
|
@ -66,6 +66,10 @@ SparcLiveProcess::SparcLiveProcess(const std::string &nm, ObjectFile *objFile,
|
|||
|
||||
// Set pointer for next thread stack. Reserve 8M for main stack.
|
||||
next_thread_stack_base = stack_base - (8 * 1024 * 1024);
|
||||
|
||||
//Initialize these to 0s
|
||||
fillStart = 0;
|
||||
spillStart = 0;
|
||||
}
|
||||
|
||||
void
|
||||
|
|
@ -88,15 +92,19 @@ SparcLiveProcess::startup()
|
|||
*/
|
||||
|
||||
//No windows contain info from other programs
|
||||
threadContexts[0]->setMiscRegWithEffect(MISCREG_OTHERWIN, 0);
|
||||
threadContexts[0]->setMiscReg(MISCREG_OTHERWIN, 0);
|
||||
//There are no windows to pop
|
||||
threadContexts[0]->setMiscRegWithEffect(MISCREG_CANRESTORE, 0);
|
||||
threadContexts[0]->setMiscReg(MISCREG_CANRESTORE, 0);
|
||||
//All windows are available to save into
|
||||
threadContexts[0]->setMiscRegWithEffect(MISCREG_CANSAVE, NWindows - 2);
|
||||
threadContexts[0]->setMiscReg(MISCREG_CANSAVE, NWindows - 2);
|
||||
//All windows are "clean"
|
||||
threadContexts[0]->setMiscRegWithEffect(MISCREG_CLEANWIN, NWindows);
|
||||
threadContexts[0]->setMiscReg(MISCREG_CLEANWIN, NWindows);
|
||||
//Start with register window 0
|
||||
threadContexts[0]->setMiscRegWithEffect(MISCREG_CWP, 0);
|
||||
threadContexts[0]->setMiscReg(MISCREG_CWP, 0);
|
||||
//Always use spill and fill traps 0
|
||||
threadContexts[0]->setMiscReg(MISCREG_WSTATE, 0);
|
||||
//Set the trap level to 0
|
||||
threadContexts[0]->setMiscReg(MISCREG_TL, 0);
|
||||
}
|
||||
|
||||
m5_auxv_t buildAuxVect(int64_t type, int64_t val)
|
||||
|
|
@ -107,6 +115,83 @@ m5_auxv_t buildAuxVect(int64_t type, int64_t val)
|
|||
return result;
|
||||
}
|
||||
|
||||
//We only use 19 instructions for the trap handlers, but there would be
|
||||
//space for 32 in a real SPARC trap table.
|
||||
const int numFillInsts = 32;
|
||||
const int numSpillInsts = 32;
|
||||
|
||||
MachInst fillHandler[numFillInsts] =
|
||||
{
|
||||
htog(0x87802018), //wr %g0, ASI_AIUP, %asi
|
||||
htog(0xe0dba7ff), //ldxa [%sp + BIAS + (0*8)] %asi, %l0
|
||||
htog(0xe2dba807), //ldxa [%sp + BIAS + (1*8)] %asi, %l1
|
||||
htog(0xe4dba80f), //ldxa [%sp + BIAS + (2*8)] %asi, %l2
|
||||
htog(0xe6dba817), //ldxa [%sp + BIAS + (3*8)] %asi, %l3
|
||||
htog(0xe8dba81f), //ldxa [%sp + BIAS + (4*8)] %asi, %l4
|
||||
htog(0xeadba827), //ldxa [%sp + BIAS + (5*8)] %asi, %l5
|
||||
htog(0xecdba82f), //ldxa [%sp + BIAS + (6*8)] %asi, %l6
|
||||
htog(0xeedba837), //ldxa [%sp + BIAS + (7*8)] %asi, %l7
|
||||
htog(0xf0dba83f), //ldxa [%sp + BIAS + (8*8)] %asi, %i0
|
||||
htog(0xf2dba847), //ldxa [%sp + BIAS + (9*8)] %asi, %i1
|
||||
htog(0xf4dba84f), //ldxa [%sp + BIAS + (10*8)] %asi, %i2
|
||||
htog(0xf6dba857), //ldxa [%sp + BIAS + (11*8)] %asi, %i3
|
||||
htog(0xf8dba85f), //ldxa [%sp + BIAS + (12*8)] %asi, %i4
|
||||
htog(0xfadba867), //ldxa [%sp + BIAS + (13*8)] %asi, %i5
|
||||
htog(0xfcdba86f), //ldxa [%sp + BIAS + (14*8)] %asi, %i6
|
||||
htog(0xfedba877), //ldxa [%sp + BIAS + (15*8)] %asi, %i7
|
||||
htog(0x83880000), //restored
|
||||
htog(0x83F00000), //retry
|
||||
htog(0x00000000), //illtrap
|
||||
htog(0x00000000), //illtrap
|
||||
htog(0x00000000), //illtrap
|
||||
htog(0x00000000), //illtrap
|
||||
htog(0x00000000), //illtrap
|
||||
htog(0x00000000), //illtrap
|
||||
htog(0x00000000), //illtrap
|
||||
htog(0x00000000), //illtrap
|
||||
htog(0x00000000), //illtrap
|
||||
htog(0x00000000), //illtrap
|
||||
htog(0x00000000), //illtrap
|
||||
htog(0x00000000), //illtrap
|
||||
htog(0x00000000) //illtrap
|
||||
};
|
||||
|
||||
MachInst spillHandler[numSpillInsts] =
|
||||
{
|
||||
htog(0x87802018), //wr %g0, ASI_AIUP, %asi
|
||||
htog(0xe0f3a7ff), //stxa %l0, [%sp + BIAS + (0*8)] %asi
|
||||
htog(0xe2f3a807), //stxa %l1, [%sp + BIAS + (1*8)] %asi
|
||||
htog(0xe4f3a80f), //stxa %l2, [%sp + BIAS + (2*8)] %asi
|
||||
htog(0xe6f3a817), //stxa %l3, [%sp + BIAS + (3*8)] %asi
|
||||
htog(0xe8f3a81f), //stxa %l4, [%sp + BIAS + (4*8)] %asi
|
||||
htog(0xeaf3a827), //stxa %l5, [%sp + BIAS + (5*8)] %asi
|
||||
htog(0xecf3a82f), //stxa %l6, [%sp + BIAS + (6*8)] %asi
|
||||
htog(0xeef3a837), //stxa %l7, [%sp + BIAS + (7*8)] %asi
|
||||
htog(0xf0f3a83f), //stxa %i0, [%sp + BIAS + (8*8)] %asi
|
||||
htog(0xf2f3a847), //stxa %i1, [%sp + BIAS + (9*8)] %asi
|
||||
htog(0xf4f3a84f), //stxa %i2, [%sp + BIAS + (10*8)] %asi
|
||||
htog(0xf6f3a857), //stxa %i3, [%sp + BIAS + (11*8)] %asi
|
||||
htog(0xf8f3a85f), //stxa %i4, [%sp + BIAS + (12*8)] %asi
|
||||
htog(0xfaf3a867), //stxa %i5, [%sp + BIAS + (13*8)] %asi
|
||||
htog(0xfcf3a86f), //stxa %i6, [%sp + BIAS + (14*8)] %asi
|
||||
htog(0xfef3a877), //stxa %i7, [%sp + BIAS + (15*8)] %asi
|
||||
htog(0x81880000), //saved
|
||||
htog(0x83F00000), //retry
|
||||
htog(0x00000000), //illtrap
|
||||
htog(0x00000000), //illtrap
|
||||
htog(0x00000000), //illtrap
|
||||
htog(0x00000000), //illtrap
|
||||
htog(0x00000000), //illtrap
|
||||
htog(0x00000000), //illtrap
|
||||
htog(0x00000000), //illtrap
|
||||
htog(0x00000000), //illtrap
|
||||
htog(0x00000000), //illtrap
|
||||
htog(0x00000000), //illtrap
|
||||
htog(0x00000000), //illtrap
|
||||
htog(0x00000000), //illtrap
|
||||
htog(0x00000000) //illtrap
|
||||
};
|
||||
|
||||
void
|
||||
SparcLiveProcess::argsInit(int intSize, int pageSize)
|
||||
{
|
||||
|
|
@ -317,6 +402,17 @@ SparcLiveProcess::argsInit(int intSize, int pageSize)
|
|||
|
||||
initVirtMem->writeBlob(argc_base, (uint8_t*)&guestArgc, intSize);
|
||||
|
||||
//Stuff the trap handlers into the processes address space.
|
||||
//Since the stack grows down and is the highest area in the processes
|
||||
//address space, we can put stuff above it and stay out of the way.
|
||||
int fillSize = sizeof(MachInst) * numFillInsts;
|
||||
int spillSize = sizeof(MachInst) * numSpillInsts;
|
||||
fillStart = stack_base;
|
||||
spillStart = fillStart + fillSize;
|
||||
initVirtMem->writeBlob(fillStart, (uint8_t*)fillHandler, fillSize);
|
||||
initVirtMem->writeBlob(spillStart, (uint8_t*)spillHandler, spillSize);
|
||||
|
||||
//Set up the thread context to start running the process
|
||||
threadContexts[0]->setIntReg(ArgumentReg0, argc);
|
||||
threadContexts[0]->setIntReg(ArgumentReg1, argv_array_base);
|
||||
threadContexts[0]->setIntReg(StackPointerReg, stack_min - StackBias);
|
||||
|
|
|
|||
|
|
@ -55,6 +55,9 @@ class SparcLiveProcess : public LiveProcess
|
|||
|
||||
static const Addr StackBias = 2047;
|
||||
|
||||
//The locations of the fill and spill handlers
|
||||
Addr fillStart, spillStart;
|
||||
|
||||
std::vector<m5_auxv_t> auxv;
|
||||
|
||||
SparcLiveProcess(const std::string &nm, ObjectFile *objFile,
|
||||
|
|
@ -71,6 +74,12 @@ class SparcLiveProcess : public LiveProcess
|
|||
|
||||
void argsInit(int intSize, int pageSize);
|
||||
|
||||
Addr readFillStart()
|
||||
{ return fillStart; }
|
||||
|
||||
Addr readSpillStart()
|
||||
{ return spillStart; }
|
||||
|
||||
};
|
||||
|
||||
#endif // __SPARC_PROCESS_HH__
|
||||
|
|
|
|||
|
|
@ -82,18 +82,21 @@ MiscReg RegFile::readMiscReg(int miscReg)
|
|||
MiscReg RegFile::readMiscRegWithEffect(int miscReg,
|
||||
Fault &fault, ThreadContext *tc)
|
||||
{
|
||||
return miscRegFile.readRegWithEffect(miscReg, fault, tc);
|
||||
fault = NoFault;
|
||||
return miscRegFile.readRegWithEffect(miscReg, tc);
|
||||
}
|
||||
|
||||
Fault RegFile::setMiscReg(int miscReg, const MiscReg &val)
|
||||
{
|
||||
return miscRegFile.setReg(miscReg, val);
|
||||
miscRegFile.setReg(miscReg, val);
|
||||
return NoFault;
|
||||
}
|
||||
|
||||
Fault RegFile::setMiscRegWithEffect(int miscReg, const MiscReg &val,
|
||||
ThreadContext * tc)
|
||||
{
|
||||
return miscRegFile.setRegWithEffect(miscReg, val, tc);
|
||||
miscRegFile.setRegWithEffect(miscReg, val, tc);
|
||||
return NoFault;
|
||||
}
|
||||
|
||||
FloatReg RegFile::readFloatReg(int floatReg, int width)
|
||||
|
|
|
|||
|
|
@ -69,4 +69,28 @@ sext(uint64_t val)
|
|||
return sign_bit ? (val | ~mask(N)) : val;
|
||||
}
|
||||
|
||||
/**
|
||||
* Return val with bits first to last set to bit_val
|
||||
*/
|
||||
template <class T, class B>
|
||||
inline
|
||||
T
|
||||
insertBits(T val, int first, int last, B bit_val)
|
||||
{
|
||||
T bmask = mask(first - last + 1) << last;
|
||||
return ((bit_val << last) & bmask) | (val & ~bmask);
|
||||
}
|
||||
|
||||
/**
|
||||
* A convenience function to replace bits first to last of val with bit_val
|
||||
* in place.
|
||||
*/
|
||||
template <class T, class B>
|
||||
inline
|
||||
void
|
||||
replaceBits(T& val, int first, int last, B bit_val)
|
||||
{
|
||||
val = insertBits(val, first, last, bit_val);
|
||||
}
|
||||
|
||||
#endif // __BASE_BITFIELD_HH__
|
||||
|
|
|
|||
|
|
@ -91,6 +91,8 @@ uid=100
|
|||
[system.membus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
width=64
|
||||
port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.physmem]
|
||||
|
|
|
|||
|
|
@ -19,6 +19,8 @@ mem_mode=atomic
|
|||
[system.membus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
width=64
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
|
|
|
|||
|
|
@ -1,18 +1,18 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 2175 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 147292 # Number of bytes of host memory used
|
||||
host_seconds 2.06 # Real time elapsed on the host
|
||||
host_tick_rate 2174 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 58121 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 148396 # Number of bytes of host memory used
|
||||
host_seconds 0.08 # Real time elapsed on the host
|
||||
host_tick_rate 57840 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 4483 # Number of instructions simulated
|
||||
sim_insts 4863 # Number of instructions simulated
|
||||
sim_seconds 0.000000 # Number of seconds simulated
|
||||
sim_ticks 4482 # Number of ticks simulated
|
||||
sim_ticks 4862 # Number of ticks simulated
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 4483 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 4483 # Number of instructions executed
|
||||
system.cpu.num_refs 965 # Number of memory references
|
||||
system.cpu.numCycles 4863 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 4863 # Number of instructions executed
|
||||
system.cpu.num_refs 1269 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -5,8 +5,8 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Oct 8 2006 14:19:59
|
||||
M5 started Sun Oct 8 14:20:03 2006
|
||||
M5 compiled Oct 27 2006 02:07:29
|
||||
M5 started Fri Oct 27 02:08:08 2006
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-atomic tests/run.py quick/00.hello/sparc/linux/simple-atomic
|
||||
Exiting @ tick 4482 because target called exit()
|
||||
command line: build/SPARC_SE/m5.debug -d build/SPARC_SE/tests/debug/quick/00.hello/sparc/linux/simple-atomic tests/run.py quick/00.hello/sparc/linux/simple-atomic
|
||||
Exiting @ tick 4862 because target called exit()
|
||||
|
|
|
|||
|
|
@ -20,7 +20,6 @@ print_effaddr=true
|
|||
print_fetchseq=false
|
||||
print_iregs=false
|
||||
print_opclass=true
|
||||
print_reg_delta=false
|
||||
print_thread=true
|
||||
speculative=true
|
||||
trace_system=client
|
||||
|
|
|
|||
|
|
@ -1,67 +1,67 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 53689 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 177104 # Number of bytes of host memory used
|
||||
host_seconds 0.08 # Real time elapsed on the host
|
||||
host_tick_rate 17808084 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 48159 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 179620 # Number of bytes of host memory used
|
||||
host_seconds 0.10 # Real time elapsed on the host
|
||||
host_tick_rate 15510230 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 4483 # Number of instructions simulated
|
||||
sim_seconds 0.000001 # Number of seconds simulated
|
||||
sim_ticks 1497001 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 464 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3972.166667 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2972.166667 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 410 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 214497 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.116379 # miss rate for ReadReq accesses
|
||||
sim_insts 4863 # Number of instructions simulated
|
||||
sim_seconds 0.000002 # Number of seconds simulated
|
||||
sim_ticks 1573001 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 608 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3971.370370 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2971.370370 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 554 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 214454 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.088816 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 160497 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.116379 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 160454 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.088816 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 501 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 3980.840580 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2980.840580 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 432 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 274678 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.137725 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 69 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 205678 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.137725 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 69 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 661 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 3981.559524 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2981.559524 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 577 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 334451 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.127080 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 84 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 250451 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.127080 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 84 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 6.845528 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 8.195652 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 965 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 3977.032520 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2977.032520 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 842 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 489175 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.127461 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 123 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_accesses 1269 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 3977.572464 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2977.572464 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 1131 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 548905 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.108747 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 138 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 366175 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.127461 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 123 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_miss_latency 410905 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.108747 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 965 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 3977.032520 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2977.032520 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_accesses 1269 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 3977.572464 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2977.572464 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 842 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 489175 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.127461 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 123 # number of overall misses
|
||||
system.cpu.dcache.overall_hits 1131 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 548905 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.108747 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 138 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 366175 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.127461 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 123 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_miss_latency 410905 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.108747 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -74,56 +74,56 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 123 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 71.370810 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 842 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 81.997528 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1131 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 4484 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 3979.178571 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2979.178571 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 4232 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 1002753 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.056200 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 252 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 750753 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.056200 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 252 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_accesses 4864 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 3977.960938 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2977.960938 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 4608 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 1018358 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.052632 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 256 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 762358 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.052632 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 256 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 16.793651 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 18 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 4484 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 3979.178571 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 2979.178571 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 4232 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 1002753 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.056200 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 252 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_accesses 4864 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 3977.960938 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 2977.960938 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 4608 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 1018358 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.052632 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 256 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 750753 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.056200 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 252 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_miss_latency 762358 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.052632 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 256 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 4484 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 3979.178571 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 2979.178571 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_accesses 4864 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 3977.960938 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 2977.960938 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 4232 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 1002753 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.056200 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 252 # number of overall misses
|
||||
system.cpu.icache.overall_hits 4608 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 1018358 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.052632 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 256 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 750753 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.056200 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 252 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_miss_latency 762358 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.052632 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 256 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -136,57 +136,57 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.sampled_refs 252 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 256 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 115.914677 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 4232 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 114.778311 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 4608 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 375 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2986.473118 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1985.473118 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_accesses 394 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2985.429668 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1984.429668 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1110968 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.992000 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 372 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 738596 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.992000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 372 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1167303 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.992386 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 391 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 775912 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.992386 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 391 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.008065 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.007673 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 375 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2986.473118 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1985.473118 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_accesses 394 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2985.429668 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1984.429668 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 1110968 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.992000 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 372 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_miss_latency 1167303 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.992386 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 391 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 738596 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.992000 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 372 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 775912 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.992386 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 391 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 375 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2986.473118 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1985.473118 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_accesses 394 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2985.429668 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1984.429668 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 3 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 1110968 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.992000 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 372 # number of overall misses
|
||||
system.cpu.l2cache.overall_miss_latency 1167303 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.992386 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 391 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 738596 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.992000 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 372 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 775912 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.992386 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 391 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -199,16 +199,16 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 372 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 391 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 185.896040 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 195.424915 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 1497001 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 4483 # Number of instructions executed
|
||||
system.cpu.num_refs 965 # Number of memory references
|
||||
system.cpu.numCycles 1573001 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 4863 # Number of instructions executed
|
||||
system.cpu.num_refs 1269 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -5,8 +5,8 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Oct 23 2006 07:47:36
|
||||
M5 started Mon Oct 23 07:47:41 2006
|
||||
M5 executing on zeep
|
||||
M5 compiled Oct 27 2006 02:07:29
|
||||
M5 started Fri Oct 27 02:08:11 2006
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/SPARC_SE/m5.debug -d build/SPARC_SE/tests/debug/quick/00.hello/sparc/linux/simple-timing tests/run.py quick/00.hello/sparc/linux/simple-timing
|
||||
Exiting @ tick 1497001 because target called exit()
|
||||
Exiting @ tick 1573001 because target called exit()
|
||||
|
|
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Reference in a new issue