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Remove mem parameter. Now the translating port asks the CPU's dcache's peer for its MemObject instead of having to have a paramter for the MemObject.

Browse source 
configs/example/fs.py:
configs/example/se.py:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
src/cpu/thread_state.cc:
src/cpu/thread_state.hh:
tests/configs/o3-timing-mp.py:
tests/configs/o3-timing.py:
tests/configs/simple-atomic-mp.py:
tests/configs/simple-atomic.py:
tests/configs/simple-timing-mp.py:
tests/configs/simple-timing.py:
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
    No need for mem parameter any more.
src/cpu/checker/cpu.cc:
    Use new constructor for simple thread (no more MemObject parameter).
src/cpu/checker/cpu.hh:
    Remove MemObject parameter.
src/cpu/memtest/memtest.hh:
    Ports now take in their MemObject owner.
src/cpu/o3/alpha/cpu_builder.cc:
    Remove mem parameter.
src/cpu/o3/alpha/cpu_impl.hh:
    Remove memory parameter and clean up handling of TranslatingPort.
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/mips/cpu_builder.cc:
src/cpu/o3/mips/cpu_impl.hh:
src/cpu/o3/params.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_builder.cc:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/simple_params.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/simple/atomic.cc:
    Remove memory parameter.

--HG--
extra : convert_revision : 43cb44a33b31320d44b69679dcf646c0380d07d3
This commit is contained in:
Kevin Lim 2006-10-31 14:33:56 -05:00
parent b26355daa8
commit bfd5eb2b08
42 changed files with 98 additions and 179 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
configs/example/fs.py
View file

@ -137,13 +137,11 @@ for i in xrange(np):
test_sys.cpu[i].addPrivateSplitL1Caches(MyCache(size = '32kB'),
MyCache(size = '64kB'))
test_sys.cpu[i].connectMemPorts(test_sys.membus)
test_sys.cpu[i].mem = test_sys.physmem
if len(bm) == 2:
drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
drive_sys.cpu = DriveCPUClass(cpu_id=0)
drive_sys.cpu.connectMemPorts(drive_sys.membus)
drive_sys.cpu.mem = drive_sys.physmem
root = makeDualRoot(test_sys, drive_sys, options.etherdump)
elif len(bm) == 1:
root = Root(clock = '1THz', system = test_sys)
@ -163,8 +161,6 @@ if options.standard_switch:
switch_cpus[i].addPrivateSplitL1Caches(MyCache(size = '32kB'),
MyCache(size = '64kB'))
switch_cpus[i].mem = test_sys.physmem
switch_cpus1[i].mem = test_sys.physmem
switch_cpus[i].connectMemPorts(test_sys.membus)
root.switch_cpus = switch_cpus
root.switch_cpus1 = switch_cpus1

5
configs/example/se.py
View file

@ -39,7 +39,7 @@ parser = optparse.OptionParser()
# Benchmark options
parser.add_option("-c", "--cmd",
default="../../tests/test-progs/hello/bin/alpha/linux/hello",
default="../tests/test-progs/hello/bin/alpha/linux/hello",
help="The binary to run in syscall emulation mode.")
parser.add_option("-o", "--options", default="",
help="The options to pass to the binary, use \" \" around the entire\
@ -131,7 +131,6 @@ system = System(cpu = cpu,
membus = Bus())
system.physmem.port = system.membus.port
system.cpu.connectMemPorts(system.membus)
system.cpu.mem = system.physmem
system.cpu.clock = '2GHz'
if options.caches and not options.standard_switch:
system.cpu.addPrivateSplitL1Caches(MyCache(size = '32kB'),
@ -155,8 +154,6 @@ if options.standard_switch:
switch_cpu.workload = process
switch_cpu1.workload = process
switch_cpu.mem = system.physmem
switch_cpu1.mem = system.physmem
switch_cpu.connectMemPorts(system.membus)
root.switch_cpu = switch_cpu
root.switch_cpu1 = switch_cpu1

20
src/cpu/checker/cpu.cc
View file

@ -72,6 +72,12 @@ CheckerCPU::CheckerCPU(Params *p)
systemPtr = NULL;
#else
process = p->process;
thread = new SimpleThread(this, /* thread_num */ 0, process,
/* asid */ 0);
thread->setStatus(ThreadContext::Suspended);
tc = thread->getTC();
threadContexts.push_back(tc);
#endif
result.integer = 0;
@ -81,20 +87,6 @@ CheckerCPU::~CheckerCPU()
{
}
void
CheckerCPU::setMemory(MemObject *mem)
{
#if !FULL_SYSTEM
memPtr = mem;
thread = new SimpleThread(this, /* thread_num */ 0, process,
/* asid */ 0, mem);
thread->setStatus(ThreadContext::Suspended);
tc = thread->getTC();
threadContexts.push_back(tc);
#endif
}
void
CheckerCPU::setSystem(System *system)
{

4
src/cpu/checker/cpu.hh
View file

@ -112,10 +112,6 @@ class CheckerCPU : public BaseCPU
Process *process;
void setMemory(MemObject *mem);
MemObject *memPtr;
void setSystem(System *system);
System *systemPtr;

2
src/cpu/memtest/memtest.hh
View file

@ -97,7 +97,7 @@ class MemTest : public MemObject
public:
CpuPort(const std::string &_name, MemTest *_memtest)
: Port(_name), memtest(_memtest)
: Port(_name, _memtest), memtest(_memtest)
{ }
protected:

6
src/cpu/o3/alpha/cpu_builder.cc
View file

@ -61,8 +61,6 @@ Param<Tick> profile;
SimObjectVectorParam<Process *> workload;
#endif // FULL_SYSTEM
SimObjectParam<MemObject *> mem;
SimObjectParam<BaseCPU *> checker;
Param<Counter> max_insts_any_thread;
@ -169,8 +167,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
INIT_PARAM(workload, "Processes to run"),
#endif // FULL_SYSTEM
INIT_PARAM(mem, "Memory"),
INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
INIT_PARAM_DFLT(max_insts_any_thread,
@ -314,8 +310,6 @@ CREATE_SIM_OBJECT(DerivO3CPU)
params->workload = workload;
#endif // FULL_SYSTEM
params->mem = mem;
params->checker = checker;
params->max_insts_any_thread = max_insts_any_thread;

18
src/cpu/o3/alpha/cpu_impl.hh
View file

@ -77,24 +77,10 @@ AlphaO3CPU<Impl>::AlphaO3CPU(Params *params)
if (i < params->workload.size()) {
DPRINTF(O3CPU, "Workload[%i] process is %#x",
i, this->thread[i]);
this->thread[i] = new Thread(this, i, params->workload[i],
i, params->mem);
this->thread[i] = new Thread(this, i, params->workload[i], i);
this->thread[i]->setStatus(ThreadContext::Suspended);
#if !FULL_SYSTEM
/* Use this port to for syscall emulation writes to memory. */
Port *mem_port;
TranslatingPort *trans_port;
trans_port = new TranslatingPort(csprintf("%s-%d-funcport",
name(), i),
params->workload[i]->pTable,
false);
mem_port = params->mem->getPort("functional");
mem_port->setPeer(trans_port);
trans_port->setPeer(mem_port);
this->thread[i]->setMemPort(trans_port);
#endif
//usedTids[i] = true;
//threadMap[i] = i;
} else {
@ -102,7 +88,7 @@ AlphaO3CPU<Impl>::AlphaO3CPU(Params *params)
//when scheduling threads to CPU
Process* dummy_proc = NULL;
this->thread[i] = new Thread(this, i, dummy_proc, i, params->mem);
this->thread[i] = new Thread(this, i, dummy_proc, i);
//usedTids[i] = false;
}
#endif // !FULL_SYSTEM

2
src/cpu/o3/cpu.cc
View file

@ -187,7 +187,6 @@ FullO3CPU<Impl>::FullO3CPU(Params *params)
system(params->system),
physmem(system->physmem),
#endif // FULL_SYSTEM
mem(params->mem),
drainCount(0),
deferRegistration(params->deferRegistration),
numThreads(number_of_threads)
@ -204,7 +203,6 @@ FullO3CPU<Impl>::FullO3CPU(Params *params)
#if USE_CHECKER
BaseCPU *temp_checker = params->checker;
checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
checker->setMemory(mem);
#if FULL_SYSTEM
checker->setSystem(params->system);
#endif

3
src/cpu/o3/cpu.hh
View file

@ -620,9 +620,6 @@ class FullO3CPU : public BaseO3CPU
PhysicalMemory *physmem;
#endif
/** Pointer to memory. */
MemObject *mem;
/** Event to call process() on once draining has completed. */
Event *drainEvent;

2
src/cpu/o3/fetch.hh
View file

@ -329,8 +329,6 @@ class DefaultFetch
/** Wire used to write any information heading to decode. */
typename TimeBuffer<FetchStruct>::wire toDecode;
MemObject *mem;
/** Icache interface. */
IcachePort *icachePort;

3
src/cpu/o3/fetch_impl.hh
View file

@ -96,8 +96,7 @@ DefaultFetch<Impl>::IcachePort::recvRetry()
template<class Impl>
DefaultFetch<Impl>::DefaultFetch(Params *params)
: mem(params->mem),
branchPred(params),
: branchPred(params),
decodeToFetchDelay(params->decodeToFetchDelay),
renameToFetchDelay(params->renameToFetchDelay),
iewToFetchDelay(params->iewToFetchDelay),

6
src/cpu/o3/mips/cpu_builder.cc
View file

@ -54,8 +54,6 @@ Param<int> activity;
SimObjectVectorParam<Process *> workload;
SimObjectParam<MemObject *> mem;
SimObjectParam<BaseCPU *> checker;
Param<Counter> max_insts_any_thread;
@ -153,8 +151,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
INIT_PARAM(workload, "Processes to run"),
INIT_PARAM(mem, "Memory"),
INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
INIT_PARAM_DFLT(max_insts_any_thread,
@ -284,8 +280,6 @@ CREATE_SIM_OBJECT(DerivO3CPU)
params->workload = workload;
params->mem = mem;
params->checker = checker;
params->max_insts_any_thread = max_insts_any_thread;

18
src/cpu/o3/mips/cpu_impl.hh
View file

@ -58,24 +58,10 @@ MipsO3CPU<Impl>::MipsO3CPU(Params *params)
if (i < params->workload.size()) {
DPRINTF(O3CPU, "Workload[%i] process is %#x",
i, this->thread[i]);
this->thread[i] = new Thread(this, i, params->workload[i],
i, params->mem);
this->thread[i] = new Thread(this, i, params->workload[i], i);
this->thread[i]->setStatus(ThreadContext::Suspended);
/* Use this port to for syscall emulation writes to memory. */
Port *mem_port;
TranslatingPort *trans_port;
trans_port = new TranslatingPort(csprintf("%s-%d-funcport",
name(), i),
params->workload[i]->pTable,
false);
mem_port = params->mem->getPort("functional");
mem_port->setPeer(trans_port);
trans_port->setPeer(mem_port);
this->thread[i]->setMemPort(trans_port);
//usedTids[i] = true;
//threadMap[i] = i;
} else {
@ -83,7 +69,7 @@ MipsO3CPU<Impl>::MipsO3CPU(Params *params)
//when scheduling threads to CPU
Process* dummy_proc = NULL;
this->thread[i] = new Thread(this, i, dummy_proc, i, params->mem);
this->thread[i] = new Thread(this, i, dummy_proc, i);
//usedTids[i] = false;
}

2
src/cpu/o3/params.hh
View file

@ -54,8 +54,6 @@ class O3Params : public BaseO3CPU::Params
Process *process;
#endif // FULL_SYSTEM
MemObject *mem;
BaseCPU *checker;
//

7
src/cpu/o3/thread_state.hh
View file

@ -77,7 +77,7 @@ struct O3ThreadState : public ThreadState {
#if FULL_SYSTEM
O3ThreadState(O3CPU *_cpu, int _thread_num)
: ThreadState(-1, _thread_num),
: ThreadState(_cpu, -1, _thread_num),
cpu(_cpu), inSyscall(0), trapPending(0)
{
if (cpu->params->profile) {
@ -95,9 +95,8 @@ struct O3ThreadState : public ThreadState {
profilePC = 3;
}
#else
O3ThreadState(O3CPU *_cpu, int _thread_num, Process *_process, int _asid,
MemObject *mem)
: ThreadState(-1, _thread_num, _process, _asid, mem),
O3ThreadState(O3CPU *_cpu, int _thread_num, Process *_process, int _asid)
: ThreadState(_cpu, -1, _thread_num, _process, _asid),
cpu(_cpu), inSyscall(0), trapPending(0)
{ }
#endif

2
src/cpu/ozone/cpu.hh
View file

@ -368,8 +368,6 @@ class OzoneCPU : public BaseCPU
virtual Port *getPort(const std::string &name, int idx);
MemObject *mem;
FrontEnd *frontEnd;
BackEnd *backEnd;

5
src/cpu/ozone/cpu_builder.cc
View file

@ -69,8 +69,6 @@ SimObjectVectorParam<Process *> workload;
//SimObjectParam<PageTable *> page_table;
#endif // FULL_SYSTEM
SimObjectParam<MemObject *> mem;
SimObjectParam<BaseCPU *> checker;
Param<Counter> max_insts_any_thread;
@ -191,8 +189,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU)
// INIT_PARAM(page_table, "Page table"),
#endif // FULL_SYSTEM
INIT_PARAM_DFLT(mem, "Memory", NULL),
INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
INIT_PARAM_DFLT(max_insts_any_thread,
@ -350,7 +346,6 @@ CREATE_SIM_OBJECT(DerivOzoneCPU)
// params->pTable = page_table;
#endif // FULL_SYSTEM
params->mem = mem;
params->checker = checker;
params->max_insts_any_thread = max_insts_any_thread;
params->max_insts_all_threads = max_insts_all_threads;

19
src/cpu/ozone/cpu_impl.hh
View file

@ -93,10 +93,10 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
#if FULL_SYSTEM
: BaseCPU(p), thread(this, 0), tickEvent(this, p->width),
#else
: BaseCPU(p), thread(this, 0, p->workload[0], 0, p->mem),
: BaseCPU(p), thread(this, 0, p->workload[0], 0),
tickEvent(this, p->width),
#endif
mem(p->mem), comm(5, 5)
comm(5, 5)
{
frontEnd = new FrontEnd(p);
backEnd = new BackEnd(p);
@ -107,7 +107,6 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
#if USE_CHECKER
BaseCPU *temp_checker = p->checker;
checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
checker->setMemory(mem);
#if FULL_SYSTEM
checker->setSystem(p->system);
#endif
@ -198,19 +197,7 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
frontEnd->renameTable.copyFrom(thread.renameTable);
backEnd->renameTable.copyFrom(thread.renameTable);
#if !FULL_SYSTEM
/* Use this port to for syscall emulation writes to memory. */
Port *mem_port;
TranslatingPort *trans_port;
trans_port = new TranslatingPort(csprintf("%s-%d-funcport",
name(), 0),
p->workload[0]->pTable,
false);
mem_port = p->mem->getPort("functional");
mem_port->setPeer(trans_port);
trans_port->setPeer(mem_port);
thread.setMemPort(trans_port);
#else
#if FULL_SYSTEM
Port *mem_port;
FunctionalPort *phys_port;
VirtualPort *virt_port;

2
src/cpu/ozone/front_end.hh
View file

@ -208,8 +208,6 @@ class FrontEnd
IcachePort icachePort;
MemObject *mem;
RequestPtr memReq;
/** Mask to get a cache block's address. */

1
src/cpu/ozone/front_end_impl.hh
View file

@ -91,7 +91,6 @@ template <class Impl>
FrontEnd<Impl>::FrontEnd(Params *params)
: branchPred(params),
icachePort(this),
mem(params->mem),
numInstsReady(params->frontEndLatency, 0),
instBufferSize(0),
maxInstBufferSize(params->maxInstBufferSize),

2
src/cpu/ozone/lw_lsq.hh
View file

@ -239,8 +239,6 @@ class OzoneLWLSQ {
/** Pointer to the back-end stage. */
BackEnd *be;
MemObject *mem;
class DcachePort : public Port
{
protected:

2
src/cpu/ozone/lw_lsq_impl.hh
View file

@ -154,8 +154,6 @@ OzoneLWLSQ<Impl>::init(Params *params, unsigned maxLQEntries,
SQIndices.push(i);
}
mem = params->mem;
usedPorts = 0;
cachePorts = params->cachePorts;

2
src/cpu/ozone/simple_params.hh
View file

@ -61,8 +61,6 @@ class SimpleParams : public BaseCPU::Params
//Page Table
PageTable *pTable;
MemObject *mem;
//
// Caches
//

6
src/cpu/ozone/thread_state.hh
View file

@ -67,7 +67,7 @@ struct OzoneThreadState : public ThreadState {
#if FULL_SYSTEM
OzoneThreadState(CPUType *_cpu, int _thread_num)
: ThreadState(-1, _thread_num),
: ThreadState(_cpu, -1, _thread_num),
intrflag(0), cpu(_cpu), inSyscall(0), trapPending(0)
{
if (cpu->params->profile) {
@ -87,8 +87,8 @@ struct OzoneThreadState : public ThreadState {
}
#else
OzoneThreadState(CPUType *_cpu, int _thread_num, Process *_process,
int _asid, MemObject *mem)
: ThreadState(-1, _thread_num, _process, _asid, mem),
int _asid)
: ThreadState(_cpu, -1, _thread_num, _process, _asid),
cpu(_cpu), inSyscall(0), trapPending(0)
{
miscRegFile.clear();

12
src/cpu/simple/atomic.cc
View file

@ -72,15 +72,6 @@ AtomicSimpleCPU::getPort(const std::string &if_name, int idx)
void
AtomicSimpleCPU::init()
{
//Create Memory Ports (conect them up)
// Port *mem_dport = mem->getPort("");
// dcachePort.setPeer(mem_dport);
// mem_dport->setPeer(&dcachePort);
// Port *mem_iport = mem->getPort("");
// icachePort.setPeer(mem_iport);
// mem_iport->setPeer(&icachePort);
BaseCPU::init();
#if FULL_SYSTEM
for (int i = 0; i < threadContexts.size(); ++i) {
@ -500,7 +491,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
Param<Counter> max_loads_any_thread;
Param<Counter> max_loads_all_threads;
Param<Tick> progress_interval;
SimObjectParam<MemObject *> mem;
SimObjectParam<System *> system;
Param<int> cpu_id;
@ -533,7 +523,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
INIT_PARAM(max_loads_all_threads,
"terminate when all threads have reached this load count"),
INIT_PARAM(progress_interval, "Progress interval"),
INIT_PARAM(mem, "memory"),
INIT_PARAM(system, "system object"),
INIT_PARAM(cpu_id, "processor ID"),
@ -571,7 +560,6 @@ CREATE_SIM_OBJECT(AtomicSimpleCPU)
params->functionTraceStart = function_trace_start;
params->width = width;
params->simulate_stalls = simulate_stalls;
params->mem = mem;
params->system = system;
params->cpu_id = cpu_id;

4
src/cpu/simple/base.cc
View file

@ -70,13 +70,13 @@ using namespace std;
using namespace TheISA;
BaseSimpleCPU::BaseSimpleCPU(Params *p)
: BaseCPU(p), mem(p->mem), thread(NULL)
: BaseCPU(p), thread(NULL)
{
#if FULL_SYSTEM
thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
#else
thread = new SimpleThread(this, /* thread_num */ 0, p->process,
/* asid */ 0, mem);
/* asid */ 0);
#endif // !FULL_SYSTEM
thread->setStatus(ThreadContext::Suspended);

3
src/cpu/simple/base.hh
View file

@ -76,8 +76,6 @@ class BaseSimpleCPU : public BaseCPU
typedef TheISA::FloatReg FloatReg;
typedef TheISA::FloatRegBits FloatRegBits;
MemObject *mem;
protected:
Trace::InstRecord *traceData;
@ -95,7 +93,6 @@ class BaseSimpleCPU : public BaseCPU
public:
struct Params : public BaseCPU::Params
{
MemObject *mem;
#if FULL_SYSTEM
AlphaITB *itb;
AlphaDTB *dtb;

3
src/cpu/simple/timing.cc
View file

@ -660,7 +660,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU)
Param<Counter> max_loads_any_thread;
Param<Counter> max_loads_all_threads;
Param<Tick> progress_interval;
SimObjectParam<MemObject *> mem;
SimObjectParam<System *> system;
Param<int> cpu_id;
@ -693,7 +692,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU)
INIT_PARAM(max_loads_all_threads,
"terminate when all threads have reached this load count"),
INIT_PARAM(progress_interval, "Progress interval"),
INIT_PARAM(mem, "memory"),
INIT_PARAM(system, "system object"),
INIT_PARAM(cpu_id, "processor ID"),
@ -729,7 +727,6 @@ CREATE_SIM_OBJECT(TimingSimpleCPU)
params->clock = clock;
params->functionTrace = function_trace;
params->functionTraceStart = function_trace_start;
params->mem = mem;
params->system = system;
params->cpu_id = cpu_id;

38
src/cpu/simple_thread.cc
View file

@ -62,7 +62,7 @@ using namespace std;
SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
AlphaITB *_itb, AlphaDTB *_dtb,
bool use_kernel_stats)
: ThreadState(-1, _thread_num), cpu(_cpu), system(_sys), itb(_itb),
: ThreadState(_cpu, -1, _thread_num), cpu(_cpu), system(_sys), itb(_itb),
dtb(_dtb)
{
@ -106,19 +106,10 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
}
#else
SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num,
Process *_process, int _asid, MemObject* memobj)
: ThreadState(-1, _thread_num, _process, _asid, memobj),
Process *_process, int _asid)
: ThreadState(_cpu, -1, _thread_num, _process, _asid),
cpu(_cpu)
{
/* Use this port to for syscall emulation writes to memory. */
Port *mem_port;
port = new TranslatingPort(csprintf("%s-%d-funcport",
cpu->name(), tid),
process->pTable, false);
mem_port = memobj->getPort("functional");
mem_port->setPeer(port);
port->setPeer(mem_port);
regs.clear();
tc = new ProxyThreadContext<SimpleThread>(this);
}
@ -127,9 +118,9 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num,
SimpleThread::SimpleThread()
#if FULL_SYSTEM
: ThreadState(-1, -1)
: ThreadState(NULL, -1, -1)
#else
: ThreadState(-1, -1, NULL, -1, NULL)
: ThreadState(NULL, -1, -1, NULL, -1)
#endif
{
tc = new ProxyThreadContext<SimpleThread>(this);
@ -332,6 +323,25 @@ SimpleThread::delVirtPort(VirtualPort *vp)
}
}
#else
TranslatingPort *
SimpleThread::getMemPort()
{
if (port != NULL)
return port;
/* Use this port to for syscall emulation writes to memory. */
Port *dcache_port;
port = new TranslatingPort(csprintf("%s-%d-funcport",
cpu->name(), tid),
process->pTable, false);
dcache_port = cpu->getPort("dcache_port");
assert(dcache_port != NULL);
dcache_port = dcache_port->getPeer();
// mem_port->setPeer(port);
port->setPeer(dcache_port);
return port;
}
#endif

6
src/cpu/simple_thread.hh
View file

@ -117,8 +117,7 @@ class SimpleThread : public ThreadState
AlphaITB *_itb, AlphaDTB *_dtb,
bool use_kernel_stats = true);
#else
SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid,
MemObject *memobj);
SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid);
#endif
SimpleThread();
@ -174,6 +173,9 @@ class SimpleThread : public ThreadState
bool simPalCheck(int palFunc);
#else
// Override this function.
TranslatingPort *getMemPort();
Fault translateInstReq(RequestPtr &req)
{
return process->pTable->translate(req);

43
src/cpu/thread_state.cc
View file

@ -29,8 +29,11 @@
*/
#include "base/output.hh"
#include "cpu/base.hh"
#include "cpu/profile.hh"
#include "cpu/thread_state.hh"
#include "mem/port.hh"
#include "mem/translating_port.hh"
#include "sim/serialize.hh"
#if FULL_SYSTEM
@ -39,15 +42,16 @@
#endif
#if FULL_SYSTEM
ThreadState::ThreadState(int _cpuId, int _tid)
: cpuId(_cpuId), tid(_tid), lastActivate(0), lastSuspend(0),
ThreadState::ThreadState(BaseCPU *cpu, int _cpuId, int _tid)
: baseCpu(cpu), cpuId(_cpuId), tid(_tid), lastActivate(0), lastSuspend(0),
profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL),
physPort(NULL), virtPort(NULL),
microPC(0), nextMicroPC(1), funcExeInst(0), storeCondFailures(0)
#else
ThreadState::ThreadState(int _cpuId, int _tid, Process *_process,
short _asid, MemObject *mem)
: cpuId(_cpuId), tid(_tid), lastActivate(0), lastSuspend(0),
process(_process), asid(_asid),
ThreadState::ThreadState(BaseCPU *cpu, int _cpuId, int _tid, Process *_process,
short _asid)
: baseCpu(cpu), cpuId(_cpuId), tid(_tid), lastActivate(0), lastSuspend(0),
port(NULL), process(_process), asid(_asid),
microPC(0), nextMicroPC(1), funcExeInst(0), storeCondFailures(0)
#endif
{
@ -108,4 +112,31 @@ ThreadState::profileSample()
profile->sample(profileNode, profilePC);
}
#else
TranslatingPort *
ThreadState::getMemPort()
{
if (port != NULL)
return port;
/* Use this port to for syscall emulation writes to memory. */
Port *dcache_port, *func_mem_port;
port = new TranslatingPort(csprintf("%s-%d-funcport",
baseCpu->name(), tid),
process->pTable, false);
dcache_port = baseCpu->getPort("dcache_port");
assert(dcache_port != NULL);
MemObject *mem_object = dcache_port->getPeer()->getOwner();
assert(mem_object != NULL);
func_mem_port = mem_object->getPort("functional");
assert(func_mem_port != NULL);
func_mem_port->setPeer(port);
port->setPeer(func_mem_port);
return port;
}
#endif

14
src/cpu/thread_state.hh
View file

@ -37,7 +37,6 @@
#if !FULL_SYSTEM
#include "mem/mem_object.hh"
#include "mem/translating_port.hh"
#include "sim/process.hh"
#endif
@ -50,7 +49,9 @@ namespace Kernel {
};
#endif
class BaseCPU;
class Checkpoint;
class TranslatingPort;
/**
* Struct for holding general thread state that is needed across CPU
@ -62,10 +63,10 @@ struct ThreadState {
typedef ThreadContext::Status Status;
#if FULL_SYSTEM
ThreadState(int _cpuId, int _tid);
ThreadState(BaseCPU *cpu, int _cpuId, int _tid);
#else
ThreadState(int _cpuId, int _tid, Process *_process,
short _asid, MemObject *mem);
ThreadState(BaseCPU *cpu, int _cpuId, int _tid, Process *_process,
short _asid);
#endif
void serialize(std::ostream &os);
@ -105,7 +106,7 @@ struct ThreadState {
#else
Process *getProcessPtr() { return process; }
TranslatingPort *getMemPort() { return port; }
TranslatingPort *getMemPort();
void setMemPort(TranslatingPort *_port) { port = _port; }
@ -153,6 +154,9 @@ struct ThreadState {
protected:
ThreadContext::Status _status;
// Pointer to the base CPU.
BaseCPU *baseCpu;
// ID of this context w.r.t. the System or Process object to which
// it belongs. For full-system mode, this is the system CPU ID.
int cpuId;

1
tests/configs/o3-timing-mp.py
View file

@ -71,7 +71,6 @@ system.l2c.mem_side = system.membus.port
for cpu in cpus:
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4))
cpu.mem = cpu.dcache
# connect cpu level-1 caches to shared level-2 cache
cpu.connectMemPorts(system.toL2Bus)

1
tests/configs/o3-timing.py
View file

@ -40,7 +40,6 @@ class MyCache(BaseCache):
cpu = DerivO3CPU()
cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
MyCache(size = '2MB'))
cpu.mem = cpu.dcache
system = System(cpu = cpu,
physmem = PhysicalMemory(),

1
tests/configs/simple-atomic-mp.py
View file

@ -70,7 +70,6 @@ system.l2c.mem_side = system.membus.port
for cpu in cpus:
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4))
cpu.mem = cpu.dcache
# connect cpu level-1 caches to shared level-2 cache
cpu.connectMemPorts(system.toL2Bus)

1
tests/configs/simple-atomic.py
View file

@ -34,6 +34,5 @@ system = System(cpu = AtomicSimpleCPU(cpu_id=0),
membus = Bus())
system.physmem.port = system.membus.port
system.cpu.connectMemPorts(system.membus)
system.cpu.mem = system.physmem
root = Root(system = system)

1
tests/configs/simple-timing-mp.py
View file

@ -70,7 +70,6 @@ system.l2c.mem_side = system.membus.port
for cpu in cpus:
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4))
cpu.mem = cpu.dcache
# connect cpu level-1 caches to shared level-2 cache
cpu.connectMemPorts(system.toL2Bus)

2
tests/configs/simple-timing.py
View file

@ -39,8 +39,6 @@ class MyCache(BaseCache):
cpu = TimingSimpleCPU(cpu_id=0)
cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
MyCache(size = '2MB'))
cpu.mem = cpu.dcache
cpu.mem = cpu.dcache
system = System(cpu = cpu,
physmem = PhysicalMemory(),
membus = Bus())

1
tests/configs/tsunami-simple-atomic-dual.py
View file

@ -36,6 +36,5 @@ system = FSConfig.makeLinuxAlphaSystem('atomic')
system.cpu = cpus
for c in cpus:
c.connectMemPorts(system.membus)
c.mem = system.physmem
root = Root(clock = '2GHz', system = system)

1
tests/configs/tsunami-simple-atomic.py
View file

@ -35,6 +35,5 @@ cpu = AtomicSimpleCPU(cpu_id=0)
system = FSConfig.makeLinuxAlphaSystem('atomic')
system.cpu = cpu
cpu.connectMemPorts(system.membus)
cpu.mem = system.physmem
root = Root(clock = '2GHz', system = system)

1
tests/configs/tsunami-simple-timing-dual.py
View file

@ -36,6 +36,5 @@ system = FSConfig.makeLinuxAlphaSystem('timing')
system.cpu = cpus
for c in cpus:
c.connectMemPorts(system.membus)
c.mem = system.physmem
root = Root(clock = '2GHz', system = system)

1
tests/configs/tsunami-simple-timing.py
View file

@ -35,6 +35,5 @@ cpu = TimingSimpleCPU(cpu_id=0)
system = FSConfig.makeLinuxAlphaSystem('timing')
system.cpu = cpu
cpu.connectMemPorts(system.membus)
cpu.mem = system.physmem
root = Root(clock = '2GHz', system = system)