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Merge zizzer.eecs.umich.edu:/bk/newmem

Browse source 
into  vm1.(none):/home/stever/bk/newmem-head

--HG--
extra : convert_revision : 8b0fbb6b1ea38d01d048381f18fd95ab63c4c0f1
This commit is contained in:
Steve Reinhardt 2006-09-01 17:12:43 -07:00
parent edeb8f39a7 d8501ec17c
commit abe18be544
29 changed files with 5770 additions and 177 deletions
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1
build_opts/ALPHA_SE
View file

@ -1,2 +1,3 @@
FULL_SYSTEM = 0
SS_COMPATIBLE_FP = 1
CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU'

5
src/arch/alpha/isa_traits.hh
View file

@ -42,7 +42,6 @@ class StaticInstPtr;
namespace AlphaISA
{
using namespace LittleEndianGuest;
// These enumerate all the registers for dependence tracking.
@ -60,12 +59,14 @@ namespace AlphaISA
StaticInstPtr decodeInst(ExtMachInst);
// Alpha Does NOT have a delay slot
#define ISA_HAS_DELAY_SLOT 0
const Addr PageShift = 13;
const Addr PageBytes = ULL(1) << PageShift;
const Addr PageMask = ~(PageBytes - 1);
const Addr PageOffset = PageBytes - 1;
#if FULL_SYSTEM
////////////////////////////////////////////////////////////////////////

3
src/arch/mips/isa_traits.hh
View file

@ -47,6 +47,9 @@ namespace MipsISA
StaticInstPtr decodeInst(ExtMachInst);
// MIPS DOES a delay slot
#define ISA_HAS_DELAY_SLOT 1
const Addr PageShift = 13;
const Addr PageBytes = ULL(1) << PageShift;
const Addr PageMask = ~(PageBytes - 1);

3
src/arch/sparc/isa_traits.hh
View file

@ -57,6 +57,9 @@ namespace SparcISA
//This makes sure the big endian versions of certain functions are used.
using namespace BigEndianGuest;
// Alpha Does NOT have a delay slot
#define ISA_HAS_DELAY_SLOT 1
//TODO this needs to be a SPARC Noop
// Alpha UNOP (ldq_u r31,0(r0))
const MachInst NoopMachInst = 0x2ffe0000;

12
src/cpu/base_dyn_inst.hh
View file

@ -291,18 +291,18 @@ class BaseDynInst : public FastAlloc, public RefCounted
/** Returns whether the instruction was predicted taken or not. */
bool predTaken()
#if THE_ISA == ALPHA_ISA
{ return predPC != (PC + sizeof(MachInst)); }
#else
#if ISA_HAS_DELAY_SLOT
{ return predPC != (nextPC + sizeof(MachInst)); }
#else
{ return predPC != (PC + sizeof(MachInst)); }
#endif
/** Returns whether the instruction mispredicted. */
bool mispredicted()
#if THE_ISA == ALPHA_ISA
{ return predPC != nextPC; }
#else
#if ISA_HAS_DELAY_SLOT
{ return predPC != nextNPC; }
#else
{ return predPC != nextPC; }
#endif
//
// Instruction types. Forward checks to StaticInst object.

12
src/cpu/o3/bpred_unit_impl.hh
View file

@ -29,6 +29,7 @@
*/
#include "arch/types.hh"
#include "arch/isa_traits.hh"
#include "base/trace.hh"
#include "base/traceflags.hh"
#include "cpu/o3/bpred_unit.hh"
@ -197,10 +198,10 @@ BPredUnit<Impl>::predict(DynInstPtr &inst, Addr &PC, unsigned tid)
++BTBLookups;
if (inst->isCall()) {
#if THE_ISA == ALPHA_ISA
Addr ras_pc = PC + sizeof(MachInst); // Next PC
#else
#if ISA_HAS_DELAY_SLOT
Addr ras_pc = PC + (2 * sizeof(MachInst)); // Next Next PC
#else
Addr ras_pc = PC + sizeof(MachInst); // Next PC
#endif
RAS[tid].push(ras_pc);
@ -209,8 +210,8 @@ BPredUnit<Impl>::predict(DynInstPtr &inst, Addr &PC, unsigned tid)
predict_record.wasCall = true;
DPRINTF(Fetch, "BranchPred: [tid:%i]: Instruction %#x was a call"
", adding %#x to the RAS.\n",
tid, inst->readPC(), ras_pc);
", adding %#x to the RAS index: %i.\n",
tid, inst->readPC(), ras_pc, RAS[tid].topIdx());
}
if (BTB.valid(PC, tid)) {
@ -283,7 +284,6 @@ BPredUnit<Impl>::squash(const InstSeqNum &squashed_sn, unsigned tid)
RAS[tid].restore(pred_hist.front().RASIndex,
pred_hist.front().RASTarget);
} else if (pred_hist.front().wasCall) {
DPRINTF(Fetch, "BranchPred: [tid:%i]: Removing speculative entry "
"added to the RAS.\n",tid);

36
src/cpu/o3/commit_impl.hh
View file

@ -722,7 +722,7 @@ DefaultCommit<Impl>::commit()
// then use one older sequence number.
InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
#if THE_ISA != ALPHA_ISA
#if ISA_HAS_DELAY_SLOT
InstSeqNum bdelay_done_seq_num;
bool squash_bdelay_slot;
@ -748,7 +748,7 @@ DefaultCommit<Impl>::commit()
if (fromIEW->includeSquashInst[tid] == true) {
squashed_inst--;
#if THE_ISA != ALPHA_ISA
#if ISA_HAS_DELAY_SLOT
bdelay_done_seq_num--;
#endif
}
@ -756,13 +756,13 @@ DefaultCommit<Impl>::commit()
// number as the youngest instruction in the ROB.
youngestSeqNum[tid] = squashed_inst;
#if THE_ISA == ALPHA_ISA
rob->squash(squashed_inst, tid);
toIEW->commitInfo[tid].squashDelaySlot = true;
#else
#if ISA_HAS_DELAY_SLOT
rob->squash(bdelay_done_seq_num, tid);
toIEW->commitInfo[tid].squashDelaySlot = squash_bdelay_slot;
toIEW->commitInfo[tid].bdelayDoneSeqNum = bdelay_done_seq_num;
#else
rob->squash(squashed_inst, tid);
toIEW->commitInfo[tid].squashDelaySlot = true;
#endif
changedROBNumEntries[tid] = true;
@ -800,7 +800,7 @@ DefaultCommit<Impl>::commit()
// Try to commit any instructions.
commitInsts();
} else {
#if THE_ISA != ALPHA_ISA
#if ISA_HAS_DELAY_SLOT
skidInsert();
#endif
}
@ -906,11 +906,11 @@ DefaultCommit<Impl>::commitInsts()
}
PC[tid] = nextPC[tid];
#if THE_ISA == ALPHA_ISA
nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst);
#else
#if ISA_HAS_DELAY_SLOT
nextPC[tid] = nextNPC[tid];
nextNPC[tid] = nextNPC[tid] + sizeof(TheISA::MachInst);
#else
nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst);
#endif
#if FULL_SYSTEM
@ -1115,10 +1115,7 @@ DefaultCommit<Impl>::getInsts()
{
DPRINTF(Commit, "Getting instructions from Rename stage.\n");
#if THE_ISA == ALPHA_ISA
// Read any renamed instructions and place them into the ROB.
int insts_to_process = std::min((int)renameWidth, fromRename->size);
#else
#if ISA_HAS_DELAY_SLOT
// Read any renamed instructions and place them into the ROB.
int insts_to_process = std::min((int)renameWidth,
(int)(fromRename->size + skidBuffer.size()));
@ -1127,15 +1124,16 @@ DefaultCommit<Impl>::getInsts()
DPRINTF(Commit, "%i insts available to process. Rename Insts:%i "
"SkidBuffer Insts:%i\n", insts_to_process, fromRename->size,
skidBuffer.size());
#else
// Read any renamed instructions and place them into the ROB.
int insts_to_process = std::min((int)renameWidth, fromRename->size);
#endif
for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
DynInstPtr inst;
#if THE_ISA == ALPHA_ISA
inst = fromRename->insts[inst_num];
#else
#if ISA_HAS_DELAY_SLOT
// Get insts from skidBuffer or from Rename
if (skidBuffer.size() > 0) {
DPRINTF(Commit, "Grabbing skidbuffer inst.\n");
@ -1145,6 +1143,8 @@ DefaultCommit<Impl>::getInsts()
DPRINTF(Commit, "Grabbing rename inst.\n");
inst = fromRename->insts[rename_idx++];
}
#else
inst = fromRename->insts[inst_num];
#endif
int tid = inst->threadNumber;
@ -1167,7 +1167,7 @@ DefaultCommit<Impl>::getInsts()
}
}
#if THE_ISA != ALPHA_ISA
#if ISA_HAS_DELAY_SLOT
if (rename_idx < fromRename->size) {
DPRINTF(Commit,"Placing Rename Insts into skidBuffer.\n");

10
src/cpu/o3/cpu.cc
View file

@ -181,7 +181,6 @@ FullO3CPU<Impl>::FullO3CPU(Params *params)
params->activity),
globalSeqNum(1),
#if FULL_SYSTEM
system(params->system),
physmem(system->physmem),
@ -322,6 +321,11 @@ FullO3CPU<Impl>::FullO3CPU(Params *params)
lastActivatedCycle = -1;
// Give renameMap & rename stage access to the freeList;
//for (int i=0; i < numThreads; i++) {
//globalSeqNum[i] = 1;
//}
contextSwitch = false;
}
@ -627,7 +631,7 @@ FullO3CPU<Impl>::insertThread(unsigned tid)
//Set PC/NPC/NNPC
setPC(src_tc->readPC(), tid);
setNextPC(src_tc->readNextPC(), tid);
#if THE_ISA != ALPHA_ISA
#if ISA_HAS_DELAY_SLOT
setNextNPC(src_tc->readNextNPC(), tid);
#endif
@ -1197,7 +1201,7 @@ FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid,
while (inst_it != end_it) {
assert(!instList.empty());
#if THE_ISA != ALPHA_ISA
#if ISA_HAS_DELAY_SLOT
if(!squash_delay_slot &&
delay_slot_seq_num >= (*inst_it)->seqNum) {
break;

2
src/cpu/o3/cpu.hh
View file

@ -598,7 +598,7 @@ class FullO3CPU : public BaseO3CPU
}
/** The global sequence number counter. */
InstSeqNum globalSeqNum;
InstSeqNum globalSeqNum;//[Impl::MaxThreads];
/** Pointer to the checker, which can dynamically verify
* instruction results at run time. This can be set to NULL if it

18
src/cpu/o3/decode_impl.hh
View file

@ -282,12 +282,7 @@ DefaultDecode<Impl>::squash(DynInstPtr &inst, unsigned tid)
toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum;
toFetch->decodeInfo[tid].squash = true;
toFetch->decodeInfo[tid].nextPC = inst->branchTarget();
#if THE_ISA == ALPHA_ISA
toFetch->decodeInfo[tid].branchTaken =
inst->readNextPC() != (inst->readPC() + sizeof(TheISA::MachInst));
InstSeqNum squash_seq_num = inst->seqNum;
#else
#if ISA_HAS_DELAY_SLOT
toFetch->decodeInfo[tid].branchTaken = inst->readNextNPC() !=
(inst->readNextPC() + sizeof(TheISA::MachInst));
@ -295,6 +290,11 @@ DefaultDecode<Impl>::squash(DynInstPtr &inst, unsigned tid)
squashAfterDelaySlot[tid] = false;
InstSeqNum squash_seq_num = bdelayDoneSeqNum[tid];
#else
toFetch->decodeInfo[tid].branchTaken =
inst->readNextPC() != (inst->readPC() + sizeof(TheISA::MachInst));
InstSeqNum squash_seq_num = inst->seqNum;
#endif
// Might have to tell fetch to unblock.
@ -317,7 +317,7 @@ DefaultDecode<Impl>::squash(DynInstPtr &inst, unsigned tid)
// insts in them.
while (!insts[tid].empty()) {
#if THE_ISA != ALPHA_ISA
#if ISA_HAS_DELAY_SLOT
if (insts[tid].front()->seqNum <= squash_seq_num) {
DPRINTF(Decode, "[tid:%i]: Cannot remove incoming decode "
"instructions before delay slot [sn:%i]. %i insts"
@ -331,7 +331,7 @@ DefaultDecode<Impl>::squash(DynInstPtr &inst, unsigned tid)
while (!skidBuffer[tid].empty()) {
#if THE_ISA != ALPHA_ISA
#if ISA_HAS_DELAY_SLOT
if (skidBuffer[tid].front()->seqNum <= squash_seq_num) {
DPRINTF(Decode, "[tid:%i]: Cannot remove skidBuffer "
"instructions before delay slot [sn:%i]. %i insts"
@ -765,7 +765,7 @@ DefaultDecode<Impl>::decodeInsts(unsigned tid)
// Might want to set some sort of boolean and just do
// a check at the end
#if THE_ISA == ALPHA_ISA
#if !ISA_HAS_DELAY_SLOT
squash(inst, inst->threadNumber);
inst->setPredTarg(inst->branchTarget());
break;

52
src/cpu/o3/fetch_impl.hh
View file

@ -339,7 +339,7 @@ DefaultFetch<Impl>::initStage()
for (int tid = 0; tid < numThreads; tid++) {
PC[tid] = cpu->readPC(tid);
nextPC[tid] = cpu->readNextPC(tid);
#if THE_ISA != ALPHA_ISA
#if ISA_HAS_DELAY_SLOT
nextNPC[tid] = cpu->readNextNPC(tid);
#endif
}
@ -429,7 +429,7 @@ DefaultFetch<Impl>::takeOverFrom()
stalls[i].commit = 0;
PC[i] = cpu->readPC(i);
nextPC[i] = cpu->readNextPC(i);
#if THE_ISA != ALPHA_ISA
#if ISA_HAS_DELAY_SLOT
nextNPC[i] = cpu->readNextNPC(i);
delaySlotInfo[i].branchSeqNum = -1;
delaySlotInfo[i].numInsts = 0;
@ -492,22 +492,20 @@ DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC,
bool predict_taken;
if (!inst->isControl()) {
#if THE_ISA == ALPHA_ISA
next_PC = next_PC + instSize;
inst->setPredTarg(next_PC);
#else
#if ISA_HAS_DELAY_SLOT
Addr cur_PC = next_PC;
next_PC = cur_PC + instSize; //next_NPC;
next_NPC = cur_PC + (2 * instSize);//next_NPC + instSize;
inst->setPredTarg(next_NPC);
#else
next_PC = next_PC + instSize;
inst->setPredTarg(next_PC);
#endif
return false;
}
int tid = inst->threadNumber;
#if THE_ISA == ALPHA_ISA
predict_taken = branchPred.predict(inst, next_PC, tid);
#else
#if ISA_HAS_DELAY_SLOT
Addr pred_PC = next_PC;
predict_taken = branchPred.predict(inst, pred_PC, tid);
@ -539,6 +537,8 @@ DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC,
next_NPC = next_NPC + instSize;
}
#else
predict_taken = branchPred.predict(inst, next_PC, tid);
#endif
++fetchedBranches;
@ -692,7 +692,7 @@ DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC,
doSquash(new_PC, tid);
#if THE_ISA != ALPHA_ISA
#if ISA_HAS_DELAY_SLOT
if (seq_num <= delaySlotInfo[tid].branchSeqNum) {
delaySlotInfo[tid].numInsts = 0;
delaySlotInfo[tid].targetAddr = 0;
@ -780,10 +780,7 @@ DefaultFetch<Impl>::squash(const Addr &new_PC, const InstSeqNum &seq_num,
doSquash(new_PC, tid);
#if THE_ISA == ALPHA_ISA
// Tell the CPU to remove any instructions that are not in the ROB.
cpu->removeInstsNotInROB(tid, true, 0);
#else
#if ISA_HAS_DELAY_SLOT
if (seq_num <= delaySlotInfo[tid].branchSeqNum) {
delaySlotInfo[tid].numInsts = 0;
delaySlotInfo[tid].targetAddr = 0;
@ -792,6 +789,9 @@ DefaultFetch<Impl>::squash(const Addr &new_PC, const InstSeqNum &seq_num,
// Tell the CPU to remove any instructions that are not in the ROB.
cpu->removeInstsNotInROB(tid, squash_delay_slot, seq_num);
#else
// Tell the CPU to remove any instructions that are not in the ROB.
cpu->removeInstsNotInROB(tid, true, 0);
#endif
}
@ -901,10 +901,10 @@ DefaultFetch<Impl>::checkSignalsAndUpdate(unsigned tid)
DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
"from commit.\n",tid);
#if THE_ISA == ALPHA_ISA
InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].doneSeqNum;
#if ISA_HAS_DELAY_SLOT
InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
#else
InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].doneSeqNum;
#endif
// In any case, squash.
squash(fromCommit->commitInfo[tid].nextPC,
@ -958,10 +958,10 @@ DefaultFetch<Impl>::checkSignalsAndUpdate(unsigned tid)
if (fetchStatus[tid] != Squashing) {
#if THE_ISA == ALPHA_ISA
InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].doneSeqNum;
#else
#if ISA_HAS_DELAY_SLOT
InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].bdelayDoneSeqNum;
#else
InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].doneSeqNum;
#endif
// Squash unless we're already squashing
squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
@ -1162,7 +1162,7 @@ DefaultFetch<Impl>::fetch(bool &status_change)
offset += instSize;
#if THE_ISA != ALPHA_ISA
#if ISA_HAS_DELAY_SLOT
if (predicted_branch) {
delaySlotInfo[tid].branchSeqNum = inst_seq;
@ -1205,11 +1205,7 @@ DefaultFetch<Impl>::fetch(bool &status_change)
// Now that fetching is completed, update the PC to signify what the next
// cycle will be.
if (fault == NoFault) {
#if THE_ISA == ALPHA_ISA
DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n",tid, next_PC);
PC[tid] = next_PC;
nextPC[tid] = next_PC + instSize;
#else
#if ISA_HAS_DELAY_SLOT
if (delaySlotInfo[tid].targetReady &&
delaySlotInfo[tid].numInsts == 0) {
// Set PC to target
@ -1225,6 +1221,10 @@ DefaultFetch<Impl>::fetch(bool &status_change)
}
DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n", tid, PC[tid]);
#else
DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n",tid, next_PC);
PC[tid] = next_PC;
nextPC[tid] = next_PC + instSize;
#endif
} else {
// We shouldn't be in an icache miss and also have a fault (an ITB

31
src/cpu/o3/iew_impl.hh
View file

@ -427,10 +427,10 @@ DefaultIEW<Impl>::squash(unsigned tid)
instQueue.squash(tid);
// Tell the LDSTQ to start squashing.
#if THE_ISA == ALPHA_ISA
ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
#else
#if ISA_HAS_DELAY_SLOT
ldstQueue.squash(fromCommit->commitInfo[tid].bdelayDoneSeqNum, tid);
#else
ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
#endif
updatedQueues = true;
@ -439,7 +439,7 @@ DefaultIEW<Impl>::squash(unsigned tid)
tid, fromCommit->commitInfo[tid].bdelayDoneSeqNum);
while (!skidBuffer[tid].empty()) {
#if THE_ISA != ALPHA_ISA
#if ISA_HAS_DELAY_SLOT
if (skidBuffer[tid].front()->seqNum <=
fromCommit->commitInfo[tid].bdelayDoneSeqNum) {
DPRINTF(IEW, "[tid:%i]: Cannot remove skidbuffer instructions "
@ -479,11 +479,7 @@ DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid)
toCommit->mispredPC[tid] = inst->readPC();
toCommit->branchMispredict[tid] = true;
#if THE_ISA == ALPHA_ISA
toCommit->branchTaken[tid] = inst->readNextPC() !=
(inst->readPC() + sizeof(TheISA::MachInst));
toCommit->nextPC[tid] = inst->readNextPC();
#else
#if ISA_HAS_DELAY_SLOT
bool branch_taken = inst->readNextNPC() !=
(inst->readNextPC() + sizeof(TheISA::MachInst));
@ -496,6 +492,10 @@ DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid)
} else {
toCommit->nextPC[tid] = inst->readNextNPC();
}
#else
toCommit->branchTaken[tid] = inst->readNextPC() !=
(inst->readPC() + sizeof(TheISA::MachInst));
toCommit->nextPC[tid] = inst->readNextPC();
#endif
toCommit->includeSquashInst[tid] = false;
@ -860,7 +860,7 @@ DefaultIEW<Impl>::sortInsts()
{
int insts_from_rename = fromRename->size;
#ifdef DEBUG
#if THE_ISA == ALPHA_ISA
#if !ISA_HAS_DELAY_SLOT
for (int i = 0; i < numThreads; i++)
assert(insts[i].empty());
#endif
@ -878,8 +878,7 @@ DefaultIEW<Impl>::emptyRenameInsts(unsigned tid)
"[sn:%i].\n", tid, bdelayDoneSeqNum[tid]);
while (!insts[tid].empty()) {
#if THE_ISA != ALPHA_ISA
#if ISA_HAS_DELAY_SLOT
if (insts[tid].front()->seqNum <= bdelayDoneSeqNum[tid]) {
DPRINTF(IEW, "[tid:%i]: Done removing, cannot remove instruction"
" that occurs at or before delay slot [sn:%i].\n",
@ -1316,12 +1315,12 @@ DefaultIEW<Impl>::executeInsts()
fetchRedirect[tid] = true;
DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
#if THE_ISA == ALPHA_ISA
DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
inst->nextPC);
#else
#if ISA_HAS_DELAY_SLOT
DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
inst->nextNPC);
#else
DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
inst->nextPC);
#endif
// If incorrect, then signal the ROB that it must be squashed.
squashDueToBranch(inst, tid);

6
src/cpu/o3/inst_queue_impl.hh
View file

@ -991,10 +991,10 @@ InstructionQueue<Impl>::squash(unsigned tid)
// Read instruction sequence number of last instruction out of the
// time buffer.
#if THE_ISA == ALPHA_ISA
squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum;
#else
#if ISA_HAS_DELAY_SLOT
squashedSeqNum[tid] = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
#else
squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum;
#endif
// Call doSquash if there are insts in the IQ

20
src/cpu/o3/rename_impl.hh
View file

@ -355,9 +355,7 @@ DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, unsigned tid)
// "insts[tid].clear();" or "skidBuffer[tid].clear()" since there is
// a possible delay slot inst for different architectures
// insts[tid].clear();
#if THE_ISA == ALPHA_ISA
insts[tid].clear();
#else
#if ISA_HAS_DELAY_SLOT
DPRINTF(Rename, "[tid:%i] Squashing incoming decode instructions until "
"[sn:%i].\n",tid, squash_seq_num);
ListIt ilist_it = insts[tid].begin();
@ -369,14 +367,14 @@ DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, unsigned tid)
}
ilist_it++;
}
#else
insts[tid].clear();
#endif
// Clear the skid buffer in case it has any data in it.
// See comments above.
// skidBuffer[tid].clear();
#if THE_ISA == ALPHA_ISA
skidBuffer[tid].clear();
#else
#if ISA_HAS_DELAY_SLOT
DPRINTF(Rename, "[tid:%i] Squashing incoming skidbuffer instructions "
"until [sn:%i].\n", tid, squash_seq_num);
ListIt slist_it = skidBuffer[tid].begin();
@ -388,6 +386,8 @@ DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, unsigned tid)
}
slist_it++;
}
#else
skidBuffer[tid].clear();
#endif
doSquash(squash_seq_num, tid);
}
@ -743,7 +743,7 @@ DefaultRename<Impl>::sortInsts()
{
int insts_from_decode = fromDecode->size;
#ifdef DEBUG
#if THE_ISA == ALPHA_ISA
#if !ISA_HAS_DELAY_SLOT
for (int i=0; i < numThreads; i++)
assert(insts[i].empty());
#endif
@ -1182,10 +1182,10 @@ DefaultRename<Impl>::checkSignalsAndUpdate(unsigned tid)
DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
"commit.\n", tid);
#if THE_ISA == ALPHA_ISA
InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum;
#else
#if ISA_HAS_DELAY_SLOT
InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
#else
InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum;
#endif
squash(squashed_seq_num, tid);

14
src/cpu/simple/base.cc
View file

@ -358,12 +358,12 @@ Fault
BaseSimpleCPU::setupFetchRequest(Request *req)
{
// set up memory request for instruction fetch
#if THE_ISA == ALPHA_ISA
DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p",thread->readPC(),
thread->readNextPC());
#else
#if ISA_HAS_DELAY_SLOT
DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",thread->readPC(),
thread->readNextPC(),thread->readNextNPC());
#else
DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p",thread->readPC(),
thread->readNextPC());
#endif
req->setVirt(0, thread->readPC() & ~3, sizeof(MachInst),
@ -450,12 +450,12 @@ BaseSimpleCPU::advancePC(Fault fault)
else {
// go to the next instruction
thread->setPC(thread->readNextPC());
#if THE_ISA == ALPHA_ISA
thread->setNextPC(thread->readNextPC() + sizeof(MachInst));
#else
#if ISA_HAS_DELAY_SLOT
thread->setNextPC(thread->readNextNPC());
thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
assert(thread->readNextPC() != thread->readNextNPC());
#else
thread->setNextPC(thread->readNextPC() + sizeof(MachInst));
#endif
}

2
tests/SConscript
View file

@ -207,7 +207,7 @@ if env['FULL_SYSTEM']:
'tsunami-simple-atomic-dual',
'tsunami-simple-timing-dual']
else:
configs += ['simple-atomic', 'simple-timing']
configs += ['simple-atomic', 'simple-timing', 'o3-timing']
cwd = os.getcwd()
os.chdir(str(Dir('.').srcdir))

52
tests/configs/o3-timing.py Normal file
View file

@ -0,0 +1,52 @@
# Copyright (c) 2006 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Steve Reinhardt
import m5
from m5.objects import *
m5.AddToPath('../configs/common')
from FullO3Config import *
class MyCache(BaseCache):
assoc = 2
block_size = 64
latency = 1
mshrs = 10
tgts_per_mshr = 5
cpu = DetailedO3CPU()
cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
MyCache(size = '2MB'))
cpu.mem = cpu.dcache
system = System(cpu = cpu,
physmem = PhysicalMemory(),
membus = Bus())
system.physmem.port = system.membus.port
cpu.connectMemPorts(system.membus)
root = Root(system = system)

4
tests/diff-out
View file

@ -398,8 +398,8 @@ if ($added_stats)
}
cleanup();
# Exit code is 0 if no stats error, 1 otherwise
$status = ($max_err_mag == 0.0) ? 0 : 1;
# Exit code is 0 if some stats found & no stats error, 1 otherwise
$status = ($#key_stats >= 0 && $max_err_mag == 0.0) ? 0 : 1;
exit $status;
sub cleanup

406
tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini Normal file
View file

@ -0,0 +1,406 @@
[root]
type=Root
children=system
checkpoint=
clock=1000000000000
max_tick=0
output_file=cout
progress_interval=0
[debug]
break_cycles=
[exetrace]
intel_format=false
pc_symbol=true
print_cpseq=false
print_cycle=true
print_data=true
print_effaddr=true
print_fetchseq=false
print_iregs=false
print_opclass=true
print_thread=true
speculative=true
trace_system=client
[serialize]
count=10
cycle=0
dir=cpt.%012d
period=0
[stats]
descriptions=true
dump_cycle=0
dump_period=0
dump_reset=false
ignore_events=
mysql_db=
mysql_host=
mysql_password=
mysql_user=
project_name=test
simulation_name=test
simulation_sample=0
text_compat=true
text_file=m5stats.txt
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
[system.cpu]
type=DerivO3CPU
children=dcache fuPool icache l2cache toL2Bus workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
LQEntries=32
RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
choiceCtrBits=2
choicePredictorSize=8192
clock=1
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
issueToExecuteDelay=1
issueWidth=8
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
mem=system.cpu.dcache
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
predType=tournament
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
squashWidth=8
system=system
trapLatency=13
wbDepth=1
wbWidth=8
workload=system.cpu.workload
[system.cpu.dcache]
type=BaseCache
adaptive_compression=false
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
do_copy=false
hash_delay=1
hit_latency=1
latency=1
lifo=false
max_miss_count=0
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=262144
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
[system.cpu.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList0
count=6
opList=system.cpu.fuPool.FUList0.opList0
[system.cpu.fuPool.FUList0.opList0]
type=OpDesc
issueLat=1
opClass=IntAlu
opLat=1
[system.cpu.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
issueLat=1
opClass=IntMult
opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
issueLat=19
opClass=IntDiv
opLat=20
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
issueLat=1
opClass=FloatCvt
opLat=2
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
issueLat=24
opClass=FloatSqrt
opLat=24
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList0
count=0
opList=system.cpu.fuPool.FUList4.opList0
[system.cpu.fuPool.FUList4.opList0]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList0
count=0
opList=system.cpu.fuPool.FUList5.opList0
[system.cpu.fuPool.FUList5.opList0]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList0 opList1
count=4
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
[system.cpu.fuPool.FUList6.opList0]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList6.opList1]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0
count=1
opList=system.cpu.fuPool.FUList7.opList0
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
issueLat=3
opClass=IprAccess
opLat=3
[system.cpu.icache]
type=BaseCache
adaptive_compression=false
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
do_copy=false
hash_delay=1
hit_latency=1
latency=1
lifo=false
max_miss_count=0
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=131072
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
[system.cpu.l2cache]
type=BaseCache
adaptive_compression=false
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
do_copy=false
hash_delay=1
hit_latency=1
latency=1
lifo=false
max_miss_count=0
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=2097152
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
[system.cpu.toL2Bus]
type=Bus
bus_id=0
[system.cpu.workload]
type=LiveProcess
cmd=hello
env=
executable=tests/test-progs/hello/bin/alpha/linux/hello
input=cin
output=cout
system=system
[system.membus]
type=Bus
bus_id=0
[system.physmem]
type=PhysicalMemory
file=
latency=1
range=0:134217727
[trace]
bufsize=0
dump_on_exit=false
file=cout
flags=
ignore=
start=0

403
tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out Normal file
View file

@ -0,0 +1,403 @@
[root]
type=Root
clock=1000000000000
max_tick=0
progress_interval=0
output_file=cout
[system.physmem]
type=PhysicalMemory
file=
range=[0,134217727]
latency=1
[system]
type=System
physmem=system.physmem
mem_mode=atomic
[system.membus]
type=Bus
bus_id=0
[system.cpu.workload]
type=LiveProcess
cmd=hello
executable=tests/test-progs/hello/bin/alpha/linux/hello
input=cin
output=cout
env=
system=system
[system.cpu.dcache]
type=BaseCache
size=262144
assoc=2
block_size=64
latency=1
mshrs=10
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
do_copy=false
protocol=null
trace_addr=0
hash_delay=1
repl=null
compressed_bus=false
store_compressed=false
adaptive_compression=false
compression_latency=0
block_size=64
max_miss_count=0
addr_range=[0,18446744073709551615]
split=false
split_size=0
lifo=false
two_queue=false
prefetch_miss=false
prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.fuPool.FUList0.opList0]
type=OpDesc
opClass=IntAlu
opLat=1
issueLat=1
[system.cpu.fuPool.FUList0]
type=FUDesc
opList=system.cpu.fuPool.FUList0.opList0
count=6
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
opClass=IntMult
opLat=3
issueLat=1
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
opClass=IntDiv
opLat=20
issueLat=19
[system.cpu.fuPool.FUList1]
type=FUDesc
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
count=2
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
opClass=FloatAdd
opLat=2
issueLat=1
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
opClass=FloatCmp
opLat=2
issueLat=1
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
opClass=FloatCvt
opLat=2
issueLat=1
[system.cpu.fuPool.FUList2]
type=FUDesc
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
count=4
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
opClass=FloatMult
opLat=4
issueLat=1
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
opClass=FloatDiv
opLat=12
issueLat=12
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
opClass=FloatSqrt
opLat=24
issueLat=24
[system.cpu.fuPool.FUList3]
type=FUDesc
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
count=2
[system.cpu.fuPool.FUList4.opList0]
type=OpDesc
opClass=MemRead
opLat=1
issueLat=1
[system.cpu.fuPool.FUList4]
type=FUDesc
opList=system.cpu.fuPool.FUList4.opList0
count=0
[system.cpu.fuPool.FUList5.opList0]
type=OpDesc
opClass=MemWrite
opLat=1
issueLat=1
[system.cpu.fuPool.FUList5]
type=FUDesc
opList=system.cpu.fuPool.FUList5.opList0
count=0
[system.cpu.fuPool.FUList6.opList0]
type=OpDesc
opClass=MemRead
opLat=1
issueLat=1
[system.cpu.fuPool.FUList6.opList1]
type=OpDesc
opClass=MemWrite
opLat=1
issueLat=1
[system.cpu.fuPool.FUList6]
type=FUDesc
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
count=4
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
opClass=IprAccess
opLat=3
issueLat=3
[system.cpu.fuPool.FUList7]
type=FUDesc
opList=system.cpu.fuPool.FUList7.opList0
count=1
[system.cpu.fuPool]
type=FUPool
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
[system.cpu]
type=DerivO3CPU
clock=1
numThreads=1
activity=0
workload=system.cpu.workload
mem=system.cpu.dcache
checker=null
max_insts_any_thread=0
max_insts_all_threads=0
max_loads_any_thread=0
max_loads_all_threads=0
cachePorts=200
decodeToFetchDelay=1
renameToFetchDelay=1
iewToFetchDelay=1
commitToFetchDelay=1
fetchWidth=8
renameToDecodeDelay=1
iewToDecodeDelay=1
commitToDecodeDelay=1
fetchToDecodeDelay=1
decodeWidth=8
iewToRenameDelay=1
commitToRenameDelay=1
decodeToRenameDelay=1
renameWidth=8
commitToIEWDelay=1
renameToIEWDelay=2
issueToExecuteDelay=1
dispatchWidth=8
issueWidth=8
wbWidth=8
wbDepth=1
fuPool=system.cpu.fuPool
iewToCommitDelay=1
renameToROBDelay=1
commitWidth=8
squashWidth=8
trapLatency=13
backComSize=5
forwardComSize=5
predType=tournament
localPredictorSize=2048
localCtrBits=2
localHistoryTableSize=2048
localHistoryBits=11
globalPredictorSize=8192
globalCtrBits=2
globalHistoryBits=13
choicePredictorSize=8192
choiceCtrBits=2
BTBEntries=4096
BTBTagSize=16
RASSize=16
LQEntries=32
SQEntries=32
LFSTSize=1024
SSITSize=1024
numPhysIntRegs=256
numPhysFloatRegs=256
numIQEntries=64
numROBEntries=192
smtNumFetchingThreads=1
smtFetchPolicy=SingleThread
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtIQPolicy=Partitioned
smtIQThreshold=100
smtROBPolicy=Partitioned
smtROBThreshold=100
smtCommitPolicy=RoundRobin
instShiftAmt=2
defer_registration=false
function_trace=false
function_trace_start=0
[system.cpu.icache]
type=BaseCache
size=131072
assoc=2
block_size=64
latency=1
mshrs=10
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
do_copy=false
protocol=null
trace_addr=0
hash_delay=1
repl=null
compressed_bus=false
store_compressed=false
adaptive_compression=false
compression_latency=0
block_size=64
max_miss_count=0
addr_range=[0,18446744073709551615]
split=false
split_size=0
lifo=false
two_queue=false
prefetch_miss=false
prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.l2cache]
type=BaseCache
size=2097152
assoc=2
block_size=64
latency=1
mshrs=10
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
do_copy=false
protocol=null
trace_addr=0
hash_delay=1
repl=null
compressed_bus=false
store_compressed=false
adaptive_compression=false
compression_latency=0
block_size=64
max_miss_count=0
addr_range=[0,18446744073709551615]
split=false
split_size=0
lifo=false
two_queue=false
prefetch_miss=false
prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.toL2Bus]
type=Bus
bus_id=0
[trace]
flags=
start=0
bufsize=0
file=cout
dump_on_exit=false
ignore=
[stats]
descriptions=true
project_name=test
simulation_name=test
simulation_sample=0
text_file=m5stats.txt
text_compat=true
mysql_db=
mysql_user=
mysql_password=
mysql_host=
events_start=-1
dump_reset=false
dump_cycle=0
dump_period=0
ignore_events=
[random]
seed=1
[exetrace]
speculative=true
print_cycle=true
print_opclass=true
print_thread=true
print_effaddr=true
print_data=true
print_iregs=false
print_fetchseq=false
print_cpseq=false
print_reg_delta=false
pc_symbol=true
intel_format=false
trace_system=client
[debug]
break_cycles=

1974
tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt Normal file
View file

File diff suppressed because it is too large Load diff

3
tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr Normal file
View file

@ -0,0 +1,3 @@
warn: Entering event queue @ 0. Starting simulation...
warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0

13
tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout Normal file
View file

@ -0,0 +1,13 @@
Hello world!
M5 Simulator System
Copyright (c) 2001-2006
The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 1 2006 16:10:44
M5 started Fri Sep 1 16:23:41 2006
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
Exiting @ tick 6870 because target called exit()

406
tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini Normal file
View file

@ -0,0 +1,406 @@
[root]
type=Root
children=system
checkpoint=
clock=1000000000000
max_tick=0
output_file=cout
progress_interval=0
[debug]
break_cycles=
[exetrace]
intel_format=false
pc_symbol=true
print_cpseq=false
print_cycle=true
print_data=true
print_effaddr=true
print_fetchseq=false
print_iregs=false
print_opclass=true
print_thread=true
speculative=true
trace_system=client
[serialize]
count=10
cycle=0
dir=cpt.%012d
period=0
[stats]
descriptions=true
dump_cycle=0
dump_period=0
dump_reset=false
ignore_events=
mysql_db=
mysql_host=
mysql_password=
mysql_user=
project_name=test
simulation_name=test
simulation_sample=0
text_compat=true
text_file=m5stats.txt
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
[system.cpu]
type=DerivO3CPU
children=dcache fuPool icache l2cache toL2Bus workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
LQEntries=32
RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
choiceCtrBits=2
choicePredictorSize=8192
clock=1
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
issueToExecuteDelay=1
issueWidth=8
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
mem=system.cpu.dcache
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
predType=tournament
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
squashWidth=8
system=system
trapLatency=13
wbDepth=1
wbWidth=8
workload=system.cpu.workload
[system.cpu.dcache]
type=BaseCache
adaptive_compression=false
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
do_copy=false
hash_delay=1
hit_latency=1
latency=1
lifo=false
max_miss_count=0
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=262144
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
[system.cpu.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList0
count=6
opList=system.cpu.fuPool.FUList0.opList0
[system.cpu.fuPool.FUList0.opList0]
type=OpDesc
issueLat=1
opClass=IntAlu
opLat=1
[system.cpu.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
issueLat=1
opClass=IntMult
opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
issueLat=19
opClass=IntDiv
opLat=20
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
issueLat=1
opClass=FloatCvt
opLat=2
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
issueLat=24
opClass=FloatSqrt
opLat=24
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList0
count=0
opList=system.cpu.fuPool.FUList4.opList0
[system.cpu.fuPool.FUList4.opList0]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList0
count=0
opList=system.cpu.fuPool.FUList5.opList0
[system.cpu.fuPool.FUList5.opList0]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList0 opList1
count=4
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
[system.cpu.fuPool.FUList6.opList0]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList6.opList1]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0
count=1
opList=system.cpu.fuPool.FUList7.opList0
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
issueLat=3
opClass=IprAccess
opLat=3
[system.cpu.icache]
type=BaseCache
adaptive_compression=false
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
do_copy=false
hash_delay=1
hit_latency=1
latency=1
lifo=false
max_miss_count=0
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=131072
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
[system.cpu.l2cache]
type=BaseCache
adaptive_compression=false
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
do_copy=false
hash_delay=1
hit_latency=1
latency=1
lifo=false
max_miss_count=0
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=2097152
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
[system.cpu.toL2Bus]
type=Bus
bus_id=0
[system.cpu.workload]
type=LiveProcess
cmd=hello
env=
executable=tests/test-progs/hello/bin/alpha/tru64/hello
input=cin
output=cout
system=system
[system.membus]
type=Bus
bus_id=0
[system.physmem]
type=PhysicalMemory
file=
latency=1
range=0:134217727
[trace]
bufsize=0
dump_on_exit=false
file=cout
flags=
ignore=
start=0

403
tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out Normal file
View file

@ -0,0 +1,403 @@
[root]
type=Root
clock=1000000000000
max_tick=0
progress_interval=0
output_file=cout
[system.physmem]
type=PhysicalMemory
file=
range=[0,134217727]
latency=1
[system]
type=System
physmem=system.physmem
mem_mode=atomic
[system.membus]
type=Bus
bus_id=0
[system.cpu.workload]
type=LiveProcess
cmd=hello
executable=tests/test-progs/hello/bin/alpha/tru64/hello
input=cin
output=cout
env=
system=system
[system.cpu.dcache]
type=BaseCache
size=262144
assoc=2
block_size=64
latency=1
mshrs=10
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
do_copy=false
protocol=null
trace_addr=0
hash_delay=1
repl=null
compressed_bus=false
store_compressed=false
adaptive_compression=false
compression_latency=0
block_size=64
max_miss_count=0
addr_range=[0,18446744073709551615]
split=false
split_size=0
lifo=false
two_queue=false
prefetch_miss=false
prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.fuPool.FUList0.opList0]
type=OpDesc
opClass=IntAlu
opLat=1
issueLat=1
[system.cpu.fuPool.FUList0]
type=FUDesc
opList=system.cpu.fuPool.FUList0.opList0
count=6
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
opClass=IntMult
opLat=3
issueLat=1
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
opClass=IntDiv
opLat=20
issueLat=19
[system.cpu.fuPool.FUList1]
type=FUDesc
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
count=2
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
opClass=FloatAdd
opLat=2
issueLat=1
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
opClass=FloatCmp
opLat=2
issueLat=1
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
opClass=FloatCvt
opLat=2
issueLat=1
[system.cpu.fuPool.FUList2]
type=FUDesc
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
count=4
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
opClass=FloatMult
opLat=4
issueLat=1
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
opClass=FloatDiv
opLat=12
issueLat=12
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
opClass=FloatSqrt
opLat=24
issueLat=24
[system.cpu.fuPool.FUList3]
type=FUDesc
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
count=2
[system.cpu.fuPool.FUList4.opList0]
type=OpDesc
opClass=MemRead
opLat=1
issueLat=1
[system.cpu.fuPool.FUList4]
type=FUDesc
opList=system.cpu.fuPool.FUList4.opList0
count=0
[system.cpu.fuPool.FUList5.opList0]
type=OpDesc
opClass=MemWrite
opLat=1
issueLat=1
[system.cpu.fuPool.FUList5]
type=FUDesc
opList=system.cpu.fuPool.FUList5.opList0
count=0
[system.cpu.fuPool.FUList6.opList0]
type=OpDesc
opClass=MemRead
opLat=1
issueLat=1
[system.cpu.fuPool.FUList6.opList1]
type=OpDesc
opClass=MemWrite
opLat=1
issueLat=1
[system.cpu.fuPool.FUList6]
type=FUDesc
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
count=4
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
opClass=IprAccess
opLat=3
issueLat=3
[system.cpu.fuPool.FUList7]
type=FUDesc
opList=system.cpu.fuPool.FUList7.opList0
count=1
[system.cpu.fuPool]
type=FUPool
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
[system.cpu]
type=DerivO3CPU
clock=1
numThreads=1
activity=0
workload=system.cpu.workload
mem=system.cpu.dcache
checker=null
max_insts_any_thread=0
max_insts_all_threads=0
max_loads_any_thread=0
max_loads_all_threads=0
cachePorts=200
decodeToFetchDelay=1
renameToFetchDelay=1
iewToFetchDelay=1
commitToFetchDelay=1
fetchWidth=8
renameToDecodeDelay=1
iewToDecodeDelay=1
commitToDecodeDelay=1
fetchToDecodeDelay=1
decodeWidth=8
iewToRenameDelay=1
commitToRenameDelay=1
decodeToRenameDelay=1
renameWidth=8
commitToIEWDelay=1
renameToIEWDelay=2
issueToExecuteDelay=1
dispatchWidth=8
issueWidth=8
wbWidth=8
wbDepth=1
fuPool=system.cpu.fuPool
iewToCommitDelay=1
renameToROBDelay=1
commitWidth=8
squashWidth=8
trapLatency=13
backComSize=5
forwardComSize=5
predType=tournament
localPredictorSize=2048
localCtrBits=2
localHistoryTableSize=2048
localHistoryBits=11
globalPredictorSize=8192
globalCtrBits=2
globalHistoryBits=13
choicePredictorSize=8192
choiceCtrBits=2
BTBEntries=4096
BTBTagSize=16
RASSize=16
LQEntries=32
SQEntries=32
LFSTSize=1024
SSITSize=1024
numPhysIntRegs=256
numPhysFloatRegs=256
numIQEntries=64
numROBEntries=192
smtNumFetchingThreads=1
smtFetchPolicy=SingleThread
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtIQPolicy=Partitioned
smtIQThreshold=100
smtROBPolicy=Partitioned
smtROBThreshold=100
smtCommitPolicy=RoundRobin
instShiftAmt=2
defer_registration=false
function_trace=false
function_trace_start=0
[system.cpu.icache]
type=BaseCache
size=131072
assoc=2
block_size=64
latency=1
mshrs=10
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
do_copy=false
protocol=null
trace_addr=0
hash_delay=1
repl=null
compressed_bus=false
store_compressed=false
adaptive_compression=false
compression_latency=0
block_size=64
max_miss_count=0
addr_range=[0,18446744073709551615]
split=false
split_size=0
lifo=false
two_queue=false
prefetch_miss=false
prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.l2cache]
type=BaseCache
size=2097152
assoc=2
block_size=64
latency=1
mshrs=10
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
do_copy=false
protocol=null
trace_addr=0
hash_delay=1
repl=null
compressed_bus=false
store_compressed=false
adaptive_compression=false
compression_latency=0
block_size=64
max_miss_count=0
addr_range=[0,18446744073709551615]
split=false
split_size=0
lifo=false
two_queue=false
prefetch_miss=false
prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.toL2Bus]
type=Bus
bus_id=0
[trace]
flags=
start=0
bufsize=0
file=cout
dump_on_exit=false
ignore=
[stats]
descriptions=true
project_name=test
simulation_name=test
simulation_sample=0
text_file=m5stats.txt
text_compat=true
mysql_db=
mysql_user=
mysql_password=
mysql_host=
events_start=-1
dump_reset=false
dump_cycle=0
dump_period=0
ignore_events=
[random]
seed=1
[exetrace]
speculative=true
print_cycle=true
print_opclass=true
print_thread=true
print_effaddr=true
print_data=true
print_iregs=false
print_fetchseq=false
print_cpseq=false
print_reg_delta=false
pc_symbol=true
intel_format=false
trace_system=client
[debug]
break_cycles=

1972
tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt Normal file
View file

File diff suppressed because it is too large Load diff

4
tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr Normal file
View file

@ -0,0 +1,4 @@
warn: Entering event queue @ 0. Starting simulation...
warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff8
warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...)

13
tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout Normal file
View file

@ -0,0 +1,13 @@
Hello world!
M5 Simulator System
Copyright (c) 2001-2006
The Regents of The University of Michigan
All Rights Reserved
M5 compiled Sep 1 2006 16:10:44
M5 started Fri Sep 1 16:23:45 2006
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing
Exiting @ tick 2886 because target called exit()

67
util/regress
View file

@ -32,39 +32,20 @@ import os
import optparse
import datetime
#
# Regression invocation:
#
# regress \
# --workdir poolfs \
# --scons-opts 'BATCH=yes USE_MYSQL=no -j 30 -Q' \
# --recurse
progname = os.path.basename(sys.argv[0])
optparser = optparse.OptionParser()
optparser.add_option('-v', '--verbose', dest='verbose', action='store_true',
default=False,
help='echo commands before executing')
optparser.add_option('--scratch', dest='scratch', action='store_true',
default=False,
help='rebuld from scratch')
optparser.add_option('--builds', dest='builds',
default='ALPHA_SE,ALPHA_FS,MIPS_SE,SPARC_SE',
help='comma-separated list of builds to test')
optparser.add_option('--variants', dest='variants',
default='opt',
help='comma-separated list of build variants to test')
optparser.add_option('--workdir', dest='workdir',
help='directory for checked-out source trees')
optparser.add_option('--scons-opts', dest='scons_opts', default='',
help='scons options')
optparser.add_option('--no-pull', dest='pull', action='store_false',
default=True,
help="don't pull changes from repository")
optparser.add_option('--recurse', dest='recurse', action='store_true',
default=False,
help='call recursively to get summary up front')
(options, tests) = optparser.parse_args()
@ -73,9 +54,6 @@ optparser.add_option('--recurse', dest='recurse', action='store_true',
builds = options.builds.split(',')
variants = options.variants.split(',')
# Repositories to clone/update
repos = ['m5']
# Call os.system() and raise exception if return status is non-zero
def system(cmd):
if options.verbose:
@ -93,56 +71,11 @@ def shellquote(s):
s = "'%s'" % s
return s
# The '--recurse' option invokes scons once to perform any necessary
# rebuilds/test runs with the (possibly verbose) output placed in a
# log file, then (if the buld was successful) returns scons to print a
# summary of the results.
if options.recurse:
sys.argv.remove('--recurse') # avoid infinite recursion...
timestr = datetime.datetime.now().isoformat('-')[:19]
logfile = '%s-%s' % (progname, timestr)
# quote args for shell
qargs = [shellquote(a) for a in sys.argv]
# always run the sub-job in verbose mode
qargs.append('-v')
cmd = '%s > %s 2>&1' % (' '.join(qargs), logfile)
try:
system(cmd)
except OSError, exc:
print "Error: recursive invocation failed, aborting."
print exc
print "======================="
os.system('cat %s' % logfile)
sys.exit(1)
# recursive call succeeded... re-run to generate summary
# don't *re*-build from scratch now
options.scratch = False
# no need to re-pull since the recursive call shoudl have done that
options.pull = False
print "Recursive invocation successful, see %s for output." % logfile
try:
if options.workdir:
if options.verbose:
print 'cd', options.workdir
os.chdir(options.workdir)
if options.scratch:
for dir in repos:
system('rm -rf %s' % dir)
system('bk clone /bk/%s' % dir)
elif options.pull:
for dir in repos:
system('cd %s; bk pull' % dir)
if not tests:
print "No tests specified."
sys.exit(1)
if options.verbose:
print 'cd m5'
os.chdir('m5')
if 'all' in tests:
targets = ['build/%s/tests/%s' % (build, variant)
for build in builds