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Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem

Browse source 
into  zizzer.eecs.umich.edu:/z/stever/bk/newmem-head

--HG--
extra : convert_revision : 54c63c9a8c7146bb45ecfa9a177ab0bda9541d1b
This commit is contained in:
Steve Reinhardt 2006-09-01 12:59:48 -04:00
commit 30c93db065
14 changed files with 117 additions and 107 deletions
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5
src/arch/alpha/isa_traits.hh
View file

@ -42,7 +42,6 @@ class StaticInstPtr;
namespace AlphaISA
{
using namespace LittleEndianGuest;
// These enumerate all the registers for dependence tracking.
@ -60,12 +59,14 @@ namespace AlphaISA
StaticInstPtr decodeInst(ExtMachInst);
// Alpha Does NOT have a delay slot
#define ISA_HAS_DELAY_SLOT 0
const Addr PageShift = 13;
const Addr PageBytes = ULL(1) << PageShift;
const Addr PageMask = ~(PageBytes - 1);
const Addr PageOffset = PageBytes - 1;
#if FULL_SYSTEM
////////////////////////////////////////////////////////////////////////

3
src/arch/mips/isa_traits.hh
View file

@ -47,6 +47,9 @@ namespace MipsISA
StaticInstPtr decodeInst(ExtMachInst);
// MIPS DOES a delay slot
#define ISA_HAS_DELAY_SLOT 1
const Addr PageShift = 13;
const Addr PageBytes = ULL(1) << PageShift;
const Addr PageMask = ~(PageBytes - 1);

3
src/arch/sparc/isa_traits.hh
View file

@ -57,6 +57,9 @@ namespace SparcISA
//This makes sure the big endian versions of certain functions are used.
using namespace BigEndianGuest;
// Alpha Does NOT have a delay slot
#define ISA_HAS_DELAY_SLOT 1
//TODO this needs to be a SPARC Noop
// Alpha UNOP (ldq_u r31,0(r0))
const MachInst NoopMachInst = 0x2ffe0000;

12
src/cpu/base_dyn_inst.hh
View file

@ -291,18 +291,18 @@ class BaseDynInst : public FastAlloc, public RefCounted
/** Returns whether the instruction was predicted taken or not. */
bool predTaken()
#if THE_ISA == ALPHA_ISA
{ return predPC != (PC + sizeof(MachInst)); }
#else
#if ISA_HAS_DELAY_SLOT
{ return predPC != (nextPC + sizeof(MachInst)); }
#else
{ return predPC != (PC + sizeof(MachInst)); }
#endif
/** Returns whether the instruction mispredicted. */
bool mispredicted()
#if THE_ISA == ALPHA_ISA
{ return predPC != nextPC; }
#else
#if ISA_HAS_DELAY_SLOT
{ return predPC != nextNPC; }
#else
{ return predPC != nextPC; }
#endif
//
// Instruction types. Forward checks to StaticInst object.

12
src/cpu/o3/bpred_unit_impl.hh
View file

@ -29,6 +29,7 @@
*/
#include "arch/types.hh"
#include "arch/isa_traits.hh"
#include "base/trace.hh"
#include "base/traceflags.hh"
#include "cpu/o3/bpred_unit.hh"
@ -197,10 +198,10 @@ BPredUnit<Impl>::predict(DynInstPtr &inst, Addr &PC, unsigned tid)
++BTBLookups;
if (inst->isCall()) {
#if THE_ISA == ALPHA_ISA
Addr ras_pc = PC + sizeof(MachInst); // Next PC
#else
#if ISA_HAS_DELAY_SLOT
Addr ras_pc = PC + (2 * sizeof(MachInst)); // Next Next PC
#else
Addr ras_pc = PC + sizeof(MachInst); // Next PC
#endif
RAS[tid].push(ras_pc);
@ -209,8 +210,8 @@ BPredUnit<Impl>::predict(DynInstPtr &inst, Addr &PC, unsigned tid)
predict_record.wasCall = true;
DPRINTF(Fetch, "BranchPred: [tid:%i]: Instruction %#x was a call"
", adding %#x to the RAS.\n",
tid, inst->readPC(), ras_pc);
", adding %#x to the RAS index: %i.\n",
tid, inst->readPC(), ras_pc, RAS[tid].topIdx());
}
if (BTB.valid(PC, tid)) {
@ -283,7 +284,6 @@ BPredUnit<Impl>::squash(const InstSeqNum &squashed_sn, unsigned tid)
RAS[tid].restore(pred_hist.front().RASIndex,
pred_hist.front().RASTarget);
} else if (pred_hist.front().wasCall) {
DPRINTF(Fetch, "BranchPred: [tid:%i]: Removing speculative entry "
"added to the RAS.\n",tid);

36
src/cpu/o3/commit_impl.hh
View file

@ -722,7 +722,7 @@ DefaultCommit<Impl>::commit()
// then use one older sequence number.
InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
#if THE_ISA != ALPHA_ISA
#if ISA_HAS_DELAY_SLOT
InstSeqNum bdelay_done_seq_num;
bool squash_bdelay_slot;
@ -748,7 +748,7 @@ DefaultCommit<Impl>::commit()
if (fromIEW->includeSquashInst[tid] == true) {
squashed_inst--;
#if THE_ISA != ALPHA_ISA
#if ISA_HAS_DELAY_SLOT
bdelay_done_seq_num--;
#endif
}
@ -756,13 +756,13 @@ DefaultCommit<Impl>::commit()
// number as the youngest instruction in the ROB.
youngestSeqNum[tid] = squashed_inst;
#if THE_ISA == ALPHA_ISA
rob->squash(squashed_inst, tid);
toIEW->commitInfo[tid].squashDelaySlot = true;
#else
#if ISA_HAS_DELAY_SLOT
rob->squash(bdelay_done_seq_num, tid);
toIEW->commitInfo[tid].squashDelaySlot = squash_bdelay_slot;
toIEW->commitInfo[tid].bdelayDoneSeqNum = bdelay_done_seq_num;
#else
rob->squash(squashed_inst, tid);
toIEW->commitInfo[tid].squashDelaySlot = true;
#endif
changedROBNumEntries[tid] = true;
@ -800,7 +800,7 @@ DefaultCommit<Impl>::commit()
// Try to commit any instructions.
commitInsts();
} else {
#if THE_ISA != ALPHA_ISA
#if ISA_HAS_DELAY_SLOT
skidInsert();
#endif
}
@ -906,11 +906,11 @@ DefaultCommit<Impl>::commitInsts()
}
PC[tid] = nextPC[tid];
#if THE_ISA == ALPHA_ISA
nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst);
#else
#if ISA_HAS_DELAY_SLOT
nextPC[tid] = nextNPC[tid];
nextNPC[tid] = nextNPC[tid] + sizeof(TheISA::MachInst);
#else
nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst);
#endif
#if FULL_SYSTEM
@ -1115,10 +1115,7 @@ DefaultCommit<Impl>::getInsts()
{
DPRINTF(Commit, "Getting instructions from Rename stage.\n");
#if THE_ISA == ALPHA_ISA
// Read any renamed instructions and place them into the ROB.
int insts_to_process = std::min((int)renameWidth, fromRename->size);
#else
#if ISA_HAS_DELAY_SLOT
// Read any renamed instructions and place them into the ROB.
int insts_to_process = std::min((int)renameWidth,
(int)(fromRename->size + skidBuffer.size()));
@ -1127,15 +1124,16 @@ DefaultCommit<Impl>::getInsts()
DPRINTF(Commit, "%i insts available to process. Rename Insts:%i "
"SkidBuffer Insts:%i\n", insts_to_process, fromRename->size,
skidBuffer.size());
#else
// Read any renamed instructions and place them into the ROB.
int insts_to_process = std::min((int)renameWidth, fromRename->size);
#endif
for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
DynInstPtr inst;
#if THE_ISA == ALPHA_ISA
inst = fromRename->insts[inst_num];
#else
#if ISA_HAS_DELAY_SLOT
// Get insts from skidBuffer or from Rename
if (skidBuffer.size() > 0) {
DPRINTF(Commit, "Grabbing skidbuffer inst.\n");
@ -1145,6 +1143,8 @@ DefaultCommit<Impl>::getInsts()
DPRINTF(Commit, "Grabbing rename inst.\n");
inst = fromRename->insts[rename_idx++];
}
#else
inst = fromRename->insts[inst_num];
#endif
int tid = inst->threadNumber;
@ -1167,7 +1167,7 @@ DefaultCommit<Impl>::getInsts()
}
}
#if THE_ISA != ALPHA_ISA
#if ISA_HAS_DELAY_SLOT
if (rename_idx < fromRename->size) {
DPRINTF(Commit,"Placing Rename Insts into skidBuffer.\n");

10
src/cpu/o3/cpu.cc
View file

@ -181,7 +181,6 @@ FullO3CPU<Impl>::FullO3CPU(Params *params)
params->activity),
globalSeqNum(1),
#if FULL_SYSTEM
system(params->system),
physmem(system->physmem),
@ -322,6 +321,11 @@ FullO3CPU<Impl>::FullO3CPU(Params *params)
lastActivatedCycle = -1;
// Give renameMap & rename stage access to the freeList;
//for (int i=0; i < numThreads; i++) {
//globalSeqNum[i] = 1;
//}
contextSwitch = false;
}
@ -627,7 +631,7 @@ FullO3CPU<Impl>::insertThread(unsigned tid)
//Set PC/NPC/NNPC
setPC(src_tc->readPC(), tid);
setNextPC(src_tc->readNextPC(), tid);
#if THE_ISA != ALPHA_ISA
#if ISA_HAS_DELAY_SLOT
setNextNPC(src_tc->readNextNPC(), tid);
#endif
@ -1197,7 +1201,7 @@ FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid,
while (inst_it != end_it) {
assert(!instList.empty());
#if THE_ISA != ALPHA_ISA
#if ISA_HAS_DELAY_SLOT
if(!squash_delay_slot &&
delay_slot_seq_num >= (*inst_it)->seqNum) {
break;

2
src/cpu/o3/cpu.hh
View file

@ -598,7 +598,7 @@ class FullO3CPU : public BaseO3CPU
}
/** The global sequence number counter. */
InstSeqNum globalSeqNum;
InstSeqNum globalSeqNum;//[Impl::MaxThreads];
/** Pointer to the checker, which can dynamically verify
* instruction results at run time. This can be set to NULL if it

18
src/cpu/o3/decode_impl.hh
View file

@ -282,12 +282,7 @@ DefaultDecode<Impl>::squash(DynInstPtr &inst, unsigned tid)
toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum;
toFetch->decodeInfo[tid].squash = true;
toFetch->decodeInfo[tid].nextPC = inst->branchTarget();
#if THE_ISA == ALPHA_ISA
toFetch->decodeInfo[tid].branchTaken =
inst->readNextPC() != (inst->readPC() + sizeof(TheISA::MachInst));
InstSeqNum squash_seq_num = inst->seqNum;
#else
#if ISA_HAS_DELAY_SLOT
toFetch->decodeInfo[tid].branchTaken = inst->readNextNPC() !=
(inst->readNextPC() + sizeof(TheISA::MachInst));
@ -295,6 +290,11 @@ DefaultDecode<Impl>::squash(DynInstPtr &inst, unsigned tid)
squashAfterDelaySlot[tid] = false;
InstSeqNum squash_seq_num = bdelayDoneSeqNum[tid];
#else
toFetch->decodeInfo[tid].branchTaken =
inst->readNextPC() != (inst->readPC() + sizeof(TheISA::MachInst));
InstSeqNum squash_seq_num = inst->seqNum;
#endif
// Might have to tell fetch to unblock.
@ -317,7 +317,7 @@ DefaultDecode<Impl>::squash(DynInstPtr &inst, unsigned tid)
// insts in them.
while (!insts[tid].empty()) {
#if THE_ISA != ALPHA_ISA
#if ISA_HAS_DELAY_SLOT
if (insts[tid].front()->seqNum <= squash_seq_num) {
DPRINTF(Decode, "[tid:%i]: Cannot remove incoming decode "
"instructions before delay slot [sn:%i]. %i insts"
@ -331,7 +331,7 @@ DefaultDecode<Impl>::squash(DynInstPtr &inst, unsigned tid)
while (!skidBuffer[tid].empty()) {
#if THE_ISA != ALPHA_ISA
#if ISA_HAS_DELAY_SLOT
if (skidBuffer[tid].front()->seqNum <= squash_seq_num) {
DPRINTF(Decode, "[tid:%i]: Cannot remove skidBuffer "
"instructions before delay slot [sn:%i]. %i insts"
@ -765,7 +765,7 @@ DefaultDecode<Impl>::decodeInsts(unsigned tid)
// Might want to set some sort of boolean and just do
// a check at the end
#if THE_ISA == ALPHA_ISA
#if !ISA_HAS_DELAY_SLOT
squash(inst, inst->threadNumber);
inst->setPredTarg(inst->branchTarget());
break;

52
src/cpu/o3/fetch_impl.hh
View file

@ -339,7 +339,7 @@ DefaultFetch<Impl>::initStage()
for (int tid = 0; tid < numThreads; tid++) {
PC[tid] = cpu->readPC(tid);
nextPC[tid] = cpu->readNextPC(tid);
#if THE_ISA != ALPHA_ISA
#if ISA_HAS_DELAY_SLOT
nextNPC[tid] = cpu->readNextNPC(tid);
#endif
}
@ -429,7 +429,7 @@ DefaultFetch<Impl>::takeOverFrom()
stalls[i].commit = 0;
PC[i] = cpu->readPC(i);
nextPC[i] = cpu->readNextPC(i);
#if THE_ISA != ALPHA_ISA
#if ISA_HAS_DELAY_SLOT
nextNPC[i] = cpu->readNextNPC(i);
delaySlotInfo[i].branchSeqNum = -1;
delaySlotInfo[i].numInsts = 0;
@ -492,22 +492,20 @@ DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC,
bool predict_taken;
if (!inst->isControl()) {
#if THE_ISA == ALPHA_ISA
next_PC = next_PC + instSize;
inst->setPredTarg(next_PC);
#else
#if ISA_HAS_DELAY_SLOT
Addr cur_PC = next_PC;
next_PC = cur_PC + instSize; //next_NPC;
next_NPC = cur_PC + (2 * instSize);//next_NPC + instSize;
inst->setPredTarg(next_NPC);
#else
next_PC = next_PC + instSize;
inst->setPredTarg(next_PC);
#endif
return false;
}
int tid = inst->threadNumber;
#if THE_ISA == ALPHA_ISA
predict_taken = branchPred.predict(inst, next_PC, tid);
#else
#if ISA_HAS_DELAY_SLOT
Addr pred_PC = next_PC;
predict_taken = branchPred.predict(inst, pred_PC, tid);
@ -539,6 +537,8 @@ DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC,
next_NPC = next_NPC + instSize;
}
#else
predict_taken = branchPred.predict(inst, next_PC, tid);
#endif
++fetchedBranches;
@ -692,7 +692,7 @@ DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC,
doSquash(new_PC, tid);
#if THE_ISA != ALPHA_ISA
#if ISA_HAS_DELAY_SLOT
if (seq_num <= delaySlotInfo[tid].branchSeqNum) {
delaySlotInfo[tid].numInsts = 0;
delaySlotInfo[tid].targetAddr = 0;
@ -780,10 +780,7 @@ DefaultFetch<Impl>::squash(const Addr &new_PC, const InstSeqNum &seq_num,
doSquash(new_PC, tid);
#if THE_ISA == ALPHA_ISA
// Tell the CPU to remove any instructions that are not in the ROB.
cpu->removeInstsNotInROB(tid, true, 0);
#else
#if ISA_HAS_DELAY_SLOT
if (seq_num <= delaySlotInfo[tid].branchSeqNum) {
delaySlotInfo[tid].numInsts = 0;
delaySlotInfo[tid].targetAddr = 0;
@ -792,6 +789,9 @@ DefaultFetch<Impl>::squash(const Addr &new_PC, const InstSeqNum &seq_num,
// Tell the CPU to remove any instructions that are not in the ROB.
cpu->removeInstsNotInROB(tid, squash_delay_slot, seq_num);
#else
// Tell the CPU to remove any instructions that are not in the ROB.
cpu->removeInstsNotInROB(tid, true, 0);
#endif
}
@ -901,10 +901,10 @@ DefaultFetch<Impl>::checkSignalsAndUpdate(unsigned tid)
DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
"from commit.\n",tid);
#if THE_ISA == ALPHA_ISA
InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].doneSeqNum;
#if ISA_HAS_DELAY_SLOT
InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
#else
InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].doneSeqNum;
#endif
// In any case, squash.
squash(fromCommit->commitInfo[tid].nextPC,
@ -958,10 +958,10 @@ DefaultFetch<Impl>::checkSignalsAndUpdate(unsigned tid)
if (fetchStatus[tid] != Squashing) {
#if THE_ISA == ALPHA_ISA
InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].doneSeqNum;
#else
#if ISA_HAS_DELAY_SLOT
InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].bdelayDoneSeqNum;
#else
InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].doneSeqNum;
#endif
// Squash unless we're already squashing
squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
@ -1162,7 +1162,7 @@ DefaultFetch<Impl>::fetch(bool &status_change)
offset += instSize;
#if THE_ISA != ALPHA_ISA
#if ISA_HAS_DELAY_SLOT
if (predicted_branch) {
delaySlotInfo[tid].branchSeqNum = inst_seq;
@ -1205,11 +1205,7 @@ DefaultFetch<Impl>::fetch(bool &status_change)
// Now that fetching is completed, update the PC to signify what the next
// cycle will be.
if (fault == NoFault) {
#if THE_ISA == ALPHA_ISA
DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n",tid, next_PC);
PC[tid] = next_PC;
nextPC[tid] = next_PC + instSize;
#else
#if ISA_HAS_DELAY_SLOT
if (delaySlotInfo[tid].targetReady &&
delaySlotInfo[tid].numInsts == 0) {
// Set PC to target
@ -1225,6 +1221,10 @@ DefaultFetch<Impl>::fetch(bool &status_change)
}
DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n", tid, PC[tid]);
#else
DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n",tid, next_PC);
PC[tid] = next_PC;
nextPC[tid] = next_PC + instSize;
#endif
} else {
// We shouldn't be in an icache miss and also have a fault (an ITB

31
src/cpu/o3/iew_impl.hh
View file

@ -427,10 +427,10 @@ DefaultIEW<Impl>::squash(unsigned tid)
instQueue.squash(tid);
// Tell the LDSTQ to start squashing.
#if THE_ISA == ALPHA_ISA
ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
#else
#if ISA_HAS_DELAY_SLOT
ldstQueue.squash(fromCommit->commitInfo[tid].bdelayDoneSeqNum, tid);
#else
ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
#endif
updatedQueues = true;
@ -439,7 +439,7 @@ DefaultIEW<Impl>::squash(unsigned tid)
tid, fromCommit->commitInfo[tid].bdelayDoneSeqNum);
while (!skidBuffer[tid].empty()) {
#if THE_ISA != ALPHA_ISA
#if ISA_HAS_DELAY_SLOT
if (skidBuffer[tid].front()->seqNum <=
fromCommit->commitInfo[tid].bdelayDoneSeqNum) {
DPRINTF(IEW, "[tid:%i]: Cannot remove skidbuffer instructions "
@ -479,11 +479,7 @@ DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid)
toCommit->mispredPC[tid] = inst->readPC();
toCommit->branchMispredict[tid] = true;
#if THE_ISA == ALPHA_ISA
toCommit->branchTaken[tid] = inst->readNextPC() !=
(inst->readPC() + sizeof(TheISA::MachInst));
toCommit->nextPC[tid] = inst->readNextPC();
#else
#if ISA_HAS_DELAY_SLOT
bool branch_taken = inst->readNextNPC() !=
(inst->readNextPC() + sizeof(TheISA::MachInst));
@ -496,6 +492,10 @@ DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid)
} else {
toCommit->nextPC[tid] = inst->readNextNPC();
}
#else
toCommit->branchTaken[tid] = inst->readNextPC() !=
(inst->readPC() + sizeof(TheISA::MachInst));
toCommit->nextPC[tid] = inst->readNextPC();
#endif
toCommit->includeSquashInst[tid] = false;
@ -860,7 +860,7 @@ DefaultIEW<Impl>::sortInsts()
{
int insts_from_rename = fromRename->size;
#ifdef DEBUG
#if THE_ISA == ALPHA_ISA
#if !ISA_HAS_DELAY_SLOT
for (int i = 0; i < numThreads; i++)
assert(insts[i].empty());
#endif
@ -878,8 +878,7 @@ DefaultIEW<Impl>::emptyRenameInsts(unsigned tid)
"[sn:%i].\n", tid, bdelayDoneSeqNum[tid]);
while (!insts[tid].empty()) {
#if THE_ISA != ALPHA_ISA
#if ISA_HAS_DELAY_SLOT
if (insts[tid].front()->seqNum <= bdelayDoneSeqNum[tid]) {
DPRINTF(IEW, "[tid:%i]: Done removing, cannot remove instruction"
" that occurs at or before delay slot [sn:%i].\n",
@ -1316,12 +1315,12 @@ DefaultIEW<Impl>::executeInsts()
fetchRedirect[tid] = true;
DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
#if THE_ISA == ALPHA_ISA
DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
inst->nextPC);
#else
#if ISA_HAS_DELAY_SLOT
DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
inst->nextNPC);
#else
DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
inst->nextPC);
#endif
// If incorrect, then signal the ROB that it must be squashed.
squashDueToBranch(inst, tid);

6
src/cpu/o3/inst_queue_impl.hh
View file

@ -991,10 +991,10 @@ InstructionQueue<Impl>::squash(unsigned tid)
// Read instruction sequence number of last instruction out of the
// time buffer.
#if THE_ISA == ALPHA_ISA
squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum;
#else
#if ISA_HAS_DELAY_SLOT
squashedSeqNum[tid] = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
#else
squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum;
#endif
// Call doSquash if there are insts in the IQ

20
src/cpu/o3/rename_impl.hh
View file

@ -355,9 +355,7 @@ DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, unsigned tid)
// "insts[tid].clear();" or "skidBuffer[tid].clear()" since there is
// a possible delay slot inst for different architectures
// insts[tid].clear();
#if THE_ISA == ALPHA_ISA
insts[tid].clear();
#else
#if ISA_HAS_DELAY_SLOT
DPRINTF(Rename, "[tid:%i] Squashing incoming decode instructions until "
"[sn:%i].\n",tid, squash_seq_num);
ListIt ilist_it = insts[tid].begin();
@ -369,14 +367,14 @@ DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, unsigned tid)
}
ilist_it++;
}
#else
insts[tid].clear();
#endif
// Clear the skid buffer in case it has any data in it.
// See comments above.
// skidBuffer[tid].clear();
#if THE_ISA == ALPHA_ISA
skidBuffer[tid].clear();
#else
#if ISA_HAS_DELAY_SLOT
DPRINTF(Rename, "[tid:%i] Squashing incoming skidbuffer instructions "
"until [sn:%i].\n", tid, squash_seq_num);
ListIt slist_it = skidBuffer[tid].begin();
@ -388,6 +386,8 @@ DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, unsigned tid)
}
slist_it++;
}
#else
skidBuffer[tid].clear();
#endif
doSquash(squash_seq_num, tid);
}
@ -743,7 +743,7 @@ DefaultRename<Impl>::sortInsts()
{
int insts_from_decode = fromDecode->size;
#ifdef DEBUG
#if THE_ISA == ALPHA_ISA
#if !ISA_HAS_DELAY_SLOT
for (int i=0; i < numThreads; i++)
assert(insts[i].empty());
#endif
@ -1182,10 +1182,10 @@ DefaultRename<Impl>::checkSignalsAndUpdate(unsigned tid)
DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
"commit.\n", tid);
#if THE_ISA == ALPHA_ISA
InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum;
#else
#if ISA_HAS_DELAY_SLOT
InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
#else
InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum;
#endif
squash(squashed_seq_num, tid);

14
src/cpu/simple/base.cc
View file

@ -358,12 +358,12 @@ Fault
BaseSimpleCPU::setupFetchRequest(Request *req)
{
// set up memory request for instruction fetch
#if THE_ISA == ALPHA_ISA
DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p",thread->readPC(),
thread->readNextPC());
#else
#if ISA_HAS_DELAY_SLOT
DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",thread->readPC(),
thread->readNextPC(),thread->readNextNPC());
#else
DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p",thread->readPC(),
thread->readNextPC());
#endif
req->setVirt(0, thread->readPC() & ~3, sizeof(MachInst),
@ -450,12 +450,12 @@ BaseSimpleCPU::advancePC(Fault fault)
else {
// go to the next instruction
thread->setPC(thread->readNextPC());
#if THE_ISA == ALPHA_ISA
thread->setNextPC(thread->readNextPC() + sizeof(MachInst));
#else
#if ISA_HAS_DELAY_SLOT
thread->setNextPC(thread->readNextNPC());
thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
assert(thread->readNextPC() != thread->readNextNPC());
#else
thread->setNextPC(thread->readNextPC() + sizeof(MachInst));
#endif
}