gem5/src
Kevin Lim dd5e2cd959 More proper handling of the ports.
src/cpu/simple_thread.cc:
    Fix up port handling to share code.
src/cpu/thread_state.cc:
    Separate code off into a function.
src/cpu/thread_state.hh:
    Make a separate function that will get the CPU's memory's functional port.

--HG--
extra : convert_revision : 96a9bb3c5e4b9ba5511678c0fd17f0017c8cd312
2006-11-02 14:58:31 -05:00
..
arch Use ISA specific makeExtMI. 2006-11-02 13:11:38 -05:00
base Merge zizzer.eecs.umich.edu:/bk/newmem 2006-10-27 02:34:26 -04:00
cpu More proper handling of the ports. 2006-11-02 14:58:31 -05:00
dev Merge ktlim@zizzer:/bk/newmem 2006-10-31 14:37:19 -05:00
doxygen Fix up doxygen. 2006-08-14 19:25:07 -04:00
kern Merge zizzer.eecs.umich.edu:/bk/newmem 2006-10-23 09:44:58 -04:00
mem Merge ktlim@zizzer:/bk/newmem 2006-10-31 14:37:19 -05:00
python Merge zizzer:/bk/newmem 2006-10-24 12:59:19 -04:00
sim remove connectAll() and connect() code since it isn't used anymore. (The python does it all) 2006-10-31 13:23:49 -05:00
unittest Merge iceaxe.:/Volumes/work/research/m5/head 2006-06-11 22:01:34 -04:00
Doxyfile Fix up doxygen. 2006-08-14 19:25:07 -04:00
SConscript remove intel nic from SConscript 2006-10-28 13:16:53 -04:00