Implemented the SPARC fill and spill handlers.
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
Added a function to do normal SPARC trap processing, and implemented the spill and fill faults for SE
src/arch/sparc/process.cc:
src/arch/sparc/process.hh:
Added fill and spill handlers which are stuffed into the processes address space. The location of these handlers are stored in fillStart and spillStart.
--HG--
extra : convert_revision : 59adb96570cce86f373fbc2c3e4c05abe1742d3b
This commit is contained in:
Gabe Black
parent
1b1495930c
commit
e2eef8859b
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@ -29,15 +29,22 @@
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* Kevin Lim
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*/
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#include <algorithm>
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#include "arch/sparc/faults.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/base.hh"
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#include "arch/sparc/isa_traits.hh"
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#include "arch/sparc/process.hh"
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#include "base/bitfield.hh"
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#include "base/trace.hh"
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#include "cpu/base.hh"
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#include "cpu/thread_context.hh"
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#if !FULL_SYSTEM
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#include "sim/process.hh"
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#include "mem/page_table.hh"
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#include "sim/process.hh"
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#endif
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using namespace std;
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namespace SparcISA
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{
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@ -229,6 +236,129 @@ FaultPriority PageTableFault::_priority = 0;
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FaultStat PageTableFault::_count;
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#endif
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/**
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* This sets everything up for a normal trap except for actually jumping to
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* the handler. It will need to be expanded to include the state machine in
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* the manual. Right now it assumes that traps will always be to the
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* privileged level.
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*/
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void doNormalFault(ThreadContext *tc, TrapType tt)
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{
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uint64_t TL = tc->readMiscReg(MISCREG_TL);
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uint64_t TSTATE = tc->readMiscReg(MISCREG_TSTATE);
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uint64_t PSTATE = tc->readMiscReg(MISCREG_PSTATE);
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uint64_t HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
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uint64_t CCR = tc->readMiscReg(MISCREG_CCR);
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uint64_t ASI = tc->readMiscReg(MISCREG_ASI);
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uint64_t CWP = tc->readMiscReg(MISCREG_CWP);
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uint64_t CANSAVE = tc->readMiscReg(MISCREG_CANSAVE);
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uint64_t GL = tc->readMiscReg(MISCREG_GL);
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uint64_t PC = tc->readPC();
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uint64_t NPC = tc->readNextPC();
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//Increment the trap level
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TL++;
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tc->setMiscReg(MISCREG_TL, TL);
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//Save off state
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//set TSTATE.gl to gl
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replaceBits(TSTATE, 42, 40, GL);
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//set TSTATE.ccr to ccr
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replaceBits(TSTATE, 39, 32, CCR);
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//set TSTATE.asi to asi
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replaceBits(TSTATE, 31, 24, ASI);
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//set TSTATE.pstate to pstate
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replaceBits(TSTATE, 20, 8, PSTATE);
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//set TSTATE.cwp to cwp
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replaceBits(TSTATE, 4, 0, CWP);
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//Write back TSTATE
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tc->setMiscReg(MISCREG_TSTATE, TSTATE);
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//set TPC to PC
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tc->setMiscReg(MISCREG_TPC, PC);
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//set TNPC to NPC
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tc->setMiscReg(MISCREG_TNPC, NPC);
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//set HTSTATE.hpstate to hpstate
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tc->setMiscReg(MISCREG_HTSTATE, HPSTATE);
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//TT = trap type;
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tc->setMiscReg(MISCREG_TT, tt);
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//Update the global register level
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if(1/*We're delivering the trap in priveleged mode*/)
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tc->setMiscReg(MISCREG_GL, max<int>(GL+1, MaxGL));
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else
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tc->setMiscReg(MISCREG_GL, max<int>(GL+1, MaxPGL));
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//PSTATE.mm is unchanged
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//PSTATE.pef = whether or not an fpu is present
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//XXX We'll say there's one present, even though there aren't
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//implementations for a decent number of the instructions
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PSTATE |= (1 << 4);
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//PSTATE.am = 0
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PSTATE &= ~(1 << 3);
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if(1/*We're delivering the trap in priveleged mode*/)
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{
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//PSTATE.priv = 1
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PSTATE |= (1 << 2);
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//PSTATE.cle = PSTATE.tle
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replaceBits(PSTATE, 9, 9, PSTATE >> 8);
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}
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else
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{
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//PSTATE.priv = 0
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PSTATE &= ~(1 << 2);
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//PSTATE.cle = 0
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PSTATE &= ~(1 << 9);
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}
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//PSTATE.ie = 0
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PSTATE &= ~(1 << 1);
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//PSTATE.tle is unchanged
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//PSTATE.tct = 0
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//XXX Where exactly is this field?
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tc->setMiscReg(MISCREG_PSTATE, PSTATE);
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if(0/*We're delivering the trap in hyperprivileged mode*/)
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{
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//HPSTATE.red = 0
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HPSTATE &= ~(1 << 5);
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//HPSTATE.hpriv = 1
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HPSTATE |= (1 << 2);
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//HPSTATE.ibe = 0
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HPSTATE &= ~(1 << 10);
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//HPSTATE.tlz is unchanged
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tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
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}
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bool changedCWP = true;
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if(tt == 0x24)
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{
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warn("Incrementing the CWP by 1\n");
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CWP++;
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}
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else if(0x80 <= tt && tt <= 0xbf)
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{
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warn("Incrementing the CWP by %d\n", CANSAVE + 2);
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CWP += (CANSAVE + 2);
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}
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else if(0xc0 <= tt && tt <= 0xff)
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{
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warn("Decrementing the CWP by 1\n");
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CWP--;
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}
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else
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changedCWP = false;
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if(changedCWP)
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{
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CWP = (CWP + NWindows) % NWindows;
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tc->setMiscRegWithEffect(MISCREG_CWP, CWP);
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}
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}
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#if FULL_SYSTEM
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void SparcFault::invoke(ThreadContext * tc)
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@ -263,6 +393,42 @@ void TrapInstruction::invoke(ThreadContext * tc)
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// Should be handled in ISA.
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}
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void SpillNNormal::invoke(ThreadContext *tc)
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{
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warn("I'm in a spill trap\n");
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doNormalFault(tc, trapType());
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Process *p = tc->getProcessPtr();
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//This will only work in faults from a SparcLiveProcess
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SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
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assert(lp);
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//Then adjust the PC and NPC
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Addr spillStart = lp->readSpillStart();
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tc->setPC(spillStart);
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tc->setNextPC(spillStart + sizeof(MachInst));
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tc->setNextNPC(spillStart + 2*sizeof(MachInst));
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}
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void FillNNormal::invoke(ThreadContext *tc)
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{
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warn("I'm in a fill trap\n");
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doNormalFault(tc, trapType());
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Process * p = tc->getProcessPtr();
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//This will only work in faults from a SparcLiveProcess
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SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
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assert(lp);
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//The adjust the PC and NPC
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Addr fillStart = lp->readFillStart();
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tc->setPC(fillStart);
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tc->setNextPC(fillStart + sizeof(MachInst));
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tc->setNextNPC(fillStart + 2*sizeof(MachInst));
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}
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void PageTableFault::invoke(ThreadContext *tc)
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{
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Process *p = tc->getProcessPtr();
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@ -282,6 +448,7 @@ void PageTableFault::invoke(ThreadContext *tc)
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FaultBase::invoke(tc);
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}
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}
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#endif
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} // namespace SparcISA
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@ -39,8 +39,8 @@
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namespace SparcISA
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{
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typedef const uint32_t TrapType;
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typedef const uint32_t FaultPriority;
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typedef uint32_t TrapType;
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typedef uint32_t FaultPriority;
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class SparcFault : public FaultBase
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{
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FaultName name() {return _name;}
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FaultPriority priority() {return _priority;}
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FaultStat & countStat() {return _count;}
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void invoke(ThreadContext * tc);
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};
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class SpillNOther : public EnumeratedFault
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@ -577,6 +578,7 @@ class FillNNormal : public EnumeratedFault
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FaultName name() {return _name;}
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FaultPriority priority() {return _priority;}
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FaultStat & countStat() {return _count;}
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void invoke(ThreadContext * tc);
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};
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class FillNOther : public EnumeratedFault
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// Set pointer for next thread stack. Reserve 8M for main stack.
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next_thread_stack_base = stack_base - (8 * 1024 * 1024);
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//Initialize these to 0s
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fillStart = 0;
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spillStart = 0;
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}
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void
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@ -88,15 +92,19 @@ SparcLiveProcess::startup()
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*/
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//No windows contain info from other programs
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threadContexts[0]->setMiscRegWithEffect(MISCREG_OTHERWIN, 0);
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threadContexts[0]->setMiscReg(MISCREG_OTHERWIN, 0);
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//There are no windows to pop
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threadContexts[0]->setMiscRegWithEffect(MISCREG_CANRESTORE, 0);
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threadContexts[0]->setMiscReg(MISCREG_CANRESTORE, 0);
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//All windows are available to save into
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threadContexts[0]->setMiscRegWithEffect(MISCREG_CANSAVE, NWindows - 2);
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threadContexts[0]->setMiscReg(MISCREG_CANSAVE, NWindows - 2);
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//All windows are "clean"
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threadContexts[0]->setMiscRegWithEffect(MISCREG_CLEANWIN, NWindows);
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threadContexts[0]->setMiscReg(MISCREG_CLEANWIN, NWindows);
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//Start with register window 0
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threadContexts[0]->setMiscRegWithEffect(MISCREG_CWP, 0);
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threadContexts[0]->setMiscReg(MISCREG_CWP, 0);
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//Always use spill and fill traps 0
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threadContexts[0]->setMiscReg(MISCREG_WSTATE, 0);
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//Set the trap level to 0
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threadContexts[0]->setMiscReg(MISCREG_TL, 0);
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}
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m5_auxv_t buildAuxVect(int64_t type, int64_t val)
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@ -107,6 +115,83 @@ m5_auxv_t buildAuxVect(int64_t type, int64_t val)
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return result;
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}
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//We only use 19 instructions for the trap handlers, but there would be
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//space for 32 in a real SPARC trap table.
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const int numFillInsts = 32;
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const int numSpillInsts = 32;
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MachInst fillHandler[numFillInsts] =
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{
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htog(0x87802018), //wr %g0, ASI_AIUP, %asi
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htog(0xe0dba7ff), //ldxa [%sp + BIAS + (0*8)] %asi, %l0
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htog(0xe2dba807), //ldxa [%sp + BIAS + (1*8)] %asi, %l1
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htog(0xe4dba80f), //ldxa [%sp + BIAS + (2*8)] %asi, %l2
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htog(0xe6dba817), //ldxa [%sp + BIAS + (3*8)] %asi, %l3
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htog(0xe8dba81f), //ldxa [%sp + BIAS + (4*8)] %asi, %l4
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htog(0xeadba827), //ldxa [%sp + BIAS + (5*8)] %asi, %l5
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htog(0xecdba82f), //ldxa [%sp + BIAS + (6*8)] %asi, %l6
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htog(0xeedba837), //ldxa [%sp + BIAS + (7*8)] %asi, %l7
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htog(0xf0dba83f), //ldxa [%sp + BIAS + (8*8)] %asi, %i0
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htog(0xf2dba847), //ldxa [%sp + BIAS + (9*8)] %asi, %i1
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htog(0xf4dba84f), //ldxa [%sp + BIAS + (10*8)] %asi, %i2
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htog(0xf6dba857), //ldxa [%sp + BIAS + (11*8)] %asi, %i3
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htog(0xf8dba85f), //ldxa [%sp + BIAS + (12*8)] %asi, %i4
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htog(0xfadba867), //ldxa [%sp + BIAS + (13*8)] %asi, %i5
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htog(0xfcdba86f), //ldxa [%sp + BIAS + (14*8)] %asi, %i6
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htog(0xfedba877), //ldxa [%sp + BIAS + (15*8)] %asi, %i7
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htog(0x83880000), //restored
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htog(0x83F00000), //retry
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htog(0x00000000), //illtrap
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htog(0x00000000), //illtrap
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htog(0x00000000), //illtrap
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htog(0x00000000), //illtrap
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htog(0x00000000), //illtrap
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htog(0x00000000), //illtrap
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htog(0x00000000), //illtrap
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htog(0x00000000), //illtrap
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htog(0x00000000), //illtrap
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htog(0x00000000), //illtrap
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htog(0x00000000), //illtrap
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htog(0x00000000), //illtrap
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htog(0x00000000) //illtrap
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};
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MachInst spillHandler[numSpillInsts] =
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{
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htog(0x87802018), //wr %g0, ASI_AIUP, %asi
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htog(0xe0f3a7ff), //stxa %l0, [%sp + BIAS + (0*8)] %asi
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htog(0xe2f3a807), //stxa %l1, [%sp + BIAS + (1*8)] %asi
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htog(0xe4f3a80f), //stxa %l2, [%sp + BIAS + (2*8)] %asi
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htog(0xe6f3a817), //stxa %l3, [%sp + BIAS + (3*8)] %asi
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htog(0xe8f3a81f), //stxa %l4, [%sp + BIAS + (4*8)] %asi
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htog(0xeaf3a827), //stxa %l5, [%sp + BIAS + (5*8)] %asi
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htog(0xecf3a82f), //stxa %l6, [%sp + BIAS + (6*8)] %asi
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htog(0xeef3a837), //stxa %l7, [%sp + BIAS + (7*8)] %asi
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htog(0xf0f3a83f), //stxa %i0, [%sp + BIAS + (8*8)] %asi
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htog(0xf2f3a847), //stxa %i1, [%sp + BIAS + (9*8)] %asi
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htog(0xf4f3a84f), //stxa %i2, [%sp + BIAS + (10*8)] %asi
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htog(0xf6f3a857), //stxa %i3, [%sp + BIAS + (11*8)] %asi
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htog(0xf8f3a85f), //stxa %i4, [%sp + BIAS + (12*8)] %asi
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htog(0xfaf3a867), //stxa %i5, [%sp + BIAS + (13*8)] %asi
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htog(0xfcf3a86f), //stxa %i6, [%sp + BIAS + (14*8)] %asi
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htog(0xfef3a877), //stxa %i7, [%sp + BIAS + (15*8)] %asi
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htog(0x81880000), //saved
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htog(0x83F00000), //retry
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htog(0x00000000), //illtrap
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htog(0x00000000), //illtrap
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htog(0x00000000), //illtrap
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htog(0x00000000), //illtrap
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htog(0x00000000), //illtrap
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htog(0x00000000), //illtrap
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htog(0x00000000), //illtrap
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htog(0x00000000), //illtrap
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htog(0x00000000), //illtrap
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htog(0x00000000), //illtrap
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htog(0x00000000), //illtrap
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htog(0x00000000), //illtrap
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htog(0x00000000) //illtrap
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};
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void
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SparcLiveProcess::argsInit(int intSize, int pageSize)
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{
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@ -317,6 +402,17 @@ SparcLiveProcess::argsInit(int intSize, int pageSize)
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initVirtMem->writeBlob(argc_base, (uint8_t*)&guestArgc, intSize);
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//Stuff the trap handlers into the processes address space.
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//Since the stack grows down and is the highest area in the processes
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//address space, we can put stuff above it and stay out of the way.
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int fillSize = sizeof(MachInst) * numFillInsts;
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int spillSize = sizeof(MachInst) * numSpillInsts;
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fillStart = stack_base;
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spillStart = fillStart + fillSize;
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initVirtMem->writeBlob(fillStart, (uint8_t*)fillHandler, fillSize);
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initVirtMem->writeBlob(spillStart, (uint8_t*)spillHandler, spillSize);
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//Set up the thread context to start running the process
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threadContexts[0]->setIntReg(ArgumentReg0, argc);
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threadContexts[0]->setIntReg(ArgumentReg1, argv_array_base);
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threadContexts[0]->setIntReg(StackPointerReg, stack_min - StackBias);
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@ -55,6 +55,9 @@ class SparcLiveProcess : public LiveProcess
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static const Addr StackBias = 2047;
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//The locations of the fill and spill handlers
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Addr fillStart, spillStart;
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std::vector<m5_auxv_t> auxv;
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SparcLiveProcess(const std::string &nm, ObjectFile *objFile,
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@ -71,6 +74,12 @@ class SparcLiveProcess : public LiveProcess
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void argsInit(int intSize, int pageSize);
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Addr readFillStart()
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{ return fillStart; }
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Addr readSpillStart()
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{ return spillStart; }
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};
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#endif // __SPARC_PROCESS_HH__
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Loading…
Reference in a new issue