Fixed up exetrace.cc to deal with microcode, and to made floating point register numbers correlate to the numbers used in SPARC in m5 and statetrace.
src/cpu/exetrace.cc:
Fixed up to deal with microcode, and to make floating point register numbers correlate to the numbers used in SPARC.
util/statetrace/arch/tracechild_sparc.cc:
util/statetrace/arch/tracechild_sparc.hh:
Make floating point register numbers correlate to the numbers used in SPARC.
--HG--
extra : convert_revision : 878897292f696092453cf61d6eac2d1c407ca13b
This commit is contained in:
Gabe Black
parent
849d5e2efb
commit
bb2ab310eb
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@ -60,61 +60,66 @@ Trace::InstRecord::dump(ostream &outs)
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if (flags[PRINT_REG_DELTA])
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{
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#if THE_ISA == SPARC_ISA
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static uint64_t regs[32] = {
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0};
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static uint64_t ccr = 0;
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static uint64_t y = 0;
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static uint64_t floats[32];
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uint64_t newVal;
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static const char * prefixes[4] = {"G", "O", "L", "I"};
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//Don't print what happens for each micro-op, just print out
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//once at the last op, and for regular instructions.
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if(!staticInst->isMicroOp() || staticInst->isLastMicroOp())
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{
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static uint64_t regs[32] = {
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0};
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static uint64_t ccr = 0;
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static uint64_t y = 0;
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static uint64_t floats[32];
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uint64_t newVal;
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static const char * prefixes[4] = {"G", "O", "L", "I"};
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char buf[256];
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sprintf(buf, "PC = 0x%016llx", thread->readNextPC());
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outs << buf;
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sprintf(buf, " NPC = 0x%016llx", thread->readNextNPC());
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outs << buf;
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newVal = thread->readMiscReg(SparcISA::MISCREG_CCR);
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if(newVal != ccr)
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{
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sprintf(buf, " CCR = 0x%016llx", newVal);
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char buf[256];
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sprintf(buf, "PC = 0x%016llx", thread->readNextPC());
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outs << buf;
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ccr = newVal;
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}
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newVal = thread->readMiscReg(SparcISA::MISCREG_Y);
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if(newVal != y)
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{
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sprintf(buf, " Y = 0x%016llx", newVal);
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sprintf(buf, " NPC = 0x%016llx", thread->readNextNPC());
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outs << buf;
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y = newVal;
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}
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for(int y = 0; y < 4; y++)
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{
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for(int x = 0; x < 8; x++)
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newVal = thread->readMiscReg(SparcISA::MISCREG_CCR);
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if(newVal != ccr)
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{
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int index = x + 8 * y;
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newVal = thread->readIntReg(index);
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if(regs[index] != newVal)
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sprintf(buf, " CCR = 0x%016llx", newVal);
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outs << buf;
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ccr = newVal;
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}
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newVal = thread->readMiscReg(SparcISA::MISCREG_Y);
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if(newVal != y)
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{
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sprintf(buf, " Y = 0x%016llx", newVal);
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outs << buf;
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y = newVal;
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}
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for(int y = 0; y < 4; y++)
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{
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for(int x = 0; x < 8; x++)
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{
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sprintf(buf, " %s%d = 0x%016llx", prefixes[y], x, newVal);
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outs << buf;
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regs[index] = newVal;
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int index = x + 8 * y;
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newVal = thread->readIntReg(index);
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if(regs[index] != newVal)
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{
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sprintf(buf, " %s%d = 0x%016llx", prefixes[y], x, newVal);
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outs << buf;
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regs[index] = newVal;
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}
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}
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}
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}
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for(int y = 0; y < 32; y++)
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{
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newVal = thread->readFloatRegBits(2 * y, 64);
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if(floats[y] != newVal)
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for(int y = 0; y < 32; y++)
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{
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sprintf(buf, " F%d = 0x%016llx", y, newVal);
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outs << buf;
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floats[y] = newVal;
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newVal = thread->readFloatRegBits(2 * y, 64);
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if(floats[y] != newVal)
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{
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sprintf(buf, " F%d = 0x%016llx", 2 * y, newVal);
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outs << buf;
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floats[y] = newVal;
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}
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}
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outs << endl;
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}
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outs << endl;
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#endif
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}
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else if (flags[INTEL_FORMAT]) {
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@ -47,10 +47,10 @@ string SparcTraceChild::regNames[numregs] = {
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//Input registers
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"i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7",
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//Floating point
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"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
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"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
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"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
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"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
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"f0", "f2", "f4", "f6", "f8", "f10", "f12", "f14",
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"f16", "f18", "f20", "f22", "f24", "f26", "f28", "f30",
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"f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46",
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"f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62",
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//Miscelaneous
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"fsr", "fprs", "pc", "npc", "y", "cwp", "pstate", "asi", "ccr"};
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@ -98,37 +98,37 @@ int64_t getRegs(regs & myregs, fpu & myfpu,
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case SparcTraceChild::I7: return inputs[7];
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//Floating point
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case SparcTraceChild::F0: return myfpu.f_fpstatus.fpu_fr[0];
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case SparcTraceChild::F1: return myfpu.f_fpstatus.fpu_fr[1];
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case SparcTraceChild::F2: return myfpu.f_fpstatus.fpu_fr[2];
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case SparcTraceChild::F3: return myfpu.f_fpstatus.fpu_fr[3];
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case SparcTraceChild::F4: return myfpu.f_fpstatus.fpu_fr[4];
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case SparcTraceChild::F5: return myfpu.f_fpstatus.fpu_fr[5];
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case SparcTraceChild::F6: return myfpu.f_fpstatus.fpu_fr[6];
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case SparcTraceChild::F7: return myfpu.f_fpstatus.fpu_fr[7];
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case SparcTraceChild::F8: return myfpu.f_fpstatus.fpu_fr[8];
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case SparcTraceChild::F9: return myfpu.f_fpstatus.fpu_fr[9];
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case SparcTraceChild::F10: return myfpu.f_fpstatus.fpu_fr[10];
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case SparcTraceChild::F11: return myfpu.f_fpstatus.fpu_fr[11];
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case SparcTraceChild::F12: return myfpu.f_fpstatus.fpu_fr[12];
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case SparcTraceChild::F13: return myfpu.f_fpstatus.fpu_fr[13];
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case SparcTraceChild::F14: return myfpu.f_fpstatus.fpu_fr[14];
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case SparcTraceChild::F15: return myfpu.f_fpstatus.fpu_fr[15];
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case SparcTraceChild::F16: return myfpu.f_fpstatus.fpu_fr[16];
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case SparcTraceChild::F17: return myfpu.f_fpstatus.fpu_fr[17];
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case SparcTraceChild::F18: return myfpu.f_fpstatus.fpu_fr[18];
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case SparcTraceChild::F19: return myfpu.f_fpstatus.fpu_fr[19];
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case SparcTraceChild::F20: return myfpu.f_fpstatus.fpu_fr[20];
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case SparcTraceChild::F21: return myfpu.f_fpstatus.fpu_fr[21];
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case SparcTraceChild::F22: return myfpu.f_fpstatus.fpu_fr[22];
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case SparcTraceChild::F23: return myfpu.f_fpstatus.fpu_fr[23];
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case SparcTraceChild::F24: return myfpu.f_fpstatus.fpu_fr[24];
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case SparcTraceChild::F25: return myfpu.f_fpstatus.fpu_fr[25];
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case SparcTraceChild::F26: return myfpu.f_fpstatus.fpu_fr[26];
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case SparcTraceChild::F27: return myfpu.f_fpstatus.fpu_fr[27];
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case SparcTraceChild::F28: return myfpu.f_fpstatus.fpu_fr[28];
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case SparcTraceChild::F29: return myfpu.f_fpstatus.fpu_fr[29];
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case SparcTraceChild::F30: return myfpu.f_fpstatus.fpu_fr[30];
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case SparcTraceChild::F31: return myfpu.f_fpstatus.fpu_fr[31];
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case SparcTraceChild::F2: return myfpu.f_fpstatus.fpu_fr[1];
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case SparcTraceChild::F4: return myfpu.f_fpstatus.fpu_fr[2];
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case SparcTraceChild::F6: return myfpu.f_fpstatus.fpu_fr[3];
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case SparcTraceChild::F8: return myfpu.f_fpstatus.fpu_fr[4];
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case SparcTraceChild::F10: return myfpu.f_fpstatus.fpu_fr[5];
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case SparcTraceChild::F12: return myfpu.f_fpstatus.fpu_fr[6];
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case SparcTraceChild::F14: return myfpu.f_fpstatus.fpu_fr[7];
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case SparcTraceChild::F16: return myfpu.f_fpstatus.fpu_fr[8];
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case SparcTraceChild::F18: return myfpu.f_fpstatus.fpu_fr[9];
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case SparcTraceChild::F20: return myfpu.f_fpstatus.fpu_fr[10];
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case SparcTraceChild::F22: return myfpu.f_fpstatus.fpu_fr[11];
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case SparcTraceChild::F24: return myfpu.f_fpstatus.fpu_fr[12];
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case SparcTraceChild::F26: return myfpu.f_fpstatus.fpu_fr[13];
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case SparcTraceChild::F28: return myfpu.f_fpstatus.fpu_fr[14];
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case SparcTraceChild::F30: return myfpu.f_fpstatus.fpu_fr[15];
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case SparcTraceChild::F32: return myfpu.f_fpstatus.fpu_fr[16];
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case SparcTraceChild::F34: return myfpu.f_fpstatus.fpu_fr[17];
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case SparcTraceChild::F36: return myfpu.f_fpstatus.fpu_fr[18];
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case SparcTraceChild::F38: return myfpu.f_fpstatus.fpu_fr[19];
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case SparcTraceChild::F40: return myfpu.f_fpstatus.fpu_fr[20];
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case SparcTraceChild::F42: return myfpu.f_fpstatus.fpu_fr[21];
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case SparcTraceChild::F44: return myfpu.f_fpstatus.fpu_fr[22];
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case SparcTraceChild::F46: return myfpu.f_fpstatus.fpu_fr[23];
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case SparcTraceChild::F48: return myfpu.f_fpstatus.fpu_fr[24];
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case SparcTraceChild::F50: return myfpu.f_fpstatus.fpu_fr[25];
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case SparcTraceChild::F52: return myfpu.f_fpstatus.fpu_fr[26];
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case SparcTraceChild::F54: return myfpu.f_fpstatus.fpu_fr[27];
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case SparcTraceChild::F56: return myfpu.f_fpstatus.fpu_fr[28];
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case SparcTraceChild::F58: return myfpu.f_fpstatus.fpu_fr[29];
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case SparcTraceChild::F60: return myfpu.f_fpstatus.fpu_fr[30];
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case SparcTraceChild::F62: return myfpu.f_fpstatus.fpu_fr[31];
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//Miscelaneous
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case SparcTraceChild::FSR: return myfpu.f_fpstatus.Fpu_fsr;
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case SparcTraceChild::FPRS: return myregs.r_fprs;
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@ -57,10 +57,10 @@ public:
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//Input registers
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I0, I1, I2, I3, I4, I5, I6, I7,
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//Floating point
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F0, F1, F2, F3, F4, F5, F6, F7,
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F8, F9, F10, F11, F12, F13, F14, F15,
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F16, F17, F18, F19, F20, F21, F22, F23,
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F24, F25, F26, F27, F28, F29, F30, F31,
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F0, F2, F4, F6, F8, F10, F12, F14,
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F16, F18, F20, F22, F24, F26, F28, F30,
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F32, F34, F36, F38, F40, F42, F44, F46,
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F48, F50, F52, F54, F56, F58, F60, F62,
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//Miscelaneous
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FSR, FPRS, PC, NPC, Y, CWP, PSTATE, ASI, CCR,
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numregs
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