Fix how upgrades work.
Remove some dead code. src/mem/cache/cache_impl.hh: Upgrades don't need a response. Moved satisfied check into bus so removed some dead code. src/mem/cache/coherence/coherence_protocol.cc: src/mem/packet.hh: Upgrades don't require a response --HG-- extra : convert_revision : dee0440ff19ba4c9e51bf9a47a5b0991265cfc1d
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src/mem/cache/cache_impl.hh
vendored
8
src/mem/cache/cache_impl.hh
vendored
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@ -63,9 +63,8 @@ doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
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if (pkt->isWrite() && (pkt->req->isLocked())) {
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pkt->req->setScResult(1);
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}
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if (!(pkt->flags & SATISFIED)) {
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access(pkt);
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}
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access(pkt);
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}
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else
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{
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@ -204,9 +203,8 @@ Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
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pkt->getAddr() & (((ULL(1))<<48)-1),
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pkt->getAddr() & ~((Addr)blkSize - 1));
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//@todo Should this return latency have the hit latency in it?
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// respond(pkt,curTick+lat);
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pkt->flags |= SATISFIED;
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//Invalidates/Upgrades need no response if they get the bus
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// return MA_HIT; //@todo, return values
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return true;
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}
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@ -271,7 +271,7 @@ CoherenceProtocol::CoherenceProtocol(const string &name,
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}
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Packet::Command writeToSharedCmd = doUpgrades ? Packet::UpgradeReq : Packet::ReadExReq;
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Packet::Command writeToSharedResp = doUpgrades ? Packet::UpgradeResp : Packet::ReadExResp;
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Packet::Command writeToSharedResp = doUpgrades ? Packet::UpgradeReq : Packet::ReadExResp;
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//@todo add in hardware prefetch to this list
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if (protocol == "msi") {
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@ -194,8 +194,7 @@ class Packet
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HardPFResp = IsRead | IsResponse | IsHWPrefetch | NeedsResponse,
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InvalidateReq = IsInvalidate | IsRequest,
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WriteInvalidateReq = IsWrite | IsInvalidate | IsRequest,
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UpgradeReq = IsInvalidate | IsRequest | NeedsResponse,
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UpgradeResp = IsInvalidate | IsResponse | NeedsResponse,
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UpgradeReq = IsInvalidate | IsRequest
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ReadExReq = IsRead | IsInvalidate | IsRequest | NeedsResponse,
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ReadExResp = IsRead | IsInvalidate | IsResponse | NeedsResponse
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};
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