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delete pcifake, tsunamifake. Combine BadAddr/IsaFake into one

Browse source 
src/SConscript:
    remove pcifake and tsunami fake from sconscript
src/dev/isa_fake.cc:
src/dev/isa_fake.hh:
    combine badaddr and isa fake into one
src/python/m5/objects/Pci.py:
    remove pcifake
src/python/m5/objects/Tsunami.py:
    make badaddr derive from isafake

--HG--
extra : convert_revision : 91470db60aa1de6b85827304e27bd3414cc9d8d1
This commit is contained in:
Ali Saidi 2006-11-06 16:24:25 -05:00
parent 84e07f3a51
commit bf3223d7ce
5 changed files with 65 additions and 117 deletions
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2
src/SConscript
View file

@ -227,7 +227,6 @@ full_system_sources = Split('''
dev/ns_gige.cc
dev/pciconfigall.cc
dev/pcidev.cc
dev/pcifake.cc
dev/pktfifo.cc
dev/platform.cc
dev/simconsole.cc
@ -235,7 +234,6 @@ full_system_sources = Split('''
dev/tsunami.cc
dev/tsunami_cchip.cc
dev/tsunami_io.cc
dev/tsunami_fake.cc
dev/tsunami_pchip.cc
dev/uart.cc

137
src/dev/isa_fake.cc
View file

@ -25,18 +25,13 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Miguel Serrano
* Ali Saidi
* Authors: Ali Saidi
*/
/** @file
* Isa Fake Device implementation
*/
#include <deque>
#include <string>
#include <vector>
#include "base/trace.hh"
#include "dev/isa_fake.hh"
#include "mem/packet.hh"
@ -49,74 +44,67 @@ using namespace std;
IsaFake::IsaFake(Params *p)
: BasicPioDevice(p)
{
pioSize = p->pio_size;
}
if (!params()->retBadAddr)
pioSize = p->pio_size;
Tick
IsaFake::read(PacketPtr pkt)
{
assert(pkt->result == Packet::Unknown);
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt->getAddr(), pkt->getSize());
switch (pkt->getSize()) {
case sizeof(uint64_t):
pkt->set(0xFFFFFFFFFFFFFFFFULL);
break;
case sizeof(uint32_t):
pkt->set((uint32_t)0xFFFFFFFF);
break;
case sizeof(uint16_t):
pkt->set((uint16_t)0xFFFF);
break;
case sizeof(uint8_t):
pkt->set((uint8_t)0xFF);
break;
default:
panic("invalid access size(?) for PCI configspace!\n");
}
pkt->result = Packet::Success;
return pioDelay;
}
Tick
IsaFake::write(PacketPtr pkt)
{
DPRINTF(Tsunami, "write - va=%#x size=%d \n", pkt->getAddr(), pkt->getSize());
pkt->result = Packet::Success;
return pioDelay;
}
BadAddr::BadAddr(Params *p)
: BasicPioDevice(p)
{
memset(&retData, p->retData, sizeof(retData));
}
void
BadAddr::init()
IsaFake::init()
{
// Only init this device if it's connected to anything.
if (pioPort)
PioDevice::init();
}
Tick
BadAddr::read(PacketPtr pkt)
IsaFake::read(PacketPtr pkt)
{
assert(pkt->result == Packet::Unknown);
DPRINTF(Tsunami, "read to bad address va=%#x size=%d\n",
pkt->getAddr(), pkt->getSize());
pkt->result = Packet::BadAddress;
if (params()->retBadAddr) {
DPRINTF(Tsunami, "read to bad address va=%#x size=%d\n",
pkt->getAddr(), pkt->getSize());
pkt->result = Packet::BadAddress;
} else {
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
DPRINTF(Tsunami, "read va=%#x size=%d\n",
pkt->getAddr(), pkt->getSize());
switch (pkt->getSize()) {
case sizeof(uint64_t):
pkt->set(retData);
break;
case sizeof(uint32_t):
pkt->set((uint32_t)retData);
break;
case sizeof(uint16_t):
pkt->set((uint16_t)retData);
break;
case sizeof(uint8_t):
pkt->set((uint8_t)retData);
break;
default:
panic("invalid access size!\n");
}
pkt->result = Packet::Success;
}
return pioDelay;
}
Tick
BadAddr::write(PacketPtr pkt)
IsaFake::write(PacketPtr pkt)
{
DPRINTF(Tsunami, "write to bad address va=%#x size=%d \n",
pkt->getAddr(), pkt->getSize());
pkt->result = Packet::BadAddress;
if (params()->retBadAddr) {
DPRINTF(Tsunami, "write to bad address va=%#x size=%d \n",
pkt->getAddr(), pkt->getSize());
pkt->result = Packet::BadAddress;
} else {
DPRINTF(Tsunami, "write - va=%#x size=%d \n",
pkt->getAddr(), pkt->getSize());
pkt->result = Packet::Success;
}
return pioDelay;
}
@ -125,6 +113,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(IsaFake)
Param<Addr> pio_addr;
Param<Tick> pio_latency;
Param<Addr> pio_size;
Param<bool> ret_bad_addr;
Param<uint8_t> ret_data;
SimObjectParam<Platform *> platform;
SimObjectParam<System *> system;
@ -135,6 +125,8 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(IsaFake)
INIT_PARAM(pio_addr, "Device Address"),
INIT_PARAM(pio_latency, "Programmed IO latency"),
INIT_PARAM(pio_size, "Size of address range"),
INIT_PARAM(ret_bad_addr, "Return pkt status BadAddr"),
INIT_PARAM(ret_data, "Data to return if not bad addr"),
INIT_PARAM(platform, "platform"),
INIT_PARAM(system, "system object")
@ -147,40 +139,11 @@ CREATE_SIM_OBJECT(IsaFake)
p->pio_addr = pio_addr;
p->pio_delay = pio_latency;
p->pio_size = pio_size;
p->retBadAddr = ret_bad_addr;
p->retData = ret_data;
p->platform = platform;
p->system = system;
return new IsaFake(p);
}
REGISTER_SIM_OBJECT("IsaFake", IsaFake)
BEGIN_DECLARE_SIM_OBJECT_PARAMS(BadAddr)
Param<Addr> pio_addr;
Param<Tick> pio_latency;
SimObjectParam<Platform *> platform;
SimObjectParam<System *> system;
END_DECLARE_SIM_OBJECT_PARAMS(BadAddr)
BEGIN_INIT_SIM_OBJECT_PARAMS(BadAddr)
INIT_PARAM(pio_addr, "Device Address"),
INIT_PARAM(pio_latency, "Programmed IO latency"),
INIT_PARAM(platform, "platform"),
INIT_PARAM(system, "system object")
END_INIT_SIM_OBJECT_PARAMS(BadAddr)
CREATE_SIM_OBJECT(BadAddr)
{
BadAddr::Params *p = new BadAddr::Params;
p->name = getInstanceName();
p->pio_addr = pio_addr;
p->pio_delay = pio_latency;
p->platform = platform;
p->system = system;
return new BadAddr(p);
}
REGISTER_SIM_OBJECT("BadAddr", BadAddr)

34
src/dev/isa_fake.hh
View file

@ -25,8 +25,7 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Miguel Serrano
* Ali Saidi
* Authors: Ali Saidi
*/
/** @file
@ -42,10 +41,11 @@
#include "mem/packet.hh"
/**
* IsaFake is a device that returns -1 on all reads and
* accepts all writes. It is meant to be placed at an address range
* IsaFake is a device that returns, BadAddr, 1 or 0 on all reads and
* rites. It is meant to be placed at an address range
* so that an mcheck doesn't occur when an os probes a piece of hw
* that doesn't exist (e.g. UARTs1-3).
* that doesn't exist (e.g. UARTs1-3), or catch requests in the memory system
* that have no responders..
*/
class IsaFake : public BasicPioDevice
{
@ -53,9 +53,12 @@ class IsaFake : public BasicPioDevice
struct Params : public BasicPioDevice::Params
{
Addr pio_size;
bool retBadAddr;
uint8_t retData;
};
protected:
const Params *params() const { return (const Params*)_params; }
uint64_t retData;
public:
/**
@ -77,23 +80,8 @@ class IsaFake : public BasicPioDevice
* @param data the data to not write.
*/
virtual Tick write(PacketPtr pkt);
void init();
};
/**
* BadAddr is a device that fills the packet's result field with "BadAddress".
* @todo: Consider consolidating with IsaFake and similar classes.
*/
class BadAddr : public BasicPioDevice
{
public:
struct Params : public BasicPioDevice::Params
{
};
BadAddr(Params *p);
virtual void init();
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);
};
#endif // __TSUNAMI_FAKE_HH__
#endif // __ISA_FAKE_HH__

3
src/python/m5/objects/Pci.py
View file

@ -57,6 +57,3 @@ class PciDevice(DmaDevice):
pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks")
configdata = Param.PciConfigData(Parent.any, "PCI Config data")
config_latency = Param.Latency('20ns', "Config read or write latency")
class PciFake(PciDevice):
type = 'PciFake'

6
src/python/m5/objects/Tsunami.py
View file

@ -14,9 +14,11 @@ class TsunamiCChip(BasicPioDevice):
class IsaFake(BasicPioDevice):
type = 'IsaFake'
pio_size = Param.Addr(0x8, "Size of address range")
ret_data = Param.UInt8(0xFF, "Default data to return")
ret_bad_addr = Param.Bool(False, "Return pkt status bad address on access")
class BadAddr(BasicPioDevice):
type = 'BadAddr'
class BadAddr(IsaFake):
ret_bad_addr = Param.Bool(True, "Return pkt status bad address on access")
class TsunamiIO(BasicPioDevice):
type = 'TsunamiIO'