Merge zizzer:/bk/newmem
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest --HG-- extra : convert_revision : c3650273684f3fbdcd2e14e95d09ee3c6de8d6b6
This commit is contained in:
Ron Dreslinski
commit
685e588b45
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@ -1285,8 +1285,8 @@ template<class Impl>
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void
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DefaultFetch<Impl>::recvRetry()
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{
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assert(cacheBlocked);
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if (retryPkt != NULL) {
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assert(cacheBlocked);
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assert(retryTid != -1);
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assert(fetchStatus[retryTid] == IcacheWaitRetry);
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19
src/mem/cache/cache_blk.hh
vendored
19
src/mem/cache/cache_blk.hh
vendored
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@ -38,8 +38,6 @@
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#include "sim/root.hh" // for Tick
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#include "arch/isa_traits.hh" // for Addr
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#include <iostream>
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/**
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* Cache block status bit assignments
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*/
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@ -180,21 +178,4 @@ class CacheBlk
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};
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/**
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* Output a CacheBlk to the given ostream.
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* @param out The stream for the output.
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* @param blk The cache block to print.
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*
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* @return The output stream.
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*/
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inline std::ostream &
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operator<<(std::ostream &out, const CacheBlk &blk)
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{
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out << std::hex << std::endl;
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out << " Tag: " << blk.tag << std::endl;
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out << " Status: " << blk.status << std::endl;
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return(out << std::dec);
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}
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#endif //__CACHE_BLK_HH__
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@ -1,40 +1,40 @@
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---------- Begin Simulation Statistics ----------
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global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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global.BPredUnit.BTBHits 542 # Number of BTB hits
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global.BPredUnit.BTBLookups 1936 # Number of BTB lookups
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global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions.
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global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect
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global.BPredUnit.condPredicted 1302 # Number of conditional branches predicted
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global.BPredUnit.lookups 2254 # Number of BP lookups
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global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target.
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host_inst_rate 46995 # Simulator instruction rate (inst/s)
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host_mem_usage 160420 # Number of bytes of host memory used
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host_seconds 0.12 # Real time elapsed on the host
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host_tick_rate 57256 # Simulator tick rate (ticks/s)
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memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads.
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memdepunit.memDep.conflictingStores 259 # Number of conflicting stores.
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memdepunit.memDep.insertedLoads 2049 # Number of loads inserted to the mem dependence unit.
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memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit.
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global.BPredUnit.BTBHits 682 # Number of BTB hits
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global.BPredUnit.BTBLookups 2437 # Number of BTB lookups
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global.BPredUnit.RASInCorrect 76 # Number of incorrect RAS predictions.
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global.BPredUnit.condIncorrect 443 # Number of conditional branches incorrect
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global.BPredUnit.condPredicted 1570 # Number of conditional branches predicted
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global.BPredUnit.lookups 5322 # Number of BP lookups
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global.BPredUnit.usedRAS 2820 # Number of times the RAS was used to get a target.
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host_inst_rate 1288 # Simulator instruction rate (inst/s)
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host_mem_usage 180572 # Number of bytes of host memory used
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host_seconds 4.37 # Real time elapsed on the host
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host_tick_rate 322418 # Simulator tick rate (ticks/s)
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memdepunit.memDep.conflictingLoads 27 # Number of conflicting loads.
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memdepunit.memDep.conflictingStores 144 # Number of conflicting stores.
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memdepunit.memDep.insertedLoads 3819 # Number of loads inserted to the mem dependence unit.
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memdepunit.memDep.insertedStores 3727 # Number of stores inserted to the mem dependence unit.
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 5623 # Number of instructions simulated
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sim_seconds 0.000000 # Number of seconds simulated
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sim_ticks 6868 # Number of ticks simulated
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sim_seconds 0.000001 # Number of seconds simulated
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sim_ticks 1408131 # Number of ticks simulated
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system.cpu.commit.COM:branches 862 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_lim_events 94 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle.samples 6115
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system.cpu.commit.COM:committed_per_cycle.samples 58722
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system.cpu.commit.COM:committed_per_cycle.min_value 0
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0 3908 6390.84%
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1 1063 1738.35%
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2 389 636.14%
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3 210 343.42%
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4 152 248.57%
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5 94 153.72%
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6 76 124.28%
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7 149 243.66%
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8 74 121.01%
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0 56096 9552.81%
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1 1495 254.59%
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2 457 77.82%
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3 225 38.32%
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4 133 22.65%
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5 92 15.67%
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6 98 16.69%
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7 32 5.45%
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8 94 16.01%
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system.cpu.commit.COM:committed_per_cycle.max_value 8
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system.cpu.commit.COM:committed_per_cycle.end_dist
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@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 979 # Nu
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system.cpu.commit.COM:membars 0 # Number of memory barriers committed
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system.cpu.commit.COM:refs 1791 # Number of memory references committed
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted
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system.cpu.commit.branchMispredicts 374 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 4342 # The number of squashed insts skipped by commit
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system.cpu.commit.commitSquashedInsts 13826 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 5623 # Number of Instructions Simulated
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system.cpu.committedInsts_total 5623 # Number of Instructions Simulated
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system.cpu.cpi 1.221412 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 1.221412 # CPI: Total CPI of All Threads
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system.cpu.dcache.ReadReq_accesses 1536 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 3.038760 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.235294 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 1407 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 392 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.083984 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 129 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 27 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 228 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.066406 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 102 # number of ReadReq MSHR misses
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system.cpu.cpi 250.423439 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 250.423439 # CPI: Total CPI of All Threads
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system.cpu.dcache.ReadReq_accesses 1597 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 6940.988166 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6843.030303 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 1428 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 1173027 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.105823 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 169 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 70 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 677460 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.061991 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 99 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 2.564246 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 633 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.220443 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 179 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.087438 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses
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system.cpu.dcache.WriteReq_avg_miss_latency 5305.074803 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5141.328767 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 558 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 1347489 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.312808 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 254 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 181 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 375317 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 11.791908 # Average number of references to valid blocks.
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system.cpu.dcache.avg_blocked_cycles_no_targets 3389.604651 # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 11.546512 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 43 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 145753 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 2348 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 2.762987 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 2.196532 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 2040 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 851 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.131175 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 308 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 135 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 380 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.073680 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 173 # number of demand (read+write) MSHR misses
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system.cpu.dcache.demand_accesses 2409 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 5958.666667 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 6120.796512 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 1986 # number of demand (read+write) hits
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||||
system.cpu.dcache.demand_miss_latency 2520516 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.175592 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 423 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 251 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 1052777 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.071399 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 172 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 2348 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 2.762987 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2.196532 # average overall mshr miss latency
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||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 2040 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 851 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.131175 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 308 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 135 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 380 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.073680 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 173 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_accesses 2409 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 5958.666667 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 6120.796512 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 1986 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 2520516 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.175592 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 423 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 251 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 1052777 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.071399 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 172 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -119,91 +119,91 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 173 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 172 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 114.960547 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 2040 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 101.103948 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1986 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 3541 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 753 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 2254 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 3904 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 13699 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.328141 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.994322 # Number of inst fetches per cycle
|
||||
system.cpu.decode.DECODE:BlockedCycles 16535 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 70 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 167 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 29787 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 36497 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 5653 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 2641 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 200 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 38 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 5322 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 6542 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 21461 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 388 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 35708 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 2149 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.086728 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 6542 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 3502 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 0.581905 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist.samples 6869
|
||||
system.cpu.fetch.rateDist.samples 61364
|
||||
system.cpu.fetch.rateDist.min_value 0
|
||||
0 4548 6621.05%
|
||||
1 174 253.31%
|
||||
2 186 270.78%
|
||||
3 157 228.56%
|
||||
4 211 307.18%
|
||||
5 153 222.74%
|
||||
6 171 248.94%
|
||||
7 105 152.86%
|
||||
8 1164 1694.57%
|
||||
0 54337 8854.87%
|
||||
1 197 32.10%
|
||||
2 585 95.33%
|
||||
3 1433 233.52%
|
||||
4 1461 238.09%
|
||||
5 241 39.27%
|
||||
6 330 53.78%
|
||||
7 1227 199.95%
|
||||
8 1553 253.08%
|
||||
system.cpu.fetch.rateDist.max_value 8
|
||||
system.cpu.fetch.rateDist.end_dist
|
||||
|
||||
system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_accesses 6541 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 5110.042601 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 4297.762058 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 6095 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 2279079 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.068185 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 446 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 135 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 1336604 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.047546 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 311 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets 3658.571429 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 19.598071 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_no_targets 7 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_targets 25610 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 327 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_accesses 6541 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 5110.042601 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 4297.762058 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 6095 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 2279079 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.068185 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 446 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 135 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 1336604 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.047546 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 311 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 1255 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 327 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_accesses 6541 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 5110.042601 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 4297.762058 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 6095 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 2279079 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.068185 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 446 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 135 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 1336604 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.047546 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 311 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -216,78 +216,79 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 311 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 176.439074 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1255 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 147.733346 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 6095 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.iew.EXEC:branches 1206 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 37 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.157374 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 2595 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 985 # Number of stores executed
|
||||
system.cpu.idleCycles 1346768 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 2391 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 45 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 0.222997 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 5561 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 2148 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 5409 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 7670 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.744130 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 6673 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 11743 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.790499 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 4025 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.116611 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 7743 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 2049 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 9982 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 1610 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 409 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 7950 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.WB:producers 5275 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.191366 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 11811 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 404 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 6301 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 3819 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 2540 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 3727 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 19466 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 3413 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 276 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 13684 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 753 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 2641 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 34 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 1736 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 81 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 41 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 45 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 1070 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 0.818725 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.818725 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 8359 # Type of FU issued
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 2840 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 2915 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 45 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 283 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 121 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 0.003993 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.003993 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 13960 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
||||
(null) 2 0.02% # Type of FU issued
|
||||
IntAlu 5573 66.67% # Type of FU issued
|
||||
IntMult 1 0.01% # Type of FU issued
|
||||
IntDiv 0 0.00% # Type of FU issued
|
||||
FloatAdd 2 0.02% # Type of FU issued
|
||||
FloatCmp 0 0.00% # Type of FU issued
|
||||
FloatCvt 0 0.00% # Type of FU issued
|
||||
FloatMult 0 0.00% # Type of FU issued
|
||||
FloatDiv 0 0.00% # Type of FU issued
|
||||
FloatSqrt 0 0.00% # Type of FU issued
|
||||
MemRead 1757 21.02% # Type of FU issued
|
||||
MemWrite 1024 12.25% # Type of FU issued
|
||||
IprAccess 0 0.00% # Type of FU issued
|
||||
InstPrefetch 0 0.00% # Type of FU issued
|
||||
(null) 2 0.01% # Type of FU issued
|
||||
IntAlu 8277 59.29% # Type of FU issued
|
||||
IntMult 1 0.01% # Type of FU issued
|
||||
IntDiv 0 0.00% # Type of FU issued
|
||||
FloatAdd 2 0.01% # Type of FU issued
|
||||
FloatCmp 0 0.00% # Type of FU issued
|
||||
FloatCvt 0 0.00% # Type of FU issued
|
||||
FloatMult 0 0.00% # Type of FU issued
|
||||
FloatDiv 0 0.00% # Type of FU issued
|
||||
FloatSqrt 0 0.00% # Type of FU issued
|
||||
MemRead 3509 25.14% # Type of FU issued
|
||||
MemWrite 2169 15.54% # Type of FU issued
|
||||
IprAccess 0 0.00% # Type of FU issued
|
||||
InstPrefetch 0 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.013758 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 93 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.006662 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full.start_dist
|
||||
(null) 0 0.00% # attempts to use FU when none available
|
||||
IntAlu 1 0.87% # attempts to use FU when none available
|
||||
IntAlu 3 3.23% # attempts to use FU when none available
|
||||
IntMult 0 0.00% # attempts to use FU when none available
|
||||
IntDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatAdd 0 0.00% # attempts to use FU when none available
|
||||
|
|
@ -296,78 +297,78 @@ system.cpu.iq.ISSUE:fu_full.start_dist
|
|||
FloatMult 0 0.00% # attempts to use FU when none available
|
||||
FloatDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatSqrt 0 0.00% # attempts to use FU when none available
|
||||
MemRead 76 66.09% # attempts to use FU when none available
|
||||
MemWrite 38 33.04% # attempts to use FU when none available
|
||||
MemRead 54 58.06% # attempts to use FU when none available
|
||||
MemWrite 36 38.71% # attempts to use FU when none available
|
||||
IprAccess 0 0.00% # attempts to use FU when none available
|
||||
InstPrefetch 0 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full.end_dist
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 6869
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 61364
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
||||
0 3761 5475.32%
|
||||
1 891 1297.13%
|
||||
2 720 1048.19%
|
||||
3 617 898.24%
|
||||
4 445 647.84%
|
||||
5 278 404.72%
|
||||
6 104 151.40%
|
||||
7 41 59.69%
|
||||
8 12 17.47%
|
||||
0 54449 8873.12%
|
||||
1 3310 539.40%
|
||||
2 1268 206.64%
|
||||
3 1704 277.69%
|
||||
4 325 52.96%
|
||||
5 194 31.61%
|
||||
6 79 12.87%
|
||||
7 22 3.59%
|
||||
8 13 2.12%
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
||||
|
||||
system.cpu.iq.ISSUE:rate 1.216917 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 9924 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 8359 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 3985 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 2568 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadReq_accesses 494 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2.071138 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
|
||||
system.cpu.iq.ISSUE:rate 0.227495 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 19398 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 13960 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 13240 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 66 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 9412 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadReq_accesses 483 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 4537.301455 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2307.006237 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1019 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.995951 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 492 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 492 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995951 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 492 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency 2182442 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.995859 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 481 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1109670 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995859 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 481 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.004065 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.004158 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 494 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2.071138 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_accesses 483 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 4537.301455 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 2307.006237 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 1019 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.995951 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 492 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_miss_latency 2182442 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.995859 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 481 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 492 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.995951 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 492 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 1109670 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.995859 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 481 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 494 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2.071138 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_accesses 483 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 4537.301455 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 2307.006237 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 2 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 1019 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.995951 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 492 # number of overall misses
|
||||
system.cpu.l2cache.overall_miss_latency 2182442 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.995859 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 481 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 492 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.995951 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 492 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 1109670 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.995859 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 481 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -380,28 +381,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 492 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 481 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 290.948901 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 248.876875 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.numCycles 6869 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking
|
||||
system.cpu.numCycles 61364 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 6939 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IdleCycles 3757 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 753 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:IQFullEvents 2 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 36651 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 412 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 9 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 36093 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 29280 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 20221 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 5480 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 2641 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 493 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 16170 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 9160 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 27 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 927 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 369 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -6,8 +6,8 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Oct 8 2006 20:54:51
|
||||
M5 started Sun Oct 8 20:55:10 2006
|
||||
M5 compiled Oct 13 2006 16:07:10
|
||||
M5 started Fri Oct 13 16:07:55 2006
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
|
||||
Exiting @ tick 6868 because target called exit()
|
||||
command line: build/ALPHA_SE/m5.debug -d build/ALPHA_SE/tests/debug/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
|
||||
Exiting @ tick 1408131 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,31 +1,31 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 152920 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 166272 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
host_tick_rate 221766 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 8293 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 179892 # Number of bytes of host memory used
|
||||
host_seconds 0.68 # Real time elapsed on the host
|
||||
host_tick_rate 2595779 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 5642 # Number of instructions simulated
|
||||
sim_seconds 0.000000 # Number of seconds simulated
|
||||
sim_ticks 8316 # Number of ticks simulated
|
||||
sim_seconds 0.000002 # Number of seconds simulated
|
||||
sim_ticks 1767066 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 979 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3990.760870 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2990.760870 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 887 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 276 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 367150 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.093973 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 92 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 184 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 275150 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.093973 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 92 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 3 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 3977.109589 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2977.109589 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 739 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 219 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 290329 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.089901 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 73 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 146 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 217329 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 1791 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 3 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 3984.721212 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2984.721212 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 1626 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 495 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 657479 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.092127 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 165 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 330 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 492479 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.092127 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 165 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 1791 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 3 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 3984.721212 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2984.721212 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 1626 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 495 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 657479 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.092127 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 165 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 330 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 492479 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.092127 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 165 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 165 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 107.125526 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 97.858233 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1626 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 5643 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 2.996390 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996390 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 3980.490975 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2980.490975 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 5366 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 830 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 1102596 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.049087 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 277 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 553 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 825596 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.049087 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 277 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 5643 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 2.996390 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 1.996390 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 3980.490975 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 2980.490975 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 5366 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 830 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 1102596 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.049087 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 277 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 553 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 825596 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.049087 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 277 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 5643 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 2.996390 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 1.996390 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_avg_miss_latency 3980.490975 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 2980.490975 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 5366 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 830 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 1102596 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.049087 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 277 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 553 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 825596 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.049087 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 277 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.sampled_refs 277 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 133.213539 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 122.802112 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 5366 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 442 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2984.340136 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1983.340136 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 882 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1316094 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.997738 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 441 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 441 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 874653 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997738 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 441 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -162,29 +162,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 442 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2984.340136 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1983.340136 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 882 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 1316094 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.997738 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 441 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 441 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 874653 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.997738 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 441 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 442 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2984.340136 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1983.340136 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 1 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 882 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 1316094 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.997738 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 441 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 441 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 874653 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.997738 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 441 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -201,12 +201,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 441 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 240.276061 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 220.802916 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 8316 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1767066 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 5642 # Number of instructions executed
|
||||
system.cpu.num_refs 1792 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -6,8 +6,8 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Oct 10 2006 01:56:36
|
||||
M5 started Tue Oct 10 01:57:04 2006
|
||||
M5 compiled Oct 13 2006 16:07:10
|
||||
M5 started Fri Oct 13 16:08:16 2006
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing
|
||||
Exiting @ tick 8316 because target called exit()
|
||||
command line: build/ALPHA_SE/m5.debug -d build/ALPHA_SE/tests/debug/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing
|
||||
Exiting @ tick 1767066 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,40 +1,40 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
global.BPredUnit.BTBHits 155 # Number of BTB hits
|
||||
global.BPredUnit.BTBHits 200 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 711 # Number of BTB lookups
|
||||
global.BPredUnit.RASInCorrect 37 # Number of incorrect RAS predictions.
|
||||
global.BPredUnit.condIncorrect 222 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 441 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 888 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 160 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 26386 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 159884 # Number of bytes of host memory used
|
||||
host_seconds 0.09 # Real time elapsed on the host
|
||||
host_tick_rate 31792 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 9 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 7 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 675 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 369 # Number of stores inserted to the mem dependence unit.
|
||||
global.BPredUnit.RASInCorrect 42 # Number of incorrect RAS predictions.
|
||||
global.BPredUnit.condIncorrect 221 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 451 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 891 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 172 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 1447 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 180084 # Number of bytes of host memory used
|
||||
host_seconds 1.65 # Real time elapsed on the host
|
||||
host_tick_rate 455868 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 10 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 8 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 784 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 376 # Number of stores inserted to the mem dependence unit.
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 2387 # Number of instructions simulated
|
||||
sim_seconds 0.000000 # Number of seconds simulated
|
||||
sim_ticks 2886 # Number of ticks simulated
|
||||
sim_seconds 0.000001 # Number of seconds simulated
|
||||
sim_ticks 752027 # Number of ticks simulated
|
||||
system.cpu.commit.COM:branches 396 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 40 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_lim_events 56 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 2646
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 28113
|
||||
system.cpu.commit.COM:committed_per_cycle.min_value 0
|
||||
0 1713 6473.92%
|
||||
1 239 903.25%
|
||||
2 322 1216.93%
|
||||
3 139 525.32%
|
||||
4 78 294.78%
|
||||
5 67 253.21%
|
||||
6 27 102.04%
|
||||
7 21 79.37%
|
||||
8 40 151.17%
|
||||
0 27203 9676.31%
|
||||
1 230 81.81%
|
||||
2 313 111.34%
|
||||
3 133 47.31%
|
||||
4 80 28.46%
|
||||
5 53 18.85%
|
||||
6 27 9.60%
|
||||
7 18 6.40%
|
||||
8 56 19.92%
|
||||
system.cpu.commit.COM:committed_per_cycle.max_value 8
|
||||
system.cpu.commit.COM:committed_per_cycle.end_dist
|
||||
|
||||
|
|
@ -43,69 +43,69 @@ system.cpu.commit.COM:loads 415 # Nu
|
|||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 709 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 138 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.branchMispredicts 144 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 1258 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 1694 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 2387 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 2387 # Number of Instructions Simulated
|
||||
system.cpu.cpi 1.209049 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 1.209049 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 534 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 469 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 195 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.121723 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 65 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 4 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 122 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.114232 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.cpi 315.051110 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 315.051110 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 562 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 7254.010870 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7288.590164 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 470 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 667369 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.163701 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 92 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 31 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 444604 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.108541 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 3.017241 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.208333 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 236 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 175 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.197279 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 58 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 34 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 53 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 6647.600000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 6571.583333 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 224 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 465332 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.238095 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 70 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 46 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 157718 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.081633 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 24 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets 1.500000 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 8.294118 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets 2980.125000 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 8.164706 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 2 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 8 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_targets 3 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_targets 23841 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 828 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 3.008130 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2.058824 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 705 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 370 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.148551 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 123 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 38 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 175 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.102657 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_accesses 856 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 6991.981481 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 7086.141176 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 694 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 1132701 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.189252 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 162 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 77 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 602322 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.099299 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 85 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 828 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 3.008130 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2.058824 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 705 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 370 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.148551 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 123 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 38 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 175 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.102657 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_accesses 856 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 6991.981481 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 7086.141176 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 694 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 1132701 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.189252 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 162 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 77 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 602322 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.099299 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 85 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
|
|
@ -121,89 +121,89 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 54.161413 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 705 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 46.684937 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 694 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 82 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 90 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 156 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 4646 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 1691 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 873 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 240 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 315 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 1 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 888 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 740 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 1663 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 77 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 5518 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 235 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.307586 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 740 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 315 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.911327 # Number of inst fetches per cycle
|
||||
system.cpu.decode.DECODE:BlockedCycles 21872 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 79 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 150 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 4868 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 5315 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 925 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 338 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 2 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 891 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 814 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 1788 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 145 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 5562 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 260 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.031316 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 814 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 372 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 0.195487 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist.samples 2887
|
||||
system.cpu.fetch.rateDist.samples 28452
|
||||
system.cpu.fetch.rateDist.min_value 0
|
||||
0 1965 6806.37%
|
||||
1 36 124.70%
|
||||
2 79 273.64%
|
||||
3 66 228.61%
|
||||
4 125 432.98%
|
||||
5 60 207.83%
|
||||
6 40 138.55%
|
||||
7 42 145.48%
|
||||
8 474 1641.84%
|
||||
0 27494 9663.29%
|
||||
1 51 17.92%
|
||||
2 92 32.34%
|
||||
3 74 26.01%
|
||||
4 117 41.12%
|
||||
5 71 24.95%
|
||||
6 43 15.11%
|
||||
7 56 19.68%
|
||||
8 454 159.57%
|
||||
system.cpu.fetch.rateDist.max_value 8
|
||||
system.cpu.fetch.rateDist.end_dist
|
||||
|
||||
system.cpu.icache.ReadReq_accesses 740 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 2.989474 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 550 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 568 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.256757 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 190 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 378 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.255405 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 189 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_accesses 814 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 4971.589641 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 4152.244565 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 563 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 1247869 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.308354 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 251 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 67 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 764013 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.226044 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 184 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 2.910053 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets 3445 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 3.059783 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_no_targets 4 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_targets 13780 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 740 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 2.989474 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 550 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 568 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.256757 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 190 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 1 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 378 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.255405 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 189 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_accesses 814 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 4971.589641 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 4152.244565 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 563 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 1247869 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.308354 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 251 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 67 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 764013 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.226044 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 184 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 740 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 2.989474 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 550 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 568 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.256757 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 190 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 1 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 378 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.255405 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 189 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_accesses 814 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 4971.589641 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 4152.244565 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 563 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 1247869 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.308354 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 251 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 67 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 764013 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.226044 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 184 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -216,78 +216,79 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.sampled_refs 189 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 184 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 115.538968 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 550 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 91.596526 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 563 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.iew.EXEC:branches 532 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 247 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.078628 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 910 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 336 # Number of stores executed
|
||||
system.cpu.idleCycles 723576 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 571 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 266 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 0.119043 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 1018 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 343 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 1788 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 3053 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.790828 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 1875 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 3246 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.785067 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 1414 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.057499 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 3067 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 158 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 675 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 7 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 127 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 369 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 3835 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 574 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 143 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 3114 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.WB:producers 1472 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.114087 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 3258 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 160 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 14741 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 784 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 71 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 376 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 4271 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 675 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 113 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 3387 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 240 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewSquashCycles 338 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 13 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 2 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 30 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 82 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 29 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 11 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 260 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 75 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 369 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 82 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 11 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 105 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 53 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 0.827096 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.827096 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 3257 # Type of FU issued
|
||||
system.cpu.iew.predictedNotTakenIncorrect 99 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 61 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 0.003174 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.003174 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 3500 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
||||
(null) 0 0.00% # Type of FU issued
|
||||
IntAlu 2308 70.86% # Type of FU issued
|
||||
IntMult 1 0.03% # Type of FU issued
|
||||
IntDiv 0 0.00% # Type of FU issued
|
||||
FloatAdd 0 0.00% # Type of FU issued
|
||||
FloatCmp 0 0.00% # Type of FU issued
|
||||
FloatCvt 0 0.00% # Type of FU issued
|
||||
FloatMult 0 0.00% # Type of FU issued
|
||||
FloatDiv 0 0.00% # Type of FU issued
|
||||
FloatSqrt 0 0.00% # Type of FU issued
|
||||
MemRead 605 18.58% # Type of FU issued
|
||||
MemWrite 343 10.53% # Type of FU issued
|
||||
IprAccess 0 0.00% # Type of FU issued
|
||||
InstPrefetch 0 0.00% # Type of FU issued
|
||||
(null) 0 0.00% # Type of FU issued
|
||||
IntAlu 2460 70.29% # Type of FU issued
|
||||
IntMult 1 0.03% # Type of FU issued
|
||||
IntDiv 0 0.00% # Type of FU issued
|
||||
FloatAdd 0 0.00% # Type of FU issued
|
||||
FloatCmp 0 0.00% # Type of FU issued
|
||||
FloatCvt 0 0.00% # Type of FU issued
|
||||
FloatMult 0 0.00% # Type of FU issued
|
||||
FloatDiv 0 0.00% # Type of FU issued
|
||||
FloatSqrt 0 0.00% # Type of FU issued
|
||||
MemRead 695 19.86% # Type of FU issued
|
||||
MemWrite 344 9.83% # Type of FU issued
|
||||
IprAccess 0 0.00% # Type of FU issued
|
||||
InstPrefetch 0 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 40 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.012281 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 35 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.010000 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full.start_dist
|
||||
(null) 0 0.00% # attempts to use FU when none available
|
||||
IntAlu 5 12.50% # attempts to use FU when none available
|
||||
IntAlu 2 5.71% # attempts to use FU when none available
|
||||
IntMult 0 0.00% # attempts to use FU when none available
|
||||
IntDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatAdd 0 0.00% # attempts to use FU when none available
|
||||
|
|
@ -296,43 +297,43 @@ system.cpu.iq.ISSUE:fu_full.start_dist
|
|||
FloatMult 0 0.00% # attempts to use FU when none available
|
||||
FloatDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatSqrt 0 0.00% # attempts to use FU when none available
|
||||
MemRead 12 30.00% # attempts to use FU when none available
|
||||
MemWrite 23 57.50% # attempts to use FU when none available
|
||||
MemRead 11 31.43% # attempts to use FU when none available
|
||||
MemWrite 22 62.86% # attempts to use FU when none available
|
||||
IprAccess 0 0.00% # attempts to use FU when none available
|
||||
InstPrefetch 0 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full.end_dist
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 2887
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 28452
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
||||
0 1607 5566.33%
|
||||
1 435 1506.75%
|
||||
2 298 1032.21%
|
||||
3 221 765.50%
|
||||
4 164 568.06%
|
||||
5 94 325.60%
|
||||
6 46 159.33%
|
||||
7 15 51.96%
|
||||
8 7 24.25%
|
||||
0 26938 9467.88%
|
||||
1 609 214.04%
|
||||
2 344 120.91%
|
||||
3 248 87.16%
|
||||
4 180 63.26%
|
||||
5 81 28.47%
|
||||
6 35 12.30%
|
||||
7 12 4.22%
|
||||
8 5 1.76%
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
||||
|
||||
system.cpu.iq.ISSUE:rate 1.128161 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 3581 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 3257 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 7 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 1088 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 503 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadReq_accesses 274 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2.018248 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_miss_latency 553 # number of ReadReq miss cycles
|
||||
system.cpu.iq.ISSUE:rate 0.123014 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 3999 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 3500 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 1423 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 25 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 761 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadReq_accesses 269 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 4622.063197 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2296.591078 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1243335 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 274 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 274 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_misses 269 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 617783 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 274 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 269 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
|
||||
|
|
@ -341,32 +342,32 @@ system.cpu.l2cache.blocked_no_targets 0 # nu
|
|||
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 274 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2.018248 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_accesses 269 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 4622.063197 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 2296.591078 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 553 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 1243335 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 274 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses 269 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 274 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 617783 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 274 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses 269 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 274 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2.018248 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_accesses 269 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 4622.063197 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 2296.591078 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 0 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 553 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 1243335 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 274 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses 269 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 274 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 617783 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 274 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses 269 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -379,27 +380,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 274 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 269 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 169.795289 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 138.802720 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.numCycles 2887 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 28452 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 14785 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IdleCycles 1780 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 2 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 4975 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 4400 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 3144 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 785 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 240 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 8 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 1376 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 74 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 10 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 62 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 8 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.RENAME:IQFullEvents 18 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 5396 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 5263 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 4690 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 3393 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 851 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 338 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 25 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 1625 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 7057 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 88 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,4 +1,22 @@
|
|||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
|
||||
warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff8
|
||||
warn: cycle 109049: fault (page_table_fault) detected @ PC 0x000000
|
||||
warn: cycle 109050: fault (page_table_fault) detected @ PC 0x000000
|
||||
warn: cycle 109051: fault (page_table_fault) detected @ PC 0x000000
|
||||
warn: cycle 109052: fault (page_table_fault) detected @ PC 0x000000
|
||||
warn: cycle 109053: fault (page_table_fault) detected @ PC 0x000000
|
||||
warn: cycle 109054: fault (page_table_fault) detected @ PC 0x000000
|
||||
warn: cycle 109055: fault (page_table_fault) detected @ PC 0x000000
|
||||
warn: cycle 109056: fault (page_table_fault) detected @ PC 0x000000
|
||||
warn: cycle 109057: fault (page_table_fault) detected @ PC 0x000000
|
||||
warn: cycle 109062: fault (page_table_fault) detected @ PC 0x000000
|
||||
warn: cycle 109063: fault (page_table_fault) detected @ PC 0x000000
|
||||
warn: cycle 109064: fault (page_table_fault) detected @ PC 0x000000
|
||||
warn: cycle 109065: fault (page_table_fault) detected @ PC 0x000000
|
||||
warn: cycle 109066: fault (page_table_fault) detected @ PC 0x000000
|
||||
warn: cycle 109067: fault (page_table_fault) detected @ PC 0x000000
|
||||
warn: cycle 109068: fault (page_table_fault) detected @ PC 0x000000
|
||||
warn: cycle 109069: fault (page_table_fault) detected @ PC 0x000000
|
||||
warn: cycle 109070: fault (page_table_fault) detected @ PC 0x000000
|
||||
warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...)
|
||||
|
|
|
|||
|
|
@ -6,8 +6,8 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Oct 8 2006 14:00:39
|
||||
M5 started Sun Oct 8 14:00:52 2006
|
||||
M5 compiled Oct 13 2006 16:07:10
|
||||
M5 started Fri Oct 13 16:08:37 2006
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing
|
||||
Exiting @ tick 2886 because target called exit()
|
||||
command line: build/ALPHA_SE/m5.debug -d build/ALPHA_SE/tests/debug/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing
|
||||
Exiting @ tick 752027 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,31 +1,31 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 120829 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 165792 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
host_tick_rate 168699 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 7429 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 179540 # Number of bytes of host memory used
|
||||
host_seconds 0.35 # Real time elapsed on the host
|
||||
host_tick_rate 2820365 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 2578 # Number of instructions simulated
|
||||
sim_seconds 0.000000 # Number of seconds simulated
|
||||
sim_ticks 3777 # Number of ticks simulated
|
||||
sim_seconds 0.000001 # Number of seconds simulated
|
||||
sim_ticks 980012 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3988.472727 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2988.472727 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 360 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 165 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 219366 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.132530 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 110 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 164366 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.132530 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 3 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 3991.518519 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2991.518519 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 267 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 81 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 107771 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.091837 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 27 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 54 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 80771 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.091837 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 27 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 709 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 3 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 3989.475610 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2989.475610 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 627 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 246 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 327137 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.115656 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 82 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 164 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 245137 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.115656 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 82 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 3 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 3989.475610 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2989.475610 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 627 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 246 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 327137 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.115656 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 82 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 164 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 245137 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.115656 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 82 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 53.009529 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 45.884153 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 627 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 2579 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 3 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 3986.705521 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2986.705521 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 2416 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 489 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 649833 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.063203 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 163 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 326 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 486833 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.063203 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 163 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 2579 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 3 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 3986.705521 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 2986.705521 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 2416 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 489 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 649833 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.063203 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 163 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 326 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 486833 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.063203 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 2579 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 3 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_avg_miss_latency 3986.705521 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 2986.705521 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 2416 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 489 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 649833 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.063203 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 163 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 326 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 486833 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.063203 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 163 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -138,18 +138,18 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 93.126257 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 76.367476 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 2416 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 245 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_miss_latency 490 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2987.632653 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1986.632653 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_miss_latency 731970 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 245 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 245 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 486725 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 245 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -161,29 +161,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 245 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2987.632653 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1986.632653 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 490 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 731970 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 245 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 245 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 486725 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 245 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2987.632653 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1986.632653 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 0 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 490 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 731970 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 245 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 245 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 486725 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 245 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -200,12 +200,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 245 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 146.200635 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 122.501625 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 3777 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 980012 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 2578 # Number of instructions executed
|
||||
system.cpu.num_refs 710 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -6,8 +6,8 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Oct 10 2006 01:56:36
|
||||
M5 started Tue Oct 10 01:57:11 2006
|
||||
M5 compiled Oct 13 2006 16:07:10
|
||||
M5 started Fri Oct 13 16:08:56 2006
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing
|
||||
Exiting @ tick 3777 because target called exit()
|
||||
command line: build/ALPHA_SE/m5.debug -d build/ALPHA_SE/tests/debug/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing
|
||||
Exiting @ tick 980012 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,31 +1,31 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 68704 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 166092 # Number of bytes of host memory used
|
||||
host_seconds 0.08 # Real time elapsed on the host
|
||||
host_tick_rate 103651 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 57798 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 179040 # Number of bytes of host memory used
|
||||
host_seconds 0.10 # Real time elapsed on the host
|
||||
host_tick_rate 17679602 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 5657 # Number of instructions simulated
|
||||
sim_seconds 0.000000 # Number of seconds simulated
|
||||
sim_ticks 8579 # Number of ticks simulated
|
||||
sim_seconds 0.000002 # Number of seconds simulated
|
||||
sim_ticks 1738011 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 1130 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3987.109756 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2987.109756 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 1048 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 246 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 326943 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.072566 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 82 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 164 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 244943 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.072566 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 82 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 3 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 3968.740000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2968.740000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 874 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 150 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 198437 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.054113 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 50 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 100 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 148437 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.054113 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 50 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 2054 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 3 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 3980.151515 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2980.151515 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 1922 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 396 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 525380 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.064265 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 132 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 264 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 393380 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.064265 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 132 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 2054 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 3 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 3980.151515 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2980.151515 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 1922 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 396 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 525380 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.064265 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 132 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 264 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 393380 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.064265 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 132 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 132 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 86.924009 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 82.396200 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1922 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 5658 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 2.993399 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.993399 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 3978.069307 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2978.069307 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 5355 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 907 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 1205355 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.053552 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 604 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 902355 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.053552 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 5658 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 2.993399 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 1.993399 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 3978.069307 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 2978.069307 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 5355 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 907 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 1205355 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.053552 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 303 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 604 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 902355 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.053552 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 5658 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 2.993399 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 1.993399 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 3978.069307 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 2978.069307 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 5355 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 907 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 1205355 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.053552 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 303 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 604 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 902355 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.053552 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 13 # number of replacements
|
||||
system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 138.192774 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 133.062649 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 5355 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 435 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2983.237875 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1982.237875 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 866 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1291742 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.995402 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 433 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 433 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 858309 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995402 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 433 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -162,29 +162,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 435 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2983.237875 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1982.237875 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 866 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 1291742 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.995402 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 433 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 433 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 858309 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.995402 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 433 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 435 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2983.237875 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1982.237875 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 2 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 866 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 1291742 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.995402 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 433 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 433 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 858309 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.995402 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 433 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -201,12 +201,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 433 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 226.406294 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 216.976175 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 0 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1738011 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 5657 # Number of instructions executed
|
||||
system.cpu.num_refs 2055 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 13 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -6,8 +6,8 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Oct 9 2006 19:28:25
|
||||
M5 started Mon Oct 9 19:28:56 2006
|
||||
M5 compiled Oct 13 2006 18:43:33
|
||||
M5 started Fri Oct 13 18:44:16 2006
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/MIPS_SE/m5.debug -d build/MIPS_SE/tests/debug/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing
|
||||
Exiting @ tick 8579 because target called exit()
|
||||
Exiting @ tick 1738011 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -16,7 +16,17 @@ warn: Default fetch doesn't update it's state from a functional call.
|
|||
warn: Default fetch doesn't update it's state from a functional call.
|
||||
warn: Default fetch doesn't update it's state from a functional call.
|
||||
warn: Default fetch doesn't update it's state from a functional call.
|
||||
warn: cycle 1311113: fault (page_table_fault) detected @ PC 0x000000
|
||||
warn: cycle 1311114: fault (page_table_fault) detected @ PC 0x000000
|
||||
warn: cycle 1311115: fault (page_table_fault) detected @ PC 0x000000
|
||||
warn: cycle 1311124: fault (page_table_fault) detected @ PC 0x000000
|
||||
warn: cycle 1311125: fault (page_table_fault) detected @ PC 0x000000
|
||||
warn: cycle 1311126: fault (page_table_fault) detected @ PC 0x000000
|
||||
warn: cycle 1311127: fault (page_table_fault) detected @ PC 0x000000
|
||||
warn: cycle 1311128: fault (page_table_fault) detected @ PC 0x000000
|
||||
warn: cycle 1311129: fault (page_table_fault) detected @ PC 0x000000
|
||||
warn: Default fetch doesn't update it's state from a functional call.
|
||||
warn: Default fetch doesn't update it's state from a functional call.
|
||||
warn: Default fetch doesn't update it's state from a functional call.
|
||||
warn: Found outstanding miss on an non-update probe
|
||||
warn: Default fetch doesn't update it's state from a functional call.
|
||||
|
|
|
|||
|
|
@ -7,8 +7,8 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Oct 10 2006 01:56:36
|
||||
M5 started Tue Oct 10 01:57:16 2006
|
||||
M5 compiled Oct 13 2006 16:07:10
|
||||
M5 started Fri Oct 13 16:09:16 2006
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing
|
||||
Exiting @ tick 8439 because target called exit()
|
||||
command line: build/ALPHA_SE/m5.debug -d build/ALPHA_SE/tests/debug/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing
|
||||
Exiting @ tick 2237162 because target called exit()
|
||||
|
|
|
|||
|
|
@ -194,6 +194,8 @@ mem_side=system.membus.port[1]
|
|||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
|
||||
[system.cpu.workload]
|
||||
|
|
@ -206,6 +208,8 @@ system=system
|
|||
[system.membus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
width=64
|
||||
port=system.physmem.port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
|
|
|
|||
|
|
@ -19,6 +19,8 @@ mem_mode=atomic
|
|||
[system.membus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
width=64
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
|
|
@ -87,6 +89,8 @@ function_trace_start=0
|
|||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
width=64
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
|
|
|
|||
|
|
@ -1,31 +1,31 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 620088 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 159272 # Number of bytes of host memory used
|
||||
host_seconds 0.81 # Real time elapsed on the host
|
||||
host_tick_rate 845969 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 66568 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 179344 # Number of bytes of host memory used
|
||||
host_seconds 7.51 # Real time elapsed on the host
|
||||
host_tick_rate 530155 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 500000 # Number of instructions simulated
|
||||
sim_seconds 0.000001 # Number of seconds simulated
|
||||
sim_ticks 682488 # Number of ticks simulated
|
||||
sim_seconds 0.000004 # Number of seconds simulated
|
||||
sim_ticks 3982316 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3670.641270 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2670.641270 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 124120 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 945 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 1156252 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.002531 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 315 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 630 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 841252 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002531 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 315 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 3 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 3907.374101 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2907.374101 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 56201 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 417 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 543125 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 139 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 278 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 404125 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 180775 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 3 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 3743.121145 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2743.121145 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 180321 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 1362 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 1699377 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.002511 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 454 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 908 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 1245377 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.002511 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 454 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 180775 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 3 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 3743.121145 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2743.121145 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 180321 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 1362 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 1699377 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.002511 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 454 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 908 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 1245377 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.002511 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 454 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 291.968600 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 227.376906 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 500000 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 3 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 3977.722084 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2977.722084 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 499597 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 1209 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 1603022 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000806 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 403 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 806 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 1200022 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000806 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 403 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 500000 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 3 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 3977.722084 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 2977.722084 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 499597 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 1209 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 1603022 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000806 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 403 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 806 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 1200022 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000806 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 403 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 500000 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 3 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_avg_miss_latency 3977.722084 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 2977.722084 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 499597 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 1209 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 1603022 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000806 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 403 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 806 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 1200022 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000806 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 403 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -138,18 +138,18 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 268.423238 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 221.721362 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 499597 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 857 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1714 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2853.441074 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1852.441074 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_miss_latency 2445399 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 857 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 857 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1587542 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 857 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -161,29 +161,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 857 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2853.441074 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1852.441074 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 1714 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 2445399 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 857 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 857 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 1587542 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 857 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 857 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2853.441074 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1852.441074 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 0 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 1714 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 2445399 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 857 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 857 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 1587542 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 857 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -200,12 +200,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 857 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 560.393094 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 449.313470 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 0 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 3982316 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 500000 # Number of instructions executed
|
||||
system.cpu.num_refs 182203 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 18 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -7,8 +7,8 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Oct 8 2006 20:54:51
|
||||
M5 started Sun Oct 8 20:55:29 2006
|
||||
M5 compiled Oct 13 2006 16:07:10
|
||||
M5 started Fri Oct 13 16:09:55 2006
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing
|
||||
Exiting @ tick 682488 because a thread reached the max instruction count
|
||||
command line: build/ALPHA_SE/m5.debug -d build/ALPHA_SE/tests/debug/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing
|
||||
Exiting @ tick 3982316 because a thread reached the max instruction count
|
||||
|
|
|
|||
Loading…
Reference in a new issue